From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
"H . Peter Anvin" <hpa@zytor.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Andrew Waterman <andrew@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Nelson Chu <nelson.chu@sifive.com>
Cc: binutils@sourceware.org
Subject: [PATCH v7 5/5] RISC-V: Add address printer tests with ADDIW
Date: Wed, 24 Aug 2022 01:26:56 +0000 [thread overview]
Message-ID: <9b9a40cab70e059db7a2a4bdbd736d49c254f741.1661304407.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1661304407.git.research_trasio@irq.a4lg.com>
Address sequences involving ADDIW/C.ADDIW instructions require special
handling to sign-extend lower 32-bits of the original result.
This commit tests whether this sign-extension works.
gas/ChangeLog:
* testsuite/gas/riscv/dis-addr-4.s: New to test the address
computation with sign extension as used in ADDIW/C.ADDIW.
* testsuite/gas/riscv/dis-addr-4a.d: Test PC sign bit 0.
* testsuite/gas/riscv/dis-addr-4b.d: Test PC sign bit 1.
---
gas/testsuite/gas/riscv/dis-addr-4.s | 28 +++++++++++++++++++++++++++
gas/testsuite/gas/riscv/dis-addr-4a.d | 18 +++++++++++++++++
gas/testsuite/gas/riscv/dis-addr-4b.d | 18 +++++++++++++++++
3 files changed, 64 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/dis-addr-4.s
create mode 100644 gas/testsuite/gas/riscv/dis-addr-4a.d
create mode 100644 gas/testsuite/gas/riscv/dis-addr-4b.d
diff --git a/gas/testsuite/gas/riscv/dis-addr-4.s b/gas/testsuite/gas/riscv/dis-addr-4.s
new file mode 100644
index 00000000000..7c878f86dd6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-4.s
@@ -0,0 +1,28 @@
+.set addr_rv64_addiw_0a, 0xfffffffffffffff8 # 0xffffffe0 + 0x18 (sext:32->64)
+.set addr_rv64_c_addiw_0a, 0xfffffffffffffffc # 0xfffffff0 + 0x0c (sext:32->64)
+.set addr_rv64_addiw_0b, 0x00000004 # 0xffffffe8 + 0x1c
+.set addr_rv64_c_addiw_0b, 0x00000008 # 0xfffffff6 + 0x12
+.set addr_rv64_addiw_1a, 0x7ffffff8 # 0x7fffffe0 + 0x18
+.set addr_rv64_c_addiw_1a, 0x7ffffffc # 0x7ffffff0 + 0x0c
+.set addr_rv64_addiw_1b, 0xffffffff80000004 # 0x7fffffe8 + 0x1c (sext:32->64)
+.set addr_rv64_c_addiw_1b, 0xffffffff80000008 # 0x7ffffff6 + 0x12 (sext:32->64)
+
+ .text
+ .global _start
+_start:
+ .option push
+ .option arch, -c
+ # _start + 0x00
+ auipc t0, 0
+ addiw t1, t0, 0x18
+ # _start + 0x08
+ auipc t2, 0
+ addiw t3, t2, 0x1c
+
+ .option pop
+ # _start + 0x10
+ auipc t4, 0
+ c.addiw t4, 0x0c
+ # _start + 0x16
+ auipc t5, 0
+ c.addiw t5, 0x12
diff --git a/gas/testsuite/gas/riscv/dis-addr-4a.d b/gas/testsuite/gas/riscv/dis-addr-4a.d
new file mode 100644
index 00000000000..91816b9f0d9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-4a.d
@@ -0,0 +1,18 @@
+#as: -march=rv64ic
+#source: dis-addr-4.s
+#objdump: -d --adjust-vma=0xffffffe0
+
+.*: file format elf64-(little|big)riscv
+
+
+Disassembly of section .text:
+
+0+ffffffe0 <_start>:
+[ ]+ffffffe0:[ ]+00000297[ ]+auipc[ ]+t0,0x0
+[ ]+ffffffe4:[ ]+0182831b[ ]+addiw[ ]+t1,t0,24 # fffffffffffffff8 <addr_rv64_addiw_0a>
+[ ]+ffffffe8:[ ]+00000397[ ]+auipc[ ]+t2,0x0
+[ ]+ffffffec:[ ]+01c38e1b[ ]+addiw[ ]+t3,t2,28 # 4 <addr_rv64_addiw_0b>
+[ ]+fffffff0:[ ]+00000e97[ ]+auipc[ ]+t4,0x0
+[ ]+fffffff4:[ ]+2eb1[ ]+addiw[ ]+t4,t4,12 # fffffffffffffffc <addr_rv64_c_addiw_0a>
+[ ]+fffffff6:[ ]+00000f17[ ]+auipc[ ]+t5,0x0
+[ ]+fffffffa:[ ]+2f49[ ]+addiw[ ]+t5,t5,18 # 8 <addr_rv64_c_addiw_0b>
diff --git a/gas/testsuite/gas/riscv/dis-addr-4b.d b/gas/testsuite/gas/riscv/dis-addr-4b.d
new file mode 100644
index 00000000000..2f78ff59411
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-4b.d
@@ -0,0 +1,18 @@
+#as: -march=rv64ic
+#source: dis-addr-4.s
+#objdump: -d --adjust-vma=0x7fffffe0
+
+.*: file format elf64-(little|big)riscv
+
+
+Disassembly of section .text:
+
+0+7fffffe0 <_start>:
+[ ]+7fffffe0:[ ]+00000297[ ]+auipc[ ]+t0,0x0
+[ ]+7fffffe4:[ ]+0182831b[ ]+addiw[ ]+t1,t0,24 # 7ffffff8 <addr_rv64_addiw_1a>
+[ ]+7fffffe8:[ ]+00000397[ ]+auipc[ ]+t2,0x0
+[ ]+7fffffec:[ ]+01c38e1b[ ]+addiw[ ]+t3,t2,28 # ffffffff80000004 <addr_rv64_addiw_1b>
+[ ]+7ffffff0:[ ]+00000e97[ ]+auipc[ ]+t4,0x0
+[ ]+7ffffff4:[ ]+2eb1[ ]+addiw[ ]+t4,t4,12 # 7ffffffc <addr_rv64_c_addiw_1a>
+[ ]+7ffffff6:[ ]+00000f17[ ]+auipc[ ]+t5,0x0
+[ ]+7ffffffa:[ ]+2f49[ ]+addiw[ ]+t5,t5,18 # ffffffff80000008 <addr_rv64_c_addiw_1b>
--
2.34.1
prev parent reply other threads:[~2022-08-24 1:28 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-29 13:10 [PATCH 0/3] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-07-29 13:10 ` [PATCH 1/3] RISC-V: Print highest address on disassembler Tsukasa OI
2022-07-29 13:10 ` [PATCH 2/3] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-07-29 13:10 ` [PATCH 3/3] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-02 5:54 ` [PATCH v2 0/4] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-02 5:54 ` [PATCH v2 1/4] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-02 5:54 ` [PATCH v2 2/4] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-02 5:54 ` [PATCH v2 3/4] RISC-V: Break early if RISCV_GP_SYMBOL is found Tsukasa OI
2022-08-02 5:54 ` [PATCH v2 4/4] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-04 4:35 ` [PATCH v3 0/3] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-04 4:35 ` [PATCH v3 1/3] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-04 4:35 ` [PATCH v3 2/3] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-04 4:35 ` [PATCH v3 3/3] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-08 18:31 ` [PATCH v3 0/3] RISC-V: Fix address printer on the disassembler H. Peter Anvin
2022-08-08 19:46 ` Palmer Dabbelt
2022-08-09 3:39 ` [PATCH v3 0/4] " Tsukasa OI
2022-08-09 3:39 ` [PATCH v3 1/4] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-09 3:39 ` [PATCH v3 2/4] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-09 3:39 ` [PATCH v3 3/4] RISC-V: Fix JALR target " Tsukasa OI
2022-08-09 3:39 ` [PATCH v3 4/4] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-09 3:44 ` [PATCH v4 0/4] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-09 3:44 ` [PATCH v4 1/4] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-09 3:44 ` [PATCH v4 2/4] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-09 3:44 ` [PATCH v4 3/4] RISC-V: Fix JALR target " Tsukasa OI
2022-08-09 3:44 ` [PATCH v4 4/4] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-09 4:41 ` [PATCH v5 0/4] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-09 4:41 ` [PATCH v5 1/4] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-09 4:41 ` [PATCH v5 2/4] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-09 4:41 ` [PATCH v5 3/4] RISC-V: Fix JALR target " Tsukasa OI
2022-08-09 4:41 ` [PATCH v5 4/4] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-13 10:10 ` [PATCH v6 0/4] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-13 10:10 ` [PATCH v6 1/4] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-13 10:10 ` [PATCH v6 2/4] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-13 10:10 ` [PATCH v6 3/4] RISC-V: Fix JALR target " Tsukasa OI
2022-08-13 10:10 ` [PATCH v6 4/4] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-24 1:26 ` [PATCH v7 0/5] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-24 1:26 ` [PATCH v7 1/5] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-24 11:22 ` Nelson Chu
2022-08-24 11:22 ` Nelson Chu
2022-08-24 12:06 ` Tsukasa OI
2022-08-25 5:07 ` Nelson Chu
2022-08-24 1:26 ` [PATCH v7 2/5] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-24 11:35 ` Nelson Chu
2022-08-24 1:26 ` [PATCH v7 3/5] RISC-V: Fix JALR target " Tsukasa OI
2022-08-24 11:36 ` Nelson Chu
2022-08-24 1:26 ` [PATCH v7 4/5] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-24 11:42 ` Nelson Chu
2022-08-24 1:26 ` Tsukasa OI [this message]
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