From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
"H . Peter Anvin" <hpa@zytor.com>,
Nelson Chu <nelson.chu@sifive.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH v5 1/4] RISC-V: Print highest address on disassembler
Date: Tue, 9 Aug 2022 13:41:35 +0900 [thread overview]
Message-ID: <4ac4a4397a50b07f2f636d5bb5d2176325cf6e56.1660020096.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1660020096.git.research_trasio@irq.a4lg.com>
This patch makes possible to print the highest address (0xffffffff on RV32,
0xffffffff_ffffffff on RV64). This is particularly useful if the highest
address space is used for I/O registers and corresponding symbols
are defined.
opcodes/ChangeLog:
* riscv-dis.c (struct riscv_private_data): Add `to_print_addr' and
`has_gp' to enable printing the highest address.
(maybe_print_address): Utilize `to_print_addr' and `has_gp'.
(riscv_disassemble_insn): Likewise.
---
opcodes/riscv-dis.c | 22 ++++++++++++++++------
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 164fd209dbd..c6d80c3ba49 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -52,6 +52,8 @@ struct riscv_private_data
bfd_vma gp;
bfd_vma print_addr;
bfd_vma hi_addr[OP_MASK_RD + 1];
+ bool to_print_addr;
+ bool has_gp;
};
/* Used for mapping symbols. */
@@ -177,10 +179,13 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
pd->print_addr = (base_reg != 0 ? pd->hi_addr[base_reg] : 0) + offset;
pd->hi_addr[base_reg] = -1;
}
- else if (base_reg == X_GP && pd->gp != (bfd_vma)-1)
+ else if (base_reg == X_GP && pd->has_gp)
pd->print_addr = pd->gp + offset;
else if (base_reg == X_TP || base_reg == 0)
pd->print_addr = offset;
+ else
+ return;
+ pd->to_print_addr = true;
/* Sign-extend a 32-bit value to a 64-bit value. */
if (wide)
@@ -595,14 +600,19 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
int i;
pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data));
- pd->gp = -1;
- pd->print_addr = -1;
+ pd->gp = 0;
+ pd->print_addr = 0;
for (i = 0; i < (int)ARRAY_SIZE (pd->hi_addr); i++)
pd->hi_addr[i] = -1;
+ pd->to_print_addr = false;
+ pd->has_gp = false;
for (i = 0; i < info->symtab_size; i++)
if (strcmp (bfd_asymbol_name (info->symtab[i]), RISCV_GP_SYMBOL) == 0)
- pd->gp = bfd_asymbol_value (info->symtab[i]);
+ {
+ pd->gp = bfd_asymbol_value (info->symtab[i]);
+ pd->has_gp = true;
+ }
}
else
pd = info->private_data;
@@ -662,13 +672,13 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
print_insn_args (op->args, word, memaddr, info);
/* Try to disassemble multi-instruction addressing sequences. */
- if (pd->print_addr != (bfd_vma)-1)
+ if (pd->to_print_addr)
{
info->target = pd->print_addr;
(*info->fprintf_styled_func)
(info->stream, dis_style_comment_start, " # ");
(*info->print_address_func) (info->target, info);
- pd->print_addr = -1;
+ pd->to_print_addr = false;
}
/* Finish filling out insn_info fields. */
--
2.34.1
next prev parent reply other threads:[~2022-08-09 4:41 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-29 13:10 [PATCH 0/3] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-07-29 13:10 ` [PATCH 1/3] RISC-V: Print highest address on disassembler Tsukasa OI
2022-07-29 13:10 ` [PATCH 2/3] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-07-29 13:10 ` [PATCH 3/3] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-02 5:54 ` [PATCH v2 0/4] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-02 5:54 ` [PATCH v2 1/4] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-02 5:54 ` [PATCH v2 2/4] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-02 5:54 ` [PATCH v2 3/4] RISC-V: Break early if RISCV_GP_SYMBOL is found Tsukasa OI
2022-08-02 5:54 ` [PATCH v2 4/4] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-04 4:35 ` [PATCH v3 0/3] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-04 4:35 ` [PATCH v3 1/3] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-04 4:35 ` [PATCH v3 2/3] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-04 4:35 ` [PATCH v3 3/3] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-08 18:31 ` [PATCH v3 0/3] RISC-V: Fix address printer on the disassembler H. Peter Anvin
2022-08-08 19:46 ` Palmer Dabbelt
2022-08-09 3:39 ` [PATCH v3 0/4] " Tsukasa OI
2022-08-09 3:39 ` [PATCH v3 1/4] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-09 3:39 ` [PATCH v3 2/4] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-09 3:39 ` [PATCH v3 3/4] RISC-V: Fix JALR target " Tsukasa OI
2022-08-09 3:39 ` [PATCH v3 4/4] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-09 3:44 ` [PATCH v4 0/4] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-09 3:44 ` [PATCH v4 1/4] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-09 3:44 ` [PATCH v4 2/4] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-09 3:44 ` [PATCH v4 3/4] RISC-V: Fix JALR target " Tsukasa OI
2022-08-09 3:44 ` [PATCH v4 4/4] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-09 4:41 ` [PATCH v5 0/4] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-09 4:41 ` Tsukasa OI [this message]
2022-08-09 4:41 ` [PATCH v5 2/4] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-09 4:41 ` [PATCH v5 3/4] RISC-V: Fix JALR target " Tsukasa OI
2022-08-09 4:41 ` [PATCH v5 4/4] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-13 10:10 ` [PATCH v6 0/4] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-13 10:10 ` [PATCH v6 1/4] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-13 10:10 ` [PATCH v6 2/4] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-13 10:10 ` [PATCH v6 3/4] RISC-V: Fix JALR target " Tsukasa OI
2022-08-13 10:10 ` [PATCH v6 4/4] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-24 1:26 ` [PATCH v7 0/5] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-24 1:26 ` [PATCH v7 1/5] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-24 11:22 ` Nelson Chu
2022-08-24 11:22 ` Nelson Chu
2022-08-24 12:06 ` Tsukasa OI
2022-08-25 5:07 ` Nelson Chu
2022-08-24 1:26 ` [PATCH v7 2/5] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-24 11:35 ` Nelson Chu
2022-08-24 1:26 ` [PATCH v7 3/5] RISC-V: Fix JALR target " Tsukasa OI
2022-08-24 11:36 ` Nelson Chu
2022-08-24 1:26 ` [PATCH v7 4/5] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-24 11:42 ` Nelson Chu
2022-08-24 1:26 ` [PATCH v7 5/5] RISC-V: Add address printer tests with ADDIW Tsukasa OI
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