From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
"H . Peter Anvin" <hpa@zytor.com>,
Nelson Chu <nelson.chu@sifive.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH v5 4/4] RISC-V: Add address printer tests on disassembler
Date: Tue, 9 Aug 2022 13:41:38 +0900 [thread overview]
Message-ID: <7f07f1f2fa6a7690eee597b8bfb914847678a569.1660020096.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1660020096.git.research_trasio@irq.a4lg.com>
This commit adds address printer tests on the disassembler focusing on
various path to/on maybe_print_address. It also tests whether the address
adjustment on RV32 (fix to PR29342) works as expected, whether the highest
address is printed with a symbol and JALR address computation is fixed.
gas/ChangeLog:
* testsuite/gas/riscv/dis-addr-a.s: Rename from auipc-x0.s.
* testsuite/gas/riscv/dis-addr-a.d: Rename from auipc-x0.d.
* testsuite/gas/riscv/dis-addr-2.s: New address printer tests
on the disassembler.
* testsuite/gas/riscv/dis-addr-2-32.d: Likewise.
* testsuite/gas/riscv/dis-addr-2-64.d: Likewise.
* testsuite/gas/riscv/dis-addr-3.s: New address printer tests
on the disassembler if `gp' is the highest address.
* testsuite/gas/riscv/dis-addr-3-32.d: Likewise.
* testsuite/gas/riscv/dis-addr-3-64.d: Likewise.
---
.../gas/riscv/{auipc-x0.d => dis-addr-1.d} | 0
.../gas/riscv/{auipc-x0.s => dis-addr-1.s} | 0
gas/testsuite/gas/riscv/dis-addr-2-32.d | 31 ++++++++
gas/testsuite/gas/riscv/dis-addr-2-64.d | 35 +++++++++
gas/testsuite/gas/riscv/dis-addr-2.s | 74 +++++++++++++++++++
gas/testsuite/gas/riscv/dis-addr-3-32.d | 12 +++
gas/testsuite/gas/riscv/dis-addr-3-64.d | 12 +++
gas/testsuite/gas/riscv/dis-addr-3.s | 15 ++++
8 files changed, 179 insertions(+)
rename gas/testsuite/gas/riscv/{auipc-x0.d => dis-addr-1.d} (100%)
rename gas/testsuite/gas/riscv/{auipc-x0.s => dis-addr-1.s} (100%)
create mode 100644 gas/testsuite/gas/riscv/dis-addr-2-32.d
create mode 100644 gas/testsuite/gas/riscv/dis-addr-2-64.d
create mode 100644 gas/testsuite/gas/riscv/dis-addr-2.s
create mode 100644 gas/testsuite/gas/riscv/dis-addr-3-32.d
create mode 100644 gas/testsuite/gas/riscv/dis-addr-3-64.d
create mode 100644 gas/testsuite/gas/riscv/dis-addr-3.s
diff --git a/gas/testsuite/gas/riscv/auipc-x0.d b/gas/testsuite/gas/riscv/dis-addr-1.d
similarity index 100%
rename from gas/testsuite/gas/riscv/auipc-x0.d
rename to gas/testsuite/gas/riscv/dis-addr-1.d
diff --git a/gas/testsuite/gas/riscv/auipc-x0.s b/gas/testsuite/gas/riscv/dis-addr-1.s
similarity index 100%
rename from gas/testsuite/gas/riscv/auipc-x0.s
rename to gas/testsuite/gas/riscv/dis-addr-1.s
diff --git a/gas/testsuite/gas/riscv/dis-addr-2-32.d b/gas/testsuite/gas/riscv/dis-addr-2-32.d
new file mode 100644
index 00000000000..5117c3d8a0c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-2-32.d
@@ -0,0 +1,31 @@
+#as: -march=rv32ic
+#source: dis-addr-2.s
+#objdump: -d
+
+.*: file format elf32-(little|big)riscv
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+fffff2b7[ ]+lui[ ]+t0,0xfffff
+[ ]+[0-9a-f]+:[ ]+ffc2a903[ ]+lw[ ]+s2,-4\(t0\) # ffffeffc <addr_load>
+[ ]+[0-9a-f]+:[ ]+ffffe337[ ]+lui[ ]+t1,0xffffe
+[ ]+[0-9a-f]+:[ ]+ff332c23[ ]+sw[ ]+s3,-8\(t1\) # ffffdff8 <addr_store>
+[ ]+[0-9a-f]+:[ ]+ffffd3b7[ ]+lui[ ]+t2,0xffffd
+[ ]+[0-9a-f]+:[ ]+000380e7[ ]+jalr[ ]+t2 # ffffd000 <addr_jalr_1>
+[ ]+[0-9a-f]+:[ ]+ffffce37[ ]+lui[ ]+t3,0xffffc
+[ ]+[0-9a-f]+:[ ]+ff4e00e7[ ]+jalr[ ]+-12\(t3\) # ffffbff4 <addr_jalr_2>
+[ ]+[0-9a-f]+:[ ]+ffffbeb7[ ]+lui[ ]+t4,0xffffb
+[ ]+[0-9a-f]+:[ ]+000e8a67[ ]+jalr[ ]+s4,t4 # ffffb000 <addr_jalr_3>
+[ ]+[0-9a-f]+:[ ]+ffffaf37[ ]+lui[ ]+t5,0xffffa
+[ ]+[0-9a-f]+:[ ]+ff0f0a93[ ]+addi[ ]+s5,t5,-16 # ffff9ff0 <addr_loadaddr>
+[ ]+[0-9a-f]+:[ ]+ffff9fb7[ ]+lui[ ]+t6,0xffff9
+[ ]+[0-9a-f]+:[ ]+1fb1[ ]+addi[ ]+t6,t6,-20 # ffff8fec <addr_loadaddr_c>
+[ ]+[0-9a-f]+:[ ]+4001a283[ ]+lw[ ]+t0,1024\(gp\) # 600 <addr_rel_gp_pos>
+[ ]+[0-9a-f]+:[ ]+c001a303[ ]+lw[ ]+t1,-1024\(gp\) # fffffe00 <addr_rel_gp_neg>
+[ ]+[0-9a-f]+:[ ]+10002383[ ]+lw[ ]+t2,256\(zero\) # 100 <addr_rel_zero_pos>
+[ ]+[0-9a-f]+:[ ]+80002e03[ ]+lw[ ]+t3,-2048\(zero\) # fffff800 <addr_rel_zero_neg>
+[ ]+[0-9a-f]+:[ ]+10400ee7[ ]+jalr[ ]+t4,260\(zero\) # 104 <addr_jalr_rel_zero_pos>
+[ ]+[0-9a-f]+:[ ]+80400f67[ ]+jalr[ ]+t5,-2044\(zero\) # fffff804 <addr_jalr_rel_zero_neg>
+[ ]+[0-9a-f]+:[ ]+fff00f83[ ]+lb[ ]+t6,-1\(zero\) # ffffffff <addr_top>
diff --git a/gas/testsuite/gas/riscv/dis-addr-2-64.d b/gas/testsuite/gas/riscv/dis-addr-2-64.d
new file mode 100644
index 00000000000..d806bad25b4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-2-64.d
@@ -0,0 +1,35 @@
+#as: -march=rv64ic -defsym rv64=1
+#source: dis-addr-2.s
+#objdump: -d
+
+.*: file format elf64-(little|big)riscv
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+fffff2b7[ ]+lui[ ]+t0,0xfffff
+[ ]+[0-9a-f]+:[ ]+ffc2a903[ ]+lw[ ]+s2,-4\(t0\) # ffffffffffffeffc <addr_load>
+[ ]+[0-9a-f]+:[ ]+ffffe337[ ]+lui[ ]+t1,0xffffe
+[ ]+[0-9a-f]+:[ ]+ff332c23[ ]+sw[ ]+s3,-8\(t1\) # ffffffffffffdff8 <addr_store>
+[ ]+[0-9a-f]+:[ ]+ffffd3b7[ ]+lui[ ]+t2,0xffffd
+[ ]+[0-9a-f]+:[ ]+000380e7[ ]+jalr[ ]+t2 # ffffffffffffd000 <addr_jalr_1>
+[ ]+[0-9a-f]+:[ ]+ffffce37[ ]+lui[ ]+t3,0xffffc
+[ ]+[0-9a-f]+:[ ]+ff4e00e7[ ]+jalr[ ]+-12\(t3\) # ffffffffffffbff4 <addr_jalr_2>
+[ ]+[0-9a-f]+:[ ]+ffffbeb7[ ]+lui[ ]+t4,0xffffb
+[ ]+[0-9a-f]+:[ ]+000e8a67[ ]+jalr[ ]+s4,t4 # ffffffffffffb000 <addr_jalr_3>
+[ ]+[0-9a-f]+:[ ]+ffffaf37[ ]+lui[ ]+t5,0xffffa
+[ ]+[0-9a-f]+:[ ]+ff0f0a93[ ]+addi[ ]+s5,t5,-16 # ffffffffffff9ff0 <addr_loadaddr>
+[ ]+[0-9a-f]+:[ ]+ffff9fb7[ ]+lui[ ]+t6,0xffff9
+[ ]+[0-9a-f]+:[ ]+1fb1[ ]+addi[ ]+t6,t6,-20 # ffffffffffff8fec <addr_loadaddr_c>
+[ ]+[0-9a-f]+:[ ]+ffff8b37[ ]+lui[ ]+s6,0xffff8
+[ ]+[0-9a-f]+:[ ]+fe8b0b9b[ ]+addiw[ ]+s7,s6,-24 # ffffffffffff7fe8 <addr_loadaddr_w>
+[ ]+[0-9a-f]+:[ ]+ffff7c37[ ]+lui[ ]+s8,0xffff7
+[ ]+[0-9a-f]+:[ ]+3c11[ ]+addiw[ ]+s8,s8,-28 # ffffffffffff6fe4 <addr_loadaddr_w_c>
+[ ]+[0-9a-f]+:[ ]+4001a283[ ]+lw[ ]+t0,1024\(gp\) # 600 <addr_rel_gp_pos>
+[ ]+[0-9a-f]+:[ ]+c001a303[ ]+lw[ ]+t1,-1024\(gp\) # fffffffffffffe00 <addr_rel_gp_neg>
+[ ]+[0-9a-f]+:[ ]+10002383[ ]+lw[ ]+t2,256\(zero\) # 100 <addr_rel_zero_pos>
+[ ]+[0-9a-f]+:[ ]+80002e03[ ]+lw[ ]+t3,-2048\(zero\) # fffffffffffff800 <addr_rel_zero_neg>
+[ ]+[0-9a-f]+:[ ]+10400ee7[ ]+jalr[ ]+t4,260\(zero\) # 104 <addr_jalr_rel_zero_pos>
+[ ]+[0-9a-f]+:[ ]+80400f67[ ]+jalr[ ]+t5,-2044\(zero\) # fffffffffffff804 <addr_jalr_rel_zero_neg>
+[ ]+[0-9a-f]+:[ ]+fff00f83[ ]+lb[ ]+t6,-1\(zero\) # ffffffffffffffff <addr_top>
diff --git a/gas/testsuite/gas/riscv/dis-addr-2.s b/gas/testsuite/gas/riscv/dis-addr-2.s
new file mode 100644
index 00000000000..cb7f0cd9dc2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-2.s
@@ -0,0 +1,74 @@
+.set __global_pointer$, 0x00000200
+
+.ifdef rv64
+topbase = 0xffffffff00000000
+.else
+topbase = 0
+.endif
+
+.set addr_load, topbase + 0xffffeffc # -0x1000 -4
+.set addr_store, topbase + 0xffffdff8 # -0x2000 -8
+.set addr_jalr_1, topbase + 0xffffd000 # -0x3000
+.set addr_jalr_2, topbase + 0xffffbff4 # -0x4000 -12
+.set addr_jalr_3, topbase + 0xffffb000 # -0x5000
+.set addr_loadaddr, topbase + 0xffff9ff0 # -0x6000 -16
+.set addr_loadaddr_c, topbase + 0xffff8fec # -0x7000 -20
+.set addr_loadaddr_w, topbase + 0xffff7fe8 # -0x8000 -24
+.set addr_loadaddr_w_c, topbase + 0xffff6fe4 # -0x9000 -28
+.set addr_rel_gp_pos, 0x00000600 # __global_pointer$ + 0x400
+.set addr_rel_gp_neg, topbase + 0xfffffe00 # __global_pointer$ - 0x400
+.set addr_rel_zero_pos, 0x00000100
+.set addr_rel_zero_neg, topbase + 0xfffff800 # -0x800
+.set addr_jalr_rel_zero_pos, 0x00000104 # 0x104
+.set addr_jalr_rel_zero_neg, topbase + 0xfffff804 # -0x7fc
+.set addr_top, topbase + 0xffffffff # -1
+
+target:
+ .option push
+ .option arch, -c
+ ## Use hi_addr
+ # Load
+ lui t0, 0xfffff
+ lw s2, -4(t0)
+ # Store
+ lui t1, 0xffffe
+ sw s3, -8(t1)
+ # JALR (implicit destination, no offset)
+ lui t2, 0xffffd
+ jalr t2
+ # JALR (implicit destination, with offset)
+ lui t3, 0xffffc
+ jalr -12(t3)
+ # JALR (explicit destination, no offset)
+ lui t4, 0xffffb
+ jalr s4, t4
+ # ADDI (not compressed)
+ lui t5, 0xffffa
+ addi s5, t5, -16
+ # C.ADDI
+ lui t6, 0xffff9
+ .option pop
+ c.addi t6, -20
+.ifdef rv64
+ .option push
+ .option arch, -c
+ # ADDIW (not compressed)
+ lui s6, 0xffff8
+ addiw s7, s6, -24
+ # C.ADDIW
+ lui s8, 0xffff7
+ .option pop
+ c.addiw s8, -28
+.endif
+
+ # Use addresses relative to gp
+ lw t0, 0x400(gp)
+ lw t1, -0x400(gp)
+ # Use addresses relative to zero
+ lw t2, 0x100(zero)
+ lw t3, -0x800(zero)
+ jalr t4, 0x104(zero)
+ jalr t5, -0x7fc(zero)
+
+ # Access to the highest address
+ lb t6, -1(zero)
diff --git a/gas/testsuite/gas/riscv/dis-addr-3-32.d b/gas/testsuite/gas/riscv/dis-addr-3-32.d
new file mode 100644
index 00000000000..42ca89850ac
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-3-32.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i
+#source: dis-addr-3.s
+#objdump: -d
+
+.*: file format elf32-(little|big)riscv
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0051a283[ ]+lw[ ]+t0,5\(gp\) # 4 <addr_rel_gp_pos>
+[ ]+[0-9a-f]+:[ ]+ffd1a303[ ]+lw[ ]+t1,-3\(gp\) # fffffffc <addr_rel_gp_neg>
diff --git a/gas/testsuite/gas/riscv/dis-addr-3-64.d b/gas/testsuite/gas/riscv/dis-addr-3-64.d
new file mode 100644
index 00000000000..394c58fac96
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-3-64.d
@@ -0,0 +1,12 @@
+#as: -march=rv64i -defsym rv64=1
+#source: dis-addr-3.s
+#objdump: -d
+
+.*: file format elf64-(little|big)riscv
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0051a283[ ]+lw[ ]+t0,5\(gp\) # 4 <addr_rel_gp_pos>
+[ ]+[0-9a-f]+:[ ]+ffd1a303[ ]+lw[ ]+t1,-3\(gp\) # fffffffffffffffc <addr_rel_gp_neg>
diff --git a/gas/testsuite/gas/riscv/dis-addr-3.s b/gas/testsuite/gas/riscv/dis-addr-3.s
new file mode 100644
index 00000000000..6ba9fc7a39d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dis-addr-3.s
@@ -0,0 +1,15 @@
+.ifdef rv64
+topbase = 0xffffffff00000000
+.else
+topbase = 0
+.endif
+
+.set __global_pointer$, topbase + 0xffffffff # -1
+.set addr_rel_gp_pos, 0x00000004 # +4
+.set addr_rel_gp_neg, topbase + 0xfffffffc # -4
+
+target:
+ # Use addresses relative to gp
+ # (gp is the highest address)
+ lw t0, +5(gp)
+ lw t1, -3(gp)
--
2.34.1
next prev parent reply other threads:[~2022-08-09 4:42 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-29 13:10 [PATCH 0/3] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-07-29 13:10 ` [PATCH 1/3] RISC-V: Print highest address on disassembler Tsukasa OI
2022-07-29 13:10 ` [PATCH 2/3] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-07-29 13:10 ` [PATCH 3/3] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-02 5:54 ` [PATCH v2 0/4] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-02 5:54 ` [PATCH v2 1/4] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-02 5:54 ` [PATCH v2 2/4] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-02 5:54 ` [PATCH v2 3/4] RISC-V: Break early if RISCV_GP_SYMBOL is found Tsukasa OI
2022-08-02 5:54 ` [PATCH v2 4/4] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-04 4:35 ` [PATCH v3 0/3] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-04 4:35 ` [PATCH v3 1/3] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-04 4:35 ` [PATCH v3 2/3] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-04 4:35 ` [PATCH v3 3/3] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-08 18:31 ` [PATCH v3 0/3] RISC-V: Fix address printer on the disassembler H. Peter Anvin
2022-08-08 19:46 ` Palmer Dabbelt
2022-08-09 3:39 ` [PATCH v3 0/4] " Tsukasa OI
2022-08-09 3:39 ` [PATCH v3 1/4] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-09 3:39 ` [PATCH v3 2/4] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-09 3:39 ` [PATCH v3 3/4] RISC-V: Fix JALR target " Tsukasa OI
2022-08-09 3:39 ` [PATCH v3 4/4] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-09 3:44 ` [PATCH v4 0/4] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-09 3:44 ` [PATCH v4 1/4] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-09 3:44 ` [PATCH v4 2/4] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-09 3:44 ` [PATCH v4 3/4] RISC-V: Fix JALR target " Tsukasa OI
2022-08-09 3:44 ` [PATCH v4 4/4] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-09 4:41 ` [PATCH v5 0/4] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-09 4:41 ` [PATCH v5 1/4] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-09 4:41 ` [PATCH v5 2/4] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-09 4:41 ` [PATCH v5 3/4] RISC-V: Fix JALR target " Tsukasa OI
2022-08-09 4:41 ` Tsukasa OI [this message]
2022-08-13 10:10 ` [PATCH v6 0/4] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-13 10:10 ` [PATCH v6 1/4] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-13 10:10 ` [PATCH v6 2/4] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-13 10:10 ` [PATCH v6 3/4] RISC-V: Fix JALR target " Tsukasa OI
2022-08-13 10:10 ` [PATCH v6 4/4] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-24 1:26 ` [PATCH v7 0/5] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-24 1:26 ` [PATCH v7 1/5] RISC-V: Print highest address on disassembler Tsukasa OI
2022-08-24 11:22 ` Nelson Chu
2022-08-24 11:22 ` Nelson Chu
2022-08-24 12:06 ` Tsukasa OI
2022-08-25 5:07 ` Nelson Chu
2022-08-24 1:26 ` [PATCH v7 2/5] RISC-V: Fix RV32 disassembler address computation Tsukasa OI
2022-08-24 11:35 ` Nelson Chu
2022-08-24 1:26 ` [PATCH v7 3/5] RISC-V: Fix JALR target " Tsukasa OI
2022-08-24 11:36 ` Nelson Chu
2022-08-24 1:26 ` [PATCH v7 4/5] RISC-V: Add address printer tests on disassembler Tsukasa OI
2022-08-24 11:42 ` Nelson Chu
2022-08-24 1:26 ` [PATCH v7 5/5] RISC-V: Add address printer tests with ADDIW Tsukasa OI
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