[PATCH v2 09/11] RISC-V: Add T-Head MemIdx vendor extension

[Christoph Muellner <christoph.muellner@vrull.eu>]

From: Christoph Müllner <christoph.muellner@vrull.eu>

T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.

This patch adds the XTheadMemIdx extension, a collection of T-Head specific
GPR memory access instructions.
The 'th' prefix and the "XTheadMemIdx" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).

In total XTheadCmo introduces the following 44 instructions
(BU,HU,WU only for loads (zero-extend instead of sign-extend)):

* {L,S}{D,W,WU,H,HU,B,BU}{IA,IB} rd, rs1, imm5, imm2
* {L,S}R{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2
* {L,S}UR{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 bfd/elfxx-riscv.c                             |   5 +
 gas/doc/c-riscv.texi                          |   5 +
 gas/testsuite/gas/riscv/x-thead-memidx-fail.d |   3 +
 gas/testsuite/gas/riscv/x-thead-memidx-fail.l |  14 ++
 gas/testsuite/gas/riscv/x-thead-memidx-fail.s |  14 ++
 gas/testsuite/gas/riscv/x-thead-memidx.d      |  53 +++++++
 gas/testsuite/gas/riscv/x-thead-memidx.s      |  48 +++++++
 include/opcode/riscv-opc.h                    | 134 ++++++++++++++++++
 include/opcode/riscv.h                        |   1 +
 opcodes/riscv-opc.c                           |  60 ++++++++
 10 files changed, 337 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.d
 create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.l
 create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.s
 create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx.d
 create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 52aa07877b9..caa690913f0 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1230,6 +1230,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
   {"xtheadcondmov",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadfmemidx",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadmac",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
+  {"xtheadmemidx",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadsync",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {NULL, 0, 0, 0, 0}
 };
@@ -2407,6 +2408,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "xtheadfmemidx");
     case INSN_CLASS_XTHEADMAC:
       return riscv_subset_supports (rps, "xtheadmac");
+    case INSN_CLASS_XTHEADMEMIDX:
+      return riscv_subset_supports (rps, "xtheadmemidx");
     case INSN_CLASS_XTHEADSYNC:
       return riscv_subset_supports (rps, "xtheadsync");
     default:
@@ -2550,6 +2553,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "xtheadfmemidx";
     case INSN_CLASS_XTHEADMAC:
       return "xtheadmac";
+    case INSN_CLASS_XTHEADMEMIDX:
+      return "xtheadmemidx";
     case INSN_CLASS_XTHEADSYNC:
       return "xtheadsync";
     default:
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 392be0e7e21..ed3d98962e4 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -739,6 +739,11 @@ The XTheadMac extension provides multiply-accumulate instructions.
 
 It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
 
+@item XTheadMemIdx
+The XTheadMemIdx extension provides GPR memory operations.
+
+It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
+
 @item XTheadSync
 The XTheadSync extension provides instructions for multi-processor synchronization.
 
diff --git a/gas/testsuite/gas/riscv/x-thead-memidx-fail.d b/gas/testsuite/gas/riscv/x-thead-memidx-fail.d
new file mode 100644
index 00000000000..086855c1030
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-memidx-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv64gc_xtheadmemidx
+#source: x-thead-memidx-fail.s
+#error_output: x-thead-memidx-fail.l
diff --git a/gas/testsuite/gas/riscv/x-thead-memidx-fail.l b/gas/testsuite/gas/riscv/x-thead-memidx-fail.l
new file mode 100644
index 00000000000..c6bd25c0268
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-memidx-fail.l
@@ -0,0 +1,14 @@
+.*: Assembler messages:
+.*: Error: improper immediate value \(-17\)
+.*: Error: improper immediate value \(18446744073709551615\)
+.*: Error: improper immediate value \(16\)
+.*: Error: improper immediate value \(4\)
+
+.*: Error: illegal operands `th.ldia a0,\(a0\),0,0'
+.*: Error: illegal operands `th.ldib a0,\(a0\),0,0'
+
+.*: Error: improper immediate value \(18446744073709551615\)
+.*: Error: improper immediate value \(4\)
+
+.*: Error: improper immediate value \(18446744073709551615\)
+.*: Error: improper immediate value \(4\)
diff --git a/gas/testsuite/gas/riscv/x-thead-memidx-fail.s b/gas/testsuite/gas/riscv/x-thead-memidx-fail.s
new file mode 100644
index 00000000000..c9eb99ce52e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-memidx-fail.s
@@ -0,0 +1,14 @@
+target:
+	th.ldia		a0, (a1), -17, 0
+	th.ldib		a0, (a1), 0, -1
+	th.sdia		a0, (a1), 16, 0
+	th.sdib		a0, (a1), 0, 4
+
+	th.ldia		a0, (a0), 0, 0
+	th.ldib		a0, (a0), 0, 0
+
+	th.lrd		a0, a1, a2, -1
+	th.srd		a0, a1, a2, 4
+
+	th.lurd		a0, a1, a2, -1
+	th.surd		a0, a1, a2, 4
diff --git a/gas/testsuite/gas/riscv/x-thead-memidx.d b/gas/testsuite/gas/riscv/x-thead-memidx.d
new file mode 100644
index 00000000000..03d39858aaa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-memidx.d
@@ -0,0 +1,53 @@
+#as: -march=rv64gc_xtheadmemidx
+#source: x-thead-memidx.s
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+7805c50b[ 	]+th.ldia[ 	]+a0,\(a1\),0,0
+[ 	]+[0-9a-f]+:[ 	]+6af5c50b[ 	]+th.ldib[ 	]+a0,\(a1\),15,1
+[ 	]+[0-9a-f]+:[ 	]+5c05c50b[ 	]+th.lwia[ 	]+a0,\(a1\),0,2
+[ 	]+[0-9a-f]+:[ 	]+4f05c50b[ 	]+th.lwib[ 	]+a0,\(a1\),-16,3
+[ 	]+[0-9a-f]+:[ 	]+d805c50b[ 	]+th.lwuia[ 	]+a0,\(a1\),0,0
+[ 	]+[0-9a-f]+:[ 	]+caf5c50b[ 	]+th.lwuib[ 	]+a0,\(a1\),15,1
+[ 	]+[0-9a-f]+:[ 	]+3c05c50b[ 	]+th.lhia[ 	]+a0,\(a1\),0,2
+[ 	]+[0-9a-f]+:[ 	]+2f05c50b[ 	]+th.lhib[ 	]+a0,\(a1\),-16,3
+[ 	]+[0-9a-f]+:[ 	]+b805c50b[ 	]+th.lhuia[ 	]+a0,\(a1\),0,0
+[ 	]+[0-9a-f]+:[ 	]+aaf5c50b[ 	]+th.lhuib[ 	]+a0,\(a1\),15,1
+[ 	]+[0-9a-f]+:[ 	]+1c05c50b[ 	]+th.lbia[ 	]+a0,\(a1\),0,2
+[ 	]+[0-9a-f]+:[ 	]+0f05c50b[ 	]+th.lbib[ 	]+a0,\(a1\),-16,3
+[ 	]+[0-9a-f]+:[ 	]+9805c50b[ 	]+th.lbuia[ 	]+a0,\(a1\),0,0
+[ 	]+[0-9a-f]+:[ 	]+8af5c50b[ 	]+th.lbuib[ 	]+a0,\(a1\),15,1
+[ 	]+[0-9a-f]+:[ 	]+7905d50b[ 	]+th.sdia[ 	]+a0,\(a1\),-16,0
+[ 	]+[0-9a-f]+:[ 	]+6bf5d50b[ 	]+th.sdib[ 	]+a0,\(a1\),-1,1
+[ 	]+[0-9a-f]+:[ 	]+5c05d50b[ 	]+th.swia[ 	]+a0,\(a1\),0,2
+[ 	]+[0-9a-f]+:[ 	]+4e15d50b[ 	]+th.swib[ 	]+a0,\(a1\),1,3
+[ 	]+[0-9a-f]+:[ 	]+3845d50b[ 	]+th.shia[ 	]+a0,\(a1\),4,0
+[ 	]+[0-9a-f]+:[ 	]+2ad5d50b[ 	]+th.shib[ 	]+a0,\(a1\),13,1
+[ 	]+[0-9a-f]+:[ 	]+1ce5d50b[ 	]+th.sbia[ 	]+a0,\(a1\),14,2
+[ 	]+[0-9a-f]+:[ 	]+0ef5d50b[ 	]+th.sbib[ 	]+a0,\(a1\),15,3
+[ 	]+[0-9a-f]+:[ 	]+60c5c50b[ 	]+th.lrd[ 	]+a0,a1,a2,0
+[ 	]+[0-9a-f]+:[ 	]+42c5c50b[ 	]+th.lrw[ 	]+a0,a1,a2,1
+[ 	]+[0-9a-f]+:[ 	]+c4c5c50b[ 	]+th.lrwu[ 	]+a0,a1,a2,2
+[ 	]+[0-9a-f]+:[ 	]+26c5c50b[ 	]+th.lrh[ 	]+a0,a1,a2,3
+[ 	]+[0-9a-f]+:[ 	]+a0c5c50b[ 	]+th.lrhu[ 	]+a0,a1,a2,0
+[ 	]+[0-9a-f]+:[ 	]+02c5c50b[ 	]+th.lrb[ 	]+a0,a1,a2,1
+[ 	]+[0-9a-f]+:[ 	]+84c5c50b[ 	]+th.lrbu[ 	]+a0,a1,a2,2
+[ 	]+[0-9a-f]+:[ 	]+66c5d50b[ 	]+th.srd[ 	]+a0,a1,a2,3
+[ 	]+[0-9a-f]+:[ 	]+40c5d50b[ 	]+th.srw[ 	]+a0,a1,a2,0
+[ 	]+[0-9a-f]+:[ 	]+22c5d50b[ 	]+th.srh[ 	]+a0,a1,a2,1
+[ 	]+[0-9a-f]+:[ 	]+04c5d50b[ 	]+th.srb[ 	]+a0,a1,a2,2
+[ 	]+[0-9a-f]+:[ 	]+70c5c50b[ 	]+th.lurd[ 	]+a0,a1,a2,0
+[ 	]+[0-9a-f]+:[ 	]+52c5c50b[ 	]+th.lurw[ 	]+a0,a1,a2,1
+[ 	]+[0-9a-f]+:[ 	]+d4c5c50b[ 	]+th.lurwu[ 	]+a0,a1,a2,2
+[ 	]+[0-9a-f]+:[ 	]+36c5c50b[ 	]+th.lurh[ 	]+a0,a1,a2,3
+[ 	]+[0-9a-f]+:[ 	]+b0c5c50b[ 	]+th.lurhu[ 	]+a0,a1,a2,0
+[ 	]+[0-9a-f]+:[ 	]+12c5c50b[ 	]+th.lurb[ 	]+a0,a1,a2,1
+[ 	]+[0-9a-f]+:[ 	]+94c5c50b[ 	]+th.lurbu[ 	]+a0,a1,a2,2
+[ 	]+[0-9a-f]+:[ 	]+76c5d50b[ 	]+th.surd[ 	]+a0,a1,a2,3
+[ 	]+[0-9a-f]+:[ 	]+50c5d50b[ 	]+th.surw[ 	]+a0,a1,a2,0
+[ 	]+[0-9a-f]+:[ 	]+32c5d50b[ 	]+th.surh[ 	]+a0,a1,a2,1
+[ 	]+[0-9a-f]+:[ 	]+14c5d50b[ 	]+th.surb[ 	]+a0,a1,a2,2
diff --git a/gas/testsuite/gas/riscv/x-thead-memidx.s b/gas/testsuite/gas/riscv/x-thead-memidx.s
new file mode 100644
index 00000000000..ef3907cf9af
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-memidx.s
@@ -0,0 +1,48 @@
+target:
+	th.ldia		a0, (a1), 0, 0
+	th.ldib		a0, (a1), 15, 1
+	th.lwia		a0, (a1), 0, 2
+	th.lwib		a0, (a1), -16, 3
+	th.lwuia	a0, (a1), 0, 0
+	th.lwuib	a0, (a1), 15, 1
+	th.lhia		a0, (a1), 0, 2
+	th.lhib		a0, (a1), -16, 3
+	th.lhuia	a0, (a1), 0, 0
+	th.lhuib	a0, (a1), 15, 1
+	th.lbia		a0, (a1), 0, 2
+	th.lbib		a0, (a1), -16, 3
+	th.lbuia	a0, (a1), 0, 0
+	th.lbuib	a0, (a1), 15, 1
+
+	th.sdia		a0, (a1), -16, 0
+	th.sdib		a0, (a1), -1, 1
+	th.swia		a0, (a1), 0, 2
+	th.swib		a0, (a1), 1, 3
+	th.shia		a0, (a1), 4, 0
+	th.shib		a0, (a1), 13, 1
+	th.sbia		a0, (a1), 14, 2
+	th.sbib		a0, (a1), 15, 3
+
+	th.lrd		a0, a1, a2, 0
+	th.lrw		a0, a1, a2, 1
+	th.lrwu		a0, a1, a2, 2
+	th.lrh		a0, a1, a2, 3
+	th.lrhu		a0, a1, a2, 0
+	th.lrb		a0, a1, a2, 1
+	th.lrbu		a0, a1, a2, 2
+	th.srd		a0, a1, a2, 3
+	th.srw		a0, a1, a2, 0
+	th.srh		a0, a1, a2, 1
+	th.srb		a0, a1, a2, 2
+
+	th.lurd		a0, a1, a2, 0
+	th.lurw		a0, a1, a2, 1
+	th.lurwu	a0, a1, a2, 2
+	th.lurh		a0, a1, a2, 3
+	th.lurhu	a0, a1, a2, 0
+	th.lurb		a0, a1, a2, 1
+	th.lurbu	a0, a1, a2, 2
+	th.surd		a0, a1, a2, 3
+	th.surw		a0, a1, a2, 0
+	th.surh		a0, a1, a2, 1
+	th.surb		a0, a1, a2, 2
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index ecba9f51c84..ab87be248f4 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2216,6 +2216,95 @@
 #define MASK_TH_MULSH 0xfe00707f
 #define MATCH_TH_MULSW 0x2600100b
 #define MASK_TH_MULSW 0xfe00707f
+/* Vendor-specific (T-Head) XTheadMemIdx instructions. */
+#define MATCH_TH_LDIA 0x7800400b
+#define MASK_TH_LDIA 0xf800707f
+#define MATCH_TH_LDIB 0x6800400b
+#define MASK_TH_LDIB 0xf800707f
+#define MATCH_TH_LWIA 0x5800400b
+#define MASK_TH_LWIA 0xf800707f
+#define MATCH_TH_LWIB 0x4800400b
+#define MASK_TH_LWIB 0xf800707f
+#define MATCH_TH_LWUIA 0xd800400b
+#define MASK_TH_LWUIA 0xf800707f
+#define MATCH_TH_LWUIB 0xc800400b
+#define MASK_TH_LWUIB 0xf800707f
+#define MATCH_TH_LHIA 0x3800400b
+#define MASK_TH_LHIA 0xf800707f
+#define MATCH_TH_LHIB 0x2800400b
+#define MASK_TH_LHIB 0xf800707f
+#define MATCH_TH_LHUIA 0xb800400b
+#define MASK_TH_LHUIA 0xf800707f
+#define MATCH_TH_LHUIB 0xa800400b
+#define MASK_TH_LHUIB 0xf800707f
+#define MATCH_TH_LBIA 0x1800400b
+#define MASK_TH_LBIA 0xf800707f
+#define MATCH_TH_LBIB 0x0800400b
+#define MASK_TH_LBIB 0xf800707f
+#define MATCH_TH_LBUIA 0x9800400b
+#define MASK_TH_LBUIA 0xf800707f
+#define MATCH_TH_LBUIB 0x8800400b
+#define MASK_TH_LBUIB 0xf800707f
+#define MATCH_TH_SDIA 0x7800500b
+#define MASK_TH_SDIA 0xf800707f
+#define MATCH_TH_SDIB 0x6800500b
+#define MASK_TH_SDIB 0xf800707f
+#define MATCH_TH_SWIA 0x5800500b
+#define MASK_TH_SWIA 0xf800707f
+#define MATCH_TH_SWIB 0x4800500b
+#define MASK_TH_SWIB 0xf800707f
+#define MATCH_TH_SHIA 0x3800500b
+#define MASK_TH_SHIA 0xf800707f
+#define MATCH_TH_SHIB 0x2800500b
+#define MASK_TH_SHIB 0xf800707f
+#define MATCH_TH_SBIA 0x1800500b
+#define MASK_TH_SBIA 0xf800707f
+#define MATCH_TH_SBIB 0x0800500b
+#define MASK_TH_SBIB 0xf800707f
+#define MATCH_TH_LRD 0x6000400b
+#define MASK_TH_LRD 0xf800707f
+#define MATCH_TH_LRW 0x4000400b
+#define MASK_TH_LRW 0xf800707f
+#define MATCH_TH_LRWU 0xc000400b
+#define MASK_TH_LRWU 0xf800707f
+#define MATCH_TH_LRH 0x2000400b
+#define MASK_TH_LRH 0xf800707f
+#define MATCH_TH_LRHU 0xa000400b
+#define MASK_TH_LRHU 0xf800707f
+#define MATCH_TH_LRB 0x0000400b
+#define MASK_TH_LRB 0xf800707f
+#define MATCH_TH_LRBU 0x8000400b
+#define MASK_TH_LRBU 0xf800707f
+#define MATCH_TH_SRD 0x6000500b
+#define MASK_TH_SRD 0xf800707f
+#define MATCH_TH_SRW 0x4000500b
+#define MASK_TH_SRW 0xf800707f
+#define MATCH_TH_SRH 0x2000500b
+#define MASK_TH_SRH 0xf800707f
+#define MATCH_TH_SRB 0x0000500b
+#define MASK_TH_SRB 0xf800707f
+#define MATCH_TH_LURD 0x7000400b
+#define MASK_TH_LURD 0xf800707f
+#define MATCH_TH_LURW 0x5000400b
+#define MASK_TH_LURW 0xf800707f
+#define MATCH_TH_LURWU 0xd000400b
+#define MASK_TH_LURWU 0xf800707f
+#define MATCH_TH_LURH 0x3000400b
+#define MASK_TH_LURH 0xf800707f
+#define MATCH_TH_LURHU 0xb000400b
+#define MASK_TH_LURHU 0xf800707f
+#define MATCH_TH_LURB 0x1000400b
+#define MASK_TH_LURB 0xf800707f
+#define MATCH_TH_LURBU 0x9000400b
+#define MASK_TH_LURBU 0xf800707f
+#define MATCH_TH_SURD 0x7000500b
+#define MASK_TH_SURD 0xf800707f
+#define MATCH_TH_SURW 0x5000500b
+#define MASK_TH_SURW 0xf800707f
+#define MATCH_TH_SURH 0x3000500b
+#define MASK_TH_SURH 0xf800707f
+#define MATCH_TH_SURB 0x1000500b
+#define MASK_TH_SURB 0xf800707f
 /* Vendor-specific (T-Head) XTheadSync instructions.  */
 #define MATCH_TH_SFENCE_VMAS 0x0400000b
 #define MASK_TH_SFENCE_VMAS 0xfe007fff
@@ -3021,6 +3110,51 @@ DECLARE_INSN(th_mulaw, MATCH_TH_MULAW, MASK_TH_MULAW)
 DECLARE_INSN(th_muls, MATCH_TH_MULS, MASK_TH_MULS)
 DECLARE_INSN(th_mulsh, MATCH_TH_MULSH, MASK_TH_MULSH)
 DECLARE_INSN(th_mulsw, MATCH_TH_MULSW, MASK_TH_MULSW)
+/* Vendor-specific (T-Head) XTheadMemIdx instructions. */
+DECLARE_INSN(th_ldia, MATCH_TH_LDIA, MASK_TH_LDIA)
+DECLARE_INSN(th_ldib, MATCH_TH_LDIB, MASK_TH_LDIB)
+DECLARE_INSN(th_lwia, MATCH_TH_LWIA, MASK_TH_LWIA)
+DECLARE_INSN(th_lwib, MATCH_TH_LWIB, MASK_TH_LWIB)
+DECLARE_INSN(th_lwuia, MATCH_TH_LWUIA, MASK_TH_LWUIA)
+DECLARE_INSN(th_lwuib, MATCH_TH_LWUIB, MASK_TH_LWUIB)
+DECLARE_INSN(th_lhia, MATCH_TH_LHIA, MASK_TH_LHIA)
+DECLARE_INSN(th_lhib, MATCH_TH_LHIB, MASK_TH_LHIB)
+DECLARE_INSN(th_lhuia, MATCH_TH_LHUIA, MASK_TH_LHUIA)
+DECLARE_INSN(th_lhuib, MATCH_TH_LHUIB, MASK_TH_LHUIB)
+DECLARE_INSN(th_lbia, MATCH_TH_LBIA, MASK_TH_LBIA)
+DECLARE_INSN(th_lbib, MATCH_TH_LBIB, MASK_TH_LBIB)
+DECLARE_INSN(th_lbuia, MATCH_TH_LBUIA, MASK_TH_LBUIA)
+DECLARE_INSN(th_lbuib, MATCH_TH_LBUIB, MASK_TH_LBUIB)
+DECLARE_INSN(th_sdia, MATCH_TH_SDIA, MASK_TH_SDIA)
+DECLARE_INSN(th_sdib, MATCH_TH_SDIB, MASK_TH_SDIB)
+DECLARE_INSN(th_swia, MATCH_TH_SWIA, MASK_TH_SWIA)
+DECLARE_INSN(th_swib, MATCH_TH_SWIB, MASK_TH_SWIB)
+DECLARE_INSN(th_shia, MATCH_TH_SHIA, MASK_TH_SHIA)
+DECLARE_INSN(th_shib, MATCH_TH_SHIB, MASK_TH_SHIB)
+DECLARE_INSN(th_sbia, MATCH_TH_SBIA, MASK_TH_SBIA)
+DECLARE_INSN(th_sbib, MATCH_TH_SBIB, MASK_TH_SBIB)
+DECLARE_INSN(th_lrd, MATCH_TH_LRD, MASK_TH_LRD)
+DECLARE_INSN(th_lrw, MATCH_TH_LRW, MASK_TH_LRW)
+DECLARE_INSN(th_lrwu, MATCH_TH_LRWU, MASK_TH_LRWU)
+DECLARE_INSN(th_lrh, MATCH_TH_LRH, MASK_TH_LRH)
+DECLARE_INSN(th_lrhu, MATCH_TH_LRHU, MASK_TH_LRHU)
+DECLARE_INSN(th_lrb, MATCH_TH_LRB, MASK_TH_LRB)
+DECLARE_INSN(th_lrbu, MATCH_TH_LRBU, MASK_TH_LRBU)
+DECLARE_INSN(th_srd, MATCH_TH_SRD, MASK_TH_SRD)
+DECLARE_INSN(th_srw, MATCH_TH_SRW, MASK_TH_SRW)
+DECLARE_INSN(th_srh, MATCH_TH_SRH, MASK_TH_SRH)
+DECLARE_INSN(th_srb, MATCH_TH_SRB, MASK_TH_SRB)
+DECLARE_INSN(th_lurd, MATCH_TH_LURD, MASK_TH_LURD)
+DECLARE_INSN(th_lurw, MATCH_TH_LURW, MASK_TH_LURW)
+DECLARE_INSN(th_lurwu, MATCH_TH_LURWU, MASK_TH_LURWU)
+DECLARE_INSN(th_lurh, MATCH_TH_LURH, MASK_TH_LURH)
+DECLARE_INSN(th_lurhu, MATCH_TH_LURHU, MASK_TH_LURHU)
+DECLARE_INSN(th_lurb, MATCH_TH_LURB, MASK_TH_LURB)
+DECLARE_INSN(th_lurbu, MATCH_TH_LURBU, MASK_TH_LURBU)
+DECLARE_INSN(th_surd, MATCH_TH_SURD, MASK_TH_SURD)
+DECLARE_INSN(th_surw, MATCH_TH_SURW, MASK_TH_SURW)
+DECLARE_INSN(th_surh, MATCH_TH_SURH, MASK_TH_SURH)
+DECLARE_INSN(th_surb, MATCH_TH_SURB, MASK_TH_SURB)
 /* Vendor-specific (T-Head) XTheadSync instructions.  */
 DECLARE_INSN(th_sfence_vmas, MATCH_TH_SFENCE_VMAS, MASK_TH_SFENCE_VMAS)
 DECLARE_INSN(th_sync, MATCH_TH_SYNC, MASK_TH_SYNC)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 1b7de3cb142..2546d6ce8d5 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -422,6 +422,7 @@ enum riscv_insn_class
   INSN_CLASS_XTHEADCONDMOV,
   INSN_CLASS_XTHEADFMEMIDX,
   INSN_CLASS_XTHEADMAC,
+  INSN_CLASS_XTHEADMEMIDX,
   INSN_CLASS_XTHEADSYNC,
 };
 
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 6c1c4c9a1ad..5aed98c1003 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -266,6 +266,18 @@ match_vd_eq_vs1_eq_vs2 (const struct riscv_opcode *op,
   return match_opcode (op, insn) && vd == vs1 && vs1 == vs2;
 }
 
+static int
+match_th_load_inc(const struct riscv_opcode *op,
+		  insn_t insn)
+{
+  /* Load-increment has the following restriction:
+   * The values of rd and rs1 must not be the same.  */
+  int rd = (insn & MASK_RD) >> OP_SH_RD;
+  int rs1 = (insn & MASK_RS1) >> OP_SH_RS1;
+
+  return rd != rs1 && match_opcode (op, insn);
+}
+
 const struct riscv_opcode riscv_opcodes[] =
 {
 /* name, xlen, isa, operands, match, mask, match_func, pinfo.  */
@@ -1881,6 +1893,54 @@ const struct riscv_opcode riscv_opcodes[] =
 {"th.fsurd",   0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSURD, MASK_TH_FSURD, match_opcode, 0},
 {"th.fsurw",   0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0},
 
+/* Vendor-specific (T-Head) XTheadMemIdx instructions.  */
+{"th.ldia",  64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LDIA,  MASK_TH_LDIA,  match_th_load_inc, 0},
+{"th.ldib",  64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LDIB,  MASK_TH_LDIB,  match_th_load_inc, 0},
+{"th.lwia",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LWIA,  MASK_TH_LWIA,  match_th_load_inc, 0},
+{"th.lwib",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LWIB,  MASK_TH_LWIB,  match_th_load_inc, 0},
+{"th.lwuia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LWUIA, MASK_TH_LWUIA, match_th_load_inc, 0},
+{"th.lwuib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LWUIB, MASK_TH_LWUIB, match_th_load_inc, 0},
+{"th.lhia",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LHIA,  MASK_TH_LHIA,  match_th_load_inc, 0},
+{"th.lhib",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LHIB,  MASK_TH_LHIB,  match_th_load_inc, 0},
+{"th.lhuia",  0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LHUIA, MASK_TH_LHUIA, match_th_load_inc, 0},
+{"th.lhuib",  0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LHUIB, MASK_TH_LHUIB, match_th_load_inc, 0},
+{"th.lbia",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LBIA,  MASK_TH_LBIA,  match_th_load_inc, 0},
+{"th.lbib",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LBIB,  MASK_TH_LBIB,  match_th_load_inc, 0},
+{"th.lbuia",  0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LBUIA, MASK_TH_LBUIA, match_th_load_inc, 0},
+{"th.lbuib",  0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LBUIB, MASK_TH_LBUIB, match_th_load_inc, 0},
+{"th.sdia",  64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_SDIA, MASK_TH_SDIA, match_opcode, 0},
+{"th.sdib",  64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_SDIB, MASK_TH_SDIB, match_opcode, 0},
+{"th.swia",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_SWIA, MASK_TH_SWIA, match_opcode, 0},
+{"th.swib",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_SWIB, MASK_TH_SWIB, match_opcode, 0},
+{"th.shia",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_SHIA, MASK_TH_SHIA, match_opcode, 0},
+{"th.shib",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_SHIB, MASK_TH_SHIB, match_opcode, 0},
+{"th.sbia",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_SBIA, MASK_TH_SBIA, match_opcode, 0},
+{"th.sbib",   0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_SBIB, MASK_TH_SBIB, match_opcode, 0},
+
+{"th.lrd",  64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LRD,  MASK_TH_LRD,  match_opcode, 0},
+{"th.lrw",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LRW,  MASK_TH_LRW,  match_opcode, 0},
+{"th.lrwu", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LRWU, MASK_TH_LRWU, match_opcode, 0},
+{"th.lrh",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LRH,  MASK_TH_LRH,  match_opcode, 0},
+{"th.lrhu",  0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LRHU, MASK_TH_LRHU, match_opcode, 0},
+{"th.lrb",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LRB,  MASK_TH_LRB,  match_opcode, 0},
+{"th.lrbu",  0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LRBU, MASK_TH_LRBU, match_opcode, 0},
+{"th.srd",  64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SRD,  MASK_TH_SRD, match_opcode, 0},
+{"th.srw",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SRW,  MASK_TH_SRW, match_opcode, 0},
+{"th.srh",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SRH,  MASK_TH_SRH, match_opcode, 0},
+{"th.srb",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SRB,  MASK_TH_SRB, match_opcode, 0},
+
+{"th.lurd",  64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LURD,  MASK_TH_LURD,  match_opcode, 0},
+{"th.lurw",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LURW,  MASK_TH_LURW,  match_opcode, 0},
+{"th.lurwu", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LURWU, MASK_TH_LURWU, match_opcode, 0},
+{"th.lurh",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LURH,  MASK_TH_LURH,  match_opcode, 0},
+{"th.lurhu",  0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LURHU, MASK_TH_LURHU, match_opcode, 0},
+{"th.lurb",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LURB,  MASK_TH_LURB,  match_opcode, 0},
+{"th.lurbu",  0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_LURBU, MASK_TH_LURBU, match_opcode, 0},
+{"th.surd",  64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SURD,  MASK_TH_SURD, match_opcode, 0},
+{"th.surw",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SURW,  MASK_TH_SURW, match_opcode, 0},
+{"th.surh",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SURH,  MASK_TH_SURH, match_opcode, 0},
+{"th.surb",   0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", MATCH_TH_SURB,  MASK_TH_SURB, match_opcode, 0},
+
 /* Vendor-specific (T-Head) XTheadMac instructions.  */
 {"th.mula",          0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULA,  MASK_TH_MULA,  match_opcode, 0},
 {"th.mulah",         0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULAH, MASK_TH_MULAH, match_opcode, 0},
-- 
2.37.2