From: Christoph Muellner <christoph.muellner@vrull.eu>
To: binutils@sourceware.org, Nelson Chu <nelson@rivosinc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Palmer Dabbelt <palmer@dabbelt.com>,
Cooper Qu <cooper.qu@linux.alibaba.com>,
Lifang Xia <lifang_xia@linux.alibaba.com>,
Yunhai Shang <yunhai@linux.alibaba.com>,
Zhiwei Liu <zhiwei_liu@linux.alibaba.com>
Cc: "Christoph Müllner" <christoph.muellner@vrull.eu>
Subject: [PATCH v2 10/11] RISC-V: Add support for literal instruction arguments
Date: Sun, 18 Sep 2022 09:23:55 +0200 [thread overview]
Message-ID: <20220918072356.2496130-11-christoph.muellner@vrull.eu> (raw)
In-Reply-To: <20220918072356.2496130-1-christoph.muellner@vrull.eu>
From: Christoph Müllner <christoph.muellner@vrull.eu>
This patch introduces support for arbitrary literal instruction
arguments, that are not encoded in the opcode.
A typical use case for this feature would be an instruction that
applies an implicit shift by a constant value on an immediate
(that is a real operand). With this patch it is possible to make
this shift visible in the dissasembly and support such artificial
parameter as part of the asssembly code.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
gas/config/tc-riscv.c | 10 ++++++++++
opcodes/riscv-dis.c | 9 +++++++++
2 files changed, 19 insertions(+)
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 694d079863d..c8bee193730 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1265,6 +1265,9 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
switch (*++oparg)
{
+ case 'l': /* Literal. */
+ oparg += strcspn(oparg, ",") - 1;
+ break;
case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */
goto use_imm;
case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */
@@ -3300,6 +3303,13 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
switch (*++oparg)
{
+ case 'l': /* Literal. */
+ n = strcspn (++oparg, ",");
+ if (strncmp (oparg, asarg, n))
+ as_bad (_("unexpected literal (%s)"), asarg);
+ oparg += n - 1;
+ asarg += n;
+ continue;
case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */
sign = true;
goto parse_imm;
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index c6ddea16dda..bc8588522d5 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -571,6 +571,15 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
switch (*++oparg)
{
+ case 'l': /* Literal. */
+ oparg++;
+ while (*oparg && *oparg != ',')
+ {
+ print (info->stream, dis_style_text, "%c", *oparg);
+ oparg++;
+ }
+ oparg--;
+ break;
case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */
sign = true;
goto print_imm;
--
2.37.2
next prev parent reply other threads:[~2022-09-18 7:24 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-18 7:23 [PATCH v2 00/11] Add support for the T-Head vendor extensions Christoph Muellner
2022-09-18 7:23 ` [PATCH v2 01/11] RISC-V: Add generic support for " Christoph Muellner
2022-09-18 7:23 ` [PATCH v2 02/11] RISC-V: Add T-Head CMO vendor extension Christoph Muellner
2022-09-18 7:23 ` [PATCH v2 03/11] RISC-V: Add T-Head SYNC " Christoph Muellner
2022-09-18 7:23 ` [PATCH v2 04/11] RISC-V: Add support for arbitrary immediate encoding formats Christoph Muellner
2022-09-18 7:23 ` [PATCH v2 05/11] RISC-V: Add T-Head Bitmanip vendor extension Christoph Muellner
2022-09-18 7:23 ` [PATCH v2 06/11] RISC-V: Add T-Head CondMov " Christoph Muellner
2022-09-18 7:23 ` [PATCH v2 07/11] RISC-V: Add T-Head MAC " Christoph Muellner
2022-09-18 7:23 ` [PATCH v2 08/11] RISC-V: Add T-Head FMemIdx " Christoph Muellner
2022-09-18 7:23 ` [PATCH v2 09/11] RISC-V: Add T-Head MemIdx " Christoph Muellner
2022-09-18 7:23 ` Christoph Muellner [this message]
2022-09-18 7:23 ` [PATCH v2 11/11] RISC-V: Add T-Head MemPair " Christoph Muellner
2022-09-22 13:55 ` [PATCH v2 00/11] Add support for the T-Head vendor extensions Nelson Chu
2022-09-22 14:06 ` Christoph Müllner
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