From: "Jiang, Haochen" <haochen.jiang@intel.com>
To: "Beulich, Jan" <JBeulich@suse.com>
Cc: "hjl.tools@gmail.com" <hjl.tools@gmail.com>,
"Hu, Lin1" <lin1.hu@intel.com>,
"binutils@sourceware.org" <binutils@sourceware.org>
Subject: RE: [PATCH 07/10] Support Intel WRMSRNS
Date: Mon, 24 Oct 2022 05:56:06 +0000 [thread overview]
Message-ID: <SA1PR11MB5946086F59BAFA212893E0B9EC2E9@SA1PR11MB5946.namprd11.prod.outlook.com> (raw)
In-Reply-To: <180b7336-c2f5-3c65-fea6-d891c57c9ff8@suse.com>
[-- Attachment #1: Type: text/plain, Size: 4870 bytes --]
> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Monday, October 17, 2022 3:18 PM
> To: Jiang, Haochen <haochen.jiang@intel.com>
> Cc: hjl.tools@gmail.com; Hu, Lin1 <lin1.hu@intel.com>;
> binutils@sourceware.org
> Subject: Re: [PATCH 07/10] Support Intel WRMSRNS
>
> On 14.10.2022 11:12, Haochen Jiang wrote:
> > --- a/gas/config/tc-i386.c
> > +++ b/gas/config/tc-i386.c
> > @@ -1099,6 +1099,7 @@ static const arch_entry cpu_arch[] =
> > SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT,
> false),
> > SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false),
> > SUBARCH (raoint, RAOINT, ANY_RAOINT, false),
> > + SUBARCH (wrmsrns, WRMSRNS, ANY_WRMSRNS, false),
>
> As for some of the earlier patches - no need for ANY_WRMSRNS afaics.
Done.
>
> > --- /dev/null
> > +++ b/gas/testsuite/gas/i386/wrmsrns.s
> > @@ -0,0 +1,9 @@
> > +# Check WRMSRNS instructions
> > +
> > + .allow_index_reg
>
> Nit: Why?
Removed since there is no register usage.
>
> > --- a/gas/testsuite/gas/i386/x86-64-lockbad-1.l
> > +++ b/gas/testsuite/gas/i386/x86-64-lockbad-1.l
> > @@ -36,9 +36,9 @@
> > .*:41: Error: .*
> > .*:42: Error: .*
> > .*:43: Error: .*
> > -.*:46: Error: .*
> > +.*:44: Error: .*
> > .*:47: Error: .*
> > -.*:49: Error: .*
> > +.*:48: Error: .*
> > .*:50: Error: .*
> > .*:51: Error: .*
> > .*:52: Error: .*
> > @@ -66,13 +66,15 @@
> > .*:74: Error: .*
> > .*:75: Error: .*
> > .*:76: Error: .*
> > -.*:78: Error: .*
> > +.*:77: Error: .*
> > .*:79: Error: .*
> > .*:80: Error: .*
> > .*:81: Error: .*
> > .*:82: Error: .*
> > .*:83: Error: .*
> > .*:84: Error: .*
> > +.*:85: Error: .*
> > +.*:86: Error: .*
> > GAS LISTING .*
>
> While for the diagnostics line numbers matter, ...
>
> > @@ -119,47 +121,49 @@ GAS LISTING .*
> > [ ]*41[ ]+lock sbb \(%rbx\), %eax
> > [ ]*42[ ]+lock sub \(%rbx\), %eax
> > [ ]*43[ ]+lock xor \(%rbx\), %eax
> > -[ ]*44[ ]+
> > -[ ]*45[ ]+\.intel_syntax noprefix
> > -[ ]*46[ ]+lock mov eax,ebx
> > -[ ]*47[ ]+lock mov eax,DWORD PTR \[rbx\]
> > -[ ]*48[ ]+
> > -[ ]*49[ ]+lock add eax,ebx
> > -[ ]*50[ ]+lock add ebx,0x64
> > -[ ]*51[ ]+lock adc eax,ebx
> > -[ ]*52[ ]+lock adc ebx,0x64
> > -[ ]*53[ ]+lock and eax,ebx
> > -[ ]*54[ ]+lock and ebx,0x64
> > -[ ]*55[ ]+lock btc ebx,eax
> > -[ ]*56[ ]+lock btc ebx,0x64
> > -[ ]*57[ ]+lock btr ebx,eax
> > +[ ]*44[ ]+lock wrmsrns
> > +[ ]*45[ ]+
> > +[ ]*46[ ]+\.intel_syntax noprefix
> > +[ ]*47[ ]+lock mov eax,ebx
> > +[ ]*48[ ]+lock mov eax,DWORD PTR \[rbx\]
> > +[ ]*49[ ]+
> > +[ ]*50[ ]+lock add eax,ebx
> > +[ ]*51[ ]+lock add ebx,0x64
> > +[ ]*52[ ]+lock adc eax,ebx
> > +[ ]*53[ ]+lock adc ebx,0x64
> > +[ ]*54[ ]+lock and eax,ebx
> > +[ ]*55[ ]+lock and ebx,0x64
> > +[ ]*56[ ]+lock btc ebx,eax
> > +[ ]*57[ ]+lock btc ebx,0x64
> >
>
> GAS LISTING .*
>
> .. please abstract away line numbers (see many other testcases) rather than
> updating them here.
>
> > --- a/gas/testsuite/gas/i386/x86-64-lockbad-1.s
> > +++ b/gas/testsuite/gas/i386/x86-64-lockbad-1.s
> > @@ -41,6 +41,7 @@ foo:
> > lock sbb (%rbx), %eax
> > lock sub (%rbx), %eax
> > lock xor (%rbx), %eax
> > + lock wrmsrns
>
> I wonder whether this is really necessary. If you limited yourself to ...
>
> > .intel_syntax noprefix
> > lock mov eax,ebx
> > @@ -82,3 +83,4 @@ foo:
> > lock sbb eax,DWORD PTR [rbx]
> > lock sub eax,DWORD PTR [rbx]
> > lock xor eax,DWORD PTR [rbx]
> > + lock wrmsrns
>
> ... this addition (which already seems excessive, as we don't test the majority of
> insns here anyway), the overall diff to the testcase would end up much smaller.
We removed the lockbad testcases here since most of insts are lockbad.
>
> > --- /dev/null
> > +++ b/gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d
> > @@ -0,0 +1,12 @@
> > +#as:
> > +#objdump: -dw -Mintel
> > +#name: x86_64 WRMSRNS insns (Intel disassembly)
> > +#source: wrmsrns.s
>
> It's not just the source which can be shared here, but also the output
> expectations.
I get your point. But how to share here?
>
> > --- a/opcodes/i386-opc.tbl
> > +++ b/opcodes/i386-opc.tbl
> > @@ -3326,3 +3326,9 @@ aor, 0xf20f38fc, None, CpuRAOINT,
> > Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ld
> > axor, 0xf30f38fc, None, CpuRAOINT,
> > Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64,
> > Dword|Qword|Unspecified|BaseIndex}
> >
> > // RAOINT instructions end.
> > +
> > +// WRMSRNS instructions.
> > +
> > +wrmsrns, 0x0f01c6, None, CpuWRMSRNS,
> > +No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
> > +
> > +// WRMSRNS instructions end.
>
> Nit: Use singular in the comments?
Done.
Haochen
>
> Jan
[-- Attachment #2: 0007-Support-Intel-WRMSRNS.patch --]
[-- Type: application/octet-stream, Size: 10076 bytes --]
From 885c7826dc33de8655ca14b677b2923dcfdaaeb4 Mon Sep 17 00:00:00 2001
From: "Hu, Lin1" <lin1.hu@intel.com>
Date: Fri, 29 Jul 2022 14:28:18 +0800
Subject: [PATCH 7/8] Support Intel WRMSRNS
gas/ChangeLog:
* NEWS: Support Intel WRMSRNS.
* config/tc-i386.c: Add wrmsrns.
* doc/c-i386.texi: Document .wrmsrns.
* testsuite/gas/i386/i386.exp: Add WRMSRNS tests.
* testsuite/gas/i386/wrmsrns-intel.d: New test.
* testsuite/gas/i386/wrmsrns.d: Ditto.
* testsuite/gas/i386/wrmsrns.s: Ditto.
* testsuite/gas/i386/x86-64-wrmsrns-intel.d: Ditto.
* testsuite/gas/i386/x86-64-wrmsrns.d: Ditto.
opcodes/ChangeLog:
* i386-dis.c (PREFIX_0F01_REG_0_MOD_3_RM_6): New.
(prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_6.
(rm_table): New entry for wrmsrns.
* i386-gen.c (cpu_flag_init): Add CPU_WRMSRNS_FLAGS
and CPU_ANY_WRMSRNS_FLAGS.
(cpu_flags): Add CpuWRMSRNS.
* i386-init.h: Regenerated.
* i386-opc.h (CpuWRMSRNS): New.
(i386_cpu_flags): Add cpuwrmsrns.
* i386-opc.tbl: Add WRMSRNS instructions.
* i386-tbl.h: Regenerated.
---
gas/NEWS | 2 +
gas/config/tc-i386.c | 1 +
gas/doc/c-i386.texi | 3 +-
gas/testsuite/gas/i386/i386.exp | 4 +
gas/testsuite/gas/i386/wrmsrns-intel.d | 12 +
gas/testsuite/gas/i386/wrmsrns.d | 12 +
gas/testsuite/gas/i386/wrmsrns.s | 8 +
gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d | 12 +
gas/testsuite/gas/i386/x86-64-wrmsrns.d | 12 +
opcodes/i386-dis.c | 7 +
opcodes/i386-gen.c | 5 +
opcodes/i386-init.h | 514 +-
opcodes/i386-opc.h | 3 +
opcodes/i386-opc.tbl | 6 +
opcodes/i386-tbl.h | 7859 +++++++++--------
15 files changed, 4288 insertions(+), 4172 deletions(-)
create mode 100644 gas/testsuite/gas/i386/wrmsrns-intel.d
create mode 100644 gas/testsuite/gas/i386/wrmsrns.d
create mode 100644 gas/testsuite/gas/i386/wrmsrns.s
create mode 100644 gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-wrmsrns.d
diff --git a/gas/NEWS b/gas/NEWS
index f352c5ab89..2d745dfc31 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for Intel WRMSRNS instructions.
+
* Add support for Intel RAO-INT instructions.
* Add support for Intel CMPccXADD instructions.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 985b64b6e1..3a4790d107 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1099,6 +1099,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false),
SUBARCH (cmpccxadd, CMPCCXADD, CMPCCXADD, false),
SUBARCH (rao_int, RAO_INT, RAO_INT, false),
+ SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false),
};
#undef SUBARCH
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 82267389f2..019401e8ab 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -199,6 +199,7 @@ accept various extension mnemonics. For example,
@code{avx_ne_convert},
@code{cmpccxadd},
@code{rao_int},
+@code{wrmsrns},
@code{amx_int8},
@code{amx_bf16},
@code{amx_tile},
@@ -1492,7 +1493,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16}
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
@item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert}
-@item @samp{.cmpccxadd} @tab @samp{.rao_int}
+@item @samp{.cmpccxadd} @tab @samp{.rao_int} @tab @samp{.wrmsrns}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 1eb0eabb6b..c924075180 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -488,6 +488,8 @@ if [gas_32_check] then {
run_list_test "cmpccxadd-inval"
run_dump_test "raoint"
run_dump_test "raoint-intel"
+ run_dump_test "wrmsrns"
+ run_dump_test "wrmsrns-intel"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "invlpgb"
@@ -1166,6 +1168,8 @@ if [gas_64_check] then {
run_dump_test "x86-64-cmpccxadd-intel"
run_dump_test "x86-64-raoint"
run_dump_test "x86-64-raoint-intel"
+ run_dump_test "x86-64-wrmsrns"
+ run_dump_test "x86-64-wrmsrns-intel"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/wrmsrns-intel.d b/gas/testsuite/gas/i386/wrmsrns-intel.d
new file mode 100644
index 0000000000..83194511a5
--- /dev/null
+++ b/gas/testsuite/gas/i386/wrmsrns-intel.d
@@ -0,0 +1,12 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 WRMSRNS insns (Intel disassembly)
+#source: wrmsrns.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
+\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
diff --git a/gas/testsuite/gas/i386/wrmsrns.d b/gas/testsuite/gas/i386/wrmsrns.d
new file mode 100644
index 0000000000..e804adc501
--- /dev/null
+++ b/gas/testsuite/gas/i386/wrmsrns.d
@@ -0,0 +1,12 @@
+#as:
+#objdump: -dw
+#name: i386 WRMSRNS insns
+#source: wrmsrns.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
+\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
diff --git a/gas/testsuite/gas/i386/wrmsrns.s b/gas/testsuite/gas/i386/wrmsrns.s
new file mode 100644
index 0000000000..a450b0536d
--- /dev/null
+++ b/gas/testsuite/gas/i386/wrmsrns.s
@@ -0,0 +1,8 @@
+# Check WRMSRNS instructions
+
+ .text
+_start:
+ wrmsrns #WRMSRNS
+
+.intel_syntax noprefix
+ wrmsrns #WRMSRNS
diff --git a/gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d b/gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d
new file mode 100644
index 0000000000..2f789ed5df
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d
@@ -0,0 +1,12 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 WRMSRNS insns (Intel disassembly)
+#source: wrmsrns.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
+\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
diff --git a/gas/testsuite/gas/i386/x86-64-wrmsrns.d b/gas/testsuite/gas/i386/x86-64-wrmsrns.d
new file mode 100644
index 0000000000..b8535c266a
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-wrmsrns.d
@@ -0,0 +1,12 @@
+#as:
+#objdump: -dw
+#name: x86_64 WRMSRNS insns
+#source: wrmsrns.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
+\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index dba5369e32..3a60837281 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -983,6 +983,7 @@ enum
enum
{
PREFIX_90 = 0,
+ PREFIX_0F01_REG_0_MOD_3_RM_6,
PREFIX_0F01_REG_1_RM_4,
PREFIX_0F01_REG_1_RM_5,
PREFIX_0F01_REG_1_RM_6,
@@ -2953,6 +2954,11 @@ static const struct dis386 prefix_table[][4] = {
{ NULL, { { NULL, 0 } }, PREFIX_IGNORED }
},
+ /* PREFIX_0F01_REG_0_MOD_3_RM_6 */
+ {
+ { "wrmsrns", { Skip_MODRM }, 0 },
+ },
+
/* PREFIX_0F01_REG_1_RM_4 */
{
{ Bad_Opcode },
@@ -8645,6 +8651,7 @@ static const struct dis386 rm_table[][8] = {
{ "vmresume", { Skip_MODRM }, 0 },
{ "vmxoff", { Skip_MODRM }, 0 },
{ "pconfig", { Skip_MODRM }, 0 },
+ { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) },
},
{
/* RM_0F01_REG_1 */
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 68269bf909..5428278d7e 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -255,6 +255,8 @@ static initializer cpu_flag_init[] =
"CpuCMPCCXADD" },
{ "CPU_RAO_INT_FLAGS",
"CpuRAO_INT" },
+ { "CPU_WRMSRNS_FLAGS",
+ "CpuWRMSRNS" },
{ "CPU_IAMCU_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
{ "CPU_ADX_FLAGS",
@@ -459,6 +461,8 @@ static initializer cpu_flag_init[] =
"CpuCMPCCXADD" },
{ "CPU_ANY_RAO_INT_FLAGS",
"CpuRAO_INT" },
+ { "CPU_ANY_WRMSRNS_FLAGS",
+ "CpuWRMSRNS" },
};
static initializer operand_type_init[] =
@@ -665,6 +669,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuAVX_NE_CONVERT),
BITFIELD (CpuCMPCCXADD),
BITFIELD (CpuRAO_INT),
+ BITFIELD (CpuWRMSRNS),
BITFIELD (CpuMWAITX),
BITFIELD (CpuCLZERO),
BITFIELD (CpuOSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 53475465b6..39229b3be6 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -219,6 +219,8 @@ enum
CpuCMPCCXADD,
/* Intel RAO INT Instructions support required. */
CpuRAO_INT,
+ /* Intel WRMSRNS Instructions support required */
+ CpuWRMSRNS,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@@ -403,6 +405,7 @@ typedef union i386_cpu_flags
unsigned int cpuavx_ne_convert:1;
unsigned int cpucmpccxadd:1;
unsigned int cpurao_int:1;
+ unsigned int cpuwrmsrns:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index b1727afb46..d142670037 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3307,3 +3307,9 @@ aor, 0xf20f38fc, None, CpuRAO_INT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_s
axor, 0xf30f38fc, None, CpuRAO_INT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
// RAO-INT instructions end.
+
+// WRMSRNS instruction.
+
+wrmsrns, 0x0f01c6, None, CpuWRMSRNS, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
+
+// WRMSRNS instruction end.
--
2.18.1
next prev parent reply other threads:[~2022-10-24 5:56 UTC|newest]
Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-14 9:12 [PATCH 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions Haochen Jiang
2022-10-14 9:12 ` [PATCH 01/10] Support Intel AVX-IFMA Haochen Jiang
2022-10-14 9:52 ` Jan Beulich
2022-10-14 18:10 ` H.J. Lu
2022-10-16 6:39 ` Jan Beulich
2022-10-17 22:23 ` H.J. Lu
2022-10-18 5:33 ` Jan Beulich
2022-10-18 21:28 ` H.J. Lu
2022-10-19 6:01 ` Jan Beulich
2022-10-19 21:27 ` H.J. Lu
2022-10-20 6:15 ` Jan Beulich
2022-10-24 2:07 ` Jiang, Haochen
2022-10-24 5:53 ` Jiang, Haochen
2022-10-24 19:09 ` H.J. Lu
2022-10-25 6:29 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 02/10] Support Intel AVX-VNNI-INT8 Haochen Jiang
2022-10-14 10:57 ` Jan Beulich
2022-10-21 3:22 ` Jiang, Haochen
2022-10-25 1:52 ` H.J. Lu
2022-10-14 9:12 ` [PATCH 03/10] Support Intel AVX-NE-CONVERT Haochen Jiang
2022-10-14 12:58 ` Jan Beulich
2022-10-24 5:37 ` Kong, Lingling
2022-10-24 5:59 ` Kong, Lingling
2022-10-24 19:25 ` H.J. Lu
2022-10-25 6:44 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 04/10] Support Intel CMPccXADD Haochen Jiang
2022-10-14 13:46 ` Jan Beulich
2022-10-14 18:27 ` H.J. Lu
2022-10-14 21:51 ` H.J. Lu
2022-10-16 6:34 ` Jan Beulich
2022-10-17 23:31 ` H.J. Lu
2022-10-16 6:25 ` Jan Beulich
2022-10-17 23:44 ` H.J. Lu
2022-10-16 6:19 ` Jan Beulich
2022-10-24 2:30 ` Jiang, Haochen
2022-10-24 19:12 ` H.J. Lu
2022-10-24 5:55 ` Jiang, Haochen
2022-10-25 6:53 ` Jan Beulich
2022-10-26 3:03 ` Jiang, Haochen
2022-10-26 8:49 ` Jan Beulich
2022-10-27 3:09 ` Jiang, Haochen
2022-10-27 6:37 ` Jan Beulich
2022-10-28 0:59 ` Jiang, Haochen
2022-10-14 9:12 ` [PATCH 05/10] Add handler for more i386_cpu_flags Haochen Jiang
2022-10-14 13:53 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 06/10] Support Intel RAO-INT Haochen Jiang
2022-10-14 14:38 ` Jan Beulich
2022-10-16 6:15 ` Jan Beulich
2022-10-24 3:12 ` Jiang, Haochen
2022-10-24 19:17 ` H.J. Lu
2022-10-24 5:56 ` Jiang, Haochen
2022-10-25 7:01 ` Jan Beulich
2022-10-26 5:16 ` Jiang, Haochen
2022-10-26 8:56 ` Jan Beulich
2022-10-27 3:50 ` Jiang, Haochen
2022-10-27 6:39 ` Jan Beulich
2022-10-27 18:46 ` H.J. Lu
2022-10-28 6:52 ` Jan Beulich
2022-10-28 8:10 ` Jiang, Haochen
2022-10-28 8:22 ` Jan Beulich
2022-10-28 8:31 ` Jiang, Haochen
2022-10-28 8:40 ` Jan Beulich
2022-10-28 16:08 ` H.J. Lu
2022-10-31 9:41 ` Jan Beulich
2022-10-31 16:49 ` H.J. Lu
2022-11-06 12:50 ` Kong, Lingling
2022-11-07 9:24 ` Jan Beulich
2022-11-07 13:37 ` Kong, Lingling
2022-11-07 20:03 ` H.J. Lu
2022-10-17 23:23 ` H.J. Lu
2022-10-18 5:38 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 07/10] Support Intel WRMSRNS Haochen Jiang
2022-10-17 7:17 ` Jan Beulich
2022-10-24 2:52 ` Jiang, Haochen
2022-10-24 5:56 ` Jiang, Haochen [this message]
2022-10-24 19:14 ` H.J. Lu
2022-10-25 7:04 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 08/10] Support Intel MSRLIST Haochen Jiang
2022-10-17 7:20 ` Jan Beulich
2022-10-24 3:03 ` Jiang, Haochen
2022-10-24 5:56 ` Jiang, Haochen
2022-10-24 19:15 ` H.J. Lu
2022-10-25 7:07 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 09/10] Support Intel AMX-FP16 Haochen Jiang
2022-10-17 7:35 ` Jan Beulich
2022-10-18 9:01 ` Cui, Lili
2022-10-18 9:23 ` Jan Beulich
2022-10-18 9:33 ` Jiang, Haochen
2022-10-19 10:33 ` Cui, Lili
2022-10-19 13:35 ` Jan Beulich
2022-10-19 14:05 ` Cui, Lili
2022-10-19 14:09 ` Jan Beulich
2022-10-19 14:41 ` Cui, Lili
2022-10-19 15:04 ` Jan Beulich
2022-10-19 15:21 ` Cui, Lili
2022-10-19 14:01 ` Jiang, Haochen
2022-10-19 14:13 ` Jan Beulich
2022-10-19 14:58 ` Jiang, Haochen
2022-10-25 6:02 ` Jan Beulich
2022-10-25 13:05 ` Cui, Lili
2022-10-14 9:12 ` [PATCH 10/10] Support Intel PREFETCHI Haochen Jiang
2022-10-17 8:15 ` Jan Beulich
2022-10-25 13:03 ` Cui, Lili
2022-10-25 15:41 ` Jan Beulich
2022-10-25 15:52 ` Jan Beulich
2022-10-25 17:01 ` H.J. Lu
2022-10-26 13:42 ` Cui, Lili
2022-10-26 13:53 ` Jan Beulich
2022-10-27 6:04 ` Cui, Lili
2022-10-27 6:45 ` Jan Beulich
2022-10-27 7:01 ` Cui, Lili
2022-10-27 7:15 ` Jan Beulich
2022-10-27 7:43 ` Cui, Lili
2022-10-28 9:03 ` Cui, Lili
2022-10-28 15:54 ` H.J. Lu
2022-10-31 13:23 ` Cui, Lili
2022-10-31 14:45 ` Mike Frysinger
2022-10-31 16:25 ` H.J. Lu
2022-10-19 14:55 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions Haochen Jiang
2022-10-19 14:56 ` [PATCH 07/10] Support Intel WRMSRNS Haochen Jiang
2022-10-19 15:15 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions (Resend) Haochen Jiang
2022-10-19 15:15 ` [PATCH 07/10] Support Intel WRMSRNS Haochen Jiang
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