From: "Cui, Lili" <lili.cui@intel.com>
To: binutils@sourceware.org
Cc: jbeulich@suse.com, hongjiu.lu@intel.com
Subject: [PATCH 7/8] Support APX NF
Date: Tue, 19 Sep 2023 15:25:26 +0000 [thread overview]
Message-ID: <20230919152527.497773-8-lili.cui@intel.com> (raw)
In-Reply-To: <20230919152527.497773-1-lili.cui@intel.com>
gas/ChangeLog:
* config/tc-i386.c (is_any_apx_encoding): Add has_nf and i.has_zero_upper
for apx encoding.
(build_evex_insns_with_extend_evex_prefix): Encode the NF bit.
(build_legacy_insns_with_apx_encoding): Likewise.
(parse_insn): Handle Prefix_NF.
(check_NfPrefix): New.
(match_template): Handle check_NfPrefix and add nf check for D.
* testsuite/gas/i386/x86-64.exp: Add apx-nf tests.
* testsuite/gas/i386/x86-64-apx-nf-intel.d: New test.
* testsuite/gas/i386/x86-64-apx-nf.d: Likewise.
* testsuite/gas/i386/x86-64-apx_nf.s: Likewise.
opcodes/ChangeLog:
* i386-dis-evex-len.h: Add %XN to the instructions that support APX NF.
* i386-dis-evex-reg.h: Likewise.
* i386-dis-evex.h: Add %XN to the instructions that support APX NF and
add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table.
* i386-dis.c (struct instr_info): Add nf.
(struct dis386): Add "XN" for EVEX.NF.
(print_insn): Use EVEX.a2 bit as appropriate
(putop): Handle "%XN".
* i386-gen.c: Add BITFIELD for NF.
* i386-mnem.h: Regenerated.
* i386-opc.h (Prefix_NoOptimize): Add Prefix_NF.
(Prefix_NF): New.
* i386-opc.tbl: Add new entries for the instructions that support APX NF.
* i386-tbl.h: Regenerated.
---
gas/config/tc-i386.c | 39 +-
gas/testsuite/gas/i386/x86-64-apx-ndd.d | 2 +-
gas/testsuite/gas/i386/x86-64-apx-nf-intel.d | 633 +++++++++
gas/testsuite/gas/i386/x86-64-apx-nf.d | 633 +++++++++
gas/testsuite/gas/i386/x86-64-apx-nf.s | 1256 ++++++++++++++++++
gas/testsuite/gas/i386/x86-64.exp | 2 +
opcodes/i386-dis-evex-len.h | 2 +-
opcodes/i386-dis-evex-reg.h | 133 +-
opcodes/i386-dis-evex.h | 60 +-
opcodes/i386-dis.c | 49 +-
opcodes/i386-gen.c | 1 +
opcodes/i386-opc.h | 9 +-
opcodes/i386-opc.tbl | 192 ++-
13 files changed, 2855 insertions(+), 156 deletions(-)
create mode 100644 gas/testsuite/gas/i386/x86-64-apx-nf-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-apx-nf.d
create mode 100644 gas/testsuite/gas/i386/x86-64-apx-nf.s
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index dd3af5dd2d5..1fe4980f26a 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -3863,7 +3863,7 @@ is_evex_encoding (const insn_template *t)
{
return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift
|| t->opcode_modifier.broadcast || t->opcode_modifier.masking
- || t->opcode_modifier.sae;
+ || t->opcode_modifier.sae || t->opcode_modifier.nf;
}
static INLINE bool
@@ -3878,6 +3878,8 @@ is_any_apx_encoding (void)
return i.rex2
|| i.rex2_encoding
|| i.tm.opcode_space == SPACE_EVEXMAP4
+ || i.has_nf
+ || i.has_zero_upper
|| (i.vex.register_specifier
&& i.vex.register_specifier->reg_flags & RegRex2);
}
@@ -4178,11 +4180,15 @@ build_evex_insns_with_extend_evex_prefix (void)
i.vex.bytes[1] &= 0xef;
if (i.vex.register_specifier
&& register_number (i.vex.register_specifier) > 0xf)
- i.vex.bytes[3] &=0xf7;
+ i.vex.bytes[3] &= 0xf7;
if (i.rex2 & REX_B)
i.vex.bytes[1] |= 0x08;
if (i.rex2 & REX_X)
i.vex.bytes[2] &= 0xfb;
+
+ /* Encode the NF bit. */
+ if (i.has_nf)
+ i.vex.bytes[3] |= 0x04;
}
/* Build the EVEX prefix (4-byte) for legacy insn
@@ -4210,6 +4216,10 @@ build_legacy_insns_with_apx_encoding (void)
/* Encode the NDD bit. */
if (i.vex.register_specifier)
i.vex.bytes[3] |= 0x10;
+
+ /* Encode the NF bit. */
+ if (i.has_nf)
+ i.vex.bytes[3] |= 0x04;
}
static void
@@ -5944,6 +5954,10 @@ parse_insn (const char *line, char *mnemonic, bool prefix_only)
/* {rex2} */
i.rex2_encoding = true;
break;
+ case Prefix_NF:
+ /* {NF} */
+ i.has_nf = true;
+ break;
case Prefix_NoOptimize:
/* {nooptimize} */
i.no_optimize = true;
@@ -7151,6 +7165,19 @@ optimize_NDD_to_nonNDD (const insn_template *t)
return 0;
}
+/* Check if NF prefix requirements are met by the instruction. */
+static int
+check_NfPrefix (const insn_template *t)
+{
+ if (i.has_nf && !t->opcode_modifier.nf)
+ {
+ /* This instruction should support nf prefix. */
+ i.error = unsupported;
+ return 1;
+ }
+ return 0;
+}
+
/* Helper function for the progress() macro in match_template(). */
static INLINE enum i386_error progress (enum i386_error new,
enum i386_error last,
@@ -7551,6 +7578,7 @@ match_template (char mnem_suffix)
goto check_operands_345;
}
else if (t->opcode_space != SPACE_BASE
+ && !t->opcode_modifier.nf
&& (t->opcode_space != SPACE_0F
/* MOV to/from CR/DR/TR, as an exception, follow
the base opcode space encoding model. */
@@ -7652,6 +7680,13 @@ match_template (char mnem_suffix)
continue;
}
+ /* Check if nf prefix are valid. */
+ if (check_NfPrefix (t))
+ {
+ specific_error = progress (i.error);
+ continue;
+ }
+
/* We've found a match; break out of loop. */
break;
}
diff --git a/gas/testsuite/gas/i386/x86-64-apx-ndd.d b/gas/testsuite/gas/i386/x86-64-apx-ndd.d
index debb99f2ff9..080c0cbd784 100644
--- a/gas/testsuite/gas/i386/x86-64-apx-ndd.d
+++ b/gas/testsuite/gas/i386/x86-64-apx-ndd.d
@@ -158,7 +158,7 @@ Disassembly of section .text:
\s*[a-f0-9]+:\s*67 62 f4 3c 18 4f 90 90 90 90 90 cmovg -0x6f6f6f70\(%eax\),%edx,%r8d
\s*[a-f0-9]+:\s*67 62 f4 3c 18 af 90 09 09 09 00 imul 0x90909\(%eax\),%edx,%r8d
\s*[a-f0-9]+:\s*62 b4 b0 10 af 94 f8 09 09 00 00 imul 0x909\(%rax,%r31,8\),%rdx,%r25
-\s*[a-f0-9]+:\s*62 f4 fc 08 ff c0\s+inc %rax
+\s*[a-f0-9]+:\s*62 f4 fc 08 ff c0\s+\{evex\} inc %rax
\s*[a-f0-9]+:\s*62 f4 ec\s+\(bad\)
\s*[a-f0-9]+:\s*08 ff\s+or %bh,%bh
\s*[a-f0-9]+:\s*c0\s+\.byte 0xc0
diff --git a/gas/testsuite/gas/i386/x86-64-apx-nf-intel.d b/gas/testsuite/gas/i386/x86-64-apx-nf-intel.d
new file mode 100644
index 00000000000..240c9ba6150
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-apx-nf-intel.d
@@ -0,0 +1,633 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 APX_F insns (Intel disassembly)
+#source: x86-64-apx-nf.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 c3 7b\s+\{nf\} add bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 c3 7b\s+\{nf\} add dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 c2 7b\s+\{nf\} add dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 c2 7b\s+\{nf\} add ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 c1 7b\s+\{nf\} add ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 c1 7b\s+\{nf\} add edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 c1 7b\s+\{nf\} add r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 83 c1 7b\s+\{nf\} add r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 84 80 23 01 00 00 7b\s+\{nf\} add BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 84 80 23 01 00 00 7b\s+\{nf\} add bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 84 80 23 01 00 00 7b\s+\{nf\} add WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 84 80 23 01 00 00 7b\s+\{nf\} add dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 84 80 23 01 00 00 7b\s+\{nf\} add DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 84 80 23 01 00 00 7b\s+\{nf\} add ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 84 80 23 01 00 00 7b\s+\{nf\} add QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 84 80 23 01 00 00 7b\s+\{nf\} add r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 00 da\s+\{nf\} add dl,bl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 00 da\s+\{nf\} add r8b,dl,bl
+\s*[a-f0-9]+:\s*62 d4 7c 0c 00 9c 80 23 01 00 00\s+\{nf\} add BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 00 9c 80 23 01 00 00\s+\{nf\} add dl,BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 01 d0\s+\{nf\} add ax,dx
+\s*[a-f0-9]+:\s*62 f4 35 1c 01 d0\s+\{nf\} add r9w,ax,dx
+\s*[a-f0-9]+:\s*62 d4 7d 0c 01 94 80 23 01 00 00\s+\{nf\} add WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 01 94 80 23 01 00 00\s+\{nf\} add ax,WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c 01 ca\s+\{nf\} add edx,ecx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 01 ca\s+\{nf\} add r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 01 8c 80 23 01 00 00\s+\{nf\} add DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 01 8c 80 23 01 00 00\s+\{nf\} add edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 5c fc 0c 01 cf\s+\{nf\} add r31,r9
+\s*[a-f0-9]+:\s*62 5c a4 1c 01 cf\s+\{nf\} add r11,r31,r9
+\s*[a-f0-9]+:\s*62 54 fc 0c 01 8c 80 23 01 00 00\s+\{nf\} add QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 54 84 14 01 8c 80 23 01 00 00\s+\{nf\} add r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c 02 9c 80 23 01 00 00\s+\{nf\} add bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 02 9c 80 23 01 00 00\s+\{nf\} add dl,bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c 03 94 80 23 01 00 00\s+\{nf\} add dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 1c 03 94 80 23 01 00 00\s+\{nf\} add ax,dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c 03 8c 80 23 01 00 00\s+\{nf\} add ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 03 8c 80 23 01 00 00\s+\{nf\} add edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c 03 8c 80 23 01 00 00\s+\{nf\} add r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 84 14 03 8c 80 23 01 00 00\s+\{nf\} add r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 e3 7b\s+\{nf\} and bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 e3 7b\s+\{nf\} and dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 e2 7b\s+\{nf\} and dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 e2 7b\s+\{nf\} and ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 e1 7b\s+\{nf\} and ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 e1 7b\s+\{nf\} and edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 e1 7b\s+\{nf\} and r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 83 e1 7b\s+\{nf\} and r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 a4 80 23 01 00 00 7b\s+\{nf\} and BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 a4 80 23 01 00 00 7b\s+\{nf\} and bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 a4 80 23 01 00 00 7b\s+\{nf\} and WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 a4 80 23 01 00 00 7b\s+\{nf\} and dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 a4 80 23 01 00 00 7b\s+\{nf\} and DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 a4 80 23 01 00 00 7b\s+\{nf\} and ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 a4 80 23 01 00 00 7b\s+\{nf\} and QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 a4 80 23 01 00 00 7b\s+\{nf\} and r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 20 da\s+\{nf\} and dl,bl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 20 da\s+\{nf\} and r8b,dl,bl
+\s*[a-f0-9]+:\s*62 d4 7c 0c 20 9c 80 23 01 00 00\s+\{nf\} and BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 20 9c 80 23 01 00 00\s+\{nf\} and dl,BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 21 d0\s+\{nf\} and ax,dx
+\s*[a-f0-9]+:\s*62 f4 35 1c 21 d0\s+\{nf\} and r9w,ax,dx
+\s*[a-f0-9]+:\s*62 d4 7d 0c 21 94 80 23 01 00 00\s+\{nf\} and WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 21 94 80 23 01 00 00\s+\{nf\} and ax,WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c 21 ca\s+\{nf\} and edx,ecx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 21 ca\s+\{nf\} and r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 21 8c 80 23 01 00 00\s+\{nf\} and DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 21 8c 80 23 01 00 00\s+\{nf\} and edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 5c fc 0c 21 cf\s+\{nf\} and r31,r9
+\s*[a-f0-9]+:\s*62 5c a4 1c 21 cf\s+\{nf\} and r11,r31,r9
+\s*[a-f0-9]+:\s*62 54 fc 0c 21 8c 80 23 01 00 00\s+\{nf\} and QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 54 84 14 21 8c 80 23 01 00 00\s+\{nf\} and r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c 22 9c 80 23 01 00 00\s+\{nf\} and bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 22 9c 80 23 01 00 00\s+\{nf\} and dl,bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c 23 94 80 23 01 00 00\s+\{nf\} and dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 1c 23 94 80 23 01 00 00\s+\{nf\} and ax,dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c 23 8c 80 23 01 00 00\s+\{nf\} and ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 23 8c 80 23 01 00 00\s+\{nf\} and edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c 23 8c 80 23 01 00 00\s+\{nf\} and r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 84 14 23 8c 80 23 01 00 00\s+\{nf\} and r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 72 6c 0c f2 d1\s+\{nf\} andn r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 52 84 04 f2 d9\s+\{nf\} andn r11,r31,r9
+\s*[a-f0-9]+:\s*62 d2 74 0c f2 94 80 23 01 00 00\s+\{nf\} andn edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 42 b4 0c f2 bc 80 23 01 00 00\s+\{nf\} andn r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 72 74 0c f7 d2\s+\{nf\} bextr r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 d2 74 0c f7 94 80 23 01 00 00\s+\{nf\} bextr edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 5a b4 0c f7 df\s+\{nf\} bextr r11,r31,r9
+\s*[a-f0-9]+:\s*62 42 b4 0c f7 bc 80 23 01 00 00\s+\{nf\} bextr r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 f2 6c 0c f3 d9\s+\{nf\} blsi edx,ecx
+\s*[a-f0-9]+:\s*62 d2 84 04 f3 d9\s+\{nf\} blsi r31,r9
+\s*[a-f0-9]+:\s*62 d2 74 0c f3 9c 80 23 01 00 00\s+\{nf\} blsi ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d2 b4 0c f3 9c 80 23 01 00 00\s+\{nf\} blsi r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f2 6c 0c f3 d1\s+\{nf\} blsmsk edx,ecx
+\s*[a-f0-9]+:\s*62 d2 84 04 f3 d1\s+\{nf\} blsmsk r31,r9
+\s*[a-f0-9]+:\s*62 d2 74 0c f3 94 80 23 01 00 00\s+\{nf\} blsmsk ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d2 b4 0c f3 94 80 23 01 00 00\s+\{nf\} blsmsk r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f2 6c 0c f3 c9\s+\{nf\} blsr edx,ecx
+\s*[a-f0-9]+:\s*62 d2 84 04 f3 c9\s+\{nf\} blsr r31,r9
+\s*[a-f0-9]+:\s*62 d2 74 0c f3 8c 80 23 01 00 00\s+\{nf\} blsr ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d2 b4 0c f3 8c 80 23 01 00 00\s+\{nf\} blsr r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 72 74 0c f5 d2\s+\{nf\} bzhi r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 d2 74 0c f5 94 80 23 01 00 00\s+\{nf\} bzhi edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 5a b4 0c f5 df\s+\{nf\} bzhi r11,r31,r9
+\s*[a-f0-9]+:\s*62 42 b4 0c f5 bc 80 23 01 00 00\s+\{nf\} bzhi r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c fe cb\s+\{nf\} dec bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c fe cb\s+\{nf\} dec dl,bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c ff ca\s+\{nf\} dec dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c ff ca\s+\{nf\} dec ax,dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c ff c9\s+\{nf\} dec ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c ff c9\s+\{nf\} dec edx,ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c ff c9\s+\{nf\} dec r9
+\s*[a-f0-9]+:\s*62 d4 84 14 ff c9\s+\{nf\} dec r31,r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c fe 8c 80 23 01 00 00\s+\{nf\} dec BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 64 1c fe 8c 80 23 01 00 00\s+\{nf\} dec bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c ff 8c 80 23 01 00 00\s+\{nf\} dec WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6d 1c ff 8c 80 23 01 00 00\s+\{nf\} dec dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c ff 8c 80 23 01 00 00\s+\{nf\} dec DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 74 1c ff 8c 80 23 01 00 00\s+\{nf\} dec ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 fc 0c ff 8c 80 23 01 00 00\s+\{nf\} dec QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 b4 1c ff 8c 80 23 01 00 00\s+\{nf\} dec r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 f3\s+\{nf\} div bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 f2\s+\{nf\} div dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 f1\s+\{nf\} div ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 f1\s+\{nf\} div r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 b4 80 23 01 00 00\s+\{nf\} div BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 b4 80 23 01 00 00\s+\{nf\} div WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 b4 80 23 01 00 00\s+\{nf\} div DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 b4 80 23 01 00 00\s+\{nf\} div QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 fb\s+\{nf\} idiv bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 fa\s+\{nf\} idiv dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 f9\s+\{nf\} idiv ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 f9\s+\{nf\} idiv r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 bc 80 23 01 00 00\s+\{nf\} idiv BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 bc 80 23 01 00 00\s+\{nf\} idiv WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 bc 80 23 01 00 00\s+\{nf\} idiv DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 bc 80 23 01 00 00\s+\{nf\} idiv QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 eb\s+\{nf\} imul bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 ea\s+\{nf\} imul dx
+\s*[a-f0-9]+:\s*62 f4 7d 0c af c2\s+\{nf\} imul ax,dx
+\s*[a-f0-9]+:\s*62 f4 35 1c af c2\s+\{nf\} imul r9w,ax,dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 e9\s+\{nf\} imul ecx
+\s*[a-f0-9]+:\s*62 f4 7c 0c af d1\s+\{nf\} imul edx,ecx
+\s*[a-f0-9]+:\s*62 f4 2c 1c af d1\s+\{nf\} imul r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 e9\s+\{nf\} imul r9
+\s*[a-f0-9]+:\s*62 44 fc 0c af f9\s+\{nf\} imul r31,r9
+\s*[a-f0-9]+:\s*62 44 a4 1c af f9\s+\{nf\} imul r11,r31,r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 ac 80 23 01 00 00\s+\{nf\} imul BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 ac 80 23 01 00 00\s+\{nf\} imul WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c af 94 80 23 01 00 00\s+\{nf\} imul dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 1c af 94 80 23 01 00 00\s+\{nf\} imul ax,dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 ac 80 23 01 00 00\s+\{nf\} imul DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c af 8c 80 23 01 00 00\s+\{nf\} imul ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c af 8c 80 23 01 00 00\s+\{nf\} imul edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 ac 80 23 01 00 00\s+\{nf\} imul QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c af 8c 80 23 01 00 00\s+\{nf\} imul r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 84 14 af 8c 80 23 01 00 00\s+\{nf\} imul r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c fe c3\s+\{nf\} inc bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c fe c3\s+\{nf\} inc dl,bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c ff c2\s+\{nf\} inc dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c ff c2\s+\{nf\} inc ax,dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c ff c1\s+\{nf\} inc ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c ff c1\s+\{nf\} inc edx,ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c ff c1\s+\{nf\} inc r9
+\s*[a-f0-9]+:\s*62 d4 84 14 ff c1\s+\{nf\} inc r31,r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c fe 84 80 23 01 00 00\s+\{nf\} inc BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 64 1c fe 84 80 23 01 00 00\s+\{nf\} inc bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c ff 84 80 23 01 00 00\s+\{nf\} inc WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6d 1c ff 84 80 23 01 00 00\s+\{nf\} inc dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c ff 84 80 23 01 00 00\s+\{nf\} inc DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 74 1c ff 84 80 23 01 00 00\s+\{nf\} inc ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 fc 0c ff 84 80 23 01 00 00\s+\{nf\} inc QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 b4 1c ff 84 80 23 01 00 00\s+\{nf\} inc r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7d 0c f5 c2\s+\{nf\} lzcnt ax,dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f5 d1\s+\{nf\} lzcnt edx,ecx
+\s*[a-f0-9]+:\s*62 44 fc 0c f5 f9\s+\{nf\} lzcnt r31,r9
+\s*[a-f0-9]+:\s*62 d4 7d 0c f5 94 80 23 01 00 00\s+\{nf\} lzcnt dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c f5 8c 80 23 01 00 00\s+\{nf\} lzcnt ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c f5 8c 80 23 01 00 00\s+\{nf\} lzcnt r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 e3\s+\{nf\} mul bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 e2\s+\{nf\} mul dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 e1\s+\{nf\} mul ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 e1\s+\{nf\} mul r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 a4 80 23 01 00 00\s+\{nf\} mul BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 a4 80 23 01 00 00\s+\{nf\} mul WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 a4 80 23 01 00 00\s+\{nf\} mul DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 a4 80 23 01 00 00\s+\{nf\} mul QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 db\s+\{nf\} neg bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c f6 db\s+\{nf\} neg dl,bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 da\s+\{nf\} neg dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c f7 da\s+\{nf\} neg ax,dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 d9\s+\{nf\} neg ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c f7 d9\s+\{nf\} neg edx,ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 d9\s+\{nf\} neg r9
+\s*[a-f0-9]+:\s*62 d4 84 14 f7 d9\s+\{nf\} neg r31,r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 9c 80 23 01 00 00\s+\{nf\} neg BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 64 1c f6 9c 80 23 01 00 00\s+\{nf\} neg bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 9c 80 23 01 00 00\s+\{nf\} neg WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6d 1c f7 9c 80 23 01 00 00\s+\{nf\} neg dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 9c 80 23 01 00 00\s+\{nf\} neg DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 74 1c f7 9c 80 23 01 00 00\s+\{nf\} neg ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 9c 80 23 01 00 00\s+\{nf\} neg QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 b4 1c f7 9c 80 23 01 00 00\s+\{nf\} neg r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 cb 7b\s+\{nf\} or bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 cb 7b\s+\{nf\} or dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 ca 7b\s+\{nf\} or dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 ca 7b\s+\{nf\} or ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 c9 7b\s+\{nf\} or ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 c9 7b\s+\{nf\} or edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 c9 7b\s+\{nf\} or r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 83 c9 7b\s+\{nf\} or r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 8c 80 23 01 00 00 7b\s+\{nf\} or BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 8c 80 23 01 00 00 7b\s+\{nf\} or bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 8c 80 23 01 00 00 7b\s+\{nf\} or WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 8c 80 23 01 00 00 7b\s+\{nf\} or dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 8c 80 23 01 00 00 7b\s+\{nf\} or DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 8c 80 23 01 00 00 7b\s+\{nf\} or ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 8c 80 23 01 00 00 7b\s+\{nf\} or QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 8c 80 23 01 00 00 7b\s+\{nf\} or r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 08 da\s+\{nf\} or dl,bl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 08 da\s+\{nf\} or r8b,dl,bl
+\s*[a-f0-9]+:\s*62 d4 7c 0c 08 9c 80 23 01 00 00\s+\{nf\} or BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 08 9c 80 23 01 00 00\s+\{nf\} or dl,BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 09 d0\s+\{nf\} or ax,dx
+\s*[a-f0-9]+:\s*62 f4 35 1c 09 d0\s+\{nf\} or r9w,ax,dx
+\s*[a-f0-9]+:\s*62 d4 7d 0c 09 94 80 23 01 00 00\s+\{nf\} or WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 09 94 80 23 01 00 00\s+\{nf\} or ax,WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c 09 ca\s+\{nf\} or edx,ecx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 09 ca\s+\{nf\} or r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 09 8c 80 23 01 00 00\s+\{nf\} or DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 09 8c 80 23 01 00 00\s+\{nf\} or edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 5c fc 0c 09 cf\s+\{nf\} or r31,r9
+\s*[a-f0-9]+:\s*62 5c a4 1c 09 cf\s+\{nf\} or r11,r31,r9
+\s*[a-f0-9]+:\s*62 54 fc 0c 09 8c 80 23 01 00 00\s+\{nf\} or QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 54 84 14 09 8c 80 23 01 00 00\s+\{nf\} or r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c 0a 9c 80 23 01 00 00\s+\{nf\} or bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 0a 9c 80 23 01 00 00\s+\{nf\} or dl,bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c 0b 94 80 23 01 00 00\s+\{nf\} or dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 1c 0b 94 80 23 01 00 00\s+\{nf\} or ax,dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c 0b 8c 80 23 01 00 00\s+\{nf\} or ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 0b 8c 80 23 01 00 00\s+\{nf\} or edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c 0b 8c 80 23 01 00 00\s+\{nf\} or r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 84 14 0b 8c 80 23 01 00 00\s+\{nf\} or r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7d 0c 88 c2\s+\{nf\} popcnt ax,dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c 88 d1\s+\{nf\} popcnt edx,ecx
+\s*[a-f0-9]+:\s*62 44 fc 0c 88 f9\s+\{nf\} popcnt r31,r9
+\s*[a-f0-9]+:\s*62 d4 7d 0c 88 94 80 23 01 00 00\s+\{nf\} popcnt dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c 88 8c 80 23 01 00 00\s+\{nf\} popcnt ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c 88 8c 80 23 01 00 00\s+\{nf\} popcnt r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 c3\s+\{nf\} rol bl,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 c3\s+\{nf\} rol dl,bl,1
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 c2\s+\{nf\} rol dx,1
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 c2\s+\{nf\} rol ax,dx,1
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 c1\s+\{nf\} rol ecx,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 c1\s+\{nf\} rol edx,ecx,1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 c1\s+\{nf\} rol r9,1
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 c1\s+\{nf\} rol r31,r9,1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 84 80 23 01 00 00\s+\{nf\} rol BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 84 80 23 01 00 00\s+\{nf\} rol bl,BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 84 80 23 01 00 00\s+\{nf\} rol WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 84 80 23 01 00 00\s+\{nf\} rol dx,WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 84 80 23 01 00 00\s+\{nf\} rol DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 84 80 23 01 00 00\s+\{nf\} rol ecx,DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 84 80 23 01 00 00\s+\{nf\} rol QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 84 80 23 01 00 00\s+\{nf\} rol r9,QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 c3 7b\s+\{nf\} rol bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 c3 7b\s+\{nf\} rol dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 c2 7b\s+\{nf\} rol dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 c2 7b\s+\{nf\} rol ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 c1 7b\s+\{nf\} rol ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 c1 7b\s+\{nf\} rol edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 c1 7b\s+\{nf\} rol r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 c1 7b\s+\{nf\} rol r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 84 80 23 01 00 00 7b\s+\{nf\} rol BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 84 80 23 01 00 00 7b\s+\{nf\} rol bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 84 80 23 01 00 00 7b\s+\{nf\} rol WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 84 80 23 01 00 00 7b\s+\{nf\} rol dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 84 80 23 01 00 00 7b\s+\{nf\} rol DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 84 80 23 01 00 00 7b\s+\{nf\} rol ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 84 80 23 01 00 00 7b\s+\{nf\} rol QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 84 80 23 01 00 00 7b\s+\{nf\} rol r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 c3\s+\{nf\} rol bl,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 c3\s+\{nf\} rol dl,bl,cl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 c2\s+\{nf\} rol dx,cl
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 c2\s+\{nf\} rol ax,dx,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 c1\s+\{nf\} rol ecx,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 c1\s+\{nf\} rol edx,ecx,cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 c1\s+\{nf\} rol r9,cl
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 c1\s+\{nf\} rol r31,r9,cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 84 80 23 01 00 00\s+\{nf\} rol BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 84 80 23 01 00 00\s+\{nf\} rol bl,BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 84 80 23 01 00 00\s+\{nf\} rol WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 84 80 23 01 00 00\s+\{nf\} rol dx,WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 84 80 23 01 00 00\s+\{nf\} rol DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 84 80 23 01 00 00\s+\{nf\} rol ecx,DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 84 80 23 01 00 00\s+\{nf\} rol QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 84 80 23 01 00 00\s+\{nf\} rol r9,QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 cb\s+\{nf\} ror bl,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 cb\s+\{nf\} ror dl,bl,1
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 ca\s+\{nf\} ror dx,1
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 ca\s+\{nf\} ror ax,dx,1
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 c9\s+\{nf\} ror ecx,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 c9\s+\{nf\} ror edx,ecx,1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 c9\s+\{nf\} ror r9,1
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 c9\s+\{nf\} ror r31,r9,1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 8c 80 23 01 00 00\s+\{nf\} ror BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 8c 80 23 01 00 00\s+\{nf\} ror bl,BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 8c 80 23 01 00 00\s+\{nf\} ror WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 8c 80 23 01 00 00\s+\{nf\} ror dx,WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 8c 80 23 01 00 00\s+\{nf\} ror DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 8c 80 23 01 00 00\s+\{nf\} ror ecx,DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 8c 80 23 01 00 00\s+\{nf\} ror QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 8c 80 23 01 00 00\s+\{nf\} ror r9,QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 cb 7b\s+\{nf\} ror bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 cb 7b\s+\{nf\} ror dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 ca 7b\s+\{nf\} ror dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 ca 7b\s+\{nf\} ror ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 c9 7b\s+\{nf\} ror ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 c9 7b\s+\{nf\} ror edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 c9 7b\s+\{nf\} ror r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 c9 7b\s+\{nf\} ror r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 8c 80 23 01 00 00 7b\s+\{nf\} ror BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 8c 80 23 01 00 00 7b\s+\{nf\} ror bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 8c 80 23 01 00 00 7b\s+\{nf\} ror r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 cb\s+\{nf\} ror bl,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 cb\s+\{nf\} ror dl,bl,cl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 ca\s+\{nf\} ror dx,cl
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 ca\s+\{nf\} ror ax,dx,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 c9\s+\{nf\} ror ecx,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 c9\s+\{nf\} ror edx,ecx,cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 c9\s+\{nf\} ror r9,cl
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 c9\s+\{nf\} ror r31,r9,cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 8c 80 23 01 00 00\s+\{nf\} ror BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 8c 80 23 01 00 00\s+\{nf\} ror bl,BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 8c 80 23 01 00 00\s+\{nf\} ror WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 8c 80 23 01 00 00\s+\{nf\} ror dx,WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 8c 80 23 01 00 00\s+\{nf\} ror DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 8c 80 23 01 00 00\s+\{nf\} ror ecx,DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 8c 80 23 01 00 00\s+\{nf\} ror QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 8c 80 23 01 00 00\s+\{nf\} ror r9,QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 fb\s+\{nf\} sar bl,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 fb\s+\{nf\} sar dl,bl,1
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 fa\s+\{nf\} sar dx,1
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 fa\s+\{nf\} sar ax,dx,1
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 f9\s+\{nf\} sar ecx,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 f9\s+\{nf\} sar edx,ecx,1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 f9\s+\{nf\} sar r9,1
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 f9\s+\{nf\} sar r31,r9,1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 bc 80 23 01 00 00\s+\{nf\} sar BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 bc 80 23 01 00 00\s+\{nf\} sar bl,BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 bc 80 23 01 00 00\s+\{nf\} sar WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 bc 80 23 01 00 00\s+\{nf\} sar dx,WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 bc 80 23 01 00 00\s+\{nf\} sar DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 bc 80 23 01 00 00\s+\{nf\} sar ecx,DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 bc 80 23 01 00 00\s+\{nf\} sar QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 bc 80 23 01 00 00\s+\{nf\} sar r9,QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 fb 7b\s+\{nf\} sar bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 fb 7b\s+\{nf\} sar dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 fa 7b\s+\{nf\} sar dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 fa 7b\s+\{nf\} sar ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 f9 7b\s+\{nf\} sar ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 f9 7b\s+\{nf\} sar edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 f9 7b\s+\{nf\} sar r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 f9 7b\s+\{nf\} sar r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 bc 80 23 01 00 00 7b\s+\{nf\} sar BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 bc 80 23 01 00 00 7b\s+\{nf\} sar bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 bc 80 23 01 00 00 7b\s+\{nf\} sar r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 fb\s+\{nf\} sar bl,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 fb\s+\{nf\} sar dl,bl,cl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 fa\s+\{nf\} sar dx,cl
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 fa\s+\{nf\} sar ax,dx,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 f9\s+\{nf\} sar ecx,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 f9\s+\{nf\} sar edx,ecx,cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 f9\s+\{nf\} sar r9,cl
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 f9\s+\{nf\} sar r31,r9,cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 bc 80 23 01 00 00\s+\{nf\} sar BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 bc 80 23 01 00 00\s+\{nf\} sar bl,BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 bc 80 23 01 00 00\s+\{nf\} sar WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 bc 80 23 01 00 00\s+\{nf\} sar dx,WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 bc 80 23 01 00 00\s+\{nf\} sar DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 bc 80 23 01 00 00\s+\{nf\} sar ecx,DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 bc 80 23 01 00 00\s+\{nf\} sar QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 bc 80 23 01 00 00\s+\{nf\} sar r9,QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 e3\s+\{nf\} shl bl,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 e3\s+\{nf\} shl dl,bl,1
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 e2\s+\{nf\} shl dx,1
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 e2\s+\{nf\} shl ax,dx,1
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 e1\s+\{nf\} shl ecx,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 e1\s+\{nf\} shl edx,ecx,1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 e1\s+\{nf\} shl r9,1
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 e1\s+\{nf\} shl r31,r9,1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 a4 80 23 01 00 00\s+\{nf\} shl BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 a4 80 23 01 00 00\s+\{nf\} shl bl,BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 a4 80 23 01 00 00\s+\{nf\} shl WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 a4 80 23 01 00 00\s+\{nf\} shl dx,WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 a4 80 23 01 00 00\s+\{nf\} shl DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 a4 80 23 01 00 00\s+\{nf\} shl ecx,DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 a4 80 23 01 00 00\s+\{nf\} shl QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 a4 80 23 01 00 00\s+\{nf\} shl r9,QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 e3 7b\s+\{nf\} shl bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 e3 7b\s+\{nf\} shl dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 e2 7b\s+\{nf\} shl dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 e2 7b\s+\{nf\} shl ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 e1 7b\s+\{nf\} shl ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 e1 7b\s+\{nf\} shl edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 e1 7b\s+\{nf\} shl r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 e1 7b\s+\{nf\} shl r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 a4 80 23 01 00 00 7b\s+\{nf\} shl BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 a4 80 23 01 00 00 7b\s+\{nf\} shl bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shl r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 e3\s+\{nf\} shl bl,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 e3\s+\{nf\} shl dl,bl,cl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 e2\s+\{nf\} shl dx,cl
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 e2\s+\{nf\} shl ax,dx,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 e1\s+\{nf\} shl ecx,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 e1\s+\{nf\} shl edx,ecx,cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 e1\s+\{nf\} shl r9,cl
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 e1\s+\{nf\} shl r31,r9,cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 a4 80 23 01 00 00\s+\{nf\} shl BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 a4 80 23 01 00 00\s+\{nf\} shl bl,BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 a4 80 23 01 00 00\s+\{nf\} shl WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 a4 80 23 01 00 00\s+\{nf\} shl dx,WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 a4 80 23 01 00 00\s+\{nf\} shl DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 a4 80 23 01 00 00\s+\{nf\} shl ecx,DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 a4 80 23 01 00 00\s+\{nf\} shl QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 a4 80 23 01 00 00\s+\{nf\} shl r9,QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 24 d0 7b\s+\{nf\} shld ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 35 1c 24 d0 7b\s+\{nf\} shld r9w,ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c 24 94 80 23 01 00 00 7b\s+\{nf\} shld WORD PTR \[r8\+rax\*4\+0x123\],dx,0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 1c 24 94 80 23 01 00 00 7b\s+\{nf\} shld ax,WORD PTR \[r8\+rax\*4\+0x123\],dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 24 ca 7b\s+\{nf\} shld edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 2c 1c 24 ca 7b\s+\{nf\} shld r10d,edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 24 8c 80 23 01 00 00 7b\s+\{nf\} shld DWORD PTR \[r8\+rax\*4\+0x123\],ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 6c 1c 24 8c 80 23 01 00 00 7b\s+\{nf\} shld edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx,0x7b
+\s*[a-f0-9]+:\s*62 5c fc 0c 24 cf 7b\s+\{nf\} shld r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 5c a4 1c 24 cf 7b\s+\{nf\} shld r11,r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 54 fc 0c 24 8c 80 23 01 00 00 7b\s+\{nf\} shld QWORD PTR \[r8\+rax\*4\+0x123\],r9,0x7b
+\s*[a-f0-9]+:\s*62 54 84 14 24 8c 80 23 01 00 00 7b\s+\{nf\} shld r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c a5 d0\s+\{nf\} shld ax,dx,cl
+\s*[a-f0-9]+:\s*62 f4 35 1c a5 d0\s+\{nf\} shld r9w,ax,dx,cl
+\s*[a-f0-9]+:\s*62 d4 7d 0c a5 94 80 23 01 00 00\s+\{nf\} shld WORD PTR \[r8\+rax\*4\+0x123\],dx,cl
+\s*[a-f0-9]+:\s*62 d4 7d 1c a5 94 80 23 01 00 00\s+\{nf\} shld ax,WORD PTR \[r8\+rax\*4\+0x123\],dx,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c a5 ca\s+\{nf\} shld edx,ecx,cl
+\s*[a-f0-9]+:\s*62 f4 2c 1c a5 ca\s+\{nf\} shld r10d,edx,ecx,cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c a5 8c 80 23 01 00 00\s+\{nf\} shld DWORD PTR \[r8\+rax\*4\+0x123\],ecx,cl
+\s*[a-f0-9]+:\s*62 d4 6c 1c a5 8c 80 23 01 00 00\s+\{nf\} shld edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx,cl
+\s*[a-f0-9]+:\s*62 5c fc 0c a5 cf\s+\{nf\} shld r31,r9,cl
+\s*[a-f0-9]+:\s*62 5c a4 1c a5 cf\s+\{nf\} shld r11,r31,r9,cl
+\s*[a-f0-9]+:\s*62 54 fc 0c a5 8c 80 23 01 00 00\s+\{nf\} shld QWORD PTR \[r8\+rax\*4\+0x123\],r9,cl
+\s*[a-f0-9]+:\s*62 54 84 14 a5 8c 80 23 01 00 00\s+\{nf\} shld r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 eb\s+\{nf\} shr bl,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 eb\s+\{nf\} shr dl,bl,1
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 ea\s+\{nf\} shr dx,1
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 ea\s+\{nf\} shr ax,dx,1
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 e9\s+\{nf\} shr ecx,1
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 e9\s+\{nf\} shr edx,ecx,1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 e9\s+\{nf\} shr r9,1
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 e9\s+\{nf\} shr r31,r9,1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 ac 80 23 01 00 00\s+\{nf\} shr BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 ac 80 23 01 00 00\s+\{nf\} shr bl,BYTE PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 ac 80 23 01 00 00\s+\{nf\} shr WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 ac 80 23 01 00 00\s+\{nf\} shr dx,WORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 ac 80 23 01 00 00\s+\{nf\} shr DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 ac 80 23 01 00 00\s+\{nf\} shr ecx,DWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 ac 80 23 01 00 00\s+\{nf\} shr QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 ac 80 23 01 00 00\s+\{nf\} shr r9,QWORD PTR \[r8\+rax\*4\+0x123\],1
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 eb 7b\s+\{nf\} shr bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 eb 7b\s+\{nf\} shr dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 ea 7b\s+\{nf\} shr dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 ea 7b\s+\{nf\} shr ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 e9 7b\s+\{nf\} shr ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 e9 7b\s+\{nf\} shr edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 e9 7b\s+\{nf\} shr r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 e9 7b\s+\{nf\} shr r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 ac 80 23 01 00 00 7b\s+\{nf\} shr BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 ac 80 23 01 00 00 7b\s+\{nf\} shr bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 ac 80 23 01 00 00 7b\s+\{nf\} shr r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 eb\s+\{nf\} shr bl,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 eb\s+\{nf\} shr dl,bl,cl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 ea\s+\{nf\} shr dx,cl
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 ea\s+\{nf\} shr ax,dx,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 e9\s+\{nf\} shr ecx,cl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 e9\s+\{nf\} shr edx,ecx,cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 e9\s+\{nf\} shr r9,cl
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 e9\s+\{nf\} shr r31,r9,cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 ac 80 23 01 00 00\s+\{nf\} shr BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 ac 80 23 01 00 00\s+\{nf\} shr bl,BYTE PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 ac 80 23 01 00 00\s+\{nf\} shr WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 ac 80 23 01 00 00\s+\{nf\} shr dx,WORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 ac 80 23 01 00 00\s+\{nf\} shr DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 ac 80 23 01 00 00\s+\{nf\} shr ecx,DWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 ac 80 23 01 00 00\s+\{nf\} shr QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 ac 80 23 01 00 00\s+\{nf\} shr r9,QWORD PTR \[r8\+rax\*4\+0x123\],cl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 2c d0 7b\s+\{nf\} shrd ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 35 1c 2c d0 7b\s+\{nf\} shrd r9w,ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c 2c 94 80 23 01 00 00 7b\s+\{nf\} shrd WORD PTR \[r8\+rax\*4\+0x123\],dx,0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 1c 2c 94 80 23 01 00 00 7b\s+\{nf\} shrd ax,WORD PTR \[r8\+rax\*4\+0x123\],dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 2c ca 7b\s+\{nf\} shrd edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 2c 1c 2c ca 7b\s+\{nf\} shrd r10d,edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd DWORD PTR \[r8\+rax\*4\+0x123\],ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 6c 1c 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx,0x7b
+\s*[a-f0-9]+:\s*62 5c fc 0c 2c cf 7b\s+\{nf\} shrd r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 5c a4 1c 2c cf 7b\s+\{nf\} shrd r11,r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 54 fc 0c 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd QWORD PTR \[r8\+rax\*4\+0x123\],r9,0x7b
+\s*[a-f0-9]+:\s*62 54 84 14 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c ad d0\s+\{nf\} shrd ax,dx,cl
+\s*[a-f0-9]+:\s*62 f4 35 1c ad d0\s+\{nf\} shrd r9w,ax,dx,cl
+\s*[a-f0-9]+:\s*62 d4 7d 0c ad 94 80 23 01 00 00\s+\{nf\} shrd WORD PTR \[r8\+rax\*4\+0x123\],dx,cl
+\s*[a-f0-9]+:\s*62 d4 7d 1c ad 94 80 23 01 00 00\s+\{nf\} shrd ax,WORD PTR \[r8\+rax\*4\+0x123\],dx,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c ad ca\s+\{nf\} shrd edx,ecx,cl
+\s*[a-f0-9]+:\s*62 f4 2c 1c ad ca\s+\{nf\} shrd r10d,edx,ecx,cl
+\s*[a-f0-9]+:\s*62 d4 7c 0c ad 8c 80 23 01 00 00\s+\{nf\} shrd DWORD PTR \[r8\+rax\*4\+0x123\],ecx,cl
+\s*[a-f0-9]+:\s*62 d4 6c 1c ad 8c 80 23 01 00 00\s+\{nf\} shrd edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx,cl
+\s*[a-f0-9]+:\s*62 5c fc 0c ad cf\s+\{nf\} shrd r31,r9,cl
+\s*[a-f0-9]+:\s*62 5c a4 1c ad cf\s+\{nf\} shrd r11,r31,r9,cl
+\s*[a-f0-9]+:\s*62 54 fc 0c ad 8c 80 23 01 00 00\s+\{nf\} shrd QWORD PTR \[r8\+rax\*4\+0x123\],r9,cl
+\s*[a-f0-9]+:\s*62 54 84 14 ad 8c 80 23 01 00 00\s+\{nf\} shrd r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9,cl
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 eb 7b\s+\{nf\} sub bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 eb 7b\s+\{nf\} sub dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 ea 7b\s+\{nf\} sub dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 ea 7b\s+\{nf\} sub ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 e9 7b\s+\{nf\} sub ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 e9 7b\s+\{nf\} sub edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 e9 7b\s+\{nf\} sub r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 83 e9 7b\s+\{nf\} sub r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 ac 80 23 01 00 00 7b\s+\{nf\} sub BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 ac 80 23 01 00 00 7b\s+\{nf\} sub bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 ac 80 23 01 00 00 7b\s+\{nf\} sub r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 28 da\s+\{nf\} sub dl,bl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 28 da\s+\{nf\} sub r8b,dl,bl
+\s*[a-f0-9]+:\s*62 d4 7c 0c 28 9c 80 23 01 00 00\s+\{nf\} sub BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 28 9c 80 23 01 00 00\s+\{nf\} sub dl,BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 29 d0\s+\{nf\} sub ax,dx
+\s*[a-f0-9]+:\s*62 f4 35 1c 29 d0\s+\{nf\} sub r9w,ax,dx
+\s*[a-f0-9]+:\s*62 d4 7d 0c 29 94 80 23 01 00 00\s+\{nf\} sub WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 29 94 80 23 01 00 00\s+\{nf\} sub ax,WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c 29 ca\s+\{nf\} sub edx,ecx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 29 ca\s+\{nf\} sub r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 29 8c 80 23 01 00 00\s+\{nf\} sub DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 29 8c 80 23 01 00 00\s+\{nf\} sub edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 5c fc 0c 29 cf\s+\{nf\} sub r31,r9
+\s*[a-f0-9]+:\s*62 5c a4 1c 29 cf\s+\{nf\} sub r11,r31,r9
+\s*[a-f0-9]+:\s*62 54 fc 0c 29 8c 80 23 01 00 00\s+\{nf\} sub QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 54 84 14 29 8c 80 23 01 00 00\s+\{nf\} sub r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c 2a 9c 80 23 01 00 00\s+\{nf\} sub bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 2a 9c 80 23 01 00 00\s+\{nf\} sub dl,bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c 2b 94 80 23 01 00 00\s+\{nf\} sub dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 1c 2b 94 80 23 01 00 00\s+\{nf\} sub ax,dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c 2b 8c 80 23 01 00 00\s+\{nf\} sub ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 2b 8c 80 23 01 00 00\s+\{nf\} sub edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c 2b 8c 80 23 01 00 00\s+\{nf\} sub r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 84 14 2b 8c 80 23 01 00 00\s+\{nf\} sub r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7d 0c f4 c2\s+\{nf\} tzcnt ax,dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f4 d1\s+\{nf\} tzcnt edx,ecx
+\s*[a-f0-9]+:\s*62 44 fc 0c f4 f9\s+\{nf\} tzcnt r31,r9
+\s*[a-f0-9]+:\s*62 d4 7d 0c f4 94 80 23 01 00 00\s+\{nf\} tzcnt dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c f4 8c 80 23 01 00 00\s+\{nf\} tzcnt ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c f4 8c 80 23 01 00 00\s+\{nf\} tzcnt r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 f3 7b\s+\{nf\} xor bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 f3 7b\s+\{nf\} xor dl,bl,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 f2 7b\s+\{nf\} xor dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 f2 7b\s+\{nf\} xor ax,dx,0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 f1 7b\s+\{nf\} xor ecx,0x7b
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 f1 7b\s+\{nf\} xor edx,ecx,0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 f1 7b\s+\{nf\} xor r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 84 14 83 f1 7b\s+\{nf\} xor r31,r9,0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 b4 80 23 01 00 00 7b\s+\{nf\} xor BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 b4 80 23 01 00 00 7b\s+\{nf\} xor bl,BYTE PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor dx,WORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor ecx,DWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 b4 80 23 01 00 00 7b\s+\{nf\} xor r9,QWORD PTR \[r8\+rax\*4\+0x123\],0x7b
+\s*[a-f0-9]+:\s*62 f4 7c 0c 30 da\s+\{nf\} xor dl,bl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 30 da\s+\{nf\} xor r8b,dl,bl
+\s*[a-f0-9]+:\s*62 d4 7c 0c 30 9c 80 23 01 00 00\s+\{nf\} xor BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 30 9c 80 23 01 00 00\s+\{nf\} xor dl,BYTE PTR \[r8\+rax\*4\+0x123\],bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 31 d0\s+\{nf\} xor ax,dx
+\s*[a-f0-9]+:\s*62 f4 35 1c 31 d0\s+\{nf\} xor r9w,ax,dx
+\s*[a-f0-9]+:\s*62 d4 7d 0c 31 94 80 23 01 00 00\s+\{nf\} xor WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 31 94 80 23 01 00 00\s+\{nf\} xor ax,WORD PTR \[r8\+rax\*4\+0x123\],dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c 31 ca\s+\{nf\} xor edx,ecx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 31 ca\s+\{nf\} xor r10d,edx,ecx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 31 8c 80 23 01 00 00\s+\{nf\} xor DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 31 8c 80 23 01 00 00\s+\{nf\} xor edx,DWORD PTR \[r8\+rax\*4\+0x123\],ecx
+\s*[a-f0-9]+:\s*62 5c fc 0c 31 cf\s+\{nf\} xor r31,r9
+\s*[a-f0-9]+:\s*62 5c a4 1c 31 cf\s+\{nf\} xor r11,r31,r9
+\s*[a-f0-9]+:\s*62 54 fc 0c 31 8c 80 23 01 00 00\s+\{nf\} xor QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 54 84 14 31 8c 80 23 01 00 00\s+\{nf\} xor r31,QWORD PTR \[r8\+rax\*4\+0x123\],r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c 32 9c 80 23 01 00 00\s+\{nf\} xor bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 32 9c 80 23 01 00 00\s+\{nf\} xor dl,bl,BYTE PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 0c 33 94 80 23 01 00 00\s+\{nf\} xor dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7d 1c 33 94 80 23 01 00 00\s+\{nf\} xor ax,dx,WORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 7c 0c 33 8c 80 23 01 00 00\s+\{nf\} xor ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 d4 6c 1c 33 8c 80 23 01 00 00\s+\{nf\} xor edx,ecx,DWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 fc 0c 33 8c 80 23 01 00 00\s+\{nf\} xor r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+\s*[a-f0-9]+:\s*62 54 84 14 33 8c 80 23 01 00 00\s+\{nf\} xor r31,r9,QWORD PTR \[r8\+rax\*4\+0x123\]
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-apx-nf.d b/gas/testsuite/gas/i386/x86-64-apx-nf.d
new file mode 100644
index 00000000000..ba166e9a98f
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-apx-nf.d
@@ -0,0 +1,633 @@
+#as:
+#objdump: -dw
+#name: x86_64 APX_F insns
+#source: x86-64-apx-nf.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 c3 7b\s+\{nf\} add \$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 c3 7b\s+\{nf\} add \$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 c2 7b\s+\{nf\} add \$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 c2 7b\s+\{nf\} add \$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 c1 7b\s+\{nf\} add \$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 c1 7b\s+\{nf\} add \$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 c1 7b\s+\{nf\} add \$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 83 c1 7b\s+\{nf\} add \$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 84 80 23 01 00 00 7b\s+\{nf\} addb \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 84 80 23 01 00 00 7b\s+\{nf\} addb \$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 84 80 23 01 00 00 7b\s+\{nf\} addw \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 84 80 23 01 00 00 7b\s+\{nf\} addw \$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 84 80 23 01 00 00 7b\s+\{nf\} addl \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 84 80 23 01 00 00 7b\s+\{nf\} addl \$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 84 80 23 01 00 00 7b\s+\{nf\} addq \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 84 80 23 01 00 00 7b\s+\{nf\} addq \$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c 00 da\s+\{nf\} add %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 00 da\s+\{nf\} add %bl,%dl,%r8b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 00 9c 80 23 01 00 00\s+\{nf\} add %bl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 00 9c 80 23 01 00 00\s+\{nf\} add %bl,0x123\(%r8,%rax,4\),%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 01 d0\s+\{nf\} add %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c 01 d0\s+\{nf\} add %dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c 01 94 80 23 01 00 00\s+\{nf\} add %dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c 01 94 80 23 01 00 00\s+\{nf\} add %dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 01 ca\s+\{nf\} add %ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 01 ca\s+\{nf\} add %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c 01 8c 80 23 01 00 00\s+\{nf\} add %ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 01 8c 80 23 01 00 00\s+\{nf\} add %ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c 01 cf\s+\{nf\} add %r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c 01 cf\s+\{nf\} add %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c 01 8c 80 23 01 00 00\s+\{nf\} add %r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 01 8c 80 23 01 00 00\s+\{nf\} add %r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 02 9c 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 02 9c 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%bl,%dl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 03 94 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 03 94 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%dx,%ax
+\s*[a-f0-9]+:\s*62 d4 7c 0c 03 8c 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 03 8c 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%ecx,%edx
+\s*[a-f0-9]+:\s*62 54 fc 0c 03 8c 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 54 84 14 03 8c 80 23 01 00 00\s+\{nf\} add 0x123\(%r8,%rax,4\),%r9,%r31
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 e3 7b\s+\{nf\} and \$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 e3 7b\s+\{nf\} and \$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 e2 7b\s+\{nf\} and \$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 e2 7b\s+\{nf\} and \$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 e1 7b\s+\{nf\} and \$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 e1 7b\s+\{nf\} and \$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 e1 7b\s+\{nf\} and \$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 83 e1 7b\s+\{nf\} and \$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 a4 80 23 01 00 00 7b\s+\{nf\} andb \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 a4 80 23 01 00 00 7b\s+\{nf\} andb \$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 a4 80 23 01 00 00 7b\s+\{nf\} andw \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 a4 80 23 01 00 00 7b\s+\{nf\} andw \$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 a4 80 23 01 00 00 7b\s+\{nf\} andl \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 a4 80 23 01 00 00 7b\s+\{nf\} andl \$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 a4 80 23 01 00 00 7b\s+\{nf\} andq \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 a4 80 23 01 00 00 7b\s+\{nf\} andq \$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c 20 da\s+\{nf\} and %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 20 da\s+\{nf\} and %bl,%dl,%r8b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 20 9c 80 23 01 00 00\s+\{nf\} and %bl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 20 9c 80 23 01 00 00\s+\{nf\} and %bl,0x123\(%r8,%rax,4\),%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 21 d0\s+\{nf\} and %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c 21 d0\s+\{nf\} and %dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c 21 94 80 23 01 00 00\s+\{nf\} and %dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c 21 94 80 23 01 00 00\s+\{nf\} and %dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 21 ca\s+\{nf\} and %ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 21 ca\s+\{nf\} and %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c 21 8c 80 23 01 00 00\s+\{nf\} and %ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 21 8c 80 23 01 00 00\s+\{nf\} and %ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c 21 cf\s+\{nf\} and %r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c 21 cf\s+\{nf\} and %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c 21 8c 80 23 01 00 00\s+\{nf\} and %r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 21 8c 80 23 01 00 00\s+\{nf\} and %r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 22 9c 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 22 9c 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%bl,%dl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 23 94 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 23 94 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%dx,%ax
+\s*[a-f0-9]+:\s*62 d4 7c 0c 23 8c 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 23 8c 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%ecx,%edx
+\s*[a-f0-9]+:\s*62 54 fc 0c 23 8c 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 54 84 14 23 8c 80 23 01 00 00\s+\{nf\} and 0x123\(%r8,%rax,4\),%r9,%r31
+\s*[a-f0-9]+:\s*62 72 6c 0c f2 d1\s+\{nf\} andn %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 52 84 04 f2 d9\s+\{nf\} andn %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 d2 74 0c f2 94 80 23 01 00 00\s+\{nf\} andn 0x123\(%r8,%rax,4\),%ecx,%edx
+\s*[a-f0-9]+:\s*62 42 b4 0c f2 bc 80 23 01 00 00\s+\{nf\} andn 0x123\(%r8,%rax,4\),%r9,%r31
+\s*[a-f0-9]+:\s*62 72 74 0c f7 d2\s+\{nf\} bextr %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d2 74 0c f7 94 80 23 01 00 00\s+\{nf\} bextr %ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5a b4 0c f7 df\s+\{nf\} bextr %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 42 b4 0c f7 bc 80 23 01 00 00\s+\{nf\} bextr %r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 f2 6c 0c f3 d9\s+\{nf\} blsi %ecx,%edx
+\s*[a-f0-9]+:\s*62 d2 84 04 f3 d9\s+\{nf\} blsi %r9,%r31
+\s*[a-f0-9]+:\s*62 d2 74 0c f3 9c 80 23 01 00 00\s+\{nf\} blsi 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d2 b4 0c f3 9c 80 23 01 00 00\s+\{nf\} blsi 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f2 6c 0c f3 d1\s+\{nf\} blsmsk %ecx,%edx
+\s*[a-f0-9]+:\s*62 d2 84 04 f3 d1\s+\{nf\} blsmsk %r9,%r31
+\s*[a-f0-9]+:\s*62 d2 74 0c f3 94 80 23 01 00 00\s+\{nf\} blsmsk 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d2 b4 0c f3 94 80 23 01 00 00\s+\{nf\} blsmsk 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f2 6c 0c f3 c9\s+\{nf\} blsr %ecx,%edx
+\s*[a-f0-9]+:\s*62 d2 84 04 f3 c9\s+\{nf\} blsr %r9,%r31
+\s*[a-f0-9]+:\s*62 d2 74 0c f3 8c 80 23 01 00 00\s+\{nf\} blsr 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d2 b4 0c f3 8c 80 23 01 00 00\s+\{nf\} blsr 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 72 74 0c f5 d2\s+\{nf\} bzhi %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d2 74 0c f5 94 80 23 01 00 00\s+\{nf\} bzhi %ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5a b4 0c f5 df\s+\{nf\} bzhi %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 42 b4 0c f5 bc 80 23 01 00 00\s+\{nf\} bzhi %r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 f4 7c 0c fe cb\s+\{nf\} dec %bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c fe cb\s+\{nf\} dec %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c ff ca\s+\{nf\} dec %dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c ff ca\s+\{nf\} dec %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c ff c9\s+\{nf\} dec %ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c ff c9\s+\{nf\} dec %ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c ff c9\s+\{nf\} dec %r9
+\s*[a-f0-9]+:\s*62 d4 84 14 ff c9\s+\{nf\} dec %r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c fe 8c 80 23 01 00 00\s+\{nf\} decb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c fe 8c 80 23 01 00 00\s+\{nf\} decb 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c ff 8c 80 23 01 00 00\s+\{nf\} decw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c ff 8c 80 23 01 00 00\s+\{nf\} decw 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c ff 8c 80 23 01 00 00\s+\{nf\} decl 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c ff 8c 80 23 01 00 00\s+\{nf\} decl 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c ff 8c 80 23 01 00 00\s+\{nf\} decq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c ff 8c 80 23 01 00 00\s+\{nf\} decq 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 f3\s+\{nf\} div %bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 f2\s+\{nf\} div %dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 f1\s+\{nf\} div %ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 f1\s+\{nf\} div %r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 b4 80 23 01 00 00\s+\{nf\} divb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 b4 80 23 01 00 00\s+\{nf\} divw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 b4 80 23 01 00 00\s+\{nf\} divl 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 b4 80 23 01 00 00\s+\{nf\} divq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 fb\s+\{nf\} idiv %bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 fa\s+\{nf\} idiv %dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 f9\s+\{nf\} idiv %ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 f9\s+\{nf\} idiv %r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 bc 80 23 01 00 00\s+\{nf\} idivb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 bc 80 23 01 00 00\s+\{nf\} idivw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 bc 80 23 01 00 00\s+\{nf\} idivl 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 bc 80 23 01 00 00\s+\{nf\} idivq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 eb\s+\{nf\} imul %bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 ea\s+\{nf\} imul %dx
+\s*[a-f0-9]+:\s*62 f4 7d 0c af c2\s+\{nf\} imul %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c af c2\s+\{nf\} imul %dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 e9\s+\{nf\} imul %ecx
+\s*[a-f0-9]+:\s*62 f4 7c 0c af d1\s+\{nf\} imul %ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c af d1\s+\{nf\} imul %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 e9\s+\{nf\} imul %r9
+\s*[a-f0-9]+:\s*62 44 fc 0c af f9\s+\{nf\} imul %r9,%r31
+\s*[a-f0-9]+:\s*62 44 a4 1c af f9\s+\{nf\} imul %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 ac 80 23 01 00 00\s+\{nf\} imulb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 ac 80 23 01 00 00\s+\{nf\} imulw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 0c af 94 80 23 01 00 00\s+\{nf\} imul 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c af 94 80 23 01 00 00\s+\{nf\} imul 0x123\(%r8,%rax,4\),%dx,%ax
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 ac 80 23 01 00 00\s+\{nf\} imull 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7c 0c af 8c 80 23 01 00 00\s+\{nf\} imul 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c af 8c 80 23 01 00 00\s+\{nf\} imul 0x123\(%r8,%rax,4\),%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 ac 80 23 01 00 00\s+\{nf\} imulq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 fc 0c af 8c 80 23 01 00 00\s+\{nf\} imul 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 54 84 14 af 8c 80 23 01 00 00\s+\{nf\} imul 0x123\(%r8,%rax,4\),%r9,%r31
+\s*[a-f0-9]+:\s*62 f4 7c 0c fe c3\s+\{nf\} inc %bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c fe c3\s+\{nf\} inc %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c ff c2\s+\{nf\} inc %dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c ff c2\s+\{nf\} inc %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c ff c1\s+\{nf\} inc %ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c ff c1\s+\{nf\} inc %ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c ff c1\s+\{nf\} inc %r9
+\s*[a-f0-9]+:\s*62 d4 84 14 ff c1\s+\{nf\} inc %r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c fe 84 80 23 01 00 00\s+\{nf\} incb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c fe 84 80 23 01 00 00\s+\{nf\} incb 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c ff 84 80 23 01 00 00\s+\{nf\} incw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c ff 84 80 23 01 00 00\s+\{nf\} incw 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c ff 84 80 23 01 00 00\s+\{nf\} incl 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c ff 84 80 23 01 00 00\s+\{nf\} incl 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c ff 84 80 23 01 00 00\s+\{nf\} incq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c ff 84 80 23 01 00 00\s+\{nf\} incq 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7d 0c f5 c2\s+\{nf\} lzcnt %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c f5 d1\s+\{nf\} lzcnt %ecx,%edx
+\s*[a-f0-9]+:\s*62 44 fc 0c f5 f9\s+\{nf\} lzcnt %r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7d 0c f5 94 80 23 01 00 00\s+\{nf\} lzcnt 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c f5 8c 80 23 01 00 00\s+\{nf\} lzcnt 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 54 fc 0c f5 8c 80 23 01 00 00\s+\{nf\} lzcnt 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 e3\s+\{nf\} mul %bl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 e2\s+\{nf\} mul %dx
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 e1\s+\{nf\} mul %ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 e1\s+\{nf\} mul %r9
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 a4 80 23 01 00 00\s+\{nf\} mulb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 a4 80 23 01 00 00\s+\{nf\} mulw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 a4 80 23 01 00 00\s+\{nf\} mull 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 a4 80 23 01 00 00\s+\{nf\} mulq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 f4 7c 0c f6 db\s+\{nf\} neg %bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c f6 db\s+\{nf\} neg %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c f7 da\s+\{nf\} neg %dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c f7 da\s+\{nf\} neg %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c f7 d9\s+\{nf\} neg %ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c f7 d9\s+\{nf\} neg %ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 d9\s+\{nf\} neg %r9
+\s*[a-f0-9]+:\s*62 d4 84 14 f7 d9\s+\{nf\} neg %r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c f6 9c 80 23 01 00 00\s+\{nf\} negb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c f6 9c 80 23 01 00 00\s+\{nf\} negb 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c f7 9c 80 23 01 00 00\s+\{nf\} negw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c f7 9c 80 23 01 00 00\s+\{nf\} negw 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c f7 9c 80 23 01 00 00\s+\{nf\} negl 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c f7 9c 80 23 01 00 00\s+\{nf\} negl 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c f7 9c 80 23 01 00 00\s+\{nf\} negq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c f7 9c 80 23 01 00 00\s+\{nf\} negq 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 cb 7b\s+\{nf\} or \$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 cb 7b\s+\{nf\} or \$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 ca 7b\s+\{nf\} or \$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 ca 7b\s+\{nf\} or \$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 c9 7b\s+\{nf\} or \$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 c9 7b\s+\{nf\} or \$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 c9 7b\s+\{nf\} or \$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 83 c9 7b\s+\{nf\} or \$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 8c 80 23 01 00 00 7b\s+\{nf\} orb \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 8c 80 23 01 00 00 7b\s+\{nf\} orb \$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 8c 80 23 01 00 00 7b\s+\{nf\} orw \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 8c 80 23 01 00 00 7b\s+\{nf\} orw \$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 8c 80 23 01 00 00 7b\s+\{nf\} orl \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 8c 80 23 01 00 00 7b\s+\{nf\} orl \$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 8c 80 23 01 00 00 7b\s+\{nf\} orq \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 8c 80 23 01 00 00 7b\s+\{nf\} orq \$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c 08 da\s+\{nf\} or %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 08 da\s+\{nf\} or %bl,%dl,%r8b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 08 9c 80 23 01 00 00\s+\{nf\} or %bl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 08 9c 80 23 01 00 00\s+\{nf\} or %bl,0x123\(%r8,%rax,4\),%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 09 d0\s+\{nf\} or %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c 09 d0\s+\{nf\} or %dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c 09 94 80 23 01 00 00\s+\{nf\} or %dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c 09 94 80 23 01 00 00\s+\{nf\} or %dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 09 ca\s+\{nf\} or %ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 09 ca\s+\{nf\} or %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c 09 8c 80 23 01 00 00\s+\{nf\} or %ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 09 8c 80 23 01 00 00\s+\{nf\} or %ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c 09 cf\s+\{nf\} or %r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c 09 cf\s+\{nf\} or %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c 09 8c 80 23 01 00 00\s+\{nf\} or %r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 09 8c 80 23 01 00 00\s+\{nf\} or %r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 0a 9c 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 0a 9c 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%bl,%dl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 0b 94 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 0b 94 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%dx,%ax
+\s*[a-f0-9]+:\s*62 d4 7c 0c 0b 8c 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 0b 8c 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%ecx,%edx
+\s*[a-f0-9]+:\s*62 54 fc 0c 0b 8c 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 54 84 14 0b 8c 80 23 01 00 00\s+\{nf\} or 0x123\(%r8,%rax,4\),%r9,%r31
+\s*[a-f0-9]+:\s*62 f4 7d 0c 88 c2\s+\{nf\} popcnt %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 88 d1\s+\{nf\} popcnt %ecx,%edx
+\s*[a-f0-9]+:\s*62 44 fc 0c 88 f9\s+\{nf\} popcnt %r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7d 0c 88 94 80 23 01 00 00\s+\{nf\} popcnt 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 88 8c 80 23 01 00 00\s+\{nf\} popcnt 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 54 fc 0c 88 8c 80 23 01 00 00\s+\{nf\} popcnt 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 c3\s+\{nf\} rol %bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 c3\s+\{nf\} rol %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 c2\s+\{nf\} rol %dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 c2\s+\{nf\} rol %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 c1\s+\{nf\} rol %ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 c1\s+\{nf\} rol %ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 c1\s+\{nf\} rol %r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 c1\s+\{nf\} rol %r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 84 80 23 01 00 00\s+\{nf\} rolb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 84 80 23 01 00 00\s+\{nf\} rolb 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 84 80 23 01 00 00\s+\{nf\} rolw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 84 80 23 01 00 00\s+\{nf\} rolw 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 84 80 23 01 00 00\s+\{nf\} roll 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 84 80 23 01 00 00\s+\{nf\} roll 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 84 80 23 01 00 00\s+\{nf\} rolq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 84 80 23 01 00 00\s+\{nf\} rolq 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 c3 7b\s+\{nf\} rol \$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 c3 7b\s+\{nf\} rol \$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 c2 7b\s+\{nf\} rol \$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 c2 7b\s+\{nf\} rol \$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 c1 7b\s+\{nf\} rol \$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 c1 7b\s+\{nf\} rol \$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 c1 7b\s+\{nf\} rol \$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 c1 7b\s+\{nf\} rol \$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 84 80 23 01 00 00 7b\s+\{nf\} rolb \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 84 80 23 01 00 00 7b\s+\{nf\} rolb \$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 84 80 23 01 00 00 7b\s+\{nf\} rolw \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 84 80 23 01 00 00 7b\s+\{nf\} rolw \$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 84 80 23 01 00 00 7b\s+\{nf\} roll \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 84 80 23 01 00 00 7b\s+\{nf\} roll \$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 84 80 23 01 00 00 7b\s+\{nf\} rolq \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 84 80 23 01 00 00 7b\s+\{nf\} rolq \$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 c3\s+\{nf\} rol %cl,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 c3\s+\{nf\} rol %cl,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 c2\s+\{nf\} rol %cl,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 c2\s+\{nf\} rol %cl,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 c1\s+\{nf\} rol %cl,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 c1\s+\{nf\} rol %cl,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 c1\s+\{nf\} rol %cl,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 c1\s+\{nf\} rol %cl,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 84 80 23 01 00 00\s+\{nf\} rolb %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 84 80 23 01 00 00\s+\{nf\} rolb %cl,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 84 80 23 01 00 00\s+\{nf\} rolw %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 84 80 23 01 00 00\s+\{nf\} rolw %cl,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 84 80 23 01 00 00\s+\{nf\} roll %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 84 80 23 01 00 00\s+\{nf\} roll %cl,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 84 80 23 01 00 00\s+\{nf\} rolq %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 84 80 23 01 00 00\s+\{nf\} rolq %cl,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 cb\s+\{nf\} ror %bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 cb\s+\{nf\} ror %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 ca\s+\{nf\} ror %dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 ca\s+\{nf\} ror %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 c9\s+\{nf\} ror %ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 c9\s+\{nf\} ror %ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 c9\s+\{nf\} ror %r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 c9\s+\{nf\} ror %r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 8c 80 23 01 00 00\s+\{nf\} rorb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 8c 80 23 01 00 00\s+\{nf\} rorb 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 8c 80 23 01 00 00\s+\{nf\} rorw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 8c 80 23 01 00 00\s+\{nf\} rorw 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 8c 80 23 01 00 00\s+\{nf\} rorl 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 8c 80 23 01 00 00\s+\{nf\} rorl 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 8c 80 23 01 00 00\s+\{nf\} rorq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 8c 80 23 01 00 00\s+\{nf\} rorq 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 cb 7b\s+\{nf\} ror \$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 cb 7b\s+\{nf\} ror \$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 ca 7b\s+\{nf\} ror \$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 ca 7b\s+\{nf\} ror \$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 c9 7b\s+\{nf\} ror \$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 c9 7b\s+\{nf\} ror \$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 c9 7b\s+\{nf\} ror \$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 c9 7b\s+\{nf\} ror \$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 8c 80 23 01 00 00 7b\s+\{nf\} rorb \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 8c 80 23 01 00 00 7b\s+\{nf\} rorb \$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 8c 80 23 01 00 00 7b\s+\{nf\} rorw \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 8c 80 23 01 00 00 7b\s+\{nf\} rorw \$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 8c 80 23 01 00 00 7b\s+\{nf\} rorl \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 8c 80 23 01 00 00 7b\s+\{nf\} rorl \$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 8c 80 23 01 00 00 7b\s+\{nf\} rorq \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 8c 80 23 01 00 00 7b\s+\{nf\} rorq \$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 cb\s+\{nf\} ror %cl,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 cb\s+\{nf\} ror %cl,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 ca\s+\{nf\} ror %cl,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 ca\s+\{nf\} ror %cl,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 c9\s+\{nf\} ror %cl,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 c9\s+\{nf\} ror %cl,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 c9\s+\{nf\} ror %cl,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 c9\s+\{nf\} ror %cl,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 8c 80 23 01 00 00\s+\{nf\} rorb %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 8c 80 23 01 00 00\s+\{nf\} rorb %cl,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 8c 80 23 01 00 00\s+\{nf\} rorw %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 8c 80 23 01 00 00\s+\{nf\} rorw %cl,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 8c 80 23 01 00 00\s+\{nf\} rorl %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 8c 80 23 01 00 00\s+\{nf\} rorl %cl,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 8c 80 23 01 00 00\s+\{nf\} rorq %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 8c 80 23 01 00 00\s+\{nf\} rorq %cl,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 fb\s+\{nf\} sar %bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 fb\s+\{nf\} sar %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 fa\s+\{nf\} sar %dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 fa\s+\{nf\} sar %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 f9\s+\{nf\} sar %ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 f9\s+\{nf\} sar %ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 f9\s+\{nf\} sar %r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 f9\s+\{nf\} sar %r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 bc 80 23 01 00 00\s+\{nf\} sarb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 bc 80 23 01 00 00\s+\{nf\} sarb 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 bc 80 23 01 00 00\s+\{nf\} sarw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 bc 80 23 01 00 00\s+\{nf\} sarw 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 bc 80 23 01 00 00\s+\{nf\} sarl 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 bc 80 23 01 00 00\s+\{nf\} sarl 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 bc 80 23 01 00 00\s+\{nf\} sarq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 bc 80 23 01 00 00\s+\{nf\} sarq 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 fb 7b\s+\{nf\} sar \$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 fb 7b\s+\{nf\} sar \$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 fa 7b\s+\{nf\} sar \$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 fa 7b\s+\{nf\} sar \$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 f9 7b\s+\{nf\} sar \$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 f9 7b\s+\{nf\} sar \$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 f9 7b\s+\{nf\} sar \$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 f9 7b\s+\{nf\} sar \$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 bc 80 23 01 00 00 7b\s+\{nf\} sarb \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 bc 80 23 01 00 00 7b\s+\{nf\} sarb \$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 bc 80 23 01 00 00 7b\s+\{nf\} sarw \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 bc 80 23 01 00 00 7b\s+\{nf\} sarw \$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 bc 80 23 01 00 00 7b\s+\{nf\} sarl \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 bc 80 23 01 00 00 7b\s+\{nf\} sarl \$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 bc 80 23 01 00 00 7b\s+\{nf\} sarq \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 bc 80 23 01 00 00 7b\s+\{nf\} sarq \$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 fb\s+\{nf\} sar %cl,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 fb\s+\{nf\} sar %cl,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 fa\s+\{nf\} sar %cl,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 fa\s+\{nf\} sar %cl,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 f9\s+\{nf\} sar %cl,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 f9\s+\{nf\} sar %cl,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 f9\s+\{nf\} sar %cl,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 f9\s+\{nf\} sar %cl,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 bc 80 23 01 00 00\s+\{nf\} sarb %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 bc 80 23 01 00 00\s+\{nf\} sarb %cl,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 bc 80 23 01 00 00\s+\{nf\} sarw %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 bc 80 23 01 00 00\s+\{nf\} sarw %cl,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 bc 80 23 01 00 00\s+\{nf\} sarl %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 bc 80 23 01 00 00\s+\{nf\} sarl %cl,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 bc 80 23 01 00 00\s+\{nf\} sarq %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 bc 80 23 01 00 00\s+\{nf\} sarq %cl,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 e3\s+\{nf\} shl %bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 e3\s+\{nf\} shl %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 e2\s+\{nf\} shl %dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 e2\s+\{nf\} shl %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 e1\s+\{nf\} shl %ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 e1\s+\{nf\} shl %ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 e1\s+\{nf\} shl %r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 e1\s+\{nf\} shl %r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 a4 80 23 01 00 00\s+\{nf\} shlb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 a4 80 23 01 00 00\s+\{nf\} shlb 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 a4 80 23 01 00 00\s+\{nf\} shlw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 a4 80 23 01 00 00\s+\{nf\} shlw 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 a4 80 23 01 00 00\s+\{nf\} shll 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 a4 80 23 01 00 00\s+\{nf\} shll 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 a4 80 23 01 00 00\s+\{nf\} shlq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 a4 80 23 01 00 00\s+\{nf\} shlq 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 e3 7b\s+\{nf\} shl \$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 e3 7b\s+\{nf\} shl \$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 e2 7b\s+\{nf\} shl \$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 e2 7b\s+\{nf\} shl \$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 e1 7b\s+\{nf\} shl \$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 e1 7b\s+\{nf\} shl \$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 e1 7b\s+\{nf\} shl \$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 e1 7b\s+\{nf\} shl \$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 a4 80 23 01 00 00 7b\s+\{nf\} shlb \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 a4 80 23 01 00 00 7b\s+\{nf\} shlb \$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shlw \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shlw \$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shll \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shll \$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 a4 80 23 01 00 00 7b\s+\{nf\} shlq \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 a4 80 23 01 00 00 7b\s+\{nf\} shlq \$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 e3\s+\{nf\} shl %cl,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 e3\s+\{nf\} shl %cl,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 e2\s+\{nf\} shl %cl,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 e2\s+\{nf\} shl %cl,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 e1\s+\{nf\} shl %cl,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 e1\s+\{nf\} shl %cl,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 e1\s+\{nf\} shl %cl,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 e1\s+\{nf\} shl %cl,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 a4 80 23 01 00 00\s+\{nf\} shlb %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 a4 80 23 01 00 00\s+\{nf\} shlb %cl,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 a4 80 23 01 00 00\s+\{nf\} shlw %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 a4 80 23 01 00 00\s+\{nf\} shlw %cl,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 a4 80 23 01 00 00\s+\{nf\} shll %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 a4 80 23 01 00 00\s+\{nf\} shll %cl,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 a4 80 23 01 00 00\s+\{nf\} shlq %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 a4 80 23 01 00 00\s+\{nf\} shlq %cl,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7d 0c 24 d0 7b\s+\{nf\} shld \$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c 24 d0 7b\s+\{nf\} shld \$0x7b,%dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c 24 94 80 23 01 00 00 7b\s+\{nf\} shld \$0x7b,%dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c 24 94 80 23 01 00 00 7b\s+\{nf\} shld \$0x7b,%dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 24 ca 7b\s+\{nf\} shld \$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 24 ca 7b\s+\{nf\} shld \$0x7b,%ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c 24 8c 80 23 01 00 00 7b\s+\{nf\} shld \$0x7b,%ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 24 8c 80 23 01 00 00 7b\s+\{nf\} shld \$0x7b,%ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c 24 cf 7b\s+\{nf\} shld \$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c 24 cf 7b\s+\{nf\} shld \$0x7b,%r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c 24 8c 80 23 01 00 00 7b\s+\{nf\} shld \$0x7b,%r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 24 8c 80 23 01 00 00 7b\s+\{nf\} shld \$0x7b,%r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 f4 7d 0c a5 d0\s+\{nf\} shld %cl,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c a5 d0\s+\{nf\} shld %cl,%dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c a5 94 80 23 01 00 00\s+\{nf\} shld %cl,%dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c a5 94 80 23 01 00 00\s+\{nf\} shld %cl,%dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c a5 ca\s+\{nf\} shld %cl,%ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c a5 ca\s+\{nf\} shld %cl,%ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c a5 8c 80 23 01 00 00\s+\{nf\} shld %cl,%ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c a5 8c 80 23 01 00 00\s+\{nf\} shld %cl,%ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c a5 cf\s+\{nf\} shld %cl,%r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c a5 cf\s+\{nf\} shld %cl,%r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c a5 8c 80 23 01 00 00\s+\{nf\} shld %cl,%r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 a5 8c 80 23 01 00 00\s+\{nf\} shld %cl,%r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 f4 7c 0c d0 eb\s+\{nf\} shr %bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d0 eb\s+\{nf\} shr %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d1 ea\s+\{nf\} shr %dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d1 ea\s+\{nf\} shr %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d1 e9\s+\{nf\} shr %ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d1 e9\s+\{nf\} shr %ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 e9\s+\{nf\} shr %r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d1 e9\s+\{nf\} shr %r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d0 ac 80 23 01 00 00\s+\{nf\} shrb 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d0 ac 80 23 01 00 00\s+\{nf\} shrb 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d1 ac 80 23 01 00 00\s+\{nf\} shrw 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d1 ac 80 23 01 00 00\s+\{nf\} shrw 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d1 ac 80 23 01 00 00\s+\{nf\} shrl 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d1 ac 80 23 01 00 00\s+\{nf\} shrl 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d1 ac 80 23 01 00 00\s+\{nf\} shrq 0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d1 ac 80 23 01 00 00\s+\{nf\} shrq 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c c0 eb 7b\s+\{nf\} shr \$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c c0 eb 7b\s+\{nf\} shr \$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c c1 ea 7b\s+\{nf\} shr \$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c c1 ea 7b\s+\{nf\} shr \$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c c1 e9 7b\s+\{nf\} shr \$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c c1 e9 7b\s+\{nf\} shr \$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 e9 7b\s+\{nf\} shr \$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 c1 e9 7b\s+\{nf\} shr \$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c c0 ac 80 23 01 00 00 7b\s+\{nf\} shrb \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c c0 ac 80 23 01 00 00 7b\s+\{nf\} shrb \$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c c1 ac 80 23 01 00 00 7b\s+\{nf\} shrw \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c c1 ac 80 23 01 00 00 7b\s+\{nf\} shrw \$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c c1 ac 80 23 01 00 00 7b\s+\{nf\} shrl \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c c1 ac 80 23 01 00 00 7b\s+\{nf\} shrl \$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c c1 ac 80 23 01 00 00 7b\s+\{nf\} shrq \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c c1 ac 80 23 01 00 00 7b\s+\{nf\} shrq \$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c d2 eb\s+\{nf\} shr %cl,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c d2 eb\s+\{nf\} shr %cl,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c d3 ea\s+\{nf\} shr %cl,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c d3 ea\s+\{nf\} shr %cl,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c d3 e9\s+\{nf\} shr %cl,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c d3 e9\s+\{nf\} shr %cl,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 e9\s+\{nf\} shr %cl,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 d3 e9\s+\{nf\} shr %cl,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c d2 ac 80 23 01 00 00\s+\{nf\} shrb %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c d2 ac 80 23 01 00 00\s+\{nf\} shrb %cl,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c d3 ac 80 23 01 00 00\s+\{nf\} shrw %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c d3 ac 80 23 01 00 00\s+\{nf\} shrw %cl,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c d3 ac 80 23 01 00 00\s+\{nf\} shrl %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c d3 ac 80 23 01 00 00\s+\{nf\} shrl %cl,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c d3 ac 80 23 01 00 00\s+\{nf\} shrq %cl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c d3 ac 80 23 01 00 00\s+\{nf\} shrq %cl,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7d 0c 2c d0 7b\s+\{nf\} shrd \$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c 2c d0 7b\s+\{nf\} shrd \$0x7b,%dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c 2c 94 80 23 01 00 00 7b\s+\{nf\} shrd \$0x7b,%dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c 2c 94 80 23 01 00 00 7b\s+\{nf\} shrd \$0x7b,%dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 2c ca 7b\s+\{nf\} shrd \$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 2c ca 7b\s+\{nf\} shrd \$0x7b,%ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd \$0x7b,%ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd \$0x7b,%ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c 2c cf 7b\s+\{nf\} shrd \$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c 2c cf 7b\s+\{nf\} shrd \$0x7b,%r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd \$0x7b,%r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 2c 8c 80 23 01 00 00 7b\s+\{nf\} shrd \$0x7b,%r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 f4 7d 0c ad d0\s+\{nf\} shrd %cl,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c ad d0\s+\{nf\} shrd %cl,%dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c ad 94 80 23 01 00 00\s+\{nf\} shrd %cl,%dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c ad 94 80 23 01 00 00\s+\{nf\} shrd %cl,%dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c ad ca\s+\{nf\} shrd %cl,%ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c ad ca\s+\{nf\} shrd %cl,%ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c ad 8c 80 23 01 00 00\s+\{nf\} shrd %cl,%ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c ad 8c 80 23 01 00 00\s+\{nf\} shrd %cl,%ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c ad cf\s+\{nf\} shrd %cl,%r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c ad cf\s+\{nf\} shrd %cl,%r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c ad 8c 80 23 01 00 00\s+\{nf\} shrd %cl,%r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 ad 8c 80 23 01 00 00\s+\{nf\} shrd %cl,%r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 eb 7b\s+\{nf\} sub \$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 eb 7b\s+\{nf\} sub \$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 ea 7b\s+\{nf\} sub \$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 ea 7b\s+\{nf\} sub \$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 e9 7b\s+\{nf\} sub \$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 e9 7b\s+\{nf\} sub \$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 e9 7b\s+\{nf\} sub \$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 83 e9 7b\s+\{nf\} sub \$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 ac 80 23 01 00 00 7b\s+\{nf\} subb \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 ac 80 23 01 00 00 7b\s+\{nf\} subb \$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 ac 80 23 01 00 00 7b\s+\{nf\} subw \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 ac 80 23 01 00 00 7b\s+\{nf\} subw \$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 ac 80 23 01 00 00 7b\s+\{nf\} subl \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 ac 80 23 01 00 00 7b\s+\{nf\} subl \$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 ac 80 23 01 00 00 7b\s+\{nf\} subq \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 ac 80 23 01 00 00 7b\s+\{nf\} subq \$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c 28 da\s+\{nf\} sub %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 28 da\s+\{nf\} sub %bl,%dl,%r8b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 28 9c 80 23 01 00 00\s+\{nf\} sub %bl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 28 9c 80 23 01 00 00\s+\{nf\} sub %bl,0x123\(%r8,%rax,4\),%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 29 d0\s+\{nf\} sub %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c 29 d0\s+\{nf\} sub %dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c 29 94 80 23 01 00 00\s+\{nf\} sub %dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c 29 94 80 23 01 00 00\s+\{nf\} sub %dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 29 ca\s+\{nf\} sub %ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 29 ca\s+\{nf\} sub %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c 29 8c 80 23 01 00 00\s+\{nf\} sub %ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 29 8c 80 23 01 00 00\s+\{nf\} sub %ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c 29 cf\s+\{nf\} sub %r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c 29 cf\s+\{nf\} sub %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c 29 8c 80 23 01 00 00\s+\{nf\} sub %r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 29 8c 80 23 01 00 00\s+\{nf\} sub %r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 2a 9c 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 2a 9c 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%bl,%dl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 2b 94 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 2b 94 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%dx,%ax
+\s*[a-f0-9]+:\s*62 d4 7c 0c 2b 8c 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 2b 8c 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%ecx,%edx
+\s*[a-f0-9]+:\s*62 54 fc 0c 2b 8c 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 54 84 14 2b 8c 80 23 01 00 00\s+\{nf\} sub 0x123\(%r8,%rax,4\),%r9,%r31
+\s*[a-f0-9]+:\s*62 f4 7d 0c f4 c2\s+\{nf\} tzcnt %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c f4 d1\s+\{nf\} tzcnt %ecx,%edx
+\s*[a-f0-9]+:\s*62 44 fc 0c f4 f9\s+\{nf\} tzcnt %r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7d 0c f4 94 80 23 01 00 00\s+\{nf\} tzcnt 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c f4 8c 80 23 01 00 00\s+\{nf\} tzcnt 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 54 fc 0c f4 8c 80 23 01 00 00\s+\{nf\} tzcnt 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c 80 f3 7b\s+\{nf\} xor \$0x7b,%bl
+\s*[a-f0-9]+:\s*62 f4 6c 1c 80 f3 7b\s+\{nf\} xor \$0x7b,%bl,%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 83 f2 7b\s+\{nf\} xor \$0x7b,%dx
+\s*[a-f0-9]+:\s*62 f4 7d 1c 83 f2 7b\s+\{nf\} xor \$0x7b,%dx,%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 83 f1 7b\s+\{nf\} xor \$0x7b,%ecx
+\s*[a-f0-9]+:\s*62 f4 6c 1c 83 f1 7b\s+\{nf\} xor \$0x7b,%ecx,%edx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 f1 7b\s+\{nf\} xor \$0x7b,%r9
+\s*[a-f0-9]+:\s*62 d4 84 14 83 f1 7b\s+\{nf\} xor \$0x7b,%r9,%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 80 b4 80 23 01 00 00 7b\s+\{nf\} xorb \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 64 1c 80 b4 80 23 01 00 00 7b\s+\{nf\} xorb \$0x7b,0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 83 b4 80 23 01 00 00 7b\s+\{nf\} xorw \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6d 1c 83 b4 80 23 01 00 00 7b\s+\{nf\} xorw \$0x7b,0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7c 0c 83 b4 80 23 01 00 00 7b\s+\{nf\} xorl \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 74 1c 83 b4 80 23 01 00 00 7b\s+\{nf\} xorl \$0x7b,0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 fc 0c 83 b4 80 23 01 00 00 7b\s+\{nf\} xorq \$0x7b,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 b4 1c 83 b4 80 23 01 00 00 7b\s+\{nf\} xorq \$0x7b,0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 f4 7c 0c 30 da\s+\{nf\} xor %bl,%dl
+\s*[a-f0-9]+:\s*62 f4 3c 1c 30 da\s+\{nf\} xor %bl,%dl,%r8b
+\s*[a-f0-9]+:\s*62 d4 7c 0c 30 9c 80 23 01 00 00\s+\{nf\} xor %bl,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 30 9c 80 23 01 00 00\s+\{nf\} xor %bl,0x123\(%r8,%rax,4\),%dl
+\s*[a-f0-9]+:\s*62 f4 7d 0c 31 d0\s+\{nf\} xor %dx,%ax
+\s*[a-f0-9]+:\s*62 f4 35 1c 31 d0\s+\{nf\} xor %dx,%ax,%r9w
+\s*[a-f0-9]+:\s*62 d4 7d 0c 31 94 80 23 01 00 00\s+\{nf\} xor %dx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 7d 1c 31 94 80 23 01 00 00\s+\{nf\} xor %dx,0x123\(%r8,%rax,4\),%ax
+\s*[a-f0-9]+:\s*62 f4 7c 0c 31 ca\s+\{nf\} xor %ecx,%edx
+\s*[a-f0-9]+:\s*62 f4 2c 1c 31 ca\s+\{nf\} xor %ecx,%edx,%r10d
+\s*[a-f0-9]+:\s*62 d4 7c 0c 31 8c 80 23 01 00 00\s+\{nf\} xor %ecx,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 d4 6c 1c 31 8c 80 23 01 00 00\s+\{nf\} xor %ecx,0x123\(%r8,%rax,4\),%edx
+\s*[a-f0-9]+:\s*62 5c fc 0c 31 cf\s+\{nf\} xor %r9,%r31
+\s*[a-f0-9]+:\s*62 5c a4 1c 31 cf\s+\{nf\} xor %r9,%r31,%r11
+\s*[a-f0-9]+:\s*62 54 fc 0c 31 8c 80 23 01 00 00\s+\{nf\} xor %r9,0x123\(%r8,%rax,4\)
+\s*[a-f0-9]+:\s*62 54 84 14 31 8c 80 23 01 00 00\s+\{nf\} xor %r9,0x123\(%r8,%rax,4\),%r31
+\s*[a-f0-9]+:\s*62 d4 7c 0c 32 9c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%bl
+\s*[a-f0-9]+:\s*62 d4 6c 1c 32 9c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%bl,%dl
+\s*[a-f0-9]+:\s*62 d4 7d 0c 33 94 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%dx
+\s*[a-f0-9]+:\s*62 d4 7d 1c 33 94 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%dx,%ax
+\s*[a-f0-9]+:\s*62 d4 7c 0c 33 8c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%ecx
+\s*[a-f0-9]+:\s*62 d4 6c 1c 33 8c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%ecx,%edx
+\s*[a-f0-9]+:\s*62 54 fc 0c 33 8c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%r9
+\s*[a-f0-9]+:\s*62 54 84 14 33 8c 80 23 01 00 00\s+\{nf\} xor 0x123\(%r8,%rax,4\),%r9,%r31
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-apx-nf.s b/gas/testsuite/gas/i386/x86-64-apx-nf.s
new file mode 100644
index 00000000000..1016dcfdd27
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-apx-nf.s
@@ -0,0 +1,1256 @@
+# Check 64bit APX_F instructions
+
+ .text
+_start:
+ {nf} add $123, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add $123, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add $123, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add $123, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add $123, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add $123, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add $123, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add $123, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} addb $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} addb $123, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} addw $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} addw $123, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} addl $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} addl $123, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} addq $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} addq $123, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add %bl, %dl, %r8b #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add %bl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add %bl, 291(%r8, %rax, 4), %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add %dx, %ax, %r9w #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add %dx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add %dx, 291(%r8, %rax, 4), %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add %ecx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add %ecx, 291(%r8, %rax, 4), %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add %r9, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add %r9, 291(%r8, %rax, 4), %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add 291(%r8, %rax, 4), %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add 291(%r8, %rax, 4), %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add 291(%r8, %rax, 4), %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add 291(%r8, %rax, 4), %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and $123, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and $123, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and $123, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and $123, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and $123, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and $123, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and $123, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and $123, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} andb $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} andb $123, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} andw $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} andw $123, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} andl $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} andl $123, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} andq $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} andq $123, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and %bl, %dl, %r8b #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and %bl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and %bl, 291(%r8, %rax, 4), %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and %dx, %ax, %r9w #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and %dx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and %dx, 291(%r8, %rax, 4), %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and %ecx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and %ecx, 291(%r8, %rax, 4), %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and %r9, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and %r9, 291(%r8, %rax, 4), %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and 291(%r8, %rax, 4), %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and 291(%r8, %rax, 4), %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and 291(%r8, %rax, 4), %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and 291(%r8, %rax, 4), %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} andn %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} andn %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} andn 291(%r8, %rax, 4), %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} andn 291(%r8, %rax, 4), %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} bextr %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} bextr %ecx, 291(%r8, %rax, 4), %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} bextr %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} bextr %r9, 291(%r8, %rax, 4), %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} blsi %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} blsi %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} blsi 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} blsi 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} blsmsk %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} blsmsk %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} blsmsk 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} blsmsk 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} blsr %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} blsr %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} blsr 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} blsr 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} bzhi %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} bzhi %ecx, 291(%r8, %rax, 4), %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} bzhi %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} bzhi %r9, 291(%r8, %rax, 4), %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} dec %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} dec %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} dec %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} dec %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} dec %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} dec %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} dec %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} dec %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} decb 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} decb 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} decw 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} decw 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} decl 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} decl 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} decq 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} decq 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} div %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} div %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} div %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} div %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} divb 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} divw 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} divl 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} divq 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} idiv %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} idiv %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} idiv %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} idiv %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} idivb 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} idivw 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} idivl 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} idivq 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul %dx, %ax, %r9w #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} imul %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} imul %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} imulb 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imulw 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul 291(%r8, %rax, 4), %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} imull 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul 291(%r8, %rax, 4), %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} imulq 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul 291(%r8, %rax, 4), %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} inc %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} inc %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} inc %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} inc %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} inc %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} inc %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} inc %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} inc %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} incb 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} incb 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} incw 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} incw 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} incl 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} incl 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} incq 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} incq 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} lzcnt %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} lzcnt %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} lzcnt %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} lzcnt 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} lzcnt 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} lzcnt 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} mul %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} mul %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} mul %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} mul %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} mulb 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} mulw 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} mull 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} mulq 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} neg %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} neg %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} neg %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} neg %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} neg %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} neg %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} neg %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} neg %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} negb 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} negb 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} negw 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} negw 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} negl 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} negl 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} negq 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} negq 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or $123, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or $123, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or $123, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or $123, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or $123, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or $123, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or $123, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or $123, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} orb $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} orb $123, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} orw $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} orw $123, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} orl $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} orl $123, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} orq $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} orq $123, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or %bl, %dl, %r8b #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or %bl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or %bl, 291(%r8, %rax, 4), %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or %dx, %ax, %r9w #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or %dx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or %dx, 291(%r8, %rax, 4), %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or %ecx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or %ecx, 291(%r8, %rax, 4), %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or %r9, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or %r9, 291(%r8, %rax, 4), %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or 291(%r8, %rax, 4), %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or 291(%r8, %rax, 4), %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or 291(%r8, %rax, 4), %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or 291(%r8, %rax, 4), %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} popcnt %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} popcnt %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} popcnt %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} popcnt 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} popcnt 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} popcnt 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol $1, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol $1, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol $1, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol $1, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol $1, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol $1, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol $1, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol $1, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rolb $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rolb $1, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rolw $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rolw $1, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} roll $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} roll $1, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rolq $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rolq $1, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol $123, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol $123, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol $123, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol $123, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol $123, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol $123, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol $123, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol $123, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rolb $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rolb $123, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rolw $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rolw $123, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} roll $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} roll $123, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rolq $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rolq $123, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol %cl, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol %cl, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol %cl, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol %cl, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol %cl, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol %cl, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol %cl, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol %cl, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rolb %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rolb %cl, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rolw %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rolw %cl, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} roll %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} roll %cl, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rolq %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rolq %cl, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror $1, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror $1, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror $1, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror $1, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror $1, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror $1, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror $1, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror $1, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rorb $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rorb $1, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rorw $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rorw $1, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rorl $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rorl $1, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rorq $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rorq $1, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror $123, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror $123, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror $123, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror $123, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror $123, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror $123, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror $123, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror $123, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rorb $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rorb $123, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rorw $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rorw $123, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rorl $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rorl $123, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rorq $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rorq $123, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror %cl, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror %cl, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror %cl, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror %cl, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror %cl, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror %cl, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror %cl, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror %cl, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rorb %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rorb %cl, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rorw %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rorw %cl, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rorl %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rorl %cl, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rorq %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rorq %cl, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar $1, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar $1, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar $1, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar $1, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar $1, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar $1, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar $1, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar $1, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sarb $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sarb $1, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sarw $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sarw $1, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sarl $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sarl $1, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sarq $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sarq $1, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar $123, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar $123, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar $123, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar $123, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar $123, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar $123, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar $123, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar $123, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sarb $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sarb $123, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sarw $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sarw $123, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sarl $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sarl $123, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sarq $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sarq $123, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar %cl, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar %cl, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar %cl, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar %cl, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar %cl, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar %cl, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar %cl, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar %cl, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sarb %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sarb %cl, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sarw %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sarw %cl, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sarl %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sarl %cl, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sarq %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sarq %cl, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl $1, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl $1, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl $1, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl $1, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl $1, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl $1, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl $1, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl $1, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shlb $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shlb $1, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shlw $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shlw $1, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shll $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shll $1, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shlq $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shlq $1, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl $123, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl $123, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl $123, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl $123, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl $123, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl $123, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl $123, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl $123, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shlb $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shlb $123, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shlw $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shlw $123, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shll $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shll $123, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shlq $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shlq $123, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl %cl, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl %cl, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl %cl, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl %cl, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl %cl, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl %cl, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl %cl, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl %cl, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shlb %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shlb %cl, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shlw %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shlw %cl, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shll %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shll %cl, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shlq %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shlq %cl, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shld $123, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shld $123, %dx, %ax, %r9w #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shld $123, %dx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shld $123, %dx, 291(%r8, %rax, 4), %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shld $123, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shld $123, %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shld $123, %ecx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shld $123, %ecx, 291(%r8, %rax, 4), %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shld $123, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shld $123, %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shld $123, %r9, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shld $123, %r9, 291(%r8, %rax, 4), %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shld %cl, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shld %cl, %dx, %ax, %r9w #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shld %cl, %dx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shld %cl, %dx, 291(%r8, %rax, 4), %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shld %cl, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shld %cl, %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shld %cl, %ecx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shld %cl, %ecx, 291(%r8, %rax, 4), %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shld %cl, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shld %cl, %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shld %cl, %r9, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shld %cl, %r9, 291(%r8, %rax, 4), %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr $1, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr $1, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr $1, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr $1, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr $1, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr $1, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr $1, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr $1, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrb $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrb $1, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrw $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrw $1, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrl $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrl $1, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrq $1, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrq $1, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr $123, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr $123, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr $123, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr $123, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr $123, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr $123, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr $123, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr $123, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrb $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrb $123, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrw $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrw $123, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrl $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrl $123, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrq $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrq $123, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr %cl, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr %cl, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr %cl, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr %cl, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr %cl, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr %cl, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr %cl, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr %cl, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrb %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrb %cl, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrw %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrw %cl, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrl %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrl %cl, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrq %cl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrq %cl, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrd $123, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrd $123, %dx, %ax, %r9w #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrd $123, %dx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrd $123, %dx, 291(%r8, %rax, 4), %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrd $123, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrd $123, %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrd $123, %ecx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrd $123, %ecx, 291(%r8, %rax, 4), %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrd $123, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrd $123, %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrd $123, %r9, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrd $123, %r9, 291(%r8, %rax, 4), %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrd %cl, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrd %cl, %dx, %ax, %r9w #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrd %cl, %dx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrd %cl, %dx, 291(%r8, %rax, 4), %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrd %cl, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrd %cl, %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrd %cl, %ecx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrd %cl, %ecx, 291(%r8, %rax, 4), %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrd %cl, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrd %cl, %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrd %cl, %r9, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrd %cl, %r9, 291(%r8, %rax, 4), %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub $123, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub $123, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub $123, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub $123, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub $123, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub $123, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub $123, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub $123, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} subb $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} subb $123, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} subw $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} subw $123, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} subl $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} subl $123, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} subq $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} subq $123, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub %bl, %dl, %r8b #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub %bl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub %bl, 291(%r8, %rax, 4), %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub %dx, %ax, %r9w #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub %dx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub %dx, 291(%r8, %rax, 4), %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub %ecx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub %ecx, 291(%r8, %rax, 4), %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub %r9, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub %r9, 291(%r8, %rax, 4), %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub 291(%r8, %rax, 4), %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub 291(%r8, %rax, 4), %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub 291(%r8, %rax, 4), %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub 291(%r8, %rax, 4), %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} tzcnt %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} tzcnt %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} tzcnt %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} tzcnt 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} tzcnt 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} tzcnt 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor $123, %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor $123, %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor $123, %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor $123, %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor $123, %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor $123, %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor $123, %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor $123, %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xorb $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xorb $123, 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xorw $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xorw $123, 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xorl $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xorl $123, 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xorq $123, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xorq $123, 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor %bl, %dl, %r8b #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor %bl, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor %bl, 291(%r8, %rax, 4), %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor %dx, %ax, %r9w #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor %dx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor %dx, 291(%r8, %rax, 4), %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor %ecx, %edx, %r10d #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor %ecx, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor %ecx, 291(%r8, %rax, 4), %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor %r9, %r31, %r11 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor %r9, 291(%r8, %rax, 4) #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor %r9, 291(%r8, %rax, 4), %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor 291(%r8, %rax, 4), %bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor 291(%r8, %rax, 4), %bl, %dl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor 291(%r8, %rax, 4), %dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor 291(%r8, %rax, 4), %dx, %ax #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor 291(%r8, %rax, 4), %ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor 291(%r8, %rax, 4), %ecx, %edx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor 291(%r8, %rax, 4), %r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor 291(%r8, %rax, 4), %r9, %r31 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+
+.intel_syntax noprefix
+ {nf} add bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add dl, bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add bl, BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add dx, WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add ecx, DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add r9, QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add r8b, dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add BYTE PTR [r8+rax*4+291], bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add dl, BYTE PTR [r8+rax*4+291], bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add r9w, ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add WORD PTR [r8+rax*4+291], dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add ax, WORD PTR [r8+rax*4+291], dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add r10d, edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add DWORD PTR [r8+rax*4+291], ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add edx, DWORD PTR [r8+rax*4+291], ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add r11, r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add QWORD PTR [r8+rax*4+291], r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add r31, QWORD PTR [r8+rax*4+291], r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add dl, bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add ax, dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add edx, ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} add r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} add r31, r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and dl, bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and bl, BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and dx, WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and ecx, DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and r9, QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and r8b, dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and BYTE PTR [r8+rax*4+291], bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and dl, BYTE PTR [r8+rax*4+291], bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and r9w, ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and WORD PTR [r8+rax*4+291], dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and ax, WORD PTR [r8+rax*4+291], dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and r10d, edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and DWORD PTR [r8+rax*4+291], ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and edx, DWORD PTR [r8+rax*4+291], ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and r11, r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and QWORD PTR [r8+rax*4+291], r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and r31, QWORD PTR [r8+rax*4+291], r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and dl, bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and ax, dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and edx, ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} and r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} and r31, r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} andn r10d, edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} andn r11, r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} andn edx, ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} andn r31, r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} bextr r10d, edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} bextr edx, DWORD PTR [r8+rax*4+291], ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} bextr r11, r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} bextr r31, QWORD PTR [r8+rax*4+291], r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} blsi edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} blsi r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} blsi ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} blsi r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} blsmsk edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} blsmsk r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} blsmsk ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} blsmsk r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} blsr edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} blsr r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} blsr ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} blsr r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} bzhi r10d, edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} bzhi edx, DWORD PTR [r8+rax*4+291], ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} bzhi r11, r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} bzhi r31, QWORD PTR [r8+rax*4+291], r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} dec bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} dec dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} dec dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} dec ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} dec ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} dec edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} dec r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} dec r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} dec BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} dec bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} dec WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} dec dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} dec DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} dec ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} dec QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} dec r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} div bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} div dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} div ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} div r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} div BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} div WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} div DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} div QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} idiv bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} idiv dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} idiv ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} idiv r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} idiv BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} idiv WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} idiv DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} idiv QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul ax, dx, 123 #APX_F OPC_EVEX_NF
+ {nf} imul edx, ecx, 123 #APX_F OPC_EVEX_NF
+ {nf} imul r31, r9, 123 #APX_F OPC_EVEX_NF
+ {nf} imul dx, WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF
+ {nf} imul ecx, DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF
+ {nf} imul r9, QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF
+ {nf} imul bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul r9w, ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} imul ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul r10d, edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} imul r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul r11, r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} imul BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul ax, dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} imul DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul edx, ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} imul QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} imul r31, r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} inc bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} inc dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} inc dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} inc ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} inc ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} inc edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} inc r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} inc r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} inc BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} inc bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} inc WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} inc dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} inc DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} inc ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} inc QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} inc r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} lzcnt ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} lzcnt edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} lzcnt r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} lzcnt dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} lzcnt ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} lzcnt r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} mul bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} mul dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} mul ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} mul r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} mul BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} mul WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} mul DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} mul QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} neg bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} neg dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} neg dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} neg ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} neg ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} neg edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} neg r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} neg r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} neg BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} neg bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} neg WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} neg dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} neg DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} neg ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} neg QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} neg r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or dl, bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or bl, BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or dx, WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or ecx, DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or r9, QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or r8b, dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or BYTE PTR [r8+rax*4+291], bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or dl, BYTE PTR [r8+rax*4+291], bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or r9w, ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or WORD PTR [r8+rax*4+291], dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or ax, WORD PTR [r8+rax*4+291], dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or r10d, edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or DWORD PTR [r8+rax*4+291], ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or edx, DWORD PTR [r8+rax*4+291], ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or r11, r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or QWORD PTR [r8+rax*4+291], r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or r31, QWORD PTR [r8+rax*4+291], r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or dl, bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or ax, dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or edx, ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} or r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} or r31, r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} popcnt ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} popcnt edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} popcnt r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} popcnt dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} popcnt ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} popcnt r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol bl, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol dl, bl, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol dx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol ax, dx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol ecx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol edx, ecx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol r9, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol r31, r9, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol BYTE PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol bl, BYTE PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol WORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol dx, WORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol DWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol ecx, DWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol QWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol r9, QWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol dl, bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol bl, BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol dx, WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol ecx, DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol r9, QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol bl, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol dl, bl, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol ax, dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol edx, ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol r31, r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol BYTE PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol bl, BYTE PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol WORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol dx, WORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol DWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol ecx, DWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} rol QWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} rol r9, QWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror bl, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror dl, bl, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror dx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror ax, dx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror ecx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror edx, ecx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror r9, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror r31, r9, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror BYTE PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror bl, BYTE PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror WORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror dx, WORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror DWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror ecx, DWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror QWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror r9, QWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror dl, bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror bl, BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror dx, WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror ecx, DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror r9, QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror bl, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror dl, bl, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror ax, dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror edx, ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror r31, r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror BYTE PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror bl, BYTE PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror WORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror dx, WORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror DWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror ecx, DWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} ror QWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} ror r9, QWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar bl, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar dl, bl, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar dx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar ax, dx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar ecx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar edx, ecx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar r9, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar r31, r9, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar BYTE PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar bl, BYTE PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar WORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar dx, WORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar DWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar ecx, DWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar QWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar r9, QWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar dl, bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar bl, BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar dx, WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar ecx, DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar r9, QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar bl, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar dl, bl, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar ax, dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar edx, ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar r31, r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar BYTE PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar bl, BYTE PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar WORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar dx, WORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar DWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar ecx, DWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sar QWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sar r9, QWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl bl, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl dl, bl, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl dx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl ax, dx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl ecx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl edx, ecx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl r9, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl r31, r9, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl BYTE PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl bl, BYTE PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl WORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl dx, WORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl DWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl ecx, DWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl QWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl r9, QWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl dl, bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl bl, BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl dx, WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl ecx, DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl r9, QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl bl, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl dl, bl, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl ax, dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl edx, ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl r31, r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl BYTE PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl bl, BYTE PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl WORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl dx, WORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl DWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl ecx, DWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shl QWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shl r9, QWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shld ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shld r9w, ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shld WORD PTR [r8+rax*4+291], dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shld ax, WORD PTR [r8+rax*4+291], dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shld edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shld r10d, edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shld DWORD PTR [r8+rax*4+291], ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shld edx, DWORD PTR [r8+rax*4+291], ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shld r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shld r11, r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shld QWORD PTR [r8+rax*4+291], r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shld r31, QWORD PTR [r8+rax*4+291], r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shld ax, dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shld r9w, ax, dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shld WORD PTR [r8+rax*4+291], dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shld ax, WORD PTR [r8+rax*4+291], dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shld edx, ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shld r10d, edx, ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shld DWORD PTR [r8+rax*4+291], ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shld edx, DWORD PTR [r8+rax*4+291], ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shld r31, r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shld r11, r31, r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shld QWORD PTR [r8+rax*4+291], r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shld r31, QWORD PTR [r8+rax*4+291], r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr bl, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr dl, bl, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr dx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr ax, dx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr ecx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr edx, ecx, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr r9, 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr r31, r9, 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr BYTE PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr bl, BYTE PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr WORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr dx, WORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr DWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr ecx, DWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr QWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr r9, QWORD PTR [r8+rax*4+291], 1 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr dl, bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr bl, BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr dx, WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr ecx, DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr r9, QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr bl, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr dl, bl, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr ax, dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr edx, ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr r31, r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr BYTE PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr bl, BYTE PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr WORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr dx, WORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr DWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr ecx, DWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shr QWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shr r9, QWORD PTR [r8+rax*4+291], cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrd ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrd r9w, ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrd WORD PTR [r8+rax*4+291], dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrd ax, WORD PTR [r8+rax*4+291], dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrd edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrd r10d, edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrd DWORD PTR [r8+rax*4+291], ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrd edx, DWORD PTR [r8+rax*4+291], ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrd r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrd r11, r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrd QWORD PTR [r8+rax*4+291], r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrd r31, QWORD PTR [r8+rax*4+291], r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrd ax, dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrd r9w, ax, dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrd WORD PTR [r8+rax*4+291], dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrd ax, WORD PTR [r8+rax*4+291], dx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrd edx, ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrd r10d, edx, ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrd DWORD PTR [r8+rax*4+291], ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrd edx, DWORD PTR [r8+rax*4+291], ecx, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrd r31, r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrd r11, r31, r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} shrd QWORD PTR [r8+rax*4+291], r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} shrd r31, QWORD PTR [r8+rax*4+291], r9, cl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub dl, bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub bl, BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub dx, WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub ecx, DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub r9, QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub r8b, dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub BYTE PTR [r8+rax*4+291], bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub dl, BYTE PTR [r8+rax*4+291], bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub r9w, ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub WORD PTR [r8+rax*4+291], dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub ax, WORD PTR [r8+rax*4+291], dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub r10d, edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub DWORD PTR [r8+rax*4+291], ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub edx, DWORD PTR [r8+rax*4+291], ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub r11, r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub QWORD PTR [r8+rax*4+291], r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub r31, QWORD PTR [r8+rax*4+291], r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub dl, bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub ax, dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub edx, ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} sub r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} sub r31, r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} tzcnt ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} tzcnt edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} tzcnt r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} tzcnt dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} tzcnt ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} tzcnt r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor dl, bl, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor ax, dx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor edx, ecx, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor r31, r9, 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor bl, BYTE PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor dx, WORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor ecx, DWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor r9, QWORD PTR [r8+rax*4+291], 123 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor r8b, dl, bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor BYTE PTR [r8+rax*4+291], bl #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor dl, BYTE PTR [r8+rax*4+291], bl #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor r9w, ax, dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor WORD PTR [r8+rax*4+291], dx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor ax, WORD PTR [r8+rax*4+291], dx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor r10d, edx, ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor DWORD PTR [r8+rax*4+291], ecx #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor edx, DWORD PTR [r8+rax*4+291], ecx #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor r11, r31, r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor QWORD PTR [r8+rax*4+291], r9 #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor r31, QWORD PTR [r8+rax*4+291], r9 #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor dl, bl, BYTE PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor ax, dx, WORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor edx, ecx, DWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
+ {nf} xor r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_EVEX
+ {nf} xor r31, r9, QWORD PTR [r8+rax*4+291] #APX_F OPC_EVEX_NF OPC_EVEX_ND
diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp
index 2d3a0387497..9aaa905393b 100644
--- a/gas/testsuite/gas/i386/x86-64.exp
+++ b/gas/testsuite/gas/i386/x86-64.exp
@@ -372,6 +372,8 @@ run_dump_test "x86-64-apx-evex-promoted"
run_dump_test "x86-64-apx-evex-promoted-intel"
run_dump_test "x86-64-apx-evex-egpr"
run_dump_test "x86-64-apx-ndd"
+run_dump_test "x86-64-apx-nf"
+run_dump_test "x86-64-apx-nf-intel"
run_dump_test "x86-64-avx512f-rcigrz-intel"
run_dump_test "x86-64-avx512f-rcigrz"
run_dump_test "x86-64-clwb"
diff --git a/opcodes/i386-dis-evex-len.h b/opcodes/i386-dis-evex-len.h
index 7c9b921bf6b..060ba3afb6c 100644
--- a/opcodes/i386-dis-evex-len.h
+++ b/opcodes/i386-dis-evex-len.h
@@ -64,7 +64,7 @@ static const struct dis386 evex_len_table[][3] = {
/* EVEX_LEN_0F38F2 */
{
- { "andnS", { Gdq, VexGdq, Edq }, 0 },
+ { "%XNandnS", { Gdq, VexGdq, Edq }, 0 },
},
/* EVEX_LEN_0F38F3 */
diff --git a/opcodes/i386-dis-evex-reg.h b/opcodes/i386-dis-evex-reg.h
index f9d313a78e1..109b43334ad 100644
--- a/opcodes/i386-dis-evex-reg.h
+++ b/opcodes/i386-dis-evex-reg.h
@@ -52,41 +52,41 @@
/* REG_EVEX_0F38F3_L_0 */
{
{ Bad_Opcode },
- { "blsrS", { VexGdq, Edq }, 0 },
- { "blsmskS", { VexGdq, Edq }, 0 },
- { "blsiS", { VexGdq, Edq }, 0 },
+ { "%XNblsrS", { VexGdq, Edq }, 0 },
+ { "%XNblsmskS", { VexGdq, Edq }, 0 },
+ { "%XNblsiS", { VexGdq, Edq }, 0 },
},
/* REG_EVEX_MAP4_80 */
{
- { "addA", { VexGb, Eb, Ib }, 0 },
- { "orA", { VexGb, Eb, Ib }, 0 },
+ { "%XNaddA", { VexGb, Eb, Ib }, 0 },
+ { "%XNorA", { VexGb, Eb, Ib }, 0 },
{ "adcA", { VexGb, Eb, Ib }, 0 },
{ "sbbA", { VexGb, Eb, Ib }, 0 },
- { "andA", { VexGb, Eb, Ib }, 0 },
- { "subA", { VexGb, Eb, Ib }, 0 },
- { "xorA", { VexGb, Eb, Ib }, 0 },
+ { "%XNandA", { VexGb, Eb, Ib }, 0 },
+ { "%XNsubA", { VexGb, Eb, Ib }, 0 },
+ { "%XNxorA", {VexGb, Eb, Ib }, 0 },
{ Bad_Opcode },
},
/* REG_EVEX_MAP4_81 */
{
- { "addQ", { VexGv, Ev, Iv }, 0 },
- { "orQ", { VexGv, Ev, Iv }, 0 },
+ { "%XNaddQ", { VexGv, Ev, Iv }, 0 },
+ { "%XNorQ", { VexGv, Ev, Iv }, 0 },
{ "adcQ", { VexGv, Ev, Iv }, 0 },
{ "sbbQ", { VexGv, Ev, Iv }, 0 },
- { "andQ", { VexGv, Ev, Iv }, 0 },
- { "subQ", { VexGv, Ev, Iv }, 0 },
- { "xorQ", { VexGv, Ev, Iv }, 0 },
+ { "%XNandQ", { VexGv, Ev, Iv }, 0 },
+ { "%XNsubQ", { VexGv, Ev, Iv }, 0 },
+ { "%XNxorQ", { VexGv, Ev, Iv }, 0 },
{ Bad_Opcode },
},
/* REG_EVEX_MAP4_83 */
{
- { "addQ", { VexGv, Ev, sIb }, 0 },
- { "orQ", { VexGv, Ev, sIb }, 0 },
+ { "%XNaddQ", { VexGv, Ev, sIb }, 0 },
+ { "%XNorQ", { VexGv, Ev, sIb }, 0 },
{ "adcQ", { VexGv, Ev, sIb }, 0 },
{ "sbbQ", { VexGv, Ev, sIb }, 0 },
- { "andQ", { VexGv, Ev, sIb }, 0 },
- { "subQ", { VexGv, Ev, sIb }, 0 },
- { "xorQ", { VexGv, Ev, sIb }, 0 },
+ { "%XNandQ", { VexGv, Ev, sIb }, 0 },
+ { "%XNsubQ", { VexGv, Ev, sIb }, 0 },
+ { "%XNxorQ", { VexGv, Ev, sIb }, 0 },
{ Bad_Opcode },
},
/* REG_EVEX_MAP4_8F_X86_64_L_0_M_1 */
@@ -95,69 +95,69 @@
},
/* REG_EVEX_MAP4_C0 */
{
- { "rolA", { VexGb, Eb, Ib }, 0 },
- { "rorA", { VexGb, Eb, Ib }, 0 },
+ { "%XNrolA", { VexGb, Eb, Ib }, 0 },
+ { "%XNrorA", { VexGb, Eb, Ib }, 0 },
{ "rclA", { VexGb, Eb, Ib }, 0 },
{ "rcrA", { VexGb, Eb, Ib }, 0 },
- { "shlA", { VexGb, Eb, Ib }, 0 },
- { "shrA", { VexGb, Eb, Ib }, 0 },
- { "shlA", { VexGb, Eb, Ib }, 0 },
- { "sarA", { VexGb, Eb, Ib }, 0 },
+ { "%XNshlA", { VexGb, Eb, Ib }, 0 },
+ { "%XNshrA", { VexGb, Eb, Ib }, 0 },
+ { "%XNshlA", { VexGb, Eb, Ib }, 0 },
+ { "%XNsarA", { VexGb, Eb, Ib }, 0 },
},
/* REG_EVEX_MAP4_C1 */
{
- { "rolQ", { VexGv, Ev, Ib }, 0 },
- { "rorQ", { VexGv, Ev, Ib }, 0 },
+ { "%XNrolQ", { VexGv, Ev, Ib }, 0 },
+ { "%XNrorQ", { VexGv, Ev, Ib }, 0 },
{ "rclQ", { VexGv, Ev, Ib }, 0 },
{ "rcrQ", { VexGv, Ev, Ib }, 0 },
- { "shlQ", { VexGv, Ev, Ib }, 0 },
- { "shrQ", { VexGv, Ev, Ib }, 0 },
- { "shlQ", { VexGv, Ev, Ib }, 0 },
- { "sarQ", { VexGv, Ev, Ib }, 0 },
+ { "%XNshlQ", { VexGv, Ev, Ib }, 0 },
+ { "%XNshrQ", { VexGv, Ev, Ib }, 0 },
+ { "%XNshlQ", { VexGv, Ev, Ib }, 0 },
+ { "%XNsarQ", { VexGv, Ev, Ib }, 0 },
},
/* REG_EVEX_MAP4_D0 */
{
- { "rolA", { VexGb, Eb, I1 }, 0 },
- { "rorA", { VexGb, Eb, I1 }, 0 },
+ { "%XNrolA", { VexGb, Eb, I1 }, 0 },
+ { "%XNrorA", { VexGb, Eb, I1 }, 0 },
{ "rclA", { VexGb, Eb, I1 }, 0 },
{ "rcrA", { VexGb, Eb, I1 }, 0 },
- { "shlA", { VexGb, Eb, I1 }, 0 },
- { "shrA", { VexGb, Eb, I1 }, 0 },
- { "shlA", { VexGb, Eb, I1 }, 0 },
- { "sarA", { VexGb, Eb, I1 }, 0 },
+ { "%XNshlA", { VexGb, Eb, I1 }, 0 },
+ { "%XNshrA", { VexGb, Eb, I1 }, 0 },
+ { "%XNshlA", { VexGb, Eb, I1 }, 0 },
+ { "%XNsarA", { VexGb, Eb, I1 }, 0 },
},
/* REG_EVEX_MAP4_D1 */
{
- { "rolQ", { VexGv, Ev, I1 }, 0 },
- { "rorQ", { VexGv, Ev, I1 }, 0 },
+ { "%XNrolQ", { VexGv, Ev, I1 }, 0 },
+ { "%XNrorQ", { VexGv, Ev, I1 }, 0 },
{ "rclQ", { VexGv, Ev, I1 }, 0 },
{ "rcrQ", { VexGv, Ev, I1 }, 0 },
- { "shlQ", { VexGv, Ev, I1 }, 0 },
- { "shrQ", { VexGv, Ev, I1 }, 0 },
- { "shlQ", { VexGv, Ev, I1 }, 0 },
- { "sarQ", { VexGv, Ev, I1 }, 0 },
+ { "%XNshlQ", { VexGv, Ev, I1 }, 0 },
+ { "%XNshrQ", { VexGv, Ev, I1 }, 0 },
+ { "%XNshlQ", { VexGv, Ev, I1 }, 0 },
+ { "%XNsarQ", { VexGv, Ev, I1 }, 0 },
},
/* REG_EVEX_MAP4_D2 */
{
- { "rolA", { VexGb, Eb, CL }, 0 },
- { "rorA", { VexGb, Eb, CL }, 0 },
+ { "%XNrolA", { VexGb, Eb, CL }, 0 },
+ { "%XNrorA", { VexGb, Eb, CL }, 0 },
{ "rclA", { VexGb, Eb, CL }, 0 },
{ "rcrA", { VexGb, Eb, CL }, 0 },
- { "shlA", { VexGb, Eb, CL }, 0 },
- { "shrA", { VexGb, Eb, CL }, 0 },
- { "shlA", { VexGb, Eb, CL }, 0 },
- { "sarA", { VexGb, Eb, CL }, 0 },
+ { "%XNshlA", { VexGb, Eb, CL }, 0 },
+ { "%XNshrA", { VexGb, Eb, CL }, 0 },
+ { "%XNshlA", { VexGb, Eb, CL }, 0 },
+ { "%XNsarA", { VexGb, Eb, CL }, 0 },
},
/* REG_EVEX_MAP4_D3 */
{
- { "rolQ", { VexGv, Ev, CL }, 0 },
- { "rorQ", { VexGv, Ev, CL }, 0 },
+ { "%XNrolQ", { VexGv, Ev, CL }, 0 },
+ { "%XNrorQ", { VexGv, Ev, CL }, 0 },
{ "rclQ", { VexGv, Ev, CL }, 0 },
{ "rcrQ", { VexGv, Ev, CL }, 0 },
- { "shlQ", { VexGv, Ev, CL }, 0 },
- { "shrQ", { VexGv, Ev, CL }, 0 },
- { "shlQ", { VexGv, Ev, CL }, 0 },
- { "sarQ", { VexGv, Ev, CL }, 0 },
+ { "%XNshlQ", { VexGv, Ev, CL }, 0 },
+ { "%XNshrQ", { VexGv, Ev, CL }, 0 },
+ { "%XNshlQ", { VexGv, Ev, CL }, 0 },
+ { "%XNsarQ", { VexGv, Ev, CL }, 0 },
},
/* REG_EVEX_MAP4_D8_PREFIX_1 */
{
@@ -170,25 +170,34 @@
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "notA", { VexGb, Eb }, 0 },
- { "negA", { VexGb, Eb }, 0 },
+ { "%XNnotA", { VexGb, Eb }, 0 },
+ { "%XNnegA", { VexGb, Eb }, 0 },
+ { "%XNmulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
+ { "%XNimulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
+ { "%XNdivA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
+ { "%XNidivA", { Eb }, 0 }, /* and idiv for consistency. */
+
},
/* REG_EVEX_MAP4_F7 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "notQ", { VexGv, Ev }, 0 },
- { "negQ", { VexGv, Ev }, 0 },
+ { "%XNnotQ", { VexGv, Ev }, 0 },
+ { "%XNnegQ", { VexGv, Ev }, 0 },
+ { "%XNmulQ", { Ev }, 0 }, /* Don't print the implicit %al register, */
+ { "%XNimulQ", { Ev }, 0 }, /* to distinguish these opcodes from other */
+ { "%XNdivQ", { Ev }, 0 }, /* mul/imul opcodes. Do the same for div */
+ { "%XNidivQ", { Ev }, 0 }, /* and idiv for consistency. */
},
/* REG_EVEX_MAP4_FE */
{
- { "incA", { VexGb ,Eb }, 0 },
- { "decA", { VexGb ,Eb }, 0 },
+ { "%XNincA", { VexGb ,Eb }, 0 },
+ { "%XNdecA", { VexGb ,Eb }, 0 },
},
/* REG_EVEX_MAP4_FF */
{
- { "incQ", { VexGv ,Ev }, 0 },
- { "decQ", { VexGv ,Ev }, 0 },
+ { "%XNincQ", { VexGv ,Ev }, 0 },
+ { "%XNdecQ", { VexGv ,Ev }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index 22fa9b2b067..0f196155054 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -875,19 +875,19 @@ static const struct dis386 evex_table[][256] = {
/* EVEX_MAP4_ */
{
/* 00 */
- { "addB", { VexGb, Eb, Gb }, 0 },
- { "addS", { VexGv, Ev, Gv }, 0 },
- { "addB", { VexGb, Gb, EbS }, 0 },
- { "addS", { VexGv, Gv, EvS }, 0 },
+ { "%XNaddB", { VexGb, Eb, Gb }, 0 },
+ { "%XNaddS", { VexGv, Ev, Gv }, 0 },
+ { "%XNaddB", { VexGb, Gb, EbS }, 0 },
+ { "%XNaddS", { VexGv, Gv, EvS }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 08 */
- { "orB", { VexGb, Eb, Gb }, 0 },
- { "orS", { VexGv, Ev, Gv }, 0 },
- { "orB", { VexGb, Gb, EbS }, 0 },
- { "orS", { VexGv, Gv, EvS }, 0 },
+ { "%XNorB", { VexGb, Eb, Gb }, 0 },
+ { "%XNorS", { VexGv, Ev, Gv }, 0 },
+ { "%XNorB", { VexGb, Gb, EbS }, 0 },
+ { "%XNorS", { VexGv, Gv, EvS }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
@@ -911,28 +911,28 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
/* 20 */
- { "andB", { VexGb, Eb, Gb }, 0 },
- { "andS", { VexGv, Ev, Gv }, 0 },
- { "andB", { VexGb, Gb, EbS }, 0 },
- { "andS", { VexGv, Gv, EvS }, 0 },
- { "shldS", { VexGv, Ev, Gv, Ib }, 0 },
+ { "%XNandB", { VexGb, Eb, Gb }, 0 },
+ { "%XNandS", { VexGv, Ev, Gv }, 0 },
+ { "%XNandB", { VexGb, Gb, EbS }, 0 },
+ { "%XNandS", { VexGv, Gv, EvS }, 0 },
+ { "%XNshldS", { VexGv, Ev, Gv, Ib }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 28 */
- { "subB", { VexGb, Eb, Gb }, 0 },
- { "subS", { VexGv, Ev, Gv }, 0 },
- { "subB", { VexGb, Gb, EbS }, 0 },
- { "subS", { VexGv, Gv, EvS }, 0 },
- { "shrdS", { VexGv, Ev, Gv, Ib }, 0 },
+ { "%XNsubB", { VexGb, Eb, Gb }, 0 },
+ { "%XNsubS", { VexGv, Ev, Gv }, 0 },
+ { "%XNsubB", { VexGb, Gb, EbS }, 0 },
+ { "%XNsubS", { VexGv, Gv, EvS }, 0 },
+ { "%XNshrdS", { VexGv, Ev, Gv, Ib }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 30 */
- { "xorB", { VexGb, Eb, Gb }, 0 },
- { "xorS", { VexGv, Ev, Gv }, 0 },
- { "xorB", { VexGb, Gb, EbS }, 0 },
- { "xorS", { VexGv, Gv, EvS }, 0 },
+ { "%XNxorB", { VexGb, Eb, Gb }, 0 },
+ { "%XNxorS", { VexGv, Ev, Gv }, 0 },
+ { "%XNxorB", { VexGb, Gb, EbS }, 0 },
+ { "%XNxorS", { VexGv, Gv, EvS }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
@@ -993,9 +993,9 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
/* 68 */
{ Bad_Opcode },
+ { "%XNimulS", { VexGv, Ev, Iv }, 0 },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { "%XNimulS", { VexGv, Ev, sIb }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
@@ -1028,7 +1028,7 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
/* 88 */
- { Bad_Opcode },
+ { "%XNpopcntS", { Gv, Ev }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
@@ -1060,7 +1060,7 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "shldS", { VexGv, Ev, Gv, CL }, 0 },
+ { "%XNshldS", { VexGv, Ev, Gv, CL }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
/* A8 */
@@ -1069,9 +1069,9 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "shrdS", { VexGv, Ev, Gv, CL }, 0 },
+ { "%XNshrdS", { VexGv, Ev, Gv, CL }, 0 },
{ Bad_Opcode },
- { "imulS", { VexGv, Gv, Ev }, 0 },
+ { "%XNimulS", { VexGv, Gv, Ev }, 0 },
/* B0 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -1149,8 +1149,8 @@ static const struct dis386 evex_table[][256] = {
{ PREFIX_TABLE (PREFIX_EVEX_MAP4_F1) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP4_F2) },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { "%XNtzcntS", { Gv, Ev }, 0 },
+ { "%XNlzcntS", { Gv, Ev }, 0 },
{ REG_TABLE (REG_EVEX_MAP4_F6) },
{ REG_TABLE (REG_EVEX_MAP4_F7) },
/* F8 */
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 4671d2e4b0e..b3ede02df06 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -224,6 +224,7 @@ struct instr_info
bool zeroing;
bool b;
bool no_broadcast;
+ bool nf;
}
vex;
@@ -1851,6 +1852,8 @@ struct dis386 {
"XV" => print "{vex} " pseudo prefix
"XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
is used by an EVEX-encoded (AVX512VL) instruction.
+ "XN" => print "{nf} " pseudo prefix when EVEX.NF = 1.
+ a valid encoding.
"YK" keep unused, to avoid ambiguity with the combined use of Y and K.
"YX" keep unused, to avoid ambiguity with the combined use of Y and X.
"LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
@@ -4119,7 +4122,7 @@ static const struct dis386 prefix_table[][4] = {
/* PREFIX_VEX_0F38F5_L_0 */
{
- { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
+ { "%XNbzhiS", { Gdq, Edq, VexGdq }, 0 },
{ "pextS", { Gdq, VexGdq, Edq }, 0 },
{ Bad_Opcode },
{ "pdepS", { Gdq, VexGdq, Edq }, 0 },
@@ -4135,7 +4138,7 @@ static const struct dis386 prefix_table[][4] = {
/* PREFIX_VEX_0F38F7_L_0 */
{
- { "bextrS", { Gdq, Edq, VexGdq }, 0 },
+ { "%XNbextrS", { Gdq, Edq, VexGdq }, 0 },
{ "sarxS", { Gdq, Edq, VexGdq }, 0 },
{ "shlxS", { Gdq, Edq, VexGdq }, 0 },
{ "shrxS", { Gdq, Edq, VexGdq }, 0 },
@@ -9111,6 +9114,10 @@ use_x86_64_table:
ins->vex.v = *ins->codep & 0x8;
ins->vex.mask_register_specifier = *ins->codep & 0x7;
ins->vex.zeroing = *ins->codep & 0x80;
+ /* Set the NF bit for the EVEX instruction extended from the legacy or
+ vex instruction, this bit will be cleared when it can be confirmed
+ that its defaut type is evex. */
+ ins->vex.nf = *ins->codep & 0x4;
if (ins->address_mode != mode_64bit)
{
@@ -9550,6 +9557,11 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax)
&& ins.vex.prefix == DATA_PREFIX_OPCODE)
sizeflag ^= DFLAG;
+ if(ins.evex_type == evex_default)
+ ins.vex.nf = false;
+ else
+ ins.vex.mask_register_specifier = 0;
+
if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0)
{
if (!get_sib (&ins, sizeflag))
@@ -10553,11 +10565,36 @@ putop (instr_info *ins, const char *in_template, int sizeflag)
*ins->obufp++ = 'r';
break;
case 'N':
- if ((ins->prefixes & PREFIX_FWAIT) == 0)
- *ins->obufp++ = 'n';
+ if (l == 1 && last[0] == 'X')
+ {
+ if (ins->vex.nf == true)
+ {
+ *ins->obufp++ = '{';
+ *ins->obufp++ = 'n';
+ *ins->obufp++ = 'f';
+ *ins->obufp++ = '}';
+ *ins->obufp++ = ' ';
+ }
+ else if (ins->evex_type == evex_from_legacy && !ins->vex.b)
+ {
+ *ins->obufp++ = '{';
+ *ins->obufp++ = 'e';
+ *ins->obufp++ = 'v';
+ *ins->obufp++ = 'e';
+ *ins->obufp++ = 'x';
+ *ins->obufp++ = '}';
+ *ins->obufp++ = ' ';
+ }
+ break;
+ }
else
- ins->used_prefixes |= PREFIX_FWAIT;
- break;
+ {
+ if ((ins->prefixes & PREFIX_FWAIT) == 0)
+ *ins->obufp++ = 'n';
+ else
+ ins->used_prefixes |= PREFIX_FWAIT;
+ break;
+ }
case 'O':
USED_REX (REX_W);
if (ins->rex & REX_W)
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index f951c452cc3..a472fba6254 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -472,6 +472,7 @@ static bitfield opcode_modifiers[] =
BITFIELD (ISA64),
BITFIELD (No_egpr),
BITFIELD (Push2Pop2),
+ BITFIELD (NF),
};
#define CLASS(n) #n, n
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 1663cc74937..05f69d4a584 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -752,6 +752,9 @@ enum
/* APX Push2Pop2 bit */
Push2Pop2,
+ /* No CSPAZO flags update indication. */
+ NF,
+
/* The last bitfield in i386_opcode_modifier. */
Opcode_Modifier_Num
};
@@ -801,6 +804,7 @@ typedef struct i386_opcode_modifier
unsigned int isa64:2;
unsigned int no_egpr:1;
unsigned int push2pop2:1;
+ unsigned int nf:1;
} i386_opcode_modifier;
/* Operand classes. */
@@ -1003,7 +1007,7 @@ typedef struct insn_template
AMD 3DNow! instructions.
If this template has no extension opcode (the usual case) use None
Instructions */
- signed int extension_opcode:0xA;
+ signed int extension_opcode:0xB;
#define None (-1) /* If no extension_opcode is possible. */
/* Pseudo prefixes. */
@@ -1017,7 +1021,8 @@ typedef struct insn_template
#define Prefix_EVEX 7 /* {evex} */
#define Prefix_REX 8 /* {rex} */
#define Prefix_REX2 9 /* {rex2} */
-#define Prefix_NoOptimize 0xA /* {nooptimize} */
+#define Prefix_NF 0xA /* {nf} */
+#define Prefix_NoOptimize 0xB /* {nooptimize} */
/* the bits in opcode_modifier are used to generate the final opcode from
the base_opcode. These bits also are used to detect alternate forms of
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 583b6676b0e..4e8ef15c28b 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -286,25 +286,41 @@ add, 0x0, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg3
add, 0x83/0, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
add, 0x4, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
add, 0x80/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-add, 0x0, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-add, 0x83/0, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-add, 0x80/0, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64}
+
+add, 0x0, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+add, 0x83/0, APX_F|x64, Modrm|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+add, 0x80/0, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+add, 0x0, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+add, 0x83/0, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+add, 0x80/0, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64}
inc, 0x40, No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }
inc, 0xfe/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-inc, 0xfe/0, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, {Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64}
+
+inc, 0xfe/0, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+inc, 0xfe/0, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, {Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64}
sub, 0x28, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
sub, 0x83/5, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
sub, 0x2c, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
sub, 0x80/5, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-sub, 0x28, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64, }
-sub, 0x83/5, APX_F|x64, Modrm|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-sub, 0x80/5, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+
+sub, 0x28, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|Optimize|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+sub, 0x83/5, APX_F|x64, Modrm|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+sub, 0x80/5, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+sub, 0x28, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4|NF|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64, }
+sub, 0x83/5, APX_F|x64, Modrm|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+sub, 0x80/5, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
dec, 0x48, No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }
dec, 0xfe/1, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-dec, 0xfe/1, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+
+dec, 0xfe/1, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+dec, 0xfe/1, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
sbb, 0x18, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
sbb, 0x83/3, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
@@ -330,25 +346,40 @@ and, 0x20, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|
and, 0x83/4, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock|Optimize, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
and, 0x24, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
and, 0x80/4, 0, W|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-and, 0x20, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-and, 0x83/4, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|Optimize, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-and, 0x80/4, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+
+and, 0x20, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|Optimize|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+and, 0x83/4, APX_F|x64, Modrm|No_bSuf|No_sSuf|Optimize|EVex128|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+and, 0x80/4, APX_F|x64, W|Modrm|No_sSuf|Optimize|EVex128|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+and, 0x20, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4|NF|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+and, 0x83/4, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|NF|Optimize, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+and, 0x80/4, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4|NF|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
or, 0x8, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
or, 0x83/1, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
or, 0xc, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
or, 0x80/1, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-or, 0x8, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-or, 0x83/1, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-or, 0x80/1, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+
+or, 0x8, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|Optimize|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+or, 0x83/1, APX_F|x64, Modrm|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+or, 0x80/1, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+or, 0x8, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4|NF|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+or, 0x83/1, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+or, 0x80/1, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
xor, 0x30, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
xor, 0x83/6, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
xor, 0x34, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
xor, 0x80/6, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-xor, 0x30, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-xor, 0x83/6, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-xor, 0x80/6, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+
+xor, 0x30, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|EVex128|EVexMap4|NF|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+xor, 0x83/6, APX_F|x64, Modrm|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+xor, 0x80/6, 0, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+xor, 0x30, APX_F|x64, D|W|CheckOperandSize|Modrm|No_sSuf|VexVVVV|EVex128|EVexMap4|NF|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+xor, 0x83/6, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+xor, 0x80/6, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
// clr with 1 operand is really xor with 2 operands.
clr, 0x30, 0, W|Modrm|No_sSuf|RegKludge|Optimize, { Reg8|Reg16|Reg32|Reg64 }
@@ -365,7 +396,8 @@ adc, 0x83/2, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|E
adc, 0x80/2, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
neg, 0xf6/3, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-neg, 0xf6/3, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+neg, 0xf6/3, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+neg, 0xf6/3, APX_F|x64, W|Modrm|CheckOperandSize|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
not, 0xf6/2, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
not, 0xf6/2, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
@@ -401,11 +433,21 @@ cqto, 0x99, x64, Size64|NoSuf, {}
// 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
// These multiplies can only be selected with single operand forms.
mul, 0xf6/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+mul, 0xf6/4, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
imul, 0xf6/5, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
imul, 0xfaf, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|Word|Dword|Qword|BaseIndex, Reg16|Reg32|Reg64 }
-imul, 0xaf, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Reg16|Reg32|Reg64|Unspecified|Word|Dword|Qword|BaseIndex, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
imul, 0x6b, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
imul, 0x69, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+
+imul, 0xf6/5, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+imul, 0xaf, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Reg16|Reg32|Reg64|Unspecified|Word|Dword|Qword|BaseIndex, Reg16|Reg32|Reg64 }
+
+imul, 0xaf, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Reg16|Reg32|Reg64|Unspecified|Word|Dword|Qword|BaseIndex, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
+
+imul, 0x6b, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+imul, 0x69, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
// imul with 2 operands mimics imul with 3 by putting the register in
// both i.rm.reg & i.rm.regmem fields. RegKludge enables this
// transformation.
@@ -416,24 +458,38 @@ div, 0xf6/6, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|
div, 0xf6/6, 0, W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
idiv, 0xf6/7, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
idiv, 0xf6/7, 0, W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
+div, 0xf6/6, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+idiv, 0xf6/7, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
rol, 0xc0/0, i186, W|Modrm|No_sSuf, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
rol, 0xd2/0, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-rol, 0xd0/0, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-rol, 0xc0/0, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-rol, 0xd2/0, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-rol, 0xd0/0, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+
+rol, 0xd0/0, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+rol, 0xc0/0, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+rol, 0xd2/0, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+rol, 0xd0/0, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+rol, 0xd0/0, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+rol, 0xc0/0, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+rol, 0xd2/0, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+rol, 0xd0/0, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
ror, 0xc0/1, i186, W|Modrm|No_sSuf, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
ror, 0xd2/1, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-ror, 0xd0/1, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-ror, 0xc0/1, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-ror, 0xd2/1, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-ror, 0xd0/1, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+
+ror, 0xd0/1, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+ror, 0xc0/1, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+ror, 0xd2/1, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+ror, 0xd0/1, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+ror, 0xd0/1, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+ror, 0xc0/1, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+ror, 0xd2/1, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+ror, 0xd0/1, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
rcl, 0xd0/2, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
rcl, 0xc0/2, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
@@ -474,42 +530,70 @@ shl, 0xd0/4, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|
shl, 0xc0/4, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
shl, 0xd2/4, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
shl, 0xd0/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-shl, 0xd0/4, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-shl, 0xc0/4, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-shl, 0xd2/4, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-shl, 0xd0/4, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+
+shl, 0xd0/4, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+shl, 0xc0/4, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+shl, 0xd2/4, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+shl, 0xd0/4, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+shl, 0xd0/4, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+shl, 0xc0/4, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+shl, 0xd2/4, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+shl, 0xd0/4, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
shr, 0xd0/5, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
shr, 0xc0/5, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
shr, 0xd2/5, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
shr, 0xd0/5, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-shr, 0xd0/5, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-shr, 0xc0/5, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-shr, 0xd2/5, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-shr, 0xd0/5, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+
+shr, 0xd0/5, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+shr, 0xc0/5, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+shr, 0xd2/5, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+shr, 0xd0/5, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+shr, 0xd0/5, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+shr, 0xc0/5, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+shr, 0xd2/5, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+shr, 0xd0/5, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
sar, 0xd0/7, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
sar, 0xc0/7, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
sar, 0xd2/7, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
sar, 0xd0/7, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-sar, 0xd0/7, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-sar, 0xc0/7, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-sar, 0xd2/7, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
-sar, 0xd0/7, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+
+sar, 0xd0/7, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+sar, 0xc0/7, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+sar, 0xd2/7, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+sar, 0xd0/7, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+sar, 0xd0/7, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+sar, 0xc0/7, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+sar, 0xd2/7, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
+sar, 0xd0/7, APX_F|x64, W|Modrm|No_sSuf|CheckOperandSize|VexVVVV|EVex128|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
shld, 0xfa4, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
shld, 0xfa5, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
shld, 0xfa5, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-shld, 0x24, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-shld, 0xa5, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-shld, 0xa5, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+
+shld, 0x24, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+shld, 0xa5, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+shld, 0xa5, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+
+shld, 0x24, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+shld, 0xa5, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+shld, 0xa5, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
shrd, 0xfac, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
shrd, 0xfad, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
shrd, 0xfad, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-shrd, 0x2c, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-shrd, 0xad, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-shrd, 0xad, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+
+shrd, 0x2c, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+shrd, 0xad, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+shrd, 0xad, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+
+shrd, 0x2c, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+shrd, 0xad, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+shrd, 0xad, APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|VexVVVV|EVex128|EVexMap4|NF, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
// Control transfer instructions.
call, 0xe8, No64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk, { Disp16|Disp32 }
@@ -971,7 +1055,8 @@ rex.wrxb, 0x4f, x64, NoSuf|IsPrefix, {}
<pseudopfx:ident:cpu, disp8:Disp8:0, disp16:Disp16:0, disp32:Disp32:0, +
load:Load:0, store:Store:0, +
vex:VEX:0, vex2:VEX:0, vex3:VEX3:0, evex:EVEX:0, +
- rex:REX:x64, rex2:REX2:x64, nooptimize:NoOptimize:0>
+ rex:REX:x64, rex2:REX2:x64, nf:NF:x64, +
+ nooptimize:NoOptimize:0>
{<pseudopfx>}, PSEUDO_PREFIX/Prefix_<pseudopfx:ident>, <pseudopfx:cpu>, NoSuf|IsPrefix, {}
@@ -1910,7 +1995,7 @@ xtest, 0xf01d6, HLE|RTM, NoSuf, {}
// BMI2 instructions.
bzhi, 0xf5, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
-bzhi, 0xf5, BMI2|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
+bzhi, 0xf5, BMI2|APX_F, Modrm|CheckOperandSize|EVex128|NF|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
mulx, 0xf2f6, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
mulx, 0xf2f6, BMI2|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
pdep, 0xf2f5, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
@@ -1995,16 +2080,17 @@ lwpins, 0x12/0, LWP, Modrm|SpaceXOP0A|NoSuf|VexVVVV|Vex, { Imm32|Imm32S, Reg32|U
// BMI instructions
andn, 0xf2, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
-andn, 0xf2, BMI|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
+andn, 0xf2, BMI|APX_F, Modrm|CheckOperandSize|EVex128|NF|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
bextr, 0xf7, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
-bextr, 0xf7, BMI|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
+bextr, 0xf7, BMI|APX_F, Modrm|CheckOperandSize|EVex128|NF|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
blsi, 0xf3/3, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
-blsi, 0xf3/3, BMI|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
+blsi, 0xf3/3, BMI|APX_F, Modrm|CheckOperandSize|EVex128|NF|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
blsmsk, 0xf3/2, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
-blsmsk, 0xf3/2, BMI|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
+blsmsk, 0xf3/2, BMI|APX_F, Modrm|CheckOperandSize|EVex128|NF|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
blsr, 0xf3/1, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
-blsr, 0xf3/1, BMI|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
+blsr, 0xf3/1, BMI|APX_F, Modrm|CheckOperandSize|EVex128|NF|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
tzcnt, 0xf30fbc, BMI, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+tzcnt, 0xf4, BMI, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
// TBM instructions
@@ -2082,9 +2168,11 @@ insertq, 0xf20f78, SSE4a, Modrm|NoSuf, { Imm8, Imm8, RegXMM, RegXMM }
// LZCNT instruction
lzcnt, 0xf30fbd, LZCNT, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+lzcnt, 0xf5, LZCNT|APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
// POPCNT instruction
popcnt, 0xf30fb8, POPCNT, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+popcnt, 0x88, POPCNT|APX_F|x64, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4|NF, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
// VIA PadLock extensions.
xstore-rng, 0xfa7c0, PadLock, NoSuf|RepPrefixOk, {}
--
2.25.1
next prev parent reply other threads:[~2023-09-19 15:25 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-19 15:25 [PATCH 0/8] [RFC] Support Intel APX EGPR Cui, Lili
2023-09-19 15:25 ` [PATCH 1/8] Support APX GPR32 with rex2 prefix Cui, Lili
2023-09-21 15:27 ` Jan Beulich
2023-09-27 15:57 ` Cui, Lili
2023-09-21 15:51 ` Jan Beulich
2023-09-27 15:59 ` Cui, Lili
2023-09-28 8:02 ` Jan Beulich
2023-10-07 3:27 ` Cui, Lili
2023-09-19 15:25 ` [PATCH 2/8] Support APX GPR32 with extend evex prefix Cui, Lili
2023-09-22 10:12 ` Jan Beulich
2023-10-17 15:48 ` Cui, Lili
2023-10-18 6:40 ` Jan Beulich
2023-10-18 10:44 ` Cui, Lili
2023-10-18 10:50 ` Jan Beulich
2023-09-22 10:50 ` Jan Beulich
2023-10-17 15:50 ` Cui, Lili
2023-10-17 16:11 ` Jan Beulich
2023-10-18 2:02 ` Cui, Lili
2023-10-18 6:10 ` Jan Beulich
2023-09-25 6:03 ` Jan Beulich
2023-10-17 15:52 ` Cui, Lili
2023-10-17 16:12 ` Jan Beulich
2023-10-18 6:31 ` Cui, Lili
2023-10-18 6:47 ` Jan Beulich
2023-10-18 7:52 ` Cui, Lili
2023-10-18 8:21 ` Jan Beulich
2023-10-18 11:30 ` Cui, Lili
2023-10-19 11:58 ` Cui, Lili
2023-10-19 15:24 ` Jan Beulich
2023-10-19 16:38 ` Cui, Lili
2023-10-20 6:25 ` Jan Beulich
2023-10-22 14:33 ` Cui, Lili
2023-09-19 15:25 ` [PATCH 3/8] Add tests for " Cui, Lili
2023-09-27 13:11 ` Jan Beulich
2023-10-17 15:53 ` FW: " Cui, Lili
2023-10-17 16:19 ` Jan Beulich
2023-10-18 2:32 ` Cui, Lili
2023-10-18 6:05 ` Jan Beulich
2023-10-18 7:16 ` Cui, Lili
2023-10-18 8:05 ` Jan Beulich
2023-10-18 11:26 ` Cui, Lili
2023-10-18 12:06 ` Jan Beulich
2023-10-25 16:03 ` Cui, Lili
2023-09-27 13:19 ` Jan Beulich
2023-09-19 15:25 ` [PATCH 4/8] Support APX NDD Cui, Lili
2023-09-27 14:44 ` Jan Beulich
2023-10-22 14:05 ` Cui, Lili
2023-10-23 7:12 ` Jan Beulich
2023-10-25 8:10 ` Cui, Lili
2023-10-25 8:47 ` Jan Beulich
2023-10-25 15:49 ` Cui, Lili
2023-10-25 15:59 ` Jan Beulich
2023-09-28 7:57 ` Jan Beulich
2023-10-22 14:57 ` Cui, Lili
2023-10-24 11:39 ` Cui, Lili
2023-10-24 11:58 ` Jan Beulich
2023-10-25 15:29 ` Cui, Lili
2023-09-19 15:25 ` [PATCH 5/8] Support APX NDD optimized encoding Cui, Lili
2023-09-28 9:29 ` Jan Beulich
2023-10-23 2:57 ` Hu, Lin1
2023-10-23 7:23 ` Jan Beulich
2023-10-23 7:50 ` Hu, Lin1
2023-10-23 8:15 ` Jan Beulich
2023-10-24 1:40 ` Hu, Lin1
2023-10-24 6:03 ` Jan Beulich
2023-10-24 6:08 ` Hu, Lin1
2023-10-23 3:07 ` [PATCH-V2] " Hu, Lin1
2023-10-23 3:30 ` [PATCH 5/8] [v2] " Hu, Lin1
2023-10-23 7:26 ` Jan Beulich
2023-09-19 15:25 ` [PATCH 6/8] Support APX Push2/Pop2 Cui, Lili
2023-09-28 11:37 ` Jan Beulich
2023-10-30 15:21 ` Cui, Lili
2023-10-30 15:31 ` Jan Beulich
2023-11-20 13:05 ` Cui, Lili
2023-09-19 15:25 ` Cui, Lili [this message]
2023-09-25 6:07 ` [PATCH 7/8] Support APX NF Jan Beulich
2023-09-28 12:42 ` Jan Beulich
2023-11-02 10:15 ` Cui, Lili
2023-11-02 10:23 ` Jan Beulich
2023-11-02 10:46 ` Cui, Lili
2023-12-12 2:59 ` H.J. Lu
2023-09-19 15:25 ` [PATCH 8/8] Support APX JMPABS Cui, Lili
2023-09-28 13:11 ` Jan Beulich
2023-11-02 2:32 ` Hu, Lin1
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