RE: [PATCH 2/8] Support APX GPR32 with extend evex prefix

["Cui, Lili" <lili.cui@intel.com>]

> -----Original Message-----
> From: Cui, Lili
> Sent: Wednesday, October 18, 2023 7:31 PM
> To: Jan Beulich <jbeulich@suse.com>
> Cc: Lu, Hongjiu <hongjiu.lu@intel.com>; binutils@sourceware.org
> Subject: RE: [PATCH 2/8] Support APX GPR32 with extend evex prefix
> 
> > >> Subject: Re: [PATCH 2/8] Support APX GPR32 with extend evex prefix
> > >>
> > >> On 18.10.2023 08:31, Cui, Lili wrote:
> > >>>>>> Similary I don't think I can spot anywhere that you would check
> > >>>>>> the other bits which need to be zero in extended EVEX. Nor
> > >>>>>> Improper use of EVEX.x4 in certain pre-existing encodings (S/G
> > >>>>>> insns at least; perhaps all
> > >>>> others are okay).
> > >>>>>
> > >>>>> Sorry, I can't get you here, what are S/G insns, could you
> > >>>>> provide more
> > >>>> details here, thanks.
> > >>>>
> > >>>> S/G is scatter/gather (i.e. AVX2 and AVX512).
> > >>>>
> > >>> I think you mean EVEX.V4, scatter/gather has VSIB which needs to
> > >>> reuse this bit (EVEX.x4 is EVEX.p[10] which is fixed value 1), For
> > >>> our current code
> > >> we will reassign that bit and now I changed it to check the upper
> > >> 16 registers of GPR32 , do you think it is ok?
> > >>>
> > >>> @@ -4252,7 +4252,7 @@ build_apx_evex_prefix (void)
> > >>>    if (i.rex2 & REX_R)
> > >>>      i.vex.bytes[1] &= 0xef;
> > >>>    if (i.vex.register_specifier
> > >>> -      && register_number (i.vex.register_specifier) > 0xf)
> > >>> +      && (i.vex.register_specifier->reg_flags & RegRex2))
> > >>>      i.vex.bytes[3] &= 0xf7;
> > >>>    if (i.rex2 & REX_B)
> > >>>      i.vex.bytes[1] |= 0x08;
> > >>
> > >> First of all my comment was disassembly related; you stripped a
> > >> little too much context for this to remain visible here. And then I
> > >> think I did mean
> > >> EVEX.x4 - as you say it needs to be fixed-1 in e.g. S/G insns, and
> > >> the checking thereof is what I'm missing.
> > >>
> > > Ok ,  I will drop the encoder changes, and add an X4 check when
> > > instruction
> > has vex_vsib* type in decoder.
> >
> > You understand though that I used the S/G insns as example only. I
> > didn't do a proper check whether any others might also be affected. In
> > particular ones not allowing for memory operands might be.
> >
> OK, I'll try to add more checks, and add description for them.
> 

Added some bit checks in the decoder.

--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -11533,6 +11642,13 @@ OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
                abort ();
              if (ins->vex.evex)
                {
+                 /* S/G EVEX insns require EVEX.P[10] == 1 */
+                 if (ins->rex2 & REX_X)
+                   {
+                     oappend (ins, "(bad)");
+                     return true;
+                   }
+
@@ -9003,6 +9003,9 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
        case 0x4:
          vex_table_index = EVEX_MAP4;
          ins->evex_type = evex_from_legacy;
+         /* EVEX from legacy instrucions require EVEX.P[2:0] must be 0x04.  */
+         if (!((*ins->codep & 0x7) == 0x04))
+           return  &bad_opcode;
          break;
        case 0x5:
          vex_table_index = EVEX_MAP5;
@@ -9063,6 +9066,22 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
        }

       ins->need_vex = 4;
+
+      /* EVEX from legacy requrie EVEX.P[17:16] must be 0, EVEX.P[23:21] must
+        be 0.
+        EVEX from evex requrie EVEX.P[17:16] must be 0. EVEX.P[23:22] must
+        be 0, EVEX.P[20] must be 0.  */
+      if (ins->evex_type == evex_from_legacy || ins->evex_type == evex_from_vex)
+       {
+         if (!((*ins->codep & 0x3) == 0)
+             || !((*ins->codep >> 6 & 0x3) == 0)
+             || (ins->evex_type == evex_from_legacy
+                 && !((*ins->codep >> 5 & 0x1) == 0))
+             || (ins->evex_type == evex_from_vex
+                 && !ins->vex.b))
+           return &bad_opcode;

Corresponding testcase

        #VSIB vpgatherqq 0x7b(%rbp,%zmm17,8),%zmm16{%k1} set EVEX.P[10] == 0(illegal value).
        .byte 0x62, 0xe2, 0xf9, 0x41, 0x91, 0x84, 0xcd, 0x7b, 0x00, 0x00, 0x00
        .byte 0xff
        #EVEX_MAP4 adox %r25d,%edx set EVEX.P[2:0] == 1 (illegal value).
        .byte 0x62, 0xdd, 0x7e, 0x08, 0x66, 0xd1
        .byte 0xff
        #EVEX_MAP4 adox %r25d,%edx set EVEX.P[17:16] == 1 (illegal value).
        .byte 0x62, 0xdc, 0x7e, 0x09, 0x66, 0xd1
        #EVEX_MAP4 adox %r25d,%edx set EVEX.P[23:21] == 1 (illegal value).
        .byte 0x62, 0xdc, 0x7e, 0x18, 0x66, 0xd1
        #EVEX from VEX enqcmd 0x123(%r31,%rax,4),%r31 EVEX.P[17:16] == 1 (illegal value).
        .byte 0x62, 0x4c, 0x7f, 0x09, 0xf8, 0xbc, 0x87, 0x23, 0x01, 0x00, 0x00
        .byte 0xff
        #EVEX from VEX enqcmd 0x123(%r31,%rax,4),%r31 EVEX.P[23:22] == 1 (illegal value).
        .byte 0x62, 0x4c, 0x7f, 0x18, 0xf8, 0xbc, 0x87, 0x23, 0x01, 0x00, 0x00

Lili.