From: "Cui, Lili" <lili.cui@intel.com>
To: "Beulich, Jan" <JBeulich@suse.com>
Cc: "Lu, Hongjiu" <hongjiu.lu@intel.com>,
"Kong, Lingling" <lingling.kong@intel.com>,
"binutils@sourceware.org" <binutils@sourceware.org>
Subject: RE: [PATCH 4/8] Support APX NDD
Date: Wed, 25 Oct 2023 15:49:03 +0000 [thread overview]
Message-ID: <SJ0PR11MB5600510F072A41597C3E26FD9EDEA@SJ0PR11MB5600.namprd11.prod.outlook.com> (raw)
In-Reply-To: <86df39d7-e555-7362-5e2e-ed9e22661407@suse.com>
> Subject: Re: [PATCH 4/8] Support APX NDD
>
> On 25.10.2023 10:10, Cui, Lili wrote:
> >> On 22.10.2023 16:05, Cui, Lili wrote:
> >>>>> --- /dev/null
> >>>>> +++ b/gas/testsuite/gas/i386/x86-64-apx-ndd.s
> >>>>> @@ -0,0 +1,156 @@
> >>>>> +# Check 64bit APX NDD instructions with evex prefix encoding
> >>>>> +
> >>>>> + .allow_index_reg
> >>>>> + .text
> >>>>> +_start:
> >>>>> +cmovge 0x90909090(%eax),%edx,%r8d cmovle
> >>>>> +0x90909090(%eax),%edx,%r8d cmovg 0x90909090(%eax),%edx,%r8d
> >>>>> +imul 0x90909(%eax),%edx,%r8d
> >>>>> +imul 0x909(%rax,%r31,8),%rdx,%r25
> >>>>
> >>>> What about imul by immediate? The present spec is quite unclear there:
> >>>> The insn page says {ND=ZU} and the table says 0/1 in the ND column.
> >>>>
> >>>
> >>> We don't support it yet, I put it in RFC.
> >>> ...
> >>> 2. Support APX ZU -- In progress
> >>> 3. Support APX CCMP and CTEST -- In progress ...
> >>>
> >>> About 0/1 in the ND column, it means ZU can be 0/1.
> >>>
> >>> IMUL with opcodes 0x69 and 0x6B in map 0 and SETcc instructions
> >>> Although these instructions do not support NDD, the EVEX.ND bit is
> >>> used to control whether its destination register has its upper bits
> >>> (namely,
> >> bits [63:OSIZE]) zeroed when OSIZE is 8b or 16b.
> >>> That is, if EVEX.ND = 1, the upper bits are always zeroed;
> >>> otherwise, they keep the old values when OSIZE is 8b or 16b. For
> >>> these instructions,
> >> EVEX.[V4,V3,V2,V1,V0] must be all zero.
> >>
> >> So ZU indeed isn't just a typo there. For 32- and 64-bit forms, is
> >> EVEX.ND then simply being ignored? The ZU really is meaningful only for
> 16-bit forms, aiui ...
> >>
> >
> > EVEX.ZU should be ignored for 32-bit and 64-bit forms. For imul (in spec 6.30
> IMUL), EVEX.ND stands for ND or ZU.
>
> In cases like this, where ignoring bits is kind of unexpected, the spec would
> better say explicitly (on the instruction page) when a meaningless bit is indeed
> ignored, rather than being reserved and causing #UD. Note how even the text
> in the APX-EVEX-INT section leaves open (or at least ambiguous, by not
> mentioning the case) whether SETcc with a memory operand ignores EVEX.ND
> or causes #UD when the bit is set.
>
Sorry, my previous answer was inaccurate, EVEX.ZU will not be ignored in 32-bit and 64-bit forms.
Prior to Intel® APX, the following rules apply in 64-bit mode when an instruction’s destination is a GPR and
OSIZE < 64b:
1. If OSIZE is 32b, the destination GPR gets the instruction’s result in bits [31:0] and all zeros in bits
[63:32].
2. If OSIZE is 8b or 16b, the destination GPR gets the instruction’s result in bits [OSIZE-1:0] but keep its
old value in bits [63:OSIZE].
The ZU indication described in items 2.(b) of Section 3.1.2.3.1 does not introduce an NDD. For those
instructions, EVEX.ND=0 keeps the current x86 behavior, but EVEX.ND=1 forces the zeroing of bits
[63:OSIZE] for any OSIZE < 64b
> > I think ZU makes sense for both the 16-bit form (imul) and the 8-bit form
> (setcc, I'm not sure if imul supports it yet).
>
> No, IMUL by immediate (or actually any IMUL with multiple operands) doesn't
> support byte register operands. For SETcc the ZU aspect is pretty clear and
> doesn't even need expressing by new syntax in (dis)assembly - you can simply
> distinguish the two forms by using either 8-bit registers (no ZU) or 32-/64-bit
> ones (with ZU). In principle that's possible with IMUL as well, of course, but it
> may be deemed a little odd:
>
> imul $17, %dx, %cx
> imul $17, %dx, %ecx
>
> Yet personally I'd still prefer this over adding e.g. {zu} on either the mnemonic
> or the destination operand. Question (as with the way to express
> {nf}) is how other assemblers are going to handle it. (Would be quite nice if
> the spec could at least give more clear hints towards suggested syntax, but
> that hadn't been the case already with the syntax extensions needed for
> AVX512.)
>
I will add suffix “zx” (for the Intel syntax) or “zwq” (for the AT&T syntax) to the mnemonic:
Intel syntax AT&T syntax
imulzx rax, word ptr[ rbx ], 0xab imulzwq $0xab, (%rbx), %rax
Lili.
next prev parent reply other threads:[~2023-10-25 15:49 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-19 15:25 [PATCH 0/8] [RFC] Support Intel APX EGPR Cui, Lili
2023-09-19 15:25 ` [PATCH 1/8] Support APX GPR32 with rex2 prefix Cui, Lili
2023-09-21 15:27 ` Jan Beulich
2023-09-27 15:57 ` Cui, Lili
2023-09-21 15:51 ` Jan Beulich
2023-09-27 15:59 ` Cui, Lili
2023-09-28 8:02 ` Jan Beulich
2023-10-07 3:27 ` Cui, Lili
2023-09-19 15:25 ` [PATCH 2/8] Support APX GPR32 with extend evex prefix Cui, Lili
2023-09-22 10:12 ` Jan Beulich
2023-10-17 15:48 ` Cui, Lili
2023-10-18 6:40 ` Jan Beulich
2023-10-18 10:44 ` Cui, Lili
2023-10-18 10:50 ` Jan Beulich
2023-09-22 10:50 ` Jan Beulich
2023-10-17 15:50 ` Cui, Lili
2023-10-17 16:11 ` Jan Beulich
2023-10-18 2:02 ` Cui, Lili
2023-10-18 6:10 ` Jan Beulich
2023-09-25 6:03 ` Jan Beulich
2023-10-17 15:52 ` Cui, Lili
2023-10-17 16:12 ` Jan Beulich
2023-10-18 6:31 ` Cui, Lili
2023-10-18 6:47 ` Jan Beulich
2023-10-18 7:52 ` Cui, Lili
2023-10-18 8:21 ` Jan Beulich
2023-10-18 11:30 ` Cui, Lili
2023-10-19 11:58 ` Cui, Lili
2023-10-19 15:24 ` Jan Beulich
2023-10-19 16:38 ` Cui, Lili
2023-10-20 6:25 ` Jan Beulich
2023-10-22 14:33 ` Cui, Lili
2023-09-19 15:25 ` [PATCH 3/8] Add tests for " Cui, Lili
2023-09-27 13:11 ` Jan Beulich
2023-10-17 15:53 ` FW: " Cui, Lili
2023-10-17 16:19 ` Jan Beulich
2023-10-18 2:32 ` Cui, Lili
2023-10-18 6:05 ` Jan Beulich
2023-10-18 7:16 ` Cui, Lili
2023-10-18 8:05 ` Jan Beulich
2023-10-18 11:26 ` Cui, Lili
2023-10-18 12:06 ` Jan Beulich
2023-10-25 16:03 ` Cui, Lili
2023-09-27 13:19 ` Jan Beulich
2023-09-19 15:25 ` [PATCH 4/8] Support APX NDD Cui, Lili
2023-09-27 14:44 ` Jan Beulich
2023-10-22 14:05 ` Cui, Lili
2023-10-23 7:12 ` Jan Beulich
2023-10-25 8:10 ` Cui, Lili
2023-10-25 8:47 ` Jan Beulich
2023-10-25 15:49 ` Cui, Lili [this message]
2023-10-25 15:59 ` Jan Beulich
2023-09-28 7:57 ` Jan Beulich
2023-10-22 14:57 ` Cui, Lili
2023-10-24 11:39 ` Cui, Lili
2023-10-24 11:58 ` Jan Beulich
2023-10-25 15:29 ` Cui, Lili
2023-09-19 15:25 ` [PATCH 5/8] Support APX NDD optimized encoding Cui, Lili
2023-09-28 9:29 ` Jan Beulich
2023-10-23 2:57 ` Hu, Lin1
2023-10-23 7:23 ` Jan Beulich
2023-10-23 7:50 ` Hu, Lin1
2023-10-23 8:15 ` Jan Beulich
2023-10-24 1:40 ` Hu, Lin1
2023-10-24 6:03 ` Jan Beulich
2023-10-24 6:08 ` Hu, Lin1
2023-10-23 3:07 ` [PATCH-V2] " Hu, Lin1
2023-10-23 3:30 ` [PATCH 5/8] [v2] " Hu, Lin1
2023-10-23 7:26 ` Jan Beulich
2023-09-19 15:25 ` [PATCH 6/8] Support APX Push2/Pop2 Cui, Lili
2023-09-28 11:37 ` Jan Beulich
2023-10-30 15:21 ` Cui, Lili
2023-10-30 15:31 ` Jan Beulich
2023-11-20 13:05 ` Cui, Lili
2023-09-19 15:25 ` [PATCH 7/8] Support APX NF Cui, Lili
2023-09-25 6:07 ` Jan Beulich
2023-09-28 12:42 ` Jan Beulich
2023-11-02 10:15 ` Cui, Lili
2023-11-02 10:23 ` Jan Beulich
2023-11-02 10:46 ` Cui, Lili
2023-12-12 2:59 ` H.J. Lu
2023-09-19 15:25 ` [PATCH 8/8] Support APX JMPABS Cui, Lili
2023-09-28 13:11 ` Jan Beulich
2023-11-02 2:32 ` Hu, Lin1
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