From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Nelson Chu <nelson@rivosinc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH v4 8/8] RISC-V: Use defined mask and match values
Date: Fri, 18 Nov 2022 02:07:55 +0000 [thread overview]
Message-ID: <3c1e28e61eb0275d0fd02a7d9ff956cc4f589104.1668737241.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1668737241.git.research_trasio@irq.a4lg.com>
This commit replaces plain constants and named values for different
instruction with defined named values matching defining instruction.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Use defined mask and match
macros rather than plain literals and macros
for different instructions.
---
opcodes/riscv-opc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 77ea6f64ea05..c0d653a95458 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -347,7 +347,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"call", 0, INSN_CLASS_I, "c", (X_RA << OP_SH_RS1)|(X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO },
{"tail", 0, INSN_CLASS_I, "c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
{"jump", 0, INSN_CLASS_I, "c,s", 0, (int) M_CALL, match_never, INSN_MACRO },
-{"nop", 0, INSN_CLASS_C, "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS },
+{"nop", 0, INSN_CLASS_C, "", MATCH_C_NOP, MASK_C_NOP, match_opcode, INSN_ALIAS },
{"nop", 0, INSN_CLASS_I, "", MATCH_ADDI, MASK_ADDI|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, INSN_ALIAS },
{"lui", 0, INSN_CLASS_C, "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS },
{"lui", 0, INSN_CLASS_I, "d,u", MATCH_LUI, MASK_LUI, match_opcode, 0 },
@@ -466,7 +466,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"sw", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_SW, match_never, INSN_MACRO },
{"fence", 0, INSN_CLASS_I, "", MATCH_FENCE|MASK_PRED|MASK_SUCC, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, INSN_ALIAS },
{"fence", 0, INSN_CLASS_I, "P,Q", MATCH_FENCE, MASK_FENCE|MASK_RD|MASK_RS1|(MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 },
-{"fence.i", 0, INSN_CLASS_ZIFENCEI, "", MATCH_FENCE_I, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, 0 },
+{"fence.i", 0, INSN_CLASS_ZIFENCEI, "", MATCH_FENCE_I, MASK_FENCE_I|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, 0 },
{"fence.tso", 0, INSN_CLASS_I, "", MATCH_FENCE_TSO, MASK_FENCE_TSO|MASK_RD|MASK_RS1, match_opcode, 0 },
{"rdcycle", 0, INSN_CLASS_I, "d", MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, INSN_ALIAS },
{"rdinstret", 0, INSN_CLASS_I, "d", MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, INSN_ALIAS },
@@ -893,7 +893,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"c.lw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, INSN_DREF|INSN_4_BYTE },
{"c.swsp", 0, INSN_CLASS_C, "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_DREF|INSN_4_BYTE },
{"c.sw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"c.nop", 0, INSN_CLASS_C, "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS },
+{"c.nop", 0, INSN_CLASS_C, "", MATCH_C_NOP, MASK_C_NOP, match_opcode, INSN_ALIAS },
{"c.nop", 0, INSN_CLASS_C, "Cj", MATCH_C_ADDI, MASK_C_ADDI|MASK_RD, match_opcode, INSN_ALIAS },
{"c.mv", 0, INSN_CLASS_C, "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add_with_hint, 0 },
{"c.lui", 0, INSN_CLASS_C, "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui_with_hint, 0 },
--
2.38.1
prev parent reply other threads:[~2022-11-18 2:09 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-09 9:09 [PATCH 0/5] RISC-V: Opcode tidying (batch 1) Tsukasa OI
2022-07-09 9:09 ` [PATCH 1/5] RISC-V: Remove unused instruction macros Tsukasa OI
2022-07-09 9:09 ` [PATCH 2/5] RISC-V: Complete tidying up with SCALL and SBREAK Tsukasa OI
2022-07-09 9:09 ` [PATCH 3/5] RISC-V: Tidying up with fmv.w.x and fmv.x.w Tsukasa OI
2022-07-09 9:09 ` [PATCH 4/5] RISC-V: Use defined mask and match values Tsukasa OI
2022-07-09 9:09 ` [PATCH 5/5] RISC-V: Make alias instructions aliases Tsukasa OI
2022-10-19 13:11 ` [PATCH v2 0/8] RISC-V: Various opcode tidying (batch 1) Tsukasa OI
2022-10-19 13:11 ` [PATCH v2 1/8] RISC-V: Add a space at the end of pinfo Tsukasa OI
2022-10-19 13:11 ` [PATCH v2 2/8] RISC-V: Fix obvious misalignments ('Zbb'/'Zba') Tsukasa OI
2022-10-19 13:11 ` [PATCH v2 3/8] RISC-V: Remove spaces in opcode entries Tsukasa OI
2022-10-19 13:11 ` [PATCH v2 4/8] RISC-V: Remove unused instruction macros Tsukasa OI
2022-10-19 13:11 ` [PATCH v2 5/8] RISC-V: Complete tidying up with SCALL and SBREAK Tsukasa OI
2022-10-19 13:12 ` [PATCH v2 6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w Tsukasa OI
2022-10-19 13:12 ` [PATCH v2 7/8] RISC-V: Make alias instructions aliases Tsukasa OI
2022-10-19 13:12 ` [PATCH v2 8/8] RISC-V: Use defined mask and match values Tsukasa OI
2022-11-05 11:51 ` [PING^1][PATCH v2 0/8] RISC-V: Various opcode tidying (batch 1) Tsukasa OI
2022-11-15 4:31 ` [PATCH v3 " Tsukasa OI
2022-11-15 4:31 ` [PATCH v3 1/8] RISC-V: Add a space at the end of pinfo Tsukasa OI
2022-11-15 4:31 ` [PATCH v3 2/8] RISC-V: Fix obvious misalignments ('Zbb'/'Zba') Tsukasa OI
2022-11-15 4:31 ` [PATCH v3 3/8] RISC-V: Remove spaces in opcode entries Tsukasa OI
2022-11-15 4:31 ` [PATCH v3 4/8] RISC-V: Remove unused instruction macros Tsukasa OI
2022-11-15 4:31 ` [PATCH v3 5/8] RISC-V: Complete tidying up with SCALL and SBREAK Tsukasa OI
2022-11-15 4:31 ` [PATCH v3 6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w Tsukasa OI
2022-11-15 4:31 ` [PATCH v3 7/8] RISC-V: Make alias instructions aliases Tsukasa OI
2022-11-15 4:31 ` [PATCH v3 8/8] RISC-V: Use defined mask and match values Tsukasa OI
2022-11-18 2:07 ` [PATCH v4 0/8] RISC-V: Various opcode tidying (batch 1) Tsukasa OI
2022-11-18 2:07 ` [PATCH v4 1/8] RISC-V: Add a space at the end of pinfo Tsukasa OI
2022-11-18 2:07 ` [PATCH v4 2/8] RISC-V: Fix obvious misalignments ('Zbb'/'Zba') Tsukasa OI
2022-11-18 2:07 ` [PATCH v4 3/8] RISC-V: Remove spaces in opcode entries Tsukasa OI
2022-11-18 2:07 ` [PATCH v4 4/8] RISC-V: Remove unused instruction macros Tsukasa OI
2022-11-18 2:07 ` [PATCH v4 5/8] RISC-V: Complete tidying up with SCALL and SBREAK Tsukasa OI
2022-11-18 2:07 ` [PATCH v4 6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w Tsukasa OI
2022-11-18 2:07 ` [PATCH v4 7/8] RISC-V: Make alias instructions aliases Tsukasa OI
2022-11-18 2:07 ` Tsukasa OI [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=3c1e28e61eb0275d0fd02a7d9ff956cc4f589104.1668737241.git.research_trasio@irq.a4lg.com \
--to=research_trasio@irq.a4lg.com \
--cc=binutils@sourceware.org \
--cc=kito.cheng@sifive.com \
--cc=nelson@rivosinc.com \
--cc=palmer@dabbelt.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).