From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Nelson Chu <nelson@rivosinc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH v4 0/8] RISC-V: Various opcode tidying (batch 1)
Date: Fri, 18 Nov 2022 02:07:47 +0000 [thread overview]
Message-ID: <cover.1668737241.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1668486687.git.research_trasio@irq.a4lg.com>
PATCH v1: <https://sourceware.org/pipermail/binutils/2022-July/121691.html>
PATCH v2: <https://sourceware.org/pipermail/binutils/2022-October/123707.html>
PATCH v3: <https://sourceware.org/pipermail/binutils/2022-November/124369.html>
[Changes: v3 -> v4]
- (Mainly related to PATCH 1/8)
Rebase to track commit 4a3bc79bf4c ("RISC-V: Add T-Head Fmv vendor
extension") and 01804a098de ("RISC-V: Add T-Head Int vendor extension").
- PATCH 3/8
Remove some extra spaces around ("|") I forgot to remove.
[Changes: v2 -> v3]
- Rebase to resolve conflict with commit a8d181c0fdae
("RISC-V: xtheadfmemidx: Use fp register in mnemonics").
This e-mail is followed by the same cover letter as v2.
=============
Hello,
This patchset contains various tidying of RISC-V opcodes that would...
(a) Make coding style more consistent and/or more readable
(b) Remove unused constants
(c) Make new instruction names primary (clean old names except aliases)
(d) Make opcode entries functionally consistent.
I call this "batch 1" and deals with the most obvious (yet small and
various) issues.
[Overview of this Patchset]
PATCH 1/8: (a) Tidying (add space at the tail of pinfo)
PATCH 2/8: (a) Tidying (fix obvious misalignments on 'Zbb'/'Zba')
PATCH 3/8: (a) Tidying (remove spaces around "|" operator)
PATCH 4/8: (b) Remove unused instruction macros
PATCH 5/8: (c) SCALL -> ECALL, SBREAK -> EBREAK (RISC-V ISA v2.1)
PATCH 6/8: (c) FMV.S.X -> FMV.W.X, FMV.X.S -> FMV.X.W (RISC-V ISA v2.2)
PATCH 7/8: (c) Make old instruction names aliases
PATCH 8/8: (d) Use defined (and named) constants for instruction defining
Thanks,
Tsukasa
Tsukasa OI (8):
RISC-V: Add a space at the end of pinfo
RISC-V: Fix obvious misalignments ('Zbb'/'Zba')
RISC-V: Remove spaces in opcode entries
RISC-V: Remove unused instruction macros
RISC-V: Complete tidying up with SCALL and SBREAK
RISC-V: Tidying up with fmv.w.x and fmv.x.w
RISC-V: Make alias instructions aliases
RISC-V: Use defined mask and match values
include/opcode/riscv-opc.h | 47 +--
opcodes/riscv-opc.c | 718 ++++++++++++++++++-------------------
2 files changed, 365 insertions(+), 400 deletions(-)
base-commit: 9c93bc90d577ac191ec94503e04cdcf87a3d2a1a
--
2.38.1
next prev parent reply other threads:[~2022-11-18 2:08 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-09 9:09 [PATCH 0/5] RISC-V: Opcode " Tsukasa OI
2022-07-09 9:09 ` [PATCH 1/5] RISC-V: Remove unused instruction macros Tsukasa OI
2022-07-09 9:09 ` [PATCH 2/5] RISC-V: Complete tidying up with SCALL and SBREAK Tsukasa OI
2022-07-09 9:09 ` [PATCH 3/5] RISC-V: Tidying up with fmv.w.x and fmv.x.w Tsukasa OI
2022-07-09 9:09 ` [PATCH 4/5] RISC-V: Use defined mask and match values Tsukasa OI
2022-07-09 9:09 ` [PATCH 5/5] RISC-V: Make alias instructions aliases Tsukasa OI
2022-10-19 13:11 ` [PATCH v2 0/8] RISC-V: Various opcode tidying (batch 1) Tsukasa OI
2022-10-19 13:11 ` [PATCH v2 1/8] RISC-V: Add a space at the end of pinfo Tsukasa OI
2022-10-19 13:11 ` [PATCH v2 2/8] RISC-V: Fix obvious misalignments ('Zbb'/'Zba') Tsukasa OI
2022-10-19 13:11 ` [PATCH v2 3/8] RISC-V: Remove spaces in opcode entries Tsukasa OI
2022-10-19 13:11 ` [PATCH v2 4/8] RISC-V: Remove unused instruction macros Tsukasa OI
2022-10-19 13:11 ` [PATCH v2 5/8] RISC-V: Complete tidying up with SCALL and SBREAK Tsukasa OI
2022-10-19 13:12 ` [PATCH v2 6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w Tsukasa OI
2022-10-19 13:12 ` [PATCH v2 7/8] RISC-V: Make alias instructions aliases Tsukasa OI
2022-10-19 13:12 ` [PATCH v2 8/8] RISC-V: Use defined mask and match values Tsukasa OI
2022-11-05 11:51 ` [PING^1][PATCH v2 0/8] RISC-V: Various opcode tidying (batch 1) Tsukasa OI
2022-11-15 4:31 ` [PATCH v3 " Tsukasa OI
2022-11-15 4:31 ` [PATCH v3 1/8] RISC-V: Add a space at the end of pinfo Tsukasa OI
2022-11-15 4:31 ` [PATCH v3 2/8] RISC-V: Fix obvious misalignments ('Zbb'/'Zba') Tsukasa OI
2022-11-15 4:31 ` [PATCH v3 3/8] RISC-V: Remove spaces in opcode entries Tsukasa OI
2022-11-15 4:31 ` [PATCH v3 4/8] RISC-V: Remove unused instruction macros Tsukasa OI
2022-11-15 4:31 ` [PATCH v3 5/8] RISC-V: Complete tidying up with SCALL and SBREAK Tsukasa OI
2022-11-15 4:31 ` [PATCH v3 6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w Tsukasa OI
2022-11-15 4:31 ` [PATCH v3 7/8] RISC-V: Make alias instructions aliases Tsukasa OI
2022-11-15 4:31 ` [PATCH v3 8/8] RISC-V: Use defined mask and match values Tsukasa OI
2022-11-18 2:07 ` Tsukasa OI [this message]
2022-11-18 2:07 ` [PATCH v4 1/8] RISC-V: Add a space at the end of pinfo Tsukasa OI
2022-11-18 2:07 ` [PATCH v4 2/8] RISC-V: Fix obvious misalignments ('Zbb'/'Zba') Tsukasa OI
2022-11-18 2:07 ` [PATCH v4 3/8] RISC-V: Remove spaces in opcode entries Tsukasa OI
2022-11-18 2:07 ` [PATCH v4 4/8] RISC-V: Remove unused instruction macros Tsukasa OI
2022-11-18 2:07 ` [PATCH v4 5/8] RISC-V: Complete tidying up with SCALL and SBREAK Tsukasa OI
2022-11-18 2:07 ` [PATCH v4 6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w Tsukasa OI
2022-11-18 2:07 ` [PATCH v4 7/8] RISC-V: Make alias instructions aliases Tsukasa OI
2022-11-18 2:07 ` [PATCH v4 8/8] RISC-V: Use defined mask and match values Tsukasa OI
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