[PATCH 0/5] RISC-V: Opcode tidying (batch 1)

[Tsukasa OI <research_trasio@irq.a4lg.com>]

Hello,

This patchset contains various tidying of RISC-V opcodes (this is the
first batch).

The background of this patchset is partially semi-automated comparison
with riscv-opc.h in GNU Binutils and encoding.h generated by
riscv-opcodes (https://github.com/riscv/riscv-opcodes).

Tracker on GitHub:
<https://github.com/a4lg/binutils-gdb/wiki/riscv_opcode_tidying_1>


[Overview of this Patchset]

1.  Instruction Name Maintainance
    a.  Remove unused instructions [PATCH 1]
    b.  Use ecall/ebreak instead of scall/sbreak
        (remove scall/sbreak-related macros) [PATCH 2]
    c.  Use fmv.w.x/fmv.x.w instead of fmv.s.x/fmv.x.s [PATCH 3]
    d.  Make alias instruction real aliases [PATCH 5]
2.  Prefer using defined mask and match values
    (applies to c.nop and fence.i) [PATCH 4]


Note that this patchset doesn't:

-   Remove existing instructions
    (just removes unused mask and match macros behind the instruction)
-   Change macro values (just names and formatting)
-   Replace riscv-opc.h with riscv-opcodes generated one.


If you use riscv-opcodes for new instructions (copy portions of
encoding.h to riscv-opc.h), porting new instruction will be easy and the
result will be more consistent.  I tried this approach on upcoming
Zihintntl patchset and it worked pretty well.

This patchset is only about refactoring and maintainance.
Nothing functional.

Thanks,
Tsukasa




Tsukasa OI (5):
  RISC-V: Remove unused instruction macros
  RISC-V: Complete tidying up with SCALL and SBREAK
  RISC-V: Tidying up with fmv.w.x and fmv.x.w
  RISC-V: Use defined mask and match values
  RISC-V: Make alias instructions aliases

 include/opcode/riscv-opc.h | 47 +++++---------------------------------
 opcodes/riscv-opc.c        | 18 +++++++--------
 sim/riscv/sim-main.c       |  6 ++---
 3 files changed, 18 insertions(+), 53 deletions(-)


base-commit: d2acd4b0c5bab349aaa152d60268bc144634a844
-- 
2.34.1