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From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
	Nelson Chu <nelson@rivosinc.com>,
	Kito Cheng <kito.cheng@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH v3 5/8] RISC-V: Complete tidying up with SCALL and SBREAK
Date: Tue, 15 Nov 2022 04:31:26 +0000	[thread overview]
Message-ID: <b43454773d597c1bc51741ef09aac960fecdfbd5.1668486687.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1668486687.git.research_trasio@irq.a4lg.com>

This commit removes SCALL and SBREAK-related references except
alias opcode entries because they are renamed to ECALL and EBREAK
(respectively) in the RISC-V ISA, version 2.1.

Note that related GDBsim part is addressed on the commit b9593cb70533
("sim/riscv: Complete tidying up with SBREAK").

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_SCALL, MASK_SCALL, MATCH_SBREAK,
	MASK_SBREAK): Remove.  Also remove corresponding DECLARE_INSN
	declarations.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Use "ebreak" instead of "sbreak".
---
 include/opcode/riscv-opc.h | 6 ------
 opcodes/riscv-opc.c        | 4 ++--
 2 files changed, 2 insertions(+), 8 deletions(-)

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index a30a21fe596..949f04d49e0 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -49,10 +49,6 @@
 #define MASK_RDTIMEH  0xfffff07f
 #define MATCH_RDINSTRETH 0xc8202073
 #define MASK_RDINSTRETH  0xfffff07f
-#define MATCH_SCALL 0x73
-#define MASK_SCALL  0xffffffff
-#define MATCH_SBREAK 0x100073
-#define MASK_SBREAK  0xffffffff
 #define MATCH_BEQ 0x63
 #define MASK_BEQ  0x707f
 #define MATCH_BNE 0x1063
@@ -2727,8 +2723,6 @@ DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET)
 DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH)
 DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH)
 DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH)
-DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
-DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK)
 DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
 DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
 DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index e01fb49564b..9593964f023 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -474,8 +474,8 @@ const struct riscv_opcode riscv_opcodes[] =
 {"rdcycleh",   32, INSN_CLASS_I, "d",         MATCH_RDCYCLEH, MASK_RDCYCLEH, match_opcode, INSN_ALIAS },
 {"rdinstreth", 32, INSN_CLASS_I, "d",         MATCH_RDINSTRETH, MASK_RDINSTRETH, match_opcode, INSN_ALIAS },
 {"rdtimeh",    32, INSN_CLASS_I, "d",         MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode, INSN_ALIAS },
-{"ecall",       0, INSN_CLASS_I, "",          MATCH_SCALL, MASK_SCALL, match_opcode, 0 },
-{"scall",       0, INSN_CLASS_I, "",          MATCH_SCALL, MASK_SCALL, match_opcode, 0 },
+{"ecall",       0, INSN_CLASS_I, "",          MATCH_ECALL, MASK_ECALL, match_opcode, 0 },
+{"scall",       0, INSN_CLASS_I, "",          MATCH_ECALL, MASK_ECALL, match_opcode, 0 },
 {"xor",         0, INSN_CLASS_I, "d,s,j",     MATCH_XORI, MASK_XORI, match_opcode, INSN_ALIAS },
 {"xor",         0, INSN_CLASS_C, "Cs,Cw,Ct",  MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS },
 {"xor",         0, INSN_CLASS_C, "Cs,Ct,Cw",  MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS },
-- 
2.37.2


  parent reply	other threads:[~2022-11-15  4:32 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-09  9:09 [PATCH 0/5] RISC-V: Opcode tidying (batch 1) Tsukasa OI
2022-07-09  9:09 ` [PATCH 1/5] RISC-V: Remove unused instruction macros Tsukasa OI
2022-07-09  9:09 ` [PATCH 2/5] RISC-V: Complete tidying up with SCALL and SBREAK Tsukasa OI
2022-07-09  9:09 ` [PATCH 3/5] RISC-V: Tidying up with fmv.w.x and fmv.x.w Tsukasa OI
2022-07-09  9:09 ` [PATCH 4/5] RISC-V: Use defined mask and match values Tsukasa OI
2022-07-09  9:09 ` [PATCH 5/5] RISC-V: Make alias instructions aliases Tsukasa OI
2022-10-19 13:11 ` [PATCH v2 0/8] RISC-V: Various opcode tidying (batch 1) Tsukasa OI
2022-10-19 13:11   ` [PATCH v2 1/8] RISC-V: Add a space at the end of pinfo Tsukasa OI
2022-10-19 13:11   ` [PATCH v2 2/8] RISC-V: Fix obvious misalignments ('Zbb'/'Zba') Tsukasa OI
2022-10-19 13:11   ` [PATCH v2 3/8] RISC-V: Remove spaces in opcode entries Tsukasa OI
2022-10-19 13:11   ` [PATCH v2 4/8] RISC-V: Remove unused instruction macros Tsukasa OI
2022-10-19 13:11   ` [PATCH v2 5/8] RISC-V: Complete tidying up with SCALL and SBREAK Tsukasa OI
2022-10-19 13:12   ` [PATCH v2 6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w Tsukasa OI
2022-10-19 13:12   ` [PATCH v2 7/8] RISC-V: Make alias instructions aliases Tsukasa OI
2022-10-19 13:12   ` [PATCH v2 8/8] RISC-V: Use defined mask and match values Tsukasa OI
2022-11-05 11:51   ` [PING^1][PATCH v2 0/8] RISC-V: Various opcode tidying (batch 1) Tsukasa OI
2022-11-15  4:31   ` [PATCH v3 " Tsukasa OI
2022-11-15  4:31     ` [PATCH v3 1/8] RISC-V: Add a space at the end of pinfo Tsukasa OI
2022-11-15  4:31     ` [PATCH v3 2/8] RISC-V: Fix obvious misalignments ('Zbb'/'Zba') Tsukasa OI
2022-11-15  4:31     ` [PATCH v3 3/8] RISC-V: Remove spaces in opcode entries Tsukasa OI
2022-11-15  4:31     ` [PATCH v3 4/8] RISC-V: Remove unused instruction macros Tsukasa OI
2022-11-15  4:31     ` Tsukasa OI [this message]
2022-11-15  4:31     ` [PATCH v3 6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w Tsukasa OI
2022-11-15  4:31     ` [PATCH v3 7/8] RISC-V: Make alias instructions aliases Tsukasa OI
2022-11-15  4:31     ` [PATCH v3 8/8] RISC-V: Use defined mask and match values Tsukasa OI
2022-11-18  2:07     ` [PATCH v4 0/8] RISC-V: Various opcode tidying (batch 1) Tsukasa OI
2022-11-18  2:07       ` [PATCH v4 1/8] RISC-V: Add a space at the end of pinfo Tsukasa OI
2022-11-18  2:07       ` [PATCH v4 2/8] RISC-V: Fix obvious misalignments ('Zbb'/'Zba') Tsukasa OI
2022-11-18  2:07       ` [PATCH v4 3/8] RISC-V: Remove spaces in opcode entries Tsukasa OI
2022-11-18  2:07       ` [PATCH v4 4/8] RISC-V: Remove unused instruction macros Tsukasa OI
2022-11-18  2:07       ` [PATCH v4 5/8] RISC-V: Complete tidying up with SCALL and SBREAK Tsukasa OI
2022-11-18  2:07       ` [PATCH v4 6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w Tsukasa OI
2022-11-18  2:07       ` [PATCH v4 7/8] RISC-V: Make alias instructions aliases Tsukasa OI
2022-11-18  2:07       ` [PATCH v4 8/8] RISC-V: Use defined mask and match values Tsukasa OI

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