From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Nelson Chu <nelson@rivosinc.com>
Cc: Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
binutils@sourceware.org
Subject: Re: [PATCH 1/1] RISC-V: Fix vector CSR requirements
Date: Thu, 8 Sep 2022 16:15:18 +0900 [thread overview]
Message-ID: <46114c9e-a641-1e28-eb61-60760111e7a8@irq.a4lg.com> (raw)
In-Reply-To: <CAPpQWtBaLr5U-=78E6EGhdRFepg1E_KS0dDsOmUGfF8biTPRkg@mail.gmail.com>
On 2022/09/08 16:12, Nelson Chu wrote:
> On Thu, Sep 8, 2022 at 2:54 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>>
>> Vector CSRs are also required on smaller vector subsets.
>>
>> Not only that the most of vector CSRs are general purpose (and must be
>> accessible for every vector subsets), current minimum vector subset 'Zve32x'
>> requires fixed point arithmetic, making remaining non-general purpose
>> (fixed point arithmetic only) CSRs mandatory for such subsets.
>>
>> So, those CSRs must be accessible from 'Zve32x', not just from 'V'.
>> This commit fixes this issue which caused CSR accessibility warnings.
>>
>> gas/ChangeLog:
>>
>> * config/tc-riscv.c (riscv_csr_address): Change vector CSR
>> requirement from 'V' to 'Zve32x'.
>> * testsuite/gas/riscv/csr-version-1p9p1.l: Change vector CSR
>> requirement from 'V' to 'Zve32x'.
>> * testsuite/gas/riscv/csr-version-1p10.l: Likewise.
>> * testsuite/gas/riscv/csr-version-1p11.l: Likewise.
>> * testsuite/gas/riscv/csr-version-1p12.l: Likewise.
>
>> * testsuite/gas/riscv/vector-csrs.s: New test.
>> * testsuite/gas/riscv/vector-csrs-v.d: Likewise.
>> * testsuite/gas/riscv/vector-csrs-zve32x.d: Likewise.
>> * testsuite/gas/riscv/vector-csrs-zve32f.d: Likewise.
>> * testsuite/gas/riscv/vector-csrs-zve64x.d: Likewise.
>> * testsuite/gas/riscv/vector-csrs-zve64f.d: Likewise.
>> * testsuite/gas/riscv/vector-csrs-zve64d.d: Likewise.
>
> These seem to test the implied rules of vector extensions, not so
> related to the csr tests. Otherwise looks good to me. Please update
> and then commit when you think it's time.
vector-csrs-zve32x.d and vector-csrs-zve64x.d has additional 'Zicsr' as
I removed a CSR implication rule. Having six tests may be too much but
can I at least keep vector-csrs-zve32x.d?
Thanks,
Tsukasa
>
> Thanks
> Nelson
>
>> ---
>> gas/config/tc-riscv.c | 2 +-
>> gas/testsuite/gas/riscv/csr-version-1p10.l | 28 ++++++++++----------
>> gas/testsuite/gas/riscv/csr-version-1p11.l | 28 ++++++++++----------
>> gas/testsuite/gas/riscv/csr-version-1p12.l | 28 ++++++++++----------
>> gas/testsuite/gas/riscv/csr-version-1p9p1.l | 28 ++++++++++----------
>> gas/testsuite/gas/riscv/vector-csrs-v.d | 21 +++++++++++++++
>> gas/testsuite/gas/riscv/vector-csrs-zve32f.d | 21 +++++++++++++++
>> gas/testsuite/gas/riscv/vector-csrs-zve32x.d | 21 +++++++++++++++
>> gas/testsuite/gas/riscv/vector-csrs-zve64d.d | 21 +++++++++++++++
>> gas/testsuite/gas/riscv/vector-csrs-zve64f.d | 21 +++++++++++++++
>> gas/testsuite/gas/riscv/vector-csrs-zve64x.d | 21 +++++++++++++++
>> gas/testsuite/gas/riscv/vector-csrs.s | 12 +++++++++
>> 12 files changed, 195 insertions(+), 57 deletions(-)
>> create mode 100644 gas/testsuite/gas/riscv/vector-csrs-v.d
>> create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32f.d
>> create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32x.d
>> create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64d.d
>> create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64f.d
>> create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64x.d
>> create mode 100644 gas/testsuite/gas/riscv/vector-csrs.s
>>
>> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
>> index 34ce68e8252..df2e201fb74 100644
>> --- a/gas/config/tc-riscv.c
>> +++ b/gas/config/tc-riscv.c
>> @@ -935,7 +935,7 @@ riscv_csr_address (const char *csr_name,
>> extension = "zkr";
>> break;
>> case CSR_CLASS_V:
>> - extension = "v";
>> + extension = "zve32x";
>> break;
>> case CSR_CLASS_SMSTATEEN:
>> case CSR_CLASS_SMSTATEEN_AND_H:
>> diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l
>> index b778453b556..999e9af1520 100644
>> --- a/gas/testsuite/gas/riscv/csr-version-1p10.l
>> +++ b/gas/testsuite/gas/riscv/csr-version-1p10.l
>> @@ -652,20 +652,20 @@
>> .*Warning: invalid CSR `fcsr', needs `f' extension
>> .*Warning: invalid CSR `seed', needs `zkr' extension
>> .*Warning: invalid CSR `seed', needs `zkr' extension
>> -.*Warning: invalid CSR `vstart', needs `v' extension
>> -.*Warning: invalid CSR `vstart', needs `v' extension
>> -.*Warning: invalid CSR `vxsat', needs `v' extension
>> -.*Warning: invalid CSR `vxsat', needs `v' extension
>> -.*Warning: invalid CSR `vxrm', needs `v' extension
>> -.*Warning: invalid CSR `vxrm', needs `v' extension
>> -.*Warning: invalid CSR `vcsr', needs `v' extension
>> -.*Warning: invalid CSR `vcsr', needs `v' extension
>> -.*Warning: invalid CSR `vl', needs `v' extension
>> -.*Warning: invalid CSR `vl', needs `v' extension
>> +.*Warning: invalid CSR `vstart', needs `zve32x' extension
>> +.*Warning: invalid CSR `vstart', needs `zve32x' extension
>> +.*Warning: invalid CSR `vxsat', needs `zve32x' extension
>> +.*Warning: invalid CSR `vxsat', needs `zve32x' extension
>> +.*Warning: invalid CSR `vxrm', needs `zve32x' extension
>> +.*Warning: invalid CSR `vxrm', needs `zve32x' extension
>> +.*Warning: invalid CSR `vcsr', needs `zve32x' extension
>> +.*Warning: invalid CSR `vcsr', needs `zve32x' extension
>> +.*Warning: invalid CSR `vl', needs `zve32x' extension
>> +.*Warning: invalid CSR `vl', needs `zve32x' extension
>> .*Warning: read-only CSR is written `csrw vl,a1'
>> -.*Warning: invalid CSR `vtype', needs `v' extension
>> -.*Warning: invalid CSR `vtype', needs `v' extension
>> +.*Warning: invalid CSR `vtype', needs `zve32x' extension
>> +.*Warning: invalid CSR `vtype', needs `zve32x' extension
>> .*Warning: read-only CSR is written `csrw vtype,a1'
>> -.*Warning: invalid CSR `vlenb', needs `v' extension
>> -.*Warning: invalid CSR `vlenb', needs `v' extension
>> +.*Warning: invalid CSR `vlenb', needs `zve32x' extension
>> +.*Warning: invalid CSR `vlenb', needs `zve32x' extension
>> .*Warning: read-only CSR is written `csrw vlenb,a1'
>> diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l
>> index 78bae817470..a099e4ecc93 100644
>> --- a/gas/testsuite/gas/riscv/csr-version-1p11.l
>> +++ b/gas/testsuite/gas/riscv/csr-version-1p11.l
>> @@ -650,20 +650,20 @@
>> .*Warning: invalid CSR `fcsr', needs `f' extension
>> .*Warning: invalid CSR `seed', needs `zkr' extension
>> .*Warning: invalid CSR `seed', needs `zkr' extension
>> -.*Warning: invalid CSR `vstart', needs `v' extension
>> -.*Warning: invalid CSR `vstart', needs `v' extension
>> -.*Warning: invalid CSR `vxsat', needs `v' extension
>> -.*Warning: invalid CSR `vxsat', needs `v' extension
>> -.*Warning: invalid CSR `vxrm', needs `v' extension
>> -.*Warning: invalid CSR `vxrm', needs `v' extension
>> -.*Warning: invalid CSR `vcsr', needs `v' extension
>> -.*Warning: invalid CSR `vcsr', needs `v' extension
>> -.*Warning: invalid CSR `vl', needs `v' extension
>> -.*Warning: invalid CSR `vl', needs `v' extension
>> +.*Warning: invalid CSR `vstart', needs `zve32x' extension
>> +.*Warning: invalid CSR `vstart', needs `zve32x' extension
>> +.*Warning: invalid CSR `vxsat', needs `zve32x' extension
>> +.*Warning: invalid CSR `vxsat', needs `zve32x' extension
>> +.*Warning: invalid CSR `vxrm', needs `zve32x' extension
>> +.*Warning: invalid CSR `vxrm', needs `zve32x' extension
>> +.*Warning: invalid CSR `vcsr', needs `zve32x' extension
>> +.*Warning: invalid CSR `vcsr', needs `zve32x' extension
>> +.*Warning: invalid CSR `vl', needs `zve32x' extension
>> +.*Warning: invalid CSR `vl', needs `zve32x' extension
>> .*Warning: read-only CSR is written `csrw vl,a1'
>> -.*Warning: invalid CSR `vtype', needs `v' extension
>> -.*Warning: invalid CSR `vtype', needs `v' extension
>> +.*Warning: invalid CSR `vtype', needs `zve32x' extension
>> +.*Warning: invalid CSR `vtype', needs `zve32x' extension
>> .*Warning: read-only CSR is written `csrw vtype,a1'
>> -.*Warning: invalid CSR `vlenb', needs `v' extension
>> -.*Warning: invalid CSR `vlenb', needs `v' extension
>> +.*Warning: invalid CSR `vlenb', needs `zve32x' extension
>> +.*Warning: invalid CSR `vlenb', needs `zve32x' extension
>> .*Warning: read-only CSR is written `csrw vlenb,a1'
>> diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l
>> index cb026bb55e0..cf8f2e25634 100644
>> --- a/gas/testsuite/gas/riscv/csr-version-1p12.l
>> +++ b/gas/testsuite/gas/riscv/csr-version-1p12.l
>> @@ -532,20 +532,20 @@
>> .*Warning: invalid CSR `fcsr', needs `f' extension
>> .*Warning: invalid CSR `seed', needs `zkr' extension
>> .*Warning: invalid CSR `seed', needs `zkr' extension
>> -.*Warning: invalid CSR `vstart', needs `v' extension
>> -.*Warning: invalid CSR `vstart', needs `v' extension
>> -.*Warning: invalid CSR `vxsat', needs `v' extension
>> -.*Warning: invalid CSR `vxsat', needs `v' extension
>> -.*Warning: invalid CSR `vxrm', needs `v' extension
>> -.*Warning: invalid CSR `vxrm', needs `v' extension
>> -.*Warning: invalid CSR `vcsr', needs `v' extension
>> -.*Warning: invalid CSR `vcsr', needs `v' extension
>> -.*Warning: invalid CSR `vl', needs `v' extension
>> -.*Warning: invalid CSR `vl', needs `v' extension
>> +.*Warning: invalid CSR `vstart', needs `zve32x' extension
>> +.*Warning: invalid CSR `vstart', needs `zve32x' extension
>> +.*Warning: invalid CSR `vxsat', needs `zve32x' extension
>> +.*Warning: invalid CSR `vxsat', needs `zve32x' extension
>> +.*Warning: invalid CSR `vxrm', needs `zve32x' extension
>> +.*Warning: invalid CSR `vxrm', needs `zve32x' extension
>> +.*Warning: invalid CSR `vcsr', needs `zve32x' extension
>> +.*Warning: invalid CSR `vcsr', needs `zve32x' extension
>> +.*Warning: invalid CSR `vl', needs `zve32x' extension
>> +.*Warning: invalid CSR `vl', needs `zve32x' extension
>> .*Warning: read-only CSR is written `csrw vl,a1'
>> -.*Warning: invalid CSR `vtype', needs `v' extension
>> -.*Warning: invalid CSR `vtype', needs `v' extension
>> +.*Warning: invalid CSR `vtype', needs `zve32x' extension
>> +.*Warning: invalid CSR `vtype', needs `zve32x' extension
>> .*Warning: read-only CSR is written `csrw vtype,a1'
>> -.*Warning: invalid CSR `vlenb', needs `v' extension
>> -.*Warning: invalid CSR `vlenb', needs `v' extension
>> +.*Warning: invalid CSR `vlenb', needs `zve32x' extension
>> +.*Warning: invalid CSR `vlenb', needs `zve32x' extension
>> .*Warning: read-only CSR is written `csrw vlenb,a1'
>> diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l b/gas/testsuite/gas/riscv/csr-version-1p9p1.l
>> index 4fac40fb589..5f298c1dda9 100644
>> --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l
>> +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.l
>> @@ -678,20 +678,20 @@
>> .*Warning: invalid CSR `fcsr', needs `f' extension
>> .*Warning: invalid CSR `seed', needs `zkr' extension
>> .*Warning: invalid CSR `seed', needs `zkr' extension
>> -.*Warning: invalid CSR `vstart', needs `v' extension
>> -.*Warning: invalid CSR `vstart', needs `v' extension
>> -.*Warning: invalid CSR `vxsat', needs `v' extension
>> -.*Warning: invalid CSR `vxsat', needs `v' extension
>> -.*Warning: invalid CSR `vxrm', needs `v' extension
>> -.*Warning: invalid CSR `vxrm', needs `v' extension
>> -.*Warning: invalid CSR `vcsr', needs `v' extension
>> -.*Warning: invalid CSR `vcsr', needs `v' extension
>> -.*Warning: invalid CSR `vl', needs `v' extension
>> -.*Warning: invalid CSR `vl', needs `v' extension
>> +.*Warning: invalid CSR `vstart', needs `zve32x' extension
>> +.*Warning: invalid CSR `vstart', needs `zve32x' extension
>> +.*Warning: invalid CSR `vxsat', needs `zve32x' extension
>> +.*Warning: invalid CSR `vxsat', needs `zve32x' extension
>> +.*Warning: invalid CSR `vxrm', needs `zve32x' extension
>> +.*Warning: invalid CSR `vxrm', needs `zve32x' extension
>> +.*Warning: invalid CSR `vcsr', needs `zve32x' extension
>> +.*Warning: invalid CSR `vcsr', needs `zve32x' extension
>> +.*Warning: invalid CSR `vl', needs `zve32x' extension
>> +.*Warning: invalid CSR `vl', needs `zve32x' extension
>> .*Warning: read-only CSR is written `csrw vl,a1'
>> -.*Warning: invalid CSR `vtype', needs `v' extension
>> -.*Warning: invalid CSR `vtype', needs `v' extension
>> +.*Warning: invalid CSR `vtype', needs `zve32x' extension
>> +.*Warning: invalid CSR `vtype', needs `zve32x' extension
>> .*Warning: read-only CSR is written `csrw vtype,a1'
>> -.*Warning: invalid CSR `vlenb', needs `v' extension
>> -.*Warning: invalid CSR `vlenb', needs `v' extension
>> +.*Warning: invalid CSR `vlenb', needs `zve32x' extension
>> +.*Warning: invalid CSR `vlenb', needs `zve32x' extension
>> .*Warning: read-only CSR is written `csrw vlenb,a1'
>> diff --git a/gas/testsuite/gas/riscv/vector-csrs-v.d b/gas/testsuite/gas/riscv/vector-csrs-v.d
>> new file mode 100644
>> index 00000000000..1376f01d83e
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/vector-csrs-v.d
>> @@ -0,0 +1,21 @@
>> +#as: -march=rv32iv -mcsr-check
>> +#source: vector-csrs.s
>> +#objdump: -d
>> +
>> +.*:[ ]+file format .*
>> +
>> +
>> +Disassembly of section .text:
>> +
>> +0+000 <target>:
>> +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart
>> +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero
>> +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat
>> +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1
>> +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm
>> +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3
>> +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr
>> +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7
>> +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl
>> +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype
>> +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
>> diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve32f.d b/gas/testsuite/gas/riscv/vector-csrs-zve32f.d
>> new file mode 100644
>> index 00000000000..9613915713b
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/vector-csrs-zve32f.d
>> @@ -0,0 +1,21 @@
>> +#as: -march=rv32i_zve32f -mcsr-check
>> +#source: vector-csrs.s
>> +#objdump: -d
>> +
>> +.*:[ ]+file format .*
>> +
>> +
>> +Disassembly of section .text:
>> +
>> +0+000 <target>:
>> +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart
>> +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero
>> +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat
>> +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1
>> +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm
>> +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3
>> +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr
>> +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7
>> +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl
>> +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype
>> +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
>> diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve32x.d b/gas/testsuite/gas/riscv/vector-csrs-zve32x.d
>> new file mode 100644
>> index 00000000000..1e18d923e8c
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/vector-csrs-zve32x.d
>> @@ -0,0 +1,21 @@
>> +#as: -march=rv32i_zicsr_zve32x -mcsr-check
>> +#source: vector-csrs.s
>> +#objdump: -d
>> +
>> +.*:[ ]+file format .*
>> +
>> +
>> +Disassembly of section .text:
>> +
>> +0+000 <target>:
>> +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart
>> +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero
>> +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat
>> +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1
>> +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm
>> +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3
>> +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr
>> +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7
>> +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl
>> +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype
>> +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
>> diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64d.d b/gas/testsuite/gas/riscv/vector-csrs-zve64d.d
>> new file mode 100644
>> index 00000000000..f42e670699a
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64d.d
>> @@ -0,0 +1,21 @@
>> +#as: -march=rv32i_zve64d -mcsr-check
>> +#source: vector-csrs.s
>> +#objdump: -d
>> +
>> +.*:[ ]+file format .*
>> +
>> +
>> +Disassembly of section .text:
>> +
>> +0+000 <target>:
>> +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart
>> +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero
>> +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat
>> +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1
>> +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm
>> +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3
>> +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr
>> +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7
>> +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl
>> +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype
>> +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
>> diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64f.d b/gas/testsuite/gas/riscv/vector-csrs-zve64f.d
>> new file mode 100644
>> index 00000000000..e88b5a3ff6e
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64f.d
>> @@ -0,0 +1,21 @@
>> +#as: -march=rv32i_zve64f -mcsr-check
>> +#source: vector-csrs.s
>> +#objdump: -d
>> +
>> +.*:[ ]+file format .*
>> +
>> +
>> +Disassembly of section .text:
>> +
>> +0+000 <target>:
>> +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart
>> +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero
>> +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat
>> +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1
>> +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm
>> +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3
>> +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr
>> +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7
>> +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl
>> +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype
>> +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
>> diff --git a/gas/testsuite/gas/riscv/vector-csrs-zve64x.d b/gas/testsuite/gas/riscv/vector-csrs-zve64x.d
>> new file mode 100644
>> index 00000000000..023dafb0364
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/vector-csrs-zve64x.d
>> @@ -0,0 +1,21 @@
>> +#as: -march=rv32i_zicsr_zve64x -mcsr-check
>> +#source: vector-csrs.s
>> +#objdump: -d
>> +
>> +.*:[ ]+file format .*
>> +
>> +
>> +Disassembly of section .text:
>> +
>> +0+000 <target>:
>> +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart
>> +[ ]+[0-9a-f]+:[ ]+00801073[ ]+csrw[ ]+vstart,zero
>> +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat
>> +[ ]+[0-9a-f]+:[ ]+0090d073[ ]+csrwi[ ]+vxsat,1
>> +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm
>> +[ ]+[0-9a-f]+:[ ]+00a1d073[ ]+csrwi[ ]+vxrm,3
>> +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr
>> +[ ]+[0-9a-f]+:[ ]+00f3d073[ ]+csrwi[ ]+vcsr,7
>> +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl
>> +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype
>> +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
>> diff --git a/gas/testsuite/gas/riscv/vector-csrs.s b/gas/testsuite/gas/riscv/vector-csrs.s
>> new file mode 100644
>> index 00000000000..7019a0588ef
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/vector-csrs.s
>> @@ -0,0 +1,12 @@
>> +target:
>> + csrr a0, vstart
>> + csrw vstart, zero
>> + csrr a0, vxsat
>> + csrwi vxsat, 1
>> + csrr a0, vxrm
>> + csrwi vxrm, 3
>> + csrr a0, vcsr
>> + csrwi vcsr, 7
>> + csrr a0, vl
>> + csrr a0, vtype
>> + csrr a0, vlenb
>> --
>> 2.34.1
>>
>
next prev parent reply other threads:[~2022-09-08 7:15 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-07 5:53 [PATCH 0/3] RISC-V: Fix CSR accessibility and implications Tsukasa OI
2022-09-07 5:53 ` [PATCH 1/3] RISC-V: Fix vector CSR requirements and imply Tsukasa OI
2022-09-07 5:53 ` [PATCH 2/3] RISC-V: Imply 'Zicsr' from 'Zkr' Tsukasa OI
2022-09-07 5:53 ` [PATCH 3/3] RISC-V: Imply 'Zicsr' from some privileged extensions Tsukasa OI
2022-09-07 6:21 ` [PATCH v2 0/3] RISC-V: Fix CSR accessibility and implications Tsukasa OI
2022-09-07 6:21 ` [PATCH v2 1/3] RISC-V: Fix vector CSR requirements and imply Tsukasa OI
2022-09-07 9:34 ` Kito Cheng
2022-09-09 11:10 ` Tsukasa OI
2022-09-07 6:21 ` [PATCH v2 2/3] RISC-V: Imply 'Zicsr' from 'Zkr' Tsukasa OI
2022-09-07 6:21 ` [PATCH v2 3/3] RISC-V: Imply 'Zicsr' from some privileged extensions Tsukasa OI
2022-09-08 6:53 ` [PATCH 0/1] RISC-V: Fix CSR accessibility on vectors Tsukasa OI
2022-09-08 6:53 ` [PATCH 1/1] RISC-V: Fix vector CSR requirements Tsukasa OI
2022-09-08 7:12 ` Nelson Chu
2022-09-08 7:15 ` Tsukasa OI [this message]
2022-09-08 7:20 ` Tsukasa OI
2022-09-07 8:49 ` [PATCH 0/3] RISC-V: Fix CSR accessibility and implications Nelson Chu
2022-09-07 9:08 ` Tsukasa OI
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