From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Nelson Chu <nelson@rivosinc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH 0/1] RISC-V: Fix CSR accessibility on vectors
Date: Thu, 8 Sep 2022 06:53:38 +0000 [thread overview]
Message-ID: <cover.1662619979.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1662531706.git.research_trasio@irq.a4lg.com>
Tracker on GitHub:
<https://github.com/a4lg/binutils-gdb/wiki/riscv_fix_csr_access_on_vector>
Previous:
<https://sourceware.org/pipermail/binutils/2022-September/122761.html>
This is a subset of previous CSR accessibility and implication patchset.
It seems making requirement of CSR_CLASS_V from 'V' to 'Zve32x' is less
debatable, I splitted this part as a separate patchset.
(Not strictly a subset; I added CSR accessibility test for 'V')
An excerpt (slightly modified) from previous cover letter follows:
On the current version of GNU Binutils, CSRs with CSR_CLASS_V means they
require the 'V' extension. However, there are a few vector subextensions
that implement vector subsets (intended for embedded processors).
- 'Zve64d' (superset of 'Zve64f')
- 'Zve64f' (superset of 'Zve32f' and 'Zve64x')
- 'Zve64x' (superset of 'Zve32x')
- 'Zve32f' (superset of 'Zve32x')
- 'Zve32x'
| Graph: Dependency graph of some vector/FP extensions and Zicsr
|
| +-------> D ---+----> F -----> Zicsr
| | ^ | ^
| | | / |
| V ---> Zve64d ---> Zve64f ---> Zve64x
| \ | |
| | V V
| +-- Zve32f ---> Zve32x
| |
| |
| +---> (Zicsr [should be added?])
They also require general purpose vector CSRs (vstart, vl, vtype and vlenb).
So, corresponding CSR_CLASS_V with the 'V' extension is inappropriate
(they should require 'Zve32x' instead, the minimum vector subset).
Remaining CSRs are:
- vxsat
- vxrm
- vcsr
They are related to fixed-point arithmetic and 18.2 "Zve*: Vector Extensions
for Embedded Processors" says:
> All Zve* extensions support all vector fixed-point arithmetic instructions
> (Vector Fixed-Point Arithmetic Instructions), except that vsmul.vv and
> vsmul.vx are not supported for EEW=64 in Zve64*.
So, their minimum requirement shall be also 'Zve32x', not 'V'.
As a consequence, we can conclude that changing requirements of CSR_CLASS_V
from 'V' to 'Zve32x' is sufficient to avoid CSR accessibility warnings.
I didn't rename CSR_CLASS_V to CSR_CLASS_ZVE32X because the name gets
difficult and there's already INSN_CLASS_V (effectively requires 'Zve32x'
with some exceptions).
Tsukasa OI (1):
RISC-V: Fix vector CSR requirements
gas/config/tc-riscv.c | 2 +-
gas/testsuite/gas/riscv/csr-version-1p10.l | 28 ++++++++++----------
gas/testsuite/gas/riscv/csr-version-1p11.l | 28 ++++++++++----------
gas/testsuite/gas/riscv/csr-version-1p12.l | 28 ++++++++++----------
gas/testsuite/gas/riscv/csr-version-1p9p1.l | 28 ++++++++++----------
gas/testsuite/gas/riscv/vector-csrs-v.d | 21 +++++++++++++++
gas/testsuite/gas/riscv/vector-csrs-zve32f.d | 21 +++++++++++++++
gas/testsuite/gas/riscv/vector-csrs-zve32x.d | 21 +++++++++++++++
gas/testsuite/gas/riscv/vector-csrs-zve64d.d | 21 +++++++++++++++
gas/testsuite/gas/riscv/vector-csrs-zve64f.d | 21 +++++++++++++++
gas/testsuite/gas/riscv/vector-csrs-zve64x.d | 21 +++++++++++++++
gas/testsuite/gas/riscv/vector-csrs.s | 12 +++++++++
12 files changed, 195 insertions(+), 57 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/vector-csrs-v.d
create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32f.d
create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve32x.d
create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64d.d
create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64f.d
create mode 100644 gas/testsuite/gas/riscv/vector-csrs-zve64x.d
create mode 100644 gas/testsuite/gas/riscv/vector-csrs.s
base-commit: f42546b6cc7468ac7d929181ed7b965ab60958ac
--
2.34.1
next prev parent reply other threads:[~2022-09-08 6:53 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-07 5:53 [PATCH 0/3] RISC-V: Fix CSR accessibility and implications Tsukasa OI
2022-09-07 5:53 ` [PATCH 1/3] RISC-V: Fix vector CSR requirements and imply Tsukasa OI
2022-09-07 5:53 ` [PATCH 2/3] RISC-V: Imply 'Zicsr' from 'Zkr' Tsukasa OI
2022-09-07 5:53 ` [PATCH 3/3] RISC-V: Imply 'Zicsr' from some privileged extensions Tsukasa OI
2022-09-07 6:21 ` [PATCH v2 0/3] RISC-V: Fix CSR accessibility and implications Tsukasa OI
2022-09-07 6:21 ` [PATCH v2 1/3] RISC-V: Fix vector CSR requirements and imply Tsukasa OI
2022-09-07 9:34 ` Kito Cheng
2022-09-09 11:10 ` Tsukasa OI
2022-09-07 6:21 ` [PATCH v2 2/3] RISC-V: Imply 'Zicsr' from 'Zkr' Tsukasa OI
2022-09-07 6:21 ` [PATCH v2 3/3] RISC-V: Imply 'Zicsr' from some privileged extensions Tsukasa OI
2022-09-08 6:53 ` Tsukasa OI [this message]
2022-09-08 6:53 ` [PATCH 1/1] RISC-V: Fix vector CSR requirements Tsukasa OI
2022-09-08 7:12 ` Nelson Chu
2022-09-08 7:15 ` Tsukasa OI
2022-09-08 7:20 ` Tsukasa OI
2022-09-07 8:49 ` [PATCH 0/3] RISC-V: Fix CSR accessibility and implications Nelson Chu
2022-09-07 9:08 ` Tsukasa OI
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