From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Nelson Chu <nelson@rivosinc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH 3/3] RISC-V: Imply 'Zicsr' from some privileged extensions
Date: Wed, 7 Sep 2022 05:53:58 +0000 [thread overview]
Message-ID: <8f1d3896c04938775d2a8bd4899474ee9e48a357.1662529938.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1662529938.git.research_trasio@irq.a4lg.com>
As 'H', 'Smstateen', 'Sscofpmf' and 'Sstc' define their own CSRs,
they implicitly require 'Zicsr' in the process.
This commit adds such implicications.
gas/ChangeLog:
* testsuite/gas/riscv/march-imply-h.d: New test, at least for 'H'.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): Add 'Zicsr' implicications
for privileged extensions 'H', 'Smstateen', 'Sscofpmf' and 'Sstc'.
---
bfd/elfxx-riscv.c | 4 ++++
gas/testsuite/gas/riscv/march-imply-h.d | 6 ++++++
2 files changed, 10 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/march-imply-h.d
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 2e91963bbfb..73848f725e6 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1047,6 +1047,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"g", "d", check_implicit_always},
{"g", "zicsr", check_implicit_always},
{"g", "zifencei", check_implicit_always},
+ {"h", "zicsr", check_implicit_always},
{"q", "d", check_implicit_always},
{"v", "d", check_implicit_always},
{"v", "zve64d", check_implicit_always},
@@ -1098,6 +1099,9 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zks", "zbkx", check_implicit_always},
{"zks", "zksed", check_implicit_always},
{"zks", "zksh", check_implicit_always},
+ {"smstateen", "zicsr", check_implicit_always},
+ {"sscofpmf", "zicsr", check_implicit_always},
+ {"sstc", "zicsr", check_implicit_always},
{NULL, NULL, NULL}
};
diff --git a/gas/testsuite/gas/riscv/march-imply-h.d b/gas/testsuite/gas/riscv/march-imply-h.d
new file mode 100644
index 00000000000..04ad9f6c0a5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-imply-h.d
@@ -0,0 +1,6 @@
+#as: -march=rv32ih -march-attr -misa-spec=20191213 -mpriv-spec=1.12
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv32i2p1_h1p0_zicsr2p0"
--
2.34.1
next prev parent reply other threads:[~2022-09-07 5:54 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-07 5:53 [PATCH 0/3] RISC-V: Fix CSR accessibility and implications Tsukasa OI
2022-09-07 5:53 ` [PATCH 1/3] RISC-V: Fix vector CSR requirements and imply Tsukasa OI
2022-09-07 5:53 ` [PATCH 2/3] RISC-V: Imply 'Zicsr' from 'Zkr' Tsukasa OI
2022-09-07 5:53 ` Tsukasa OI [this message]
2022-09-07 6:21 ` [PATCH v2 0/3] RISC-V: Fix CSR accessibility and implications Tsukasa OI
2022-09-07 6:21 ` [PATCH v2 1/3] RISC-V: Fix vector CSR requirements and imply Tsukasa OI
2022-09-07 9:34 ` Kito Cheng
2022-09-09 11:10 ` Tsukasa OI
2022-09-07 6:21 ` [PATCH v2 2/3] RISC-V: Imply 'Zicsr' from 'Zkr' Tsukasa OI
2022-09-07 6:21 ` [PATCH v2 3/3] RISC-V: Imply 'Zicsr' from some privileged extensions Tsukasa OI
2022-09-08 6:53 ` [PATCH 0/1] RISC-V: Fix CSR accessibility on vectors Tsukasa OI
2022-09-08 6:53 ` [PATCH 1/1] RISC-V: Fix vector CSR requirements Tsukasa OI
2022-09-08 7:12 ` Nelson Chu
2022-09-08 7:15 ` Tsukasa OI
2022-09-08 7:20 ` Tsukasa OI
2022-09-07 8:49 ` [PATCH 0/3] RISC-V: Fix CSR accessibility and implications Nelson Chu
2022-09-07 9:08 ` Tsukasa OI
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