From: jiawei@iscas.ac.cn
To: "Tsukasa OI" <research_trasio@irq.a4lg.com>
Cc: "Nelson Chu" <nelson.chu@sifive.com>,
"Kito Cheng" <kito.cheng@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
binutils@sourceware.org
Subject: Re: [REVIEW ONLY 2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions
Date: Tue, 29 Nov 2022 14:35:30 +0800 (GMT+08:00) [thread overview]
Message-ID: <47b60bda.af2d.184c2190405.Coremail.jiawei@iscas.ac.cn> (raw)
In-Reply-To: <20220627020348.11920-6-research_trasio@irq.a4lg.com>
> [DO NOT MERGE]
> RISC-V Profiles are frozen but -- from my view -- this document will still
> change in some way. Meanwhile, this patch should not be merged upstream.
> This commit uses tentative version 1.0 (as there are no versions).
>
> RISC-V Profiles document defines number of "extensions" that indicate
> certain platform properties/capabilities just like 'Zkt' extension from the
> RISC-V cryptography extensions.
>
> This commit defines 19 platform property/capability extensions as defined
> in the RISC-V Profiles documentation.
> The version number is tentatively set to 1.0.
>
> The only exception: 'Ssstateen' extension is defined separately because it
> defines a subset (supervisor/hypervisor view) of the 'Smstateen' extension.
>
> This is based on the latest version of RISC-V Profiles (version 0.9-draft):
> <https: github.com="" riscv="" riscv-profiles="" commit="" 226b7f643067b29abc6723fac60d5f6d3f9eb901="">
>
> [Definition]
>
> "Main memory regions": memory regions with both the cacheability
> and coherence PMAs.
>
> [New Unprivileged Extensions]
>
> 1. 'Ziccif'
> "Main memory regions" support instruction fetch and any instruction
> fetches of naturally aligned power-of-2 sizes up to min(ILEN, XLEN)
> are atomic.
> 2. 'Ziccrse'
> "Main memory regions" provide the eventual success guarantee for
> LR/SC sequence.
> 3. 'Ziccamoa'
> "Main memory regions" support all AMO operations including atomic swap,
> logical and arithmetic operations.
> 4. 'Za64rs'
> For LR/SC instructions, reservation sets are contiguous, naturally
> aligned and at most 64-bytes in size.
> 5. 'Za128rs'
> Likewise, but reservation sets are at most 128-bytes in size.
> 6. 'Zicclsm'
> Misaligned loads / stores to "main memory regions" are supported.
> Those include both regular scalar and vector access but does not include
> AMOs and other specialized forms of memory access.
> 7. 'Zic64b'
> Cache blocks are (exactly) 64-bytes in size and naturally aligned.
>
> [New Privileged Extensions]
>
> 1. 'Svbare'
> "satp" mode Bare is supported.
> 2. 'Ssptead'
> Page-fault exceptions are raised when a page is accessed when A bit is
> clear, or written when D bit is clear.
> 3. 'Ssccptr'
> "Main memory regions" support hardware page-table reads.
> 4. 'Sstvecd'
> "stvec" mode Direct is supported. When "stvec" mode is Direct,
> "stvec.BASE" is capable of holding any valid 4-byte aligned address.
> 5. 'Sstvala'
> "stval" is always written with a nonzero value whenever possible as
> specified in the Privileged Architecture documentation
> (version 20211203: see section 4.1.9).
> 6. 'Ssu64xl'
> "sstatus.UXL"=64 [sic].
> 7. 'Shcounterenw'
> For any "hpmcounter" that is not read-only zero, the corresponding bit
> in "hcounteren" is writable.
> 8. 'Shvstvala'
> Similar to 'Sstvala' but the same rule applies to "vstval".
> 9. 'Shtvala'
> "htval" is written with the faulting guest physical address as long as
> permitted by the ISA (a bit similar to 'Sstvala' and 'Shvstvala').
> 10. 'Shvstvecd'
> Similar to 'Sstvecd' but the same rule applies to "vstvec".
> 11. 'Shvsatpa'
> All translation modes supported in "satp" are also supported in "vsatp".
> 12. 'Shgatpa'
> For each supported virtual memory scheme SvNN supported in "satp", the
> corresponding "hgatp" SvNNx4 mode is supported. The "hgatp" mode Bare
> is also supported.
>
> [Implications]
>
> (Due to reservation set size constraints)
> - 'Za64rs' -> 'Za128rs'
>
> (Due to the fact that a privileged "extension" directly refers a CSR)
> - 'Svbare' -> 'Zicsr'
> - 'Sstvecd' -> 'Zicsr'
> - 'Sstvala' -> 'Zicsr'
> - 'Ssu64xl' -> 'Zicsr'
>
> (Due to the fact that a privileged "extension" indirectly depends on CSRs)
> - 'Ssptead' -> 'Zicsr'
> - 'Ssccptr' -> 'Zicsr'
>
> (Due to the fact that a privileged "extension" is a hypervisor property)
> - 'Shcounterenw' -> 'H'
> - 'Shvstvala' -> 'H'
> - 'Shtvala' -> 'H'
> - 'Shvstvecd' -> 'H'
> - 'Shvsatpa' -> 'H'
> - 'Shgatpa' -> 'H'
>
> bfd/ChangeLog:
>
> * elfxx-riscv.c
> (riscv_implicit_subsets): Add 13 implication rules.
> (riscv_supported_std_z_ext) Add 7 property/capability extensions.
> (riscv_supported_std_s_ext) Add 12 property/capability extensions.
> ---
> bfd/elfxx-riscv.c | 34 +++++++++++++++++++++++++++++++++-
> 1 file changed, 33 insertions(+), 1 deletion(-)
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 781b57cbd98..64811a138a3 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1047,7 +1047,6 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
> {"g", "zicsr", check_implicit_always},
> {"g", "zifencei", check_implicit_always},
> {"m", "zmmul", check_implicit_always},
> - {"h", "zicsr", check_implicit_always},
> {"q", "d", check_implicit_always},
> {"v", "d", check_implicit_always},
> {"v", "zve64d", check_implicit_always},
> @@ -1083,6 +1082,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
> {"zhinx", "zhinxmin", check_implicit_always},
> {"zhinxmin", "zfinx", check_implicit_always},
> {"zfinx", "zicsr", check_implicit_always},
> + {"za64rs", "za128rs", check_implicit_always},
> {"zk", "zkn", check_implicit_always},
> {"zk", "zkr", check_implicit_always},
> {"zk", "zkt", check_implicit_always},
> @@ -1099,9 +1099,22 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
> {"zks", "zksh", check_implicit_always},
> {"smstateen", "ssstateen", check_implicit_always},
> {"smepmp", "zicsr", check_implicit_always},
> + {"shcounterenw", "h", check_implicit_always},
> + {"shgatpa", "h", check_implicit_always},
> + {"shtvala", "h", check_implicit_always},
> + {"shvsatpa", "h", check_implicit_always},
> + {"shvstvala", "h", check_implicit_always},
> + {"shvstvecd", "h", check_implicit_always},
> + {"h", "zicsr", check_implicit_always},
> + {"ssccptr", "zicsr", check_implicit_always},
> {"sscofpmf", "zicsr", check_implicit_always},
> + {"ssptead", "zicsr", check_implicit_always},
> {"ssstateen", "zicsr", check_implicit_always},
> {"sstc", "zicsr", check_implicit_always},
> + {"sstvala", "zicsr", check_implicit_always},
> + {"sstvecd", "zicsr", check_implicit_always},
> + {"ssu64xl", "zicsr", check_implicit_always},
> + {"svbare", "zicsr", check_implicit_always},
> {NULL, NULL, NULL}
> };
>
> @@ -1159,6 +1172,11 @@ static struct riscv_supported_ext riscv_supported_std_ext[] =
>
> static struct riscv_supported_ext riscv_supported_std_z_ext[] =
> {
> + {"zic64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"ziccamoa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"ziccif", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zicclsm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"ziccrse", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> @@ -1168,6 +1186,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
> {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
> {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
> {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"za64rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"za128rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> @@ -1217,11 +1237,23 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
>
> static struct riscv_supported_ext riscv_supported_std_s_ext[] =
> {
> + {"shcounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"shgatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"shtvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"shvsatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"shvstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"shvstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"ssccptr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"ssptead", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"ssstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"sstc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"sstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"sstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"ssu64xl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"svbare", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"svinval", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"svnapot", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"svpbmt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> --
> 2.37.2
LGTM, since some extensions are optional in profile and not documented yet,
I'm not sure if we need to add all of them here, anyway thanks for your works.
</https:>
next prev parent reply other threads:[~2022-11-29 6:35 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-27 2:03 [PATCH v2 0/8] RISC-V: Combined floating point enhancements Tsukasa OI
2022-06-27 2:03 ` [PATCH v2 1/8] RISC-V: Refactor Zfh/Zhinx-related constants Tsukasa OI
2022-06-27 2:03 ` [PATCH v2 2/8] RISC-V: Add instruction declaration for Zfh/Zhinx Tsukasa OI
2022-06-27 2:03 ` [PATCH v2 3/8] RISC-V: Add Zfhmin/Zhinxmin (with refactoring) Tsukasa OI
2022-07-05 14:21 ` Kito Cheng
2022-07-05 23:19 ` Andrew Waterman
2022-07-07 2:57 ` Kito Cheng
2022-07-07 4:43 ` Nelson Chu
2022-07-08 5:37 ` Tsukasa OI
2022-07-07 6:10 ` Andrew Waterman
2022-07-07 8:59 ` Nelson Chu
2022-06-27 2:03 ` [PATCH v2 4/8] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI
2022-07-07 2:58 ` Kito Cheng
2022-07-07 4:25 ` Nelson Chu
2022-06-27 2:03 ` [PATCH v2 5/8] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI
2022-06-27 2:29 ` jiawei
2022-11-29 6:35 ` jiawei [this message]
2022-06-27 2:03 ` [PATCH v2 6/8] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-06-27 2:03 ` [PATCH v2 7/8] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-06-27 2:03 ` [PATCH v2 8/8] RISC-V: Add testcases for Z[dq]inx " Tsukasa OI
2022-11-03 12:26 [REVIEW ONLY 0/2] NEAR RATIFICATION RISC-V: Extensions from the RISC-V Profiles Tsukasa OI
2022-11-03 12:26 ` [REVIEW ONLY 2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions Tsukasa OI
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