From: Kito Cheng <kito.cheng@gmail.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: Weiwei Li <liweiwei@iscas.ac.cn>,
Nelson Chu <nelson.chu@sifive.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Binutils <binutils@sourceware.org>
Subject: Re: [PATCH v2 4/8] RISC-V: Fix disassembling Zfinx with -M numeric
Date: Thu, 7 Jul 2022 10:58:39 +0800 [thread overview]
Message-ID: <CA+yXCZC38qwJagrNGCUNsYr0jC_+C86fit8FiGi4e6WjwsJDbA@mail.gmail.com> (raw)
In-Reply-To: <20220627020348.11920-5-research_trasio@irq.a4lg.com>
LGTM
On Mon, Jun 27, 2022 at 10:08 AM Tsukasa OI via Binutils
<binutils@sourceware.org> wrote:
>
> This commit fixes floating point operand register names from ABI ones
> to dynamically set ones.
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/zfinx-dis-numeric.s: Test new behavior of
> Zfinx extension and -M numeric disassembler option.
> * testsuite/gas/riscv/zfinx-dis-numeric.d: Likewise.
>
> opcodes/ChangeLog:
>
> * riscv-dis.c (riscv_disassemble_insn): Use dynamically set GPR
> names to disassemble Zfinx instructions.
> ---
> gas/testsuite/gas/riscv/zfinx-dis-numeric.d | 10 ++++++++++
> gas/testsuite/gas/riscv/zfinx-dis-numeric.s | 2 ++
> opcodes/riscv-dis.c | 2 +-
> 3 files changed, 13 insertions(+), 1 deletion(-)
> create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.d
> create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.s
>
> diff --git a/gas/testsuite/gas/riscv/zfinx-dis-numeric.d b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d
> new file mode 100644
> index 00000000000..ba3f62295eb
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d
> @@ -0,0 +1,10 @@
> +#as: -march=rv64ima_zfinx
> +#source: zfinx-dis-numeric.s
> +#objdump: -dr -Mnumeric
> +
> +.*:[ ]+file format .*
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+a0c5a553[ ]+feq.s[ ]+x10,x11,x12
> diff --git a/gas/testsuite/gas/riscv/zfinx-dis-numeric.s b/gas/testsuite/gas/riscv/zfinx-dis-numeric.s
> new file mode 100644
> index 00000000000..b55cbd56b21
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zfinx-dis-numeric.s
> @@ -0,0 +1,2 @@
> +target:
> + feq.s a0, a1, a2
> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> index 9ff31167775..164fd209dbd 100644
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -639,7 +639,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
>
> /* If arch has ZFINX flags, use gpr for disassemble. */
> if(riscv_subset_supports (&riscv_rps_dis, "zfinx"))
> - riscv_fpr_names = riscv_gpr_names_abi;
> + riscv_fpr_names = riscv_gpr_names;
>
> for (; op->name; op++)
> {
> --
> 2.25.1
>
next prev parent reply other threads:[~2022-07-07 2:58 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-27 2:03 [PATCH v2 0/8] RISC-V: Combined floating point enhancements Tsukasa OI
2022-06-27 2:03 ` [PATCH v2 1/8] RISC-V: Refactor Zfh/Zhinx-related constants Tsukasa OI
2022-06-27 2:03 ` [PATCH v2 2/8] RISC-V: Add instruction declaration for Zfh/Zhinx Tsukasa OI
2022-06-27 2:03 ` [PATCH v2 3/8] RISC-V: Add Zfhmin/Zhinxmin (with refactoring) Tsukasa OI
2022-07-05 14:21 ` Kito Cheng
2022-07-05 23:19 ` Andrew Waterman
2022-07-07 2:57 ` Kito Cheng
2022-07-07 4:43 ` Nelson Chu
2022-07-08 5:37 ` Tsukasa OI
2022-07-07 6:10 ` Andrew Waterman
2022-07-07 8:59 ` Nelson Chu
2022-06-27 2:03 ` [PATCH v2 4/8] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI
2022-07-07 2:58 ` Kito Cheng [this message]
2022-07-07 4:25 ` Nelson Chu
2022-06-27 2:03 ` [PATCH v2 5/8] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI
2022-06-27 2:29 ` jiawei
2022-11-29 6:35 ` [REVIEW ONLY 2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions jiawei
2022-06-27 2:03 ` [PATCH v2 6/8] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-06-27 2:03 ` [PATCH v2 7/8] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-06-27 2:03 ` [PATCH v2 8/8] RISC-V: Add testcases for Z[dq]inx " Tsukasa OI
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