From: Nelson Chu <nelson.chu@sifive.com>
To: Andrew Waterman <andrew@sifive.com>
Cc: Kito Cheng <kito.cheng@gmail.com>,
Tsukasa OI <research_trasio@irq.a4lg.com>,
Kito Cheng <kito.cheng@sifive.com>,
Weiwei Li <liweiwei@iscas.ac.cn>,
Binutils <binutils@sourceware.org>
Subject: Re: [PATCH v2 3/8] RISC-V: Add Zfhmin/Zhinxmin (with refactoring)
Date: Thu, 7 Jul 2022 16:59:05 +0800 [thread overview]
Message-ID: <CAJYME4EgWxaOnT=u4EyE+RxF+4vT=376UG8d43MzOnd1uoRtMQ@mail.gmail.com> (raw)
In-Reply-To: <CA++6G0D4_fUYBgtBY3tCn+RbNMwOE8XWT2dLHkNjkKzHKvLExw@mail.gmail.com>
OK, thanks.
Fixed conflicts which were caused by the commit
37cf60c6a6d36bbf5cf1523697906c4bdb4eb468, and then committed.
Nelson
On Thu, Jul 7, 2022 at 2:10 PM Andrew Waterman <andrew@sifive.com> wrote:
>
> On Wed, Jul 6, 2022 at 7:57 PM Kito Cheng <kito.cheng@gmail.com> wrote:
> >
> > Hi Andrew:
> >
> > The sound makes sense to me, but personally I would prefer to keep
> > fmv.h for zfh to make that consistent with fmv.* :P
>
> SGTM, the symmetry argument works for me.
>
> >
> > Hi Tsukasa, Nelson:
> >
> > I am OK with the current version, and verified with GCC.
> >
> > On Wed, Jul 6, 2022 at 7:19 AM Andrew Waterman <andrew@sifive.com> wrote:
> > >
> > > IMO, we should not add this alias for Zfhmin, reason being that it
> > > would mean FMV.H has different semantics in Zfhmin vs. Zfh.
> > >
> > > Yes, the behavior is the same if the input is a NaN-boxed
> > > half-precision number, but what if it isn't? Namely, what if the
> > > programmer accidentally uses FMV.H to move a single-precision number?
> > > This would work correctly when assembling for Zfhmin, but would fail
> > > when assembling for Zfh. Obviously, this is a programming error, but
> > > it still seems a bit unfortunate to me.
> > >
> > > (In fact, we could consider deleting the FMV.H alias altogether--even
> > > for Zfh. We would then recommend programmers and compilers always use
> > > FMV.S to move half-precision floating-point numbers for both Zfh and
> > > Zfhmin.)
> > >
> > >
> > >
> > > On Tue, Jul 5, 2022 at 7:22 AM Kito Cheng via Binutils
> > > <binutils@sourceware.org> wrote:
> > > >
> > > > > +{"fmv.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,U", MATCH_FSGNJ_H, MASK_FSGNJ_H, match_rs1_eq_rs2, INSN_ALIAS },
> > > > Maybe we need one more alias for ZFHMIN? like this: {"fmv.h", 0,
> > > > INSN_CLASS_ZFHMIN, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S,
> > > > match_rs1_eq_rs2, INSN_ALIAS },
> > > >
> > > > ---
> > > > Spec say:
> > > > Zfhmin does not include the FSGNJ.H instruction, because it suffices to
> > > > instead use the FSGNJ.S instruction to move half-precision values between
> > > > floating-point registers.
next prev parent reply other threads:[~2022-07-07 8:59 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-27 2:03 [PATCH v2 0/8] RISC-V: Combined floating point enhancements Tsukasa OI
2022-06-27 2:03 ` [PATCH v2 1/8] RISC-V: Refactor Zfh/Zhinx-related constants Tsukasa OI
2022-06-27 2:03 ` [PATCH v2 2/8] RISC-V: Add instruction declaration for Zfh/Zhinx Tsukasa OI
2022-06-27 2:03 ` [PATCH v2 3/8] RISC-V: Add Zfhmin/Zhinxmin (with refactoring) Tsukasa OI
2022-07-05 14:21 ` Kito Cheng
2022-07-05 23:19 ` Andrew Waterman
2022-07-07 2:57 ` Kito Cheng
2022-07-07 4:43 ` Nelson Chu
2022-07-08 5:37 ` Tsukasa OI
2022-07-07 6:10 ` Andrew Waterman
2022-07-07 8:59 ` Nelson Chu [this message]
2022-06-27 2:03 ` [PATCH v2 4/8] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI
2022-07-07 2:58 ` Kito Cheng
2022-07-07 4:25 ` Nelson Chu
2022-06-27 2:03 ` [PATCH v2 5/8] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI
2022-06-27 2:29 ` jiawei
2022-11-29 6:35 ` [REVIEW ONLY 2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions jiawei
2022-06-27 2:03 ` [PATCH v2 6/8] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-06-27 2:03 ` [PATCH v2 7/8] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-06-27 2:03 ` [PATCH v2 8/8] RISC-V: Add testcases for Z[dq]inx " Tsukasa OI
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