Re: [PATCH v2 4/8] RISC-V: Fix disassembling Zfinx with -M numeric

[Nelson Chu <nelson.chu@sifive.com>]

Committed, thanks.

Nelson

On Thu, Jul 7, 2022 at 10:58 AM Kito Cheng <kito.cheng@gmail.com> wrote:
>
> LGTM
>
> On Mon, Jun 27, 2022 at 10:08 AM Tsukasa OI via Binutils
> <binutils@sourceware.org> wrote:
> >
> > This commit fixes floating point operand register names from ABI ones
> > to dynamically set ones.
> >
> > gas/ChangeLog:
> >
> >         * testsuite/gas/riscv/zfinx-dis-numeric.s: Test new behavior of
> >         Zfinx extension and -M numeric disassembler option.
> >         * testsuite/gas/riscv/zfinx-dis-numeric.d: Likewise.
> >
> > opcodes/ChangeLog:
> >
> >         * riscv-dis.c (riscv_disassemble_insn): Use dynamically set GPR
> >         names to disassemble Zfinx instructions.
> > ---
> >  gas/testsuite/gas/riscv/zfinx-dis-numeric.d | 10 ++++++++++
> >  gas/testsuite/gas/riscv/zfinx-dis-numeric.s |  2 ++
> >  opcodes/riscv-dis.c                         |  2 +-
> >  3 files changed, 13 insertions(+), 1 deletion(-)
> >  create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.d
> >  create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.s
> >
> > diff --git a/gas/testsuite/gas/riscv/zfinx-dis-numeric.d b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d
> > new file mode 100644
> > index 00000000000..ba3f62295eb
> > --- /dev/null
> > +++ b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d
> > @@ -0,0 +1,10 @@
> > +#as: -march=rv64ima_zfinx
> > +#source: zfinx-dis-numeric.s
> > +#objdump: -dr -Mnumeric
> > +
> > +.*:[   ]+file format .*
> > +
> > +Disassembly of section .text:
> > +
> > +0+000 <target>:
> > +[      ]+[0-9a-f]+:[   ]+a0c5a553[     ]+feq.s[        ]+x10,x11,x12
> > diff --git a/gas/testsuite/gas/riscv/zfinx-dis-numeric.s b/gas/testsuite/gas/riscv/zfinx-dis-numeric.s
> > new file mode 100644
> > index 00000000000..b55cbd56b21
> > --- /dev/null
> > +++ b/gas/testsuite/gas/riscv/zfinx-dis-numeric.s
> > @@ -0,0 +1,2 @@
> > +target:
> > +       feq.s   a0, a1, a2
> > diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> > index 9ff31167775..164fd209dbd 100644
> > --- a/opcodes/riscv-dis.c
> > +++ b/opcodes/riscv-dis.c
> > @@ -639,7 +639,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
> >
> >        /* If arch has ZFINX flags, use gpr for disassemble.  */
> >        if(riscv_subset_supports (&riscv_rps_dis, "zfinx"))
> > -       riscv_fpr_names = riscv_gpr_names_abi;
> > +       riscv_fpr_names = riscv_gpr_names;
> >
> >        for (; op->name; op++)
> >         {
> > --
> > 2.25.1
> >