From: Kito Cheng <kito.cheng@gmail.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: Weiwei Li <liweiwei@iscas.ac.cn>,
Nelson Chu <nelson.chu@sifive.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Binutils <binutils@sourceware.org>
Subject: Re: [PATCH v2 3/8] RISC-V: Add Zfhmin/Zhinxmin (with refactoring)
Date: Tue, 5 Jul 2022 22:21:35 +0800 [thread overview]
Message-ID: <CA+yXCZCFvrvwr56DkJuUW1D91NJByzueh6=tSFdWEMYdw59VVw@mail.gmail.com> (raw)
In-Reply-To: <20220627020348.11920-4-research_trasio@irq.a4lg.com>
> +{"fmv.h", 0, INSN_CLASS_ZFH_OR_ZHINX, "D,U", MATCH_FSGNJ_H, MASK_FSGNJ_H, match_rs1_eq_rs2, INSN_ALIAS },
Maybe we need one more alias for ZFHMIN? like this: {"fmv.h", 0,
INSN_CLASS_ZFHMIN, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S,
match_rs1_eq_rs2, INSN_ALIAS },
---
Spec say:
Zfhmin does not include the FSGNJ.H instruction, because it suffices to
instead use the FSGNJ.S instruction to move half-precision values between
floating-point registers.
next prev parent reply other threads:[~2022-07-05 14:21 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-27 2:03 [PATCH v2 0/8] RISC-V: Combined floating point enhancements Tsukasa OI
2022-06-27 2:03 ` [PATCH v2 1/8] RISC-V: Refactor Zfh/Zhinx-related constants Tsukasa OI
2022-06-27 2:03 ` [PATCH v2 2/8] RISC-V: Add instruction declaration for Zfh/Zhinx Tsukasa OI
2022-06-27 2:03 ` [PATCH v2 3/8] RISC-V: Add Zfhmin/Zhinxmin (with refactoring) Tsukasa OI
2022-07-05 14:21 ` Kito Cheng [this message]
2022-07-05 23:19 ` Andrew Waterman
2022-07-07 2:57 ` Kito Cheng
2022-07-07 4:43 ` Nelson Chu
2022-07-08 5:37 ` Tsukasa OI
2022-07-07 6:10 ` Andrew Waterman
2022-07-07 8:59 ` Nelson Chu
2022-06-27 2:03 ` [PATCH v2 4/8] RISC-V: Fix disassembling Zfinx with -M numeric Tsukasa OI
2022-07-07 2:58 ` Kito Cheng
2022-07-07 4:25 ` Nelson Chu
2022-06-27 2:03 ` [PATCH v2 5/8] RISC-V: Reorganize and enhance Zfinx tests Tsukasa OI
2022-06-27 2:29 ` jiawei
2022-11-29 6:35 ` [REVIEW ONLY 2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions jiawei
2022-06-27 2:03 ` [PATCH v2 6/8] RISC-V: Relax `fmv.[sdq]' requirements Tsukasa OI
2022-06-27 2:03 ` [PATCH v2 7/8] RISC-V: Validate Zdinx/Zqinx register pairs Tsukasa OI
2022-06-27 2:03 ` [PATCH v2 8/8] RISC-V: Add testcases for Z[dq]inx " Tsukasa OI
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CA+yXCZCFvrvwr56DkJuUW1D91NJByzueh6=tSFdWEMYdw59VVw@mail.gmail.com' \
--to=kito.cheng@gmail.com \
--cc=binutils@sourceware.org \
--cc=kito.cheng@sifive.com \
--cc=liweiwei@iscas.ac.cn \
--cc=nelson.chu@sifive.com \
--cc=palmer@dabbelt.com \
--cc=research_trasio@irq.a4lg.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).