From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: binutils@sourceware.org
Subject: [PATCH 3/5] RISC-V: Cache management instruction testcases
Date: Thu, 16 Dec 2021 20:04:56 +0900 [thread overview]
Message-ID: <66adc97da6d4f94d8d4cfec4c907dbbbe7033c35.1639652695.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1639652695.git.research_trasio@irq.a4lg.com>
This commit adds assembler testsuite for Zicbom/Zicboz instructions.
* testsuite/gas/riscv/zicbom.d: New cache-block management
instruction tests.
* testsuite/gas/riscv/zicbom.s: Likewise.
* testsuite/gas/riscv/zicboz.d: New cache-block zero instruction
tests.
* testsuite/gas/riscv/zicboz.s: Likewise.
---
gas/testsuite/gas/riscv/zicbom.d | 15 +++++++++++++++
gas/testsuite/gas/riscv/zicbom.s | 7 +++++++
gas/testsuite/gas/riscv/zicboz.d | 11 +++++++++++
gas/testsuite/gas/riscv/zicboz.s | 3 +++
4 files changed, 36 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zicbom.d
create mode 100644 gas/testsuite/gas/riscv/zicbom.s
create mode 100644 gas/testsuite/gas/riscv/zicboz.d
create mode 100644 gas/testsuite/gas/riscv/zicboz.s
diff --git a/gas/testsuite/gas/riscv/zicbom.d b/gas/testsuite/gas/riscv/zicbom.d
new file mode 100644
index 00000000000..3a194cf6edf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbom.d
@@ -0,0 +1,15 @@
+#as: -march=rv64g_zicbom
+#source: zicbom.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0010a00f[ ]+cbo\.clean[ ]+ra
+[ ]+[0-9a-f]+:[ ]+001f200f[ ]+cbo\.clean[ ]+t5
+[ ]+[0-9a-f]+:[ ]+0020a00f[ ]+cbo\.flush[ ]+ra
+[ ]+[0-9a-f]+:[ ]+002f200f[ ]+cbo\.flush[ ]+t5
+[ ]+[0-9a-f]+:[ ]+0000a00f[ ]+cbo\.inval[ ]+ra
+[ ]+[0-9a-f]+:[ ]+000f200f[ ]+cbo\.inval[ ]+t5
diff --git a/gas/testsuite/gas/riscv/zicbom.s b/gas/testsuite/gas/riscv/zicbom.s
new file mode 100644
index 00000000000..778a61e76f3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbom.s
@@ -0,0 +1,7 @@
+target:
+ cbo.clean x1
+ cbo.clean x30
+ cbo.flush x1
+ cbo.flush x30
+ cbo.inval x1
+ cbo.inval x30
diff --git a/gas/testsuite/gas/riscv/zicboz.d b/gas/testsuite/gas/riscv/zicboz.d
new file mode 100644
index 00000000000..7686edbe677
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicboz.d
@@ -0,0 +1,11 @@
+#as: -march=rv64g_zicboz
+#source: zicboz.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0040a00f[ ]+cbo\.zero[ ]+ra
+[ ]+[0-9a-f]+:[ ]+004f200f[ ]+cbo\.zero[ ]+t5
diff --git a/gas/testsuite/gas/riscv/zicboz.s b/gas/testsuite/gas/riscv/zicboz.s
new file mode 100644
index 00000000000..ba75b787b00
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicboz.s
@@ -0,0 +1,3 @@
+target:
+ cbo.zero x1
+ cbo.zero x30
--
2.32.0
next prev parent reply other threads:[~2021-12-16 11:07 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-16 11:04 [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions Tsukasa OI
2021-12-16 11:04 ` [PATCH 1/5] RISC-V: Add mininal support for Zicbo[mpz] Tsukasa OI
2021-12-16 11:04 ` [PATCH 2/5] RISC-V: Cache management instructions Tsukasa OI
2022-01-04 8:01 ` Jan Beulich
2022-01-04 22:15 ` Andrew Waterman
2022-01-05 3:17 ` Tsukasa OI
2021-12-16 11:04 ` Tsukasa OI [this message]
2021-12-16 11:04 ` [PATCH 4/5] RISC-V: Prefetch hint instructions and operand set Tsukasa OI
2021-12-17 15:15 ` Nelson Chu
2021-12-16 11:04 ` [PATCH 5/5] RISC-V: Prefetch hint instruction testcases Tsukasa OI
2021-12-17 15:23 ` [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions Nelson Chu
2021-12-17 17:24 ` Tsukasa OI
2021-12-17 17:39 ` Nelson Chu
2022-02-09 2:29 [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions (with paren) Tsukasa OI
2022-02-09 2:29 ` [PATCH 3/5] RISC-V: Cache management instruction testcases Tsukasa OI
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