Re: [PATCH 2/5] RISC-V: Cache management instructions

[Tsukasa OI <research_trasio@irq.a4lg.com>]

Jan,

On 2022/01/04 17:01, Jan Beulich wrote:
> On 16.12.2021 12:04, Tsukasa OI via Binutils wrote:
>> --- a/opcodes/riscv-opc.c
>> +++ b/opcodes/riscv-opc.c
>> @@ -849,6 +849,12 @@ const struct riscv_opcode riscv_opcodes[] =
>>  {"sfence.vma", 0, INSN_CLASS_I,    "s,t",      MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
>>  {"wfi",        0, INSN_CLASS_I,    "",         MATCH_WFI, MASK_WFI, match_opcode, 0 },
>>  
>> +/* Zicbom and Zicboz instructions.  */
>> +{"cbo.clean",  0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_CLEAN, MASK_CBO_CLEAN, match_opcode, 0 },
>> +{"cbo.flush",  0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_FLUSH, MASK_CBO_FLUSH, match_opcode, 0 },
>> +{"cbo.inval",  0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
>> +{"cbo.zero",   0, INSN_CLASS_ZICBOZ, "s", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },
> 
> Perhaps more a spec question / remark than one on the implementation:
> Wouldn't it be more natural for CBO.* to have memory-like operands,
> e.g. "cbo.zero (x1)" instead of "cbo.zero x1"?

I would have been agreed unless mnemonic is specified on the spec.
Actually, I used "0(s)" instead of "s" for Zicbom/z instructions until
my re-review of the specification (before submission of PATCH v1).

note: "0(s)" allows "cbo.zero (x1)", "cbo.zero 0(x1)" and its equivalents.

https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0-rc2.pdf

[5.1 - cbo.clean]
Mnemonic:
	cbo.clean base

[5.5 - prefetch.i]
Mnemonic:
	prefetch.i offset(base)

If we really want to change that, we need to talk some RISC-V guys to
change the specification.

Thanks,
Tsukasa

> 
> Jan
>