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From: Jan Beulich <jbeulich@suse.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: binutils@sourceware.org
Subject: Re: [PATCH 2/5] RISC-V: Cache management instructions
Date: Tue, 4 Jan 2022 09:01:47 +0100	[thread overview]
Message-ID: <dc08970d-3cb2-3c70-4130-ae3b091bb04f@suse.com> (raw)
In-Reply-To: <a8d7e5bf6f21f2ca84fdff42237629b085d21929.1639652695.git.research_trasio@irq.a4lg.com>

On 16.12.2021 12:04, Tsukasa OI via Binutils wrote:
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -849,6 +849,12 @@ const struct riscv_opcode riscv_opcodes[] =
>  {"sfence.vma", 0, INSN_CLASS_I,    "s,t",      MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
>  {"wfi",        0, INSN_CLASS_I,    "",         MATCH_WFI, MASK_WFI, match_opcode, 0 },
>  
> +/* Zicbom and Zicboz instructions.  */
> +{"cbo.clean",  0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_CLEAN, MASK_CBO_CLEAN, match_opcode, 0 },
> +{"cbo.flush",  0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_FLUSH, MASK_CBO_FLUSH, match_opcode, 0 },
> +{"cbo.inval",  0, INSN_CLASS_ZICBOM, "s", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
> +{"cbo.zero",   0, INSN_CLASS_ZICBOZ, "s", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },

Perhaps more a spec question / remark than one on the implementation:
Wouldn't it be more natural for CBO.* to have memory-like operands,
e.g. "cbo.zero (x1)" instead of "cbo.zero x1"?

Jan


  reply	other threads:[~2022-01-04  8:01 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-16 11:04 [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions Tsukasa OI
2021-12-16 11:04 ` [PATCH 1/5] RISC-V: Add mininal support for Zicbo[mpz] Tsukasa OI
2021-12-16 11:04 ` [PATCH 2/5] RISC-V: Cache management instructions Tsukasa OI
2022-01-04  8:01   ` Jan Beulich [this message]
2022-01-04 22:15     ` Andrew Waterman
2022-01-05  3:17     ` Tsukasa OI
2021-12-16 11:04 ` [PATCH 3/5] RISC-V: Cache management instruction testcases Tsukasa OI
2021-12-16 11:04 ` [PATCH 4/5] RISC-V: Prefetch hint instructions and operand set Tsukasa OI
2021-12-17 15:15   ` Nelson Chu
2021-12-16 11:04 ` [PATCH 5/5] RISC-V: Prefetch hint instruction testcases Tsukasa OI
2021-12-17 15:23 ` [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions Nelson Chu
2021-12-17 17:24   ` Tsukasa OI
2021-12-17 17:39     ` Nelson Chu
2022-02-09  2:29 [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions (with paren) Tsukasa OI
2022-02-09  2:29 ` [PATCH 2/5] RISC-V: Cache management instructions Tsukasa OI

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