From: Jan Beulich <jbeulich@suse.com>
To: Binutils <binutils@sourceware.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Andrew Waterman <andrew@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Nelson Chu <nelson@rivosinc.com>
Subject: Re: [PATCH 2/3] RISC-V: move OR and XOR aliases down
Date: Tue, 14 Feb 2023 08:26:31 +0100 [thread overview]
Message-ID: <66ca084b-8e9e-ebd9-866c-58b9a1dc5724@suse.com> (raw)
In-Reply-To: <63fa0796-59e6-6429-6c86-b8707cc9f8d9@suse.com>
On 13.01.2023 11:19, Jan Beulich via Binutils wrote:
> While benign right now, everywhere else register forms come ahead of
> immediate (alias) ones. That way both also end up next to their non-
> alias (i-suffixed) forms, making it easier to see that the pairs are
> identical (except for INSN_ALIAS of course).
With the equate considerations in [1] it may actually be the case that
the adjustments want to be the other way around, for all immediate
operand aliases to come ahead of their otherwise similar register-only
forms. Yet as said there - first of all it needs to be established
what the intended (and then consistent) behavior is to be.
Jan
[1] https://sourceware.org/pipermail/binutils/2023-February/125993.html
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -438,10 +438,10 @@ const struct riscv_opcode riscv_opcodes[
> {"lw", 0, INSN_CLASS_I, "d,o(s)", MATCH_LW, MASK_LW, match_opcode, INSN_DREF|INSN_4_BYTE },
> {"lw", 0, INSN_CLASS_I, "d,A", 0, (int) M_LW, match_never, INSN_MACRO },
> {"not", 0, INSN_CLASS_I, "d,s", MATCH_XORI|MASK_IMM, MASK_XORI|MASK_IMM, match_opcode, INSN_ALIAS },
> -{"or", 0, INSN_CLASS_I, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, INSN_ALIAS },
> {"or", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
> {"or", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
> {"or", 0, INSN_CLASS_I, "d,s,t", MATCH_OR, MASK_OR, match_opcode, 0 },
> +{"or", 0, INSN_CLASS_I, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, INSN_ALIAS },
> {"ori", 0, INSN_CLASS_I, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, 0 },
> {"auipc", 0, INSN_CLASS_I, "d,u", MATCH_AUIPC, MASK_AUIPC, match_opcode, 0 },
> {"seqz", 0, INSN_CLASS_I, "d,s", MATCH_SLTIU|ENCODE_ITYPE_IMM (1), MASK_SLTIU | MASK_IMM, match_opcode, INSN_ALIAS },
> @@ -476,10 +476,10 @@ const struct riscv_opcode riscv_opcodes[
> {"rdtimeh", 32, INSN_CLASS_I, "d", MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode, INSN_ALIAS },
> {"ecall", 0, INSN_CLASS_I, "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 },
> {"scall", 0, INSN_CLASS_I, "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 },
> -{"xor", 0, INSN_CLASS_I, "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, INSN_ALIAS },
> {"xor", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS },
> {"xor", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS },
> {"xor", 0, INSN_CLASS_I, "d,s,t", MATCH_XOR, MASK_XOR, match_opcode, 0 },
> +{"xor", 0, INSN_CLASS_I, "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, INSN_ALIAS },
> {"xori", 0, INSN_CLASS_I, "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, 0 },
> {"lwu", 64, INSN_CLASS_I, "d,o(s)", MATCH_LWU, MASK_LWU, match_opcode, INSN_DREF|INSN_4_BYTE },
> {"lwu", 64, INSN_CLASS_I, "d,A", 0, (int) M_LWU, match_never, INSN_MACRO },
>
next prev parent reply other threads:[~2023-02-14 7:26 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-13 10:18 [PATCH 0/3] RISC-V: further alias insn handling adjustments Jan Beulich
2023-01-13 10:19 ` [PATCH 1/3] RISC-V: prefer SLT{,U} aliases for SLTI{,U} Jan Beulich
2023-01-15 4:35 ` Maciej W. Rozycki
2023-01-16 7:46 ` Jan Beulich
2023-01-25 0:42 ` Maciej W. Rozycki
2023-01-25 15:02 ` Jan Beulich
2023-01-25 15:22 ` Maciej W. Rozycki
2023-01-26 1:29 ` Andrew Waterman
2023-01-26 9:35 ` Jan Beulich
2023-01-26 22:20 ` Andrew Waterman
2023-01-26 9:41 ` Jan Beulich
2023-01-26 23:27 ` Maciej W. Rozycki
2023-01-13 10:19 ` [PATCH 2/3] RISC-V: move OR and XOR aliases down Jan Beulich
2023-01-20 9:23 ` Ping: " Jan Beulich
2023-02-14 7:26 ` Jan Beulich [this message]
2023-01-13 10:20 ` [PATCH 3/3] RISC-V: prefer FSRM/FSFLAGS aliases for FSRMI/FSFLAGSI Jan Beulich
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