RE: [PATCH 2/2] Support Intel AVX-NE-CONVERT

["Jiang, Haochen" <haochen.jiang@intel.com>]

> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Monday, October 31, 2022 5:15 PM
> To: Jiang, Haochen <haochen.jiang@intel.com>
> Cc: hjl.tools@gmail.com; Kong, Lingling <lingling.kong@intel.com>;
> binutils@sourceware.org
> Subject: Re: [PATCH 2/2] Support Intel AVX-NE-CONVERT
> 
> On 31.10.2022 07:06, Haochen Jiang wrote:
> > @@ -7786,6 +7819,14 @@ static const struct dis386 vex_w_table[][2] = {
> >      /* VEX_W_0F3879 */
> >      { "%XEvpbroadcastw",	{ XM, EXw }, PREFIX_DATA },
> >    },
> > +  {
> > +    /* VEX_W_0F38B0_M_1 */
> > +    { PREFIX_TABLE (PREFIX_VEX_0F38B0_M_1_W_0) },  },  {
> > +    /* VEX_W_0F38B1_M_1 */
> > +    { PREFIX_TABLE (PREFIX_VEX_0F38B1_M_1_W_0) },  },
> >    {
> >      /* VEX_W_0F38B4 */
> >      { Bad_Opcode },
> > @@ -8611,6 +8652,14 @@ static const struct dis386 mod_table[][2] = {
> >      /* MOD_VEX_0F388E */
> >      { "vpmaskmov%DQ",	{ Mx, Vex, XM }, PREFIX_DATA },
> >    },
> > +  {
> > +    /* MOD_VEX_0F38B0 */
> > +    { VEX_W_TABLE (VEX_W_0F38B0_M_1) },  },  {
> > +    /* MOD_VEX_0F38B1 */
> > +    { VEX_W_TABLE (VEX_W_0F38B1_M_1) },  },
> 
> Why ..._M_1 when these are used in slot 0 of the array?

We will change that. It should be zero.

> 
> > --- a/opcodes/i386-opc.tbl
> > +++ b/opcodes/i386-opc.tbl
> > @@ -3056,6 +3056,18 @@ vdpbf16ps, 0xf352, None, CpuAVX512_BF16,
> > Modrm|Space0F38|VexVVVV|Masking=3|VexW0
> >
> >  // AVX512_BF16 instructions end.
> >
> > +// AVX-NE-CONVERT instructions.
> > +
> > +vbcstnebf162ps, 0xf3b1, None, CpuAVX_NE_CONVERT,
> >
> +Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
> o_qSuf|No_
> > +ldSuf, { Word|Unspecified|BaseIndex, RegXMM|RegYMM }
> vbcstnesh2ps,
> > +0x66b1, None, CpuAVX_NE_CONVERT,
> >
> +Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
> o_qSuf|No_
> > +ldSuf, { Word|Unspecified|BaseIndex, RegXMM|RegYMM }
> vcvtneebf162ps,
> > +0xf3b0, None, CpuAVX_NE_CONVERT,
> >
> +Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
> o_qSuf|No_
> > +ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex,
> RegXMM|RegYMM }
> > +vcvtneeph2ps, 0x66b0, None, CpuAVX_NE_CONVERT,
> >
> +Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
> o_qSuf|No_
> > +ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex,
> RegXMM|RegYMM }
> > +vcvtneobf162ps, 0xf2b0, None, CpuAVX_NE_CONVERT,
> >
> +Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
> o_qSuf|No_
> > +ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex,
> RegXMM|RegYMM }
> > +vcvtneoph2ps, 0xb0, None, CpuAVX_NE_CONVERT,
> >
> +Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
> o_qSuf|No_
> > +ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex,
> RegXMM|RegYMM }
> 
> There's still no CheckRegSize for these last four.

Sorry for not mention that. I checked code and I suppose if we are using one
memory operand and one register operand, CheckRegSize seems like doing
nothing since the check function will return 1 for memory operand.

Correct me if I am wrong.

Haochen 

> 
> Jan