From: Jan Beulich <jbeulich@suse.com>
To: "Jiang, Haochen" <haochen.jiang@intel.com>
Cc: "hjl.tools@gmail.com" <hjl.tools@gmail.com>,
"Kong, Lingling" <lingling.kong@intel.com>,
"binutils@sourceware.org" <binutils@sourceware.org>
Subject: Re: [PATCH 2/2] Support Intel AVX-NE-CONVERT
Date: Tue, 1 Nov 2022 07:50:33 +0100 [thread overview]
Message-ID: <086f787f-e886-ab4b-d8ed-4100f5bd3f8e@suse.com> (raw)
In-Reply-To: <SA1PR11MB59462642931A2653A373CF28EC369@SA1PR11MB5946.namprd11.prod.outlook.com>
On 01.11.2022 02:24, Jiang, Haochen wrote:
>> -----Original Message-----
>> From: Jan Beulich <jbeulich@suse.com>
>> Sent: Monday, October 31, 2022 5:15 PM
>>
>> On 31.10.2022 07:06, Haochen Jiang wrote:
>>> --- a/opcodes/i386-opc.tbl
>>> +++ b/opcodes/i386-opc.tbl
>>> @@ -3056,6 +3056,18 @@ vdpbf16ps, 0xf352, None, CpuAVX512_BF16,
>>> Modrm|Space0F38|VexVVVV|Masking=3|VexW0
>>>
>>> // AVX512_BF16 instructions end.
>>>
>>> +// AVX-NE-CONVERT instructions.
>>> +
>>> +vbcstnebf162ps, 0xf3b1, None, CpuAVX_NE_CONVERT,
>>>
>> +Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
>> o_qSuf|No_
>>> +ldSuf, { Word|Unspecified|BaseIndex, RegXMM|RegYMM }
>> vbcstnesh2ps,
>>> +0x66b1, None, CpuAVX_NE_CONVERT,
>>>
>> +Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
>> o_qSuf|No_
>>> +ldSuf, { Word|Unspecified|BaseIndex, RegXMM|RegYMM }
>> vcvtneebf162ps,
>>> +0xf3b0, None, CpuAVX_NE_CONVERT,
>>>
>> +Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
>> o_qSuf|No_
>>> +ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex,
>> RegXMM|RegYMM }
>>> +vcvtneeph2ps, 0x66b0, None, CpuAVX_NE_CONVERT,
>>>
>> +Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
>> o_qSuf|No_
>>> +ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex,
>> RegXMM|RegYMM }
>>> +vcvtneobf162ps, 0xf2b0, None, CpuAVX_NE_CONVERT,
>>>
>> +Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
>> o_qSuf|No_
>>> +ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex,
>> RegXMM|RegYMM }
>>> +vcvtneoph2ps, 0xb0, None, CpuAVX_NE_CONVERT,
>>>
>> +Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
>> o_qSuf|No_
>>> +ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex,
>> RegXMM|RegYMM }
>>
>> There's still no CheckRegSize for these last four.
>
> Sorry for not mention that. I checked code and I suppose if we are using one
> memory operand and one register operand, CheckRegSize seems like doing
> nothing since the check function will return 1 for memory operand.
A comment ahead of the function specifically says "Some Intel syntax memory
operand size checking also happens here." And as I've said earlier on - if
that for some reason doesn't work here, it needs fixing. The only criteria
that's relevant here is whether mismatched operands like in
vcvtneoph2ps xmm, ymmword ptr [rax]
vcvtneoph2ps ymm, xmmword ptr [rax]
are properly rejected.
Jan
next prev parent reply other threads:[~2022-11-01 6:50 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-31 6:05 [PATCH v4 0/2] " Haochen Jiang
2022-10-31 6:06 ` [PATCH 1/2] i386: Add <Vxy> and <Exy> Haochen Jiang
2022-10-31 9:04 ` Jan Beulich
2022-10-31 16:30 ` H.J. Lu
2022-11-01 8:50 ` Kong, Lingling
2022-11-01 14:42 ` H.J. Lu
2022-10-31 6:06 ` [PATCH 2/2] Support Intel AVX-NE-CONVERT Haochen Jiang
2022-10-31 9:14 ` Jan Beulich
2022-11-01 1:24 ` Jiang, Haochen
2022-11-01 6:50 ` Jan Beulich [this message]
2022-11-01 8:08 ` Kong, Lingling
2022-11-01 9:04 ` Kong, Lingling
2022-11-02 7:47 ` Jan Beulich
2022-11-02 8:50 ` Kong, Lingling
2022-11-02 9:53 ` Jan Beulich
2022-11-03 2:44 ` H.J. Lu
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