From: Jan Beulich <jbeulich@suse.com>
To: Haochen Jiang <haochen.jiang@intel.com>
Cc: hjl.tools@gmail.com, konglin1 <lingling.kong@intel.com>,
binutils@sourceware.org
Subject: Re: [PATCH 2/2] Support Intel AVX-NE-CONVERT
Date: Mon, 31 Oct 2022 10:14:32 +0100 [thread overview]
Message-ID: <ac86975b-be13-236d-ba08-1e4477ecb2d3@suse.com> (raw)
In-Reply-To: <20221031060601.38460-3-haochen.jiang@intel.com>
On 31.10.2022 07:06, Haochen Jiang wrote:
> @@ -7786,6 +7819,14 @@ static const struct dis386 vex_w_table[][2] = {
> /* VEX_W_0F3879 */
> { "%XEvpbroadcastw", { XM, EXw }, PREFIX_DATA },
> },
> + {
> + /* VEX_W_0F38B0_M_1 */
> + { PREFIX_TABLE (PREFIX_VEX_0F38B0_M_1_W_0) },
> + },
> + {
> + /* VEX_W_0F38B1_M_1 */
> + { PREFIX_TABLE (PREFIX_VEX_0F38B1_M_1_W_0) },
> + },
> {
> /* VEX_W_0F38B4 */
> { Bad_Opcode },
> @@ -8611,6 +8652,14 @@ static const struct dis386 mod_table[][2] = {
> /* MOD_VEX_0F388E */
> { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
> },
> + {
> + /* MOD_VEX_0F38B0 */
> + { VEX_W_TABLE (VEX_W_0F38B0_M_1) },
> + },
> + {
> + /* MOD_VEX_0F38B1 */
> + { VEX_W_TABLE (VEX_W_0F38B1_M_1) },
> + },
Why ..._M_1 when these are used in slot 0 of the array?
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -3056,6 +3056,18 @@ vdpbf16ps, 0xf352, None, CpuAVX512_BF16, Modrm|Space0F38|VexVVVV|Masking=3|VexW0
>
> // AVX512_BF16 instructions end.
>
> +// AVX-NE-CONVERT instructions.
> +
> +vbcstnebf162ps, 0xf3b1, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex, RegXMM|RegYMM }
> +vbcstnesh2ps, 0x66b1, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex, RegXMM|RegYMM }
> +vcvtneebf162ps, 0xf3b0, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM }
> +vcvtneeph2ps, 0x66b0, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM }
> +vcvtneobf162ps, 0xf2b0, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM }
> +vcvtneoph2ps, 0xb0, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM }
There's still no CheckRegSize for these last four.
Jan
next prev parent reply other threads:[~2022-10-31 9:14 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-31 6:05 [PATCH v4 0/2] " Haochen Jiang
2022-10-31 6:06 ` [PATCH 1/2] i386: Add <Vxy> and <Exy> Haochen Jiang
2022-10-31 9:04 ` Jan Beulich
2022-10-31 16:30 ` H.J. Lu
2022-11-01 8:50 ` Kong, Lingling
2022-11-01 14:42 ` H.J. Lu
2022-10-31 6:06 ` [PATCH 2/2] Support Intel AVX-NE-CONVERT Haochen Jiang
2022-10-31 9:14 ` Jan Beulich [this message]
2022-11-01 1:24 ` Jiang, Haochen
2022-11-01 6:50 ` Jan Beulich
2022-11-01 8:08 ` Kong, Lingling
2022-11-01 9:04 ` Kong, Lingling
2022-11-02 7:47 ` Jan Beulich
2022-11-02 8:50 ` Kong, Lingling
2022-11-02 9:53 ` Jan Beulich
2022-11-03 2:44 ` H.J. Lu
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