From: "H.J. Lu" <hjl.tools@gmail.com>
To: "Cui, Lili" <lili.cui@intel.com>
Cc: "Beulich, Jan" <JBeulich@suse.com>,
"binutils@sourceware.org" <binutils@sourceware.org>,
"Jiang, Haochen" <haochen.jiang@intel.com>
Subject: Re: [PATCH 10/10] Support Intel PREFETCHI
Date: Fri, 28 Oct 2022 08:54:07 -0700 [thread overview]
Message-ID: <CAMe9rOqa+JhN3qi_dtOiTAFEAjfKLmq8KrKYM2rZa3WkD+3keQ@mail.gmail.com> (raw)
In-Reply-To: <SJ0PR11MB5600F50EBB6B19B87B0631519E339@SJ0PR11MB5600.namprd11.prod.outlook.com>
On Thu, Oct 27, 2022 at 12:01 AM Cui, Lili <lili.cui@intel.com> wrote:
>
> > > - /* Update operand types and check extended states. */
> > > + /* 1. Update operand types and check extended states.
> > > + 2. Check IP-relative addressing for prefetchi. */
> > > for (j = 0; j < i.operands; j++)
> > > {
> > > + /* Check if IP-relative addressing requirements can be satisfied. */
> > > + if (i.tm.cpu_flags.bitfield.cpuprefetchi
> > > + && !(i.base_reg && i.base_reg->reg_num == RegIP))
> > > + as_warn (_("only support RIP-relative address"));
> >
> > One final suggestion:
> >
> > as_warn (_("`%s' only supports RIP-relative address"), i.tm.name);
> >
> Done.
>
> > And maybe also keep code and comment in sync as to the sequence of
> > things done.
> >
> Changed, thanks Jan.
>
> > Jan
>
>
> gas/ChangeLog:
>
> * NEWS: Add support for Intel PREFETCHI instruction.
> * config/tc-i386.c (load_insn_p): Use prefetch* to fold all prefetches.
> (md_assemble): Add warning for illegal input of PREFETCHI.
> * doc/c-i386.texi: Document .prefetchi.
> * testsuite/gas/i386/i386.exp: Run PREFETCHI tests.
> * testsuite/gas/i386/x86-64-lfence-load.d: Add PREFETCHI.
> * testsuite/gas/i386/x86-64-lfence-load.s: Likewise.
> * testsuite/gas/i386/x86-64-prefetch.d: New test.
> * testsuite/gas/i386/x86-64-prefetchi-intel.d: Likewise.
> * testsuite/gas/i386/x86-64-prefetchi-inval-register.d: Likewise..
> * testsuite/gas/i386/x86-64-prefetchi-inval-register.s: Likewise.
> * testsuite/gas/i386/x86-64-prefetchi-warn.l: Likewise.
> * testsuite/gas/i386/x86-64-prefetchi-warn.s: Likewise.
> * testsuite/gas/i386/x86-64-prefetchi.d: Likewise.
> * testsuite/gas/i386/x86-64-prefetchi.s: Likewise.
>
> opcodes/ChangeLog:
>
> * i386-dis.c (reg_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7
> (x86_64_table): Add X86_64_0F18_REG_6_MOD_0 and X86_64_0F18_REG_7_MOD_0.
> (mod_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7.
> (prefix_table): Add PREFIX_0F18_REG_6_MOD_0_X86_64 and
> PREFIX_0F18_REG_7_MOD_0_X86_64.
> (PREFETCHI_Fixup): New.
> * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHI_FLAGS.
> (cpu_flags): Add CpuPREFETCHI.
> * i386-opc.h (CpuPREFETCHI): New.
> (i386_cpu_flags): Add cpuprefetchi.
> * i386-opc.tbl: Add Intel PREFETCHI instructions.
> * i386-init.h: Regenerated.
> * i386-tbl.h: Likewise.
> ---
> gas/NEWS | 2 +
> gas/config/tc-i386.c | 14 +++-
> gas/doc/c-i386.texi | 3 +-
> gas/testsuite/gas/i386/i386.exp | 4 +
> gas/testsuite/gas/i386/x86-64-lfence-load.d | 2 +
> gas/testsuite/gas/i386/x86-64-lfence-load.s | 2 +
> .../gas/i386/x86-64-prefetchi-intel.d | 16 ++++
> .../i386/x86-64-prefetchi-inval-register.d | 13 ++++
> .../i386/x86-64-prefetchi-inval-register.s | 9 +++
> .../gas/i386/x86-64-prefetchi-warn.l | 5 ++
> .../gas/i386/x86-64-prefetchi-warn.s | 11 +++
> gas/testsuite/gas/i386/x86-64-prefetchi.d | 15 ++++
> gas/testsuite/gas/i386/x86-64-prefetchi.s | 14 ++++
> opcodes/i386-dis.c | 78 ++++++++++++++++++-
> opcodes/i386-gen.c | 3 +
> opcodes/i386-opc.h | 3 +
> opcodes/i386-opc.tbl | 7 ++
> 17 files changed, 194 insertions(+), 7 deletions(-)
> create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi-intel.d
> create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d
> create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s
> create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi-warn.l
> create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi-warn.s
> create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi.d
> create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi.s
>
> diff --git a/gas/NEWS b/gas/NEWS
> index 961449545d..5eb479f5a1 100644
> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -1,5 +1,7 @@
> -*- text -*-
>
> +* Add support for Intel PREFETCHI instructions.
> +
> * Add support for Intel AMX-FP16 instructions.
>
> * Add support for Intel MSRLIST instructions.
> diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
> index c1623f216e..52993dfbd9 100644
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -1102,6 +1102,7 @@ static const arch_entry cpu_arch[] =
> SUBARCH (rao_int, RAO_INT, RAO_INT, false),
> SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false),
> SUBARCH (msrlist, MSRLIST, MSRLIST, false),
> + SUBARCH (prefetchi, PREFETCHI, PREFETCHI, false),
> };
>
> #undef SUBARCH
> @@ -4520,9 +4521,8 @@ load_insn_p (void)
>
> if (!any_vex_p)
> {
> - /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
> - prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
> - bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
> + /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
> + bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */
> if (i.tm.opcode_modifier.anysize)
> return 0;
>
> @@ -5057,9 +5057,15 @@ md_assemble (char *line)
> if (!process_suffix ())
> return;
>
> - /* Update operand types and check extended states. */
> + /* 1. Check IP-relative addressing for prefetchi.
> + 2. Update operand types and check extended states. */
> for (j = 0; j < i.operands; j++)
> {
> + /* Check if IP-relative addressing requirements can be satisfied. */
> + if (i.tm.cpu_flags.bitfield.cpuprefetchi
> + && !(i.base_reg && i.base_reg->reg_num == RegIP))
> + as_warn (_("only support RIP-relative address"), i.tm.name);
Please move this check before the loop. OK with this change.
> i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
> switch (i.tm.operand_types[j].bitfield.class)
> {
> diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
> index b33f17c698..fae902c034 100644
> --- a/gas/doc/c-i386.texi
> +++ b/gas/doc/c-i386.texi
> @@ -201,6 +201,7 @@ accept various extension mnemonics. For example,
> @code{rao_int},
> @code{wrmsrns},
> @code{msrlist},
> +@code{prefetchi},
> @code{amx_int8},
> @code{amx_bf16},
> @code{amx_fp16},
> @@ -1496,7 +1497,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
> @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
> @item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert}
> @item @samp{.cmpccxadd} @tab @samp{.rao_int} @tab @samp{.wrmsrns}
> -@item @samp{.msrlist}
> +@item @samp{.msrlist} @tab @samp{.prefetchi}
> @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
> @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
> @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
> diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
> index 9f5fa7f612..2081339dc9 100644
> --- a/gas/testsuite/gas/i386/i386.exp
> +++ b/gas/testsuite/gas/i386/i386.exp
> @@ -1209,6 +1209,10 @@ if [gas_64_check] then {
> run_dump_test "x86-64-tdx"
> run_dump_test "x86-64-tsxldtrk"
> run_dump_test "x86-64-hreset"
> + run_dump_test "x86-64-prefetchi"
> + run_dump_test "x86-64-prefetchi-intel"
> + run_dump_test "x86-64-prefetchi-inval-register"
> + run_list_test "x86-64-prefetchi-warn"
> run_dump_test "x86-64-vp2intersect"
> run_dump_test "x86-64-vp2intersect-intel"
> run_list_test "x86-64-vp2intersect-inval-bcast"
> diff --git a/gas/testsuite/gas/i386/x86-64-lfence-load.d b/gas/testsuite/gas/i386/x86-64-lfence-load.d
> index 2af86fc93f..17c3b9f286 100644
> --- a/gas/testsuite/gas/i386/x86-64-lfence-load.d
> +++ b/gas/testsuite/gas/i386/x86-64-lfence-load.d
> @@ -33,6 +33,8 @@ Disassembly of section .text:
> +[a-f0-9]+: 0f 18 55 00 prefetcht1 0x0\(%rbp\)
> +[a-f0-9]+: 0f 18 5d 00 prefetcht2 0x0\(%rbp\)
> +[a-f0-9]+: 0f 0d 4d 00 prefetchw 0x0\(%rbp\)
> + +[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
> + +[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
> +[a-f0-9]+: 0f a1 pop %fs
> +[a-f0-9]+: 0f ae e8 lfence
> +[a-f0-9]+: 9d popf
> diff --git a/gas/testsuite/gas/i386/x86-64-lfence-load.s b/gas/testsuite/gas/i386/x86-64-lfence-load.s
> index 2a3ac6b7d2..c478082416 100644
> --- a/gas/testsuite/gas/i386/x86-64-lfence-load.s
> +++ b/gas/testsuite/gas/i386/x86-64-lfence-load.s
> @@ -20,6 +20,8 @@ _start:
> prefetcht1 (%rbp)
> prefetcht2 (%rbp)
> prefetchw (%rbp)
> + prefetchit0 0x12345678(%rip)
> + prefetchit1 0x12345678(%rip)
> pop %fs
> popf
> xlatb (%rbx)
> diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-intel.d b/gas/testsuite/gas/i386/x86-64-prefetchi-intel.d
> new file mode 100644
> index 0000000000..7f72f0a1eb
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-prefetchi-intel.d
> @@ -0,0 +1,16 @@
> +#as:
> +#objdump: -dwMintel
> +#name: x86-64 PREFETCHI insns (Intel disassembly)
> +#source: x86-64-prefetchi.s
> +
> +.*: +file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+ <_start>:
> +[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+>
> +[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+>
> +[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+>
> +[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+>
> +#pass
> diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d
> new file mode 100644
> index 0000000000..b29b1ae237
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d
> @@ -0,0 +1,13 @@
> +#as:
> +#objdump: -dw
> +#name: x86-64 PREFETCHI INVAL REGISTER insns
> +
> +.*: +file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+ <\.text>:
> +[ ]*[a-f0-9]+:[ ]0f 18 39[ ]*nopl \(%rcx\)
> +[ ]*[a-f0-9]+:[ ]0f 18 31[ ]*nopl \(%rcx\)
> +#pass
> diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s
> new file mode 100644
> index 0000000000..550449a0c9
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s
> @@ -0,0 +1,9 @@
> +.text
> + #prefetchit0 (%rcx) PREFETCHIT0/1 apply without RIP-relative addressing, should stay NOPs.
> + .byte 0x0f
> + .byte 0x18
> + .byte 0x39
> + #prefetchit1 (%rcx) PREFETCHIT1/1 apply without RIP-relative addressing, should stay NOPs.
> + .byte 0x0f
> + .byte 0x18
> + .byte 0x31
> diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-warn.l b/gas/testsuite/gas/i386/x86-64-prefetchi-warn.l
> new file mode 100644
> index 0000000000..4e15389463
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-prefetchi-warn.l
> @@ -0,0 +1,5 @@
> +.*: Assembler messages:
> +.*:[0-9]*: Warning: only support RIP-relative address
> +.*:[0-9]*: Warning: only support RIP-relative address
> +.*:[0-9]*: Warning: only support RIP-relative address
> +.*:[0-9]*: Warning: only support RIP-relative address
> diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-warn.s b/gas/testsuite/gas/i386/x86-64-prefetchi-warn.s
> new file mode 100644
> index 0000000000..330ff31c75
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-prefetchi-warn.s
> @@ -0,0 +1,11 @@
> +# Check error for ICACHE-PREFETCH 64-bit instruction
> +
> + .allow_index_reg
> + .text
> +_start:
> + prefetchit0 0x12345678(%rax)
> + prefetchit1 0x12345678(%rax)
> +
> + .intel_syntax noprefix
> + prefetchit0 BYTE PTR [rax+0x12345678]
> + prefetchit1 BYTE PTR [rax+0x12345678]
> diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi.d b/gas/testsuite/gas/i386/x86-64-prefetchi.d
> new file mode 100644
> index 0000000000..c8ab92d147
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-prefetchi.d
> @@ -0,0 +1,15 @@
> +#as:
> +#objdump: -dw
> +#name: x86-64 PREFETCHI insns
> +
> +.*: +file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+ <_start>:
> +[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
> +[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
> +[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
> +[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
> +#pass
> diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi.s b/gas/testsuite/gas/i386/x86-64-prefetchi.s
> new file mode 100644
> index 0000000000..cc7c61e9a9
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-prefetchi.s
> @@ -0,0 +1,14 @@
> +# Check 64bit PREFETCHI instructions
> +
> + .allow_index_reg
> + .text
> +_start:
> +
> + prefetchit0 0x12345678(%rip)
> + prefetchit1 0x12345678(%rip)
> +
> + .intel_syntax noprefix
> +
> + prefetchit0 BYTE PTR [rip+0x12345678]
> + prefetchit1 BYTE PTR [rip+0x12345678]
> +
> diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
> index 27ae8eaf46..9ef3d7a6ae 100644
> --- a/opcodes/i386-dis.c
> +++ b/opcodes/i386-dis.c
> @@ -114,6 +114,7 @@ static void FXSAVE_Fixup (instr_info *, int, int);
>
> static void MOVSXD_Fixup (instr_info *, int, int);
> static void DistinctDest_Fixup (instr_info *, int, int);
> +static void PREFETCHI_Fixup (instr_info *, int, int);
>
> /* This character is used to encode style information within the output
> buffers. See oappend_insert_style for more details. */
> @@ -841,6 +842,8 @@ enum
> MOD_0F18_REG_1,
> MOD_0F18_REG_2,
> MOD_0F18_REG_3,
> + MOD_0F18_REG_6,
> + MOD_0F18_REG_7,
> MOD_0F1A_PREFIX_0,
> MOD_0F1B_PREFIX_0,
> MOD_0F1B_PREFIX_1,
> @@ -1006,6 +1009,8 @@ enum
> PREFIX_0F11,
> PREFIX_0F12,
> PREFIX_0F16,
> + PREFIX_0F18_REG_6_MOD_0_X86_64,
> + PREFIX_0F18_REG_7_MOD_0_X86_64,
> PREFIX_0F1A,
> PREFIX_0F1B,
> PREFIX_0F1C,
> @@ -1280,6 +1285,8 @@ enum
> X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
> X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
> X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
> + X86_64_0F18_REG_6_MOD_0,
> + X86_64_0F18_REG_7_MOD_0,
> X86_64_0F24,
> X86_64_0F26,
> X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
> @@ -2751,8 +2758,8 @@ static const struct dis386 reg_table[][8] = {
> { MOD_TABLE (MOD_0F18_REG_3) },
> { "nopQ", { Ev }, 0 },
> { "nopQ", { Ev }, 0 },
> - { "nopQ", { Ev }, 0 },
> - { "nopQ", { Ev }, 0 },
> + { MOD_TABLE (MOD_0F18_REG_6) },
> + { MOD_TABLE (MOD_0F18_REG_7) },
> },
> /* REG_0F1C_P_0_MOD_0 */
> {
> @@ -3118,6 +3125,22 @@ static const struct dis386 prefix_table[][4] = {
> { MOD_TABLE (MOD_0F16_PREFIX_2) },
> },
>
> + /* PREFIX_0F18_REG_6_MOD_0_X86_64 */
> + {
> + { "prefetchit1", { { PREFETCHI_Fixup, b_mode } }, 0 },
> + { "nopQ", { Ev }, 0 },
> + { "nopQ", { Ev }, 0 },
> + { "nopQ", { Ev }, 0 },
> + },
> +
> + /* PREFIX_0F18_REG_7_MOD_0_X86_64 */
> + {
> + { "prefetchit0", { { PREFETCHI_Fixup, b_mode } }, 0 },
> + { "nopQ", { Ev }, 0 },
> + { "nopQ", { Ev }, 0 },
> + { "nopQ", { Ev }, 0 },
> + },
> +
> /* PREFIX_0F1A */
> {
> { MOD_TABLE (MOD_0F1A_PREFIX_0) },
> @@ -4394,6 +4417,18 @@ static const struct dis386 x86_64_table[][2] = {
> { "psmash", { Skip_MODRM }, 0 },
> },
>
> + /* X86_64_0F18_REG_6_MOD_0 */
> + {
> + { "nopQ", { Ev }, 0 },
> + { PREFIX_TABLE (PREFIX_0F18_REG_6_MOD_0_X86_64) },
> + },
> +
> + /* X86_64_0F18_REG_7_MOD_0 */
> + {
> + { "nopQ", { Ev }, 0 },
> + { PREFIX_TABLE (PREFIX_0F18_REG_7_MOD_0_X86_64) },
> + },
> +
> {
> /* X86_64_0F24 */
> { "movZ", { Em, Td }, 0 },
> @@ -8193,6 +8228,16 @@ static const struct dis386 mod_table[][2] = {
> { "prefetcht2", { Mb }, 0 },
> { "nopQ", { Ev }, 0 },
> },
> + {
> + /* MOD_0F18_REG_6 */
> + { X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) },
> + { "nopQ", { Ev }, 0 },
> + },
> + {
> + /* MOD_0F18_REG_7 */
> + { X86_64_TABLE (X86_64_0F18_REG_7_MOD_0) },
> + { "nopQ", { Ev }, 0 },
> + },
> {
> /* MOD_0F1A_PREFIX_0 */
> { "bndldx", { Gbnd, Mv_bnd }, 0 },
> @@ -13940,3 +13985,32 @@ OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
> }
> oappend (ins, "sae}");
> }
> +
> +static void
> +PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag)
> +{
> + if (ins->modrm.mod != 0 || ins->modrm.rm != 5)
> + {
> + if (ins->intel_syntax)
> + {
> + ins->mnemonicendp = stpcpy (ins->obuf, "nop ");
> + }
> + else
> + {
> + USED_REX (REX_W);
> + if (ins->rex & REX_W)
> + ins->mnemonicendp = stpcpy (ins->obuf, "nopq ");
> + else
> + {
> + if (sizeflag & DFLAG)
> + ins->mnemonicendp = stpcpy (ins->obuf, "nopl ");
> + else
> + ins->mnemonicendp = stpcpy (ins->obuf, "nopw ");
> + ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
> + }
> + }
> + bytemode = v_mode;
> + }
> +
> + OP_M (ins, bytemode, sizeflag);
> +}
> diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
> index 237f147ad4..33339ba840 100644
> --- a/opcodes/i386-gen.c
> +++ b/opcodes/i386-gen.c
> @@ -259,6 +259,8 @@ static initializer cpu_flag_init[] =
> "CpuWRMSRNS" },
> { "CPU_MSRLIST_FLAGS",
> "CpuMSRLIST" },
> + { "CPU_PREFETCHI_FLAGS",
> + "CpuPREFETCHI"},
> { "CPU_IAMCU_FLAGS",
> "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
> { "CPU_ADX_FLAGS",
> @@ -677,6 +679,7 @@ static bitfield cpu_flags[] =
> BITFIELD (CpuRAO_INT),
> BITFIELD (CpuWRMSRNS),
> BITFIELD (CpuMSRLIST),
> + BITFIELD (CpuPREFETCHI),
> BITFIELD (CpuMWAITX),
> BITFIELD (CpuCLZERO),
> BITFIELD (CpuOSPKE),
> diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
> index 645abe7f34..1ed319c20b 100644
> --- a/opcodes/i386-opc.h
> +++ b/opcodes/i386-opc.h
> @@ -223,6 +223,8 @@ enum
> CpuWRMSRNS,
> /* Intel MSRLIST Instructions support required. */
> CpuMSRLIST,
> + /* PREFETCHI instruction required */
> + CpuPREFETCHI,
> /* mwaitx instruction required */
> CpuMWAITX,
> /* Clzero instruction required */
> @@ -411,6 +413,7 @@ typedef union i386_cpu_flags
> unsigned int cpurao_int:1;
> unsigned int cpuwrmsrns:1;
> unsigned int cpumsrlist:1;
> + unsigned int cpuprefetchi:1;
> unsigned int cpumwaitx:1;
> unsigned int cpuclzero:1;
> unsigned int cpuospke:1;
> diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
> index bb5dc6799d..d63aa1dfb2 100644
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -3323,3 +3323,10 @@ rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
> wrmsrlist, 0xf30f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
>
> // MSRLIST instructions end.
> +
> +// PREFETCHI instructions.
> +
> +prefetchit0, 0xf18, 0x7, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
> +prefetchit1, 0xf18, 0x6, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
> +
> +// PREFETCHI instructions end.
> --
> 2.17.1
> Thanks,
> Lili.
>
>
Thanks.
--
H.J.
next prev parent reply other threads:[~2022-10-28 15:54 UTC|newest]
Thread overview: 123+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-14 9:12 [PATCH 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions Haochen Jiang
2022-10-14 9:12 ` [PATCH 01/10] Support Intel AVX-IFMA Haochen Jiang
2022-10-14 9:52 ` Jan Beulich
2022-10-14 18:10 ` H.J. Lu
2022-10-16 6:39 ` Jan Beulich
2022-10-17 22:23 ` H.J. Lu
2022-10-18 5:33 ` Jan Beulich
2022-10-18 21:28 ` H.J. Lu
2022-10-19 6:01 ` Jan Beulich
2022-10-19 21:27 ` H.J. Lu
2022-10-20 6:15 ` Jan Beulich
2022-10-24 2:07 ` Jiang, Haochen
2022-10-24 5:53 ` Jiang, Haochen
2022-10-24 19:09 ` H.J. Lu
2022-10-25 6:29 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 02/10] Support Intel AVX-VNNI-INT8 Haochen Jiang
2022-10-14 10:57 ` Jan Beulich
2022-10-21 3:22 ` Jiang, Haochen
2022-10-25 1:52 ` H.J. Lu
2022-10-14 9:12 ` [PATCH 03/10] Support Intel AVX-NE-CONVERT Haochen Jiang
2022-10-14 12:58 ` Jan Beulich
2022-10-24 5:37 ` Kong, Lingling
2022-10-24 5:59 ` Kong, Lingling
2022-10-24 19:25 ` H.J. Lu
2022-10-25 6:44 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 04/10] Support Intel CMPccXADD Haochen Jiang
2022-10-14 13:46 ` Jan Beulich
2022-10-14 18:27 ` H.J. Lu
2022-10-14 21:51 ` H.J. Lu
2022-10-16 6:34 ` Jan Beulich
2022-10-17 23:31 ` H.J. Lu
2022-10-16 6:25 ` Jan Beulich
2022-10-17 23:44 ` H.J. Lu
2022-10-16 6:19 ` Jan Beulich
2022-10-24 2:30 ` Jiang, Haochen
2022-10-24 19:12 ` H.J. Lu
2022-10-24 5:55 ` Jiang, Haochen
2022-10-25 6:53 ` Jan Beulich
2022-10-26 3:03 ` Jiang, Haochen
2022-10-26 8:49 ` Jan Beulich
2022-10-27 3:09 ` Jiang, Haochen
2022-10-27 6:37 ` Jan Beulich
2022-10-28 0:59 ` Jiang, Haochen
2022-10-14 9:12 ` [PATCH 05/10] Add handler for more i386_cpu_flags Haochen Jiang
2022-10-14 13:53 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 06/10] Support Intel RAO-INT Haochen Jiang
2022-10-14 14:38 ` Jan Beulich
2022-10-16 6:15 ` Jan Beulich
2022-10-24 3:12 ` Jiang, Haochen
2022-10-24 19:17 ` H.J. Lu
2022-10-24 5:56 ` Jiang, Haochen
2022-10-25 7:01 ` Jan Beulich
2022-10-26 5:16 ` Jiang, Haochen
2022-10-26 8:56 ` Jan Beulich
2022-10-27 3:50 ` Jiang, Haochen
2022-10-27 6:39 ` Jan Beulich
2022-10-27 18:46 ` H.J. Lu
2022-10-28 6:52 ` Jan Beulich
2022-10-28 8:10 ` Jiang, Haochen
2022-10-28 8:22 ` Jan Beulich
2022-10-28 8:31 ` Jiang, Haochen
2022-10-28 8:40 ` Jan Beulich
2022-10-28 16:08 ` H.J. Lu
2022-10-31 9:41 ` Jan Beulich
2022-10-31 16:49 ` H.J. Lu
2022-11-06 12:50 ` Kong, Lingling
2022-11-07 9:24 ` Jan Beulich
2022-11-07 13:37 ` Kong, Lingling
2022-11-07 20:03 ` H.J. Lu
2022-10-17 23:23 ` H.J. Lu
2022-10-18 5:38 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 07/10] Support Intel WRMSRNS Haochen Jiang
2022-10-17 7:17 ` Jan Beulich
2022-10-24 2:52 ` Jiang, Haochen
2022-10-24 5:56 ` Jiang, Haochen
2022-10-24 19:14 ` H.J. Lu
2022-10-25 7:04 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 08/10] Support Intel MSRLIST Haochen Jiang
2022-10-17 7:20 ` Jan Beulich
2022-10-24 3:03 ` Jiang, Haochen
2022-10-24 5:56 ` Jiang, Haochen
2022-10-24 19:15 ` H.J. Lu
2022-10-25 7:07 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 09/10] Support Intel AMX-FP16 Haochen Jiang
2022-10-17 7:35 ` Jan Beulich
2022-10-18 9:01 ` Cui, Lili
2022-10-18 9:23 ` Jan Beulich
2022-10-18 9:33 ` Jiang, Haochen
2022-10-19 10:33 ` Cui, Lili
2022-10-19 13:35 ` Jan Beulich
2022-10-19 14:05 ` Cui, Lili
2022-10-19 14:09 ` Jan Beulich
2022-10-19 14:41 ` Cui, Lili
2022-10-19 15:04 ` Jan Beulich
2022-10-19 15:21 ` Cui, Lili
2022-10-19 14:01 ` Jiang, Haochen
2022-10-19 14:13 ` Jan Beulich
2022-10-19 14:58 ` Jiang, Haochen
2022-10-25 6:02 ` Jan Beulich
2022-10-25 13:05 ` Cui, Lili
2022-10-14 9:12 ` [PATCH 10/10] Support Intel PREFETCHI Haochen Jiang
2022-10-17 8:15 ` Jan Beulich
2022-10-25 13:03 ` Cui, Lili
2022-10-25 15:41 ` Jan Beulich
2022-10-25 15:52 ` Jan Beulich
2022-10-25 17:01 ` H.J. Lu
2022-10-26 13:42 ` Cui, Lili
2022-10-26 13:53 ` Jan Beulich
2022-10-27 6:04 ` Cui, Lili
2022-10-27 6:45 ` Jan Beulich
2022-10-27 7:01 ` Cui, Lili
2022-10-27 7:15 ` Jan Beulich
2022-10-27 7:43 ` Cui, Lili
2022-10-28 9:03 ` Cui, Lili
2022-10-28 15:54 ` H.J. Lu [this message]
2022-10-31 13:23 ` Cui, Lili
2022-10-31 14:45 ` Mike Frysinger
2022-10-31 16:25 ` H.J. Lu
2022-10-19 14:55 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions Haochen Jiang
2022-10-19 14:56 ` [PATCH 10/10] Support Intel PREFETCHI Haochen Jiang
2022-10-19 15:15 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions (Resend) Haochen Jiang
2022-10-19 15:15 ` [PATCH 10/10] Support Intel PREFETCHI Haochen Jiang
2022-10-25 7:11 ` Jan Beulich
2022-10-25 7:49 ` Cui, Lili
2022-10-25 8:31 ` Jan Beulich
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