From: Haochen Jiang <haochen.jiang@intel.com>
To: binutils@sourceware.org
Cc: jbeulich@suse.com, hjl.tools@gmail.com, "Cui, Lili" <lili.cui@intel.com>
Subject: [PATCH 10/10] Support Intel PREFETCHI
Date: Fri, 14 Oct 2022 17:12:48 +0800 [thread overview]
Message-ID: <20221014091248.4920-11-haochen.jiang@intel.com> (raw)
In-Reply-To: <20221014091248.4920-1-haochen.jiang@intel.com>
From: "Cui, Lili" <lili.cui@intel.com>
gas/
* NEWS: Add support for Intel PREFETCHI instruction.
* config/tc-i386.c: Add prefetchi.
* doc/c-i386.texi: Document .prefetchi, noprefetchi.
* testsuite/gas/i386/i386.exp: Run PREFETCHI tests.
* testsuite/gas/i386/x86-64-prefetchi-intel.d: New test.
* testsuite/gas/i386/x86-64-prefetchi-inval-register.d: Likewise.
* testsuite/gas/i386/x86-64-prefetchi-inval-register.s: Likewise.
* testsuite/gas/i386/x86-64-prefetchi.d: Likewise.
* testsuite/gas/i386/x86-64-prefetchi.s: Likewise.
opcodes/
* i386-dis.c (MOD_0F18_REG_6): New.
(MOD_0F18_REG_7): Ditto.
(X86_64_MOD_0F18_REG_6): Ditto.
(X86_64_MOD_0F18_REG_7): Ditto.
(x86_64_table): Add X86_64_MOD_0F18_REG_6 and X86_64_MOD_0F18_REG_7.
(mod_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7.
(PREFETCHI_Fixup): New.
* i386-gen.c (cpu_flag_init): Add CPU_PREFETCHI_FLAGS and
CPU_ANY_PREFETCHI_FLAGS.
(cpu_flags): Add CpuPREFETCHI.
* i386-opc.h (CpuPREFETCHI): New.
(i386_cpu_flags): Add cpuprefetchi.
* i386-opc.tbl: Add Intel PREFETCHI instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
---
gas/NEWS | 2 +
gas/config/tc-i386.c | 4 +-
gas/doc/c-i386.texi | 4 +-
gas/testsuite/gas/i386/i386.exp | 3 +
gas/testsuite/gas/i386/x86-64-lfence-load.d | 2 +
gas/testsuite/gas/i386/x86-64-lfence-load.s | 2 +
gas/testsuite/gas/i386/x86-64-lockbad-1.l | 104 +-
gas/testsuite/gas/i386/x86-64-lockbad-1.s | 4 +
.../gas/i386/x86-64-prefetchi-intel.d | 16 +
.../i386/x86-64-prefetchi-inval-register.d | 13 +
.../i386/x86-64-prefetchi-inval-register.s | 9 +
gas/testsuite/gas/i386/x86-64-prefetchi.d | 15 +
gas/testsuite/gas/i386/x86-64-prefetchi.s | 14 +
opcodes/i386-dis.c | 46 +-
opcodes/i386-gen.c | 5 +
opcodes/i386-init.h | 522 +-
opcodes/i386-opc.h | 3 +
opcodes/i386-opc.tbl | 7 +
opcodes/i386-tbl.h | 7846 +++++++++--------
19 files changed, 4407 insertions(+), 4214 deletions(-)
create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d
create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s
create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi.d
create mode 100644 gas/testsuite/gas/i386/x86-64-prefetchi.s
diff --git a/gas/NEWS b/gas/NEWS
index 961449545d..5eb479f5a1 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for Intel PREFETCHI instructions.
+
* Add support for Intel AMX-FP16 instructions.
* Add support for Intel MSRLIST instructions.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 73aa2c66aa..65dd5de935 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1102,6 +1102,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (wrmsrns, WRMSRNS, ANY_WRMSRNS, false),
SUBARCH (msrlist, MSRLIST, ANY_MSRLIST, false),
SUBARCH (amx_fp16, AMX_FP16, ANY_AMX_FP16, false),
+ SUBARCH (prefetchi, PREFETCHI, ANY_PREFETCHI, false),
};
#undef SUBARCH
@@ -4522,7 +4523,8 @@ load_insn_p (void)
{
/* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
- bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
+ bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote, prefetchit0
+ prefetchit1. */
if (i.tm.opcode_modifier.anysize)
return 0;
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index dc7e281e6d..1cf4e6b9d8 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -221,6 +221,7 @@ accept various extension mnemonics. For example,
@code{wrmsrns},
@code{msrlist},
@code{amx_fp16},
+@code{prefetchi},
@code{noavx512f},
@code{noavx512cd},
@code{noavx512er},
@@ -249,6 +250,7 @@ accept various extension mnemonics. For example,
@code{nowrmsrns},
@code{nomsrlist},
@code{noamx_fp16},
+@code{noprefetchi},
@code{noenqcmd},
@code{noserialize},
@code{notsxldtrk},
@@ -1551,7 +1553,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
@item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert}
@item @samp{.cmpccxadd} @tab @samp{.raoint} @tab @samp{.wrmsrns}
-@item @samp{.msrlist} @tab @samp{.amx_fp16}
+@item @samp{.msrlist} @tab @samp{.amx_fp16} @tab @samp{.prefetchi}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 9f5fa7f612..80bd2835ca 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -1209,6 +1209,9 @@ if [gas_64_check] then {
run_dump_test "x86-64-tdx"
run_dump_test "x86-64-tsxldtrk"
run_dump_test "x86-64-hreset"
+ run_dump_test "x86-64-prefetchi"
+ run_dump_test "x86-64-prefetchi-intel"
+ run_dump_test "x86-64-prefetchi-inval-register"
run_dump_test "x86-64-vp2intersect"
run_dump_test "x86-64-vp2intersect-intel"
run_list_test "x86-64-vp2intersect-inval-bcast"
diff --git a/gas/testsuite/gas/i386/x86-64-lfence-load.d b/gas/testsuite/gas/i386/x86-64-lfence-load.d
index 2af86fc93f..17c3b9f286 100644
--- a/gas/testsuite/gas/i386/x86-64-lfence-load.d
+++ b/gas/testsuite/gas/i386/x86-64-lfence-load.d
@@ -33,6 +33,8 @@ Disassembly of section .text:
+[a-f0-9]+: 0f 18 55 00 prefetcht1 0x0\(%rbp\)
+[a-f0-9]+: 0f 18 5d 00 prefetcht2 0x0\(%rbp\)
+[a-f0-9]+: 0f 0d 4d 00 prefetchw 0x0\(%rbp\)
+ +[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+ +[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[a-f0-9]+: 0f a1 pop %fs
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 9d popf
diff --git a/gas/testsuite/gas/i386/x86-64-lfence-load.s b/gas/testsuite/gas/i386/x86-64-lfence-load.s
index 2a3ac6b7d2..c478082416 100644
--- a/gas/testsuite/gas/i386/x86-64-lfence-load.s
+++ b/gas/testsuite/gas/i386/x86-64-lfence-load.s
@@ -20,6 +20,8 @@ _start:
prefetcht1 (%rbp)
prefetcht2 (%rbp)
prefetchw (%rbp)
+ prefetchit0 0x12345678(%rip)
+ prefetchit1 0x12345678(%rip)
pop %fs
popf
xlatb (%rbx)
diff --git a/gas/testsuite/gas/i386/x86-64-lockbad-1.l b/gas/testsuite/gas/i386/x86-64-lockbad-1.l
index 6469991605..24b13d9f46 100644
--- a/gas/testsuite/gas/i386/x86-64-lockbad-1.l
+++ b/gas/testsuite/gas/i386/x86-64-lockbad-1.l
@@ -39,10 +39,10 @@
.*:44: Error: .*
.*:45: Error: .*
.*:46: Error: .*
-.*:49: Error: .*
-.*:50: Error: .*
+.*:47: Error: .*
+.*:48: Error: .*
+.*:51: Error: .*
.*:52: Error: .*
-.*:53: Error: .*
.*:54: Error: .*
.*:55: Error: .*
.*:56: Error: .*
@@ -69,8 +69,8 @@
.*:77: Error: .*
.*:78: Error: .*
.*:79: Error: .*
+.*:80: Error: .*
.*:81: Error: .*
-.*:82: Error: .*
.*:83: Error: .*
.*:84: Error: .*
.*:85: Error: .*
@@ -79,6 +79,10 @@
.*:88: Error: .*
.*:89: Error: .*
.*:90: Error: .*
+.*:91: Error: .*
+.*:92: Error: .*
+.*:93: Error: .*
+.*:94: Error: .*
GAS LISTING .*
@@ -128,50 +132,54 @@ GAS LISTING .*
[ ]*44[ ]+lock wrmsrns
[ ]*45[ ]+lock rdmsrlist
[ ]*46[ ]+lock wrmsrlist
-[ ]*47[ ]+
-[ ]*48[ ]+\.intel_syntax noprefix
-[ ]*49[ ]+lock mov eax,ebx
-[ ]*50[ ]+lock mov eax,DWORD PTR \[rbx\]
-[ ]*51[ ]+
-[ ]*52[ ]+lock add eax,ebx
-[ ]*53[ ]+lock add ebx,0x64
-[ ]*54[ ]+lock adc eax,ebx
-[ ]*55[ ]+lock adc ebx,0x64
-[ ]*56[ ]+lock and eax,ebx
-[ ]*57[ ]+lock and ebx,0x64
+[ ]*47[ ]+lock prefetchit0 0x12345678\(%rip\)
+[ ]*48[ ]+lock prefetchit1 0x12345678\(%rip\)
+[ ]*49[ ]+
+[ ]*50[ ]+\.intel_syntax noprefix
+[ ]*51[ ]+lock mov eax,ebx
+[ ]*52[ ]+lock mov eax,DWORD PTR \[rbx\]
+[ ]*53[ ]+
+[ ]*54[ ]+lock add eax,ebx
+[ ]*55[ ]+lock add ebx,0x64
+[ ]*56[ ]+lock adc eax,ebx
+[ ]*57[ ]+lock adc ebx,0x64
\fGAS LISTING .*
-[ ]*58[ ]+lock btc ebx,eax
-[ ]*59[ ]+lock btc ebx,0x64
-[ ]*60[ ]+lock btr ebx,eax
-[ ]*61[ ]+lock btr ebx,0x64
-[ ]*62[ ]+lock bts ebx,eax
-[ ]*63[ ]+lock bts ebx,0x64
-[ ]*64[ ]+lock cmpxchg ebx,eax
-[ ]*65[ ]+lock dec ebx
-[ ]*66[ ]+lock inc ebx
-[ ]*67[ ]+lock neg ebx
-[ ]*68[ ]+lock not ebx
-[ ]*69[ ]+lock or eax,ebx
-[ ]*70[ ]+lock or ebx,0x64
-[ ]*71[ ]+lock sbb eax,ebx
-[ ]*72[ ]+lock sbb ebx,0x64
-[ ]*73[ ]+lock sub eax,ebx
-[ ]*74[ ]+lock sub ebx,0x64
-[ ]*75[ ]+lock xadd ebx,eax
-[ ]*76[ ]+lock xchg ebx,eax
-[ ]*77[ ]+lock xchg ebx,eax
-[ ]*78[ ]+lock xor eax,ebx
-[ ]*79[ ]+lock xor ebx,0x64
-[ ]*80[ ]+
-[ ]*81[ ]+lock add eax,DWORD PTR \[rbx\]
-[ ]*82[ ]+lock adc eax,DWORD PTR \[rbx\]
-[ ]*83[ ]+lock and eax,DWORD PTR \[rbx\]
-[ ]*84[ ]+lock or eax,DWORD PTR \[rbx\]
-[ ]*85[ ]+lock sbb eax,DWORD PTR \[rbx\]
-[ ]*86[ ]+lock sub eax,DWORD PTR \[rbx\]
-[ ]*87[ ]+lock xor eax,DWORD PTR \[rbx\]
-[ ]*88[ ]+lock wrmsrns
-[ ]*89[ ]+lock rdmsrlist
-[ ]*90[ ]+lock wrmsrlist
+[ ]*58[ ]+lock and eax,ebx
+[ ]*59[ ]+lock and ebx,0x64
+[ ]*60[ ]+lock btc ebx,eax
+[ ]*61[ ]+lock btc ebx,0x64
+[ ]*62[ ]+lock btr ebx,eax
+[ ]*63[ ]+lock btr ebx,0x64
+[ ]*64[ ]+lock bts ebx,eax
+[ ]*65[ ]+lock bts ebx,0x64
+[ ]*66[ ]+lock cmpxchg ebx,eax
+[ ]*67[ ]+lock dec ebx
+[ ]*68[ ]+lock inc ebx
+[ ]*69[ ]+lock neg ebx
+[ ]*70[ ]+lock not ebx
+[ ]*71[ ]+lock or eax,ebx
+[ ]*72[ ]+lock or ebx,0x64
+[ ]*73[ ]+lock sbb eax,ebx
+[ ]*74[ ]+lock sbb ebx,0x64
+[ ]*75[ ]+lock sub eax,ebx
+[ ]*76[ ]+lock sub ebx,0x64
+[ ]*77[ ]+lock xadd ebx,eax
+[ ]*78[ ]+lock xchg ebx,eax
+[ ]*79[ ]+lock xchg ebx,eax
+[ ]*80[ ]+lock xor eax,ebx
+[ ]*81[ ]+lock xor ebx,0x64
+[ ]*82[ ]+
+[ ]*83[ ]+lock add eax,DWORD PTR \[rbx\]
+[ ]*84[ ]+lock adc eax,DWORD PTR \[rbx\]
+[ ]*85[ ]+lock and eax,DWORD PTR \[rbx\]
+[ ]*86[ ]+lock or eax,DWORD PTR \[rbx\]
+[ ]*87[ ]+lock sbb eax,DWORD PTR \[rbx\]
+[ ]*88[ ]+lock sub eax,DWORD PTR \[rbx\]
+[ ]*89[ ]+lock xor eax,DWORD PTR \[rbx\]
+[ ]*90[ ]+lock wrmsrns
+[ ]*91[ ]+lock rdmsrlist
+[ ]*92[ ]+lock wrmsrlist
+[ ]*93[ ]+lock prefetchit0 BYTE PTR \[rip\+0x12345678\]
+[ ]*94[ ]+lock prefetchit1 BYTE PTR \[rip\+0x12345678\]
diff --git a/gas/testsuite/gas/i386/x86-64-lockbad-1.s b/gas/testsuite/gas/i386/x86-64-lockbad-1.s
index fcea969fb9..cdd4721793 100644
--- a/gas/testsuite/gas/i386/x86-64-lockbad-1.s
+++ b/gas/testsuite/gas/i386/x86-64-lockbad-1.s
@@ -44,6 +44,8 @@ foo:
lock wrmsrns
lock rdmsrlist
lock wrmsrlist
+ lock prefetchit0 0x12345678(%rip)
+ lock prefetchit1 0x12345678(%rip)
.intel_syntax noprefix
lock mov eax,ebx
@@ -88,3 +90,5 @@ foo:
lock wrmsrns
lock rdmsrlist
lock wrmsrlist
+ lock prefetchit0 BYTE PTR [rip+0x12345678]
+ lock prefetchit1 BYTE PTR [rip+0x12345678]
diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-intel.d b/gas/testsuite/gas/i386/x86-64-prefetchi-intel.d
new file mode 100644
index 0000000000..7f72f0a1eb
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetchi-intel.d
@@ -0,0 +1,16 @@
+#as:
+#objdump: -dwMintel
+#name: x86-64 PREFETCHI insns (Intel disassembly)
+#source: x86-64-prefetchi.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d
new file mode 100644
index 0000000000..b29b1ae237
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d
@@ -0,0 +1,13 @@
+#as:
+#objdump: -dw
+#name: x86-64 PREFETCHI INVAL REGISTER insns
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <\.text>:
+[ ]*[a-f0-9]+:[ ]0f 18 39[ ]*nopl \(%rcx\)
+[ ]*[a-f0-9]+:[ ]0f 18 31[ ]*nopl \(%rcx\)
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s
new file mode 100644
index 0000000000..550449a0c9
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s
@@ -0,0 +1,9 @@
+.text
+ #prefetchit0 (%rcx) PREFETCHIT0/1 apply without RIP-relative addressing, should stay NOPs.
+ .byte 0x0f
+ .byte 0x18
+ .byte 0x39
+ #prefetchit1 (%rcx) PREFETCHIT1/1 apply without RIP-relative addressing, should stay NOPs.
+ .byte 0x0f
+ .byte 0x18
+ .byte 0x31
diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi.d b/gas/testsuite/gas/i386/x86-64-prefetchi.d
new file mode 100644
index 0000000000..c8ab92d147
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetchi.d
@@ -0,0 +1,15 @@
+#as:
+#objdump: -dw
+#name: x86-64 PREFETCHI insns
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi.s b/gas/testsuite/gas/i386/x86-64-prefetchi.s
new file mode 100644
index 0000000000..cc7c61e9a9
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetchi.s
@@ -0,0 +1,14 @@
+# Check 64bit PREFETCHI instructions
+
+ .allow_index_reg
+ .text
+_start:
+
+ prefetchit0 0x12345678(%rip)
+ prefetchit1 0x12345678(%rip)
+
+ .intel_syntax noprefix
+
+ prefetchit0 BYTE PTR [rip+0x12345678]
+ prefetchit1 BYTE PTR [rip+0x12345678]
+
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index be25d3f612..8e799aa3bb 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -114,6 +114,7 @@ static void FXSAVE_Fixup (instr_info *, int, int);
static void MOVSXD_Fixup (instr_info *, int, int);
static void DistinctDest_Fixup (instr_info *, int, int);
+static void PREFETCHI_Fixup (instr_info *, int, int);
/* This character is used to encode style information within the output
buffers. See oappend_insert_style for more details. */
@@ -841,6 +842,8 @@ enum
MOD_0F18_REG_1,
MOD_0F18_REG_2,
MOD_0F18_REG_3,
+ MOD_0F18_REG_6,
+ MOD_0F18_REG_7,
MOD_0F1A_PREFIX_0,
MOD_0F1B_PREFIX_0,
MOD_0F1B_PREFIX_1,
@@ -1297,6 +1300,8 @@ enum
X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
+ X86_64_MOD_0F18_REG_6,
+ X86_64_MOD_0F18_REG_7,
X86_64_0F24,
X86_64_0F26,
X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
@@ -2768,8 +2773,8 @@ static const struct dis386 reg_table[][8] = {
{ MOD_TABLE (MOD_0F18_REG_3) },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
- { "nopQ", { Ev }, 0 },
- { "nopQ", { Ev }, 0 },
+ { MOD_TABLE (MOD_0F18_REG_6) },
+ { MOD_TABLE (MOD_0F18_REG_7) },
},
/* REG_0F1C_P_0_MOD_0 */
{
@@ -4414,6 +4419,18 @@ static const struct dis386 x86_64_table[][2] = {
{ "psmash", { Skip_MODRM }, 0 },
},
+ /* X86_64_MOD_0F18_REG_6 */
+ {
+ { "nopQ", { Ev }, 0 },
+ { "prefetchit1", { { PREFETCHI_Fixup, b_mode } }, 0 },
+ },
+
+ /* X86_64_MOD_0F18_REG_7 */
+ {
+ { "nopQ", { Ev }, 0 },
+ { "prefetchit0", { { PREFETCHI_Fixup, b_mode } }, 0 },
+ },
+
{
/* X86_64_0F24 */
{ "movZ", { Em, Td }, 0 },
@@ -8213,6 +8230,16 @@ static const struct dis386 mod_table[][2] = {
{ "prefetcht2", { Mb }, 0 },
{ "nopQ", { Ev }, 0 },
},
+ {
+ /* MOD_0F18_REG_6 */
+ { X86_64_TABLE (X86_64_MOD_0F18_REG_6) },
+ { "nopQ", { Ev }, 0 },
+ },
+ {
+ /* MOD_0F18_REG_7 */
+ { X86_64_TABLE (X86_64_MOD_0F18_REG_7) },
+ { "nopQ", { Ev }, 0 },
+ },
{
/* MOD_0F1A_PREFIX_0 */
{ "bndldx", { Gbnd, Mv_bnd }, 0 },
@@ -14021,3 +14048,18 @@ OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
}
oappend (ins, "sae}");
}
+
+static void
+PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag)
+{
+ if (ins->modrm.mod != 0 || ins->modrm.rm != 5)
+ {
+ if (ins->intel_syntax)
+ ins->mnemonicendp = stpcpy (ins->obuf, "nop ");
+ else
+ ins->mnemonicendp = stpcpy (ins->obuf, "nopl ");
+ bytemode = v_mode;
+ }
+
+ OP_M (ins, bytemode, sizeflag);
+}
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index d10b462548..1e61d3f735 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -261,6 +261,8 @@ static initializer cpu_flag_init[] =
"CpuMSRLIST" },
{ "CPU_AMX_FP16_FLAGS",
"CpuAMX_FP16" },
+ { "CPU_PREFETCHI_FLAGS",
+ "CpuPREFETCHI"},
{ "CPU_IAMCU_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
{ "CPU_ADX_FLAGS",
@@ -471,6 +473,8 @@ static initializer cpu_flag_init[] =
"CpuMSRLIST" },
{ "CPU_ANY_AMX_FP16_FLAGS",
"CpuAMX_FP16" },
+ { "CPU_ANY_PREFETCHI_FLAGS",
+ "CpuPREFETCHI" },
};
static initializer operand_type_init[] =
@@ -680,6 +684,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuWRMSRNS),
BITFIELD (CpuMSRLIST),
BITFIELD (CpuAMX_FP16),
+ BITFIELD (CpuPREFETCHI),
BITFIELD (CpuMWAITX),
BITFIELD (CpuCLZERO),
BITFIELD (CpuOSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 0dec14e365..f2cb673be4 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -225,6 +225,8 @@ enum
CpuMSRLIST,
/* AMX-FP16 instructions required */
CpuAMX_FP16,
+ /* PREFETCHI instruction required */
+ CpuPREFETCHI,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@@ -412,6 +414,7 @@ typedef union i386_cpu_flags
unsigned int cpuwrmsrns:1;
unsigned int cpumsrlist:1;
unsigned int cpuamx_fp16:1;
+ unsigned int cpuprefetchi:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 95bb2fc1fd..4755b02ed5 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3345,3 +3345,10 @@ wrmsrlist, 0xf30f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
tdpfp16ps, 0xf25c, None, CpuAMX_FP16|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegTMM, RegTMM, RegTMM }
// AMX-FP16 instructions end.
+
+// PREFETCHI instructions.
+
+prefetchit0, 0xf18, 0x7, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
+prefetchit1, 0xf18, 0x6, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
+
+// PREFETCHI instructions end.
--
2.18.2
next prev parent reply other threads:[~2022-10-14 9:15 UTC|newest]
Thread overview: 123+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-14 9:12 [PATCH 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions Haochen Jiang
2022-10-14 9:12 ` [PATCH 01/10] Support Intel AVX-IFMA Haochen Jiang
2022-10-14 9:52 ` Jan Beulich
2022-10-14 18:10 ` H.J. Lu
2022-10-16 6:39 ` Jan Beulich
2022-10-17 22:23 ` H.J. Lu
2022-10-18 5:33 ` Jan Beulich
2022-10-18 21:28 ` H.J. Lu
2022-10-19 6:01 ` Jan Beulich
2022-10-19 21:27 ` H.J. Lu
2022-10-20 6:15 ` Jan Beulich
2022-10-24 2:07 ` Jiang, Haochen
2022-10-24 5:53 ` Jiang, Haochen
2022-10-24 19:09 ` H.J. Lu
2022-10-25 6:29 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 02/10] Support Intel AVX-VNNI-INT8 Haochen Jiang
2022-10-14 10:57 ` Jan Beulich
2022-10-21 3:22 ` Jiang, Haochen
2022-10-25 1:52 ` H.J. Lu
2022-10-14 9:12 ` [PATCH 03/10] Support Intel AVX-NE-CONVERT Haochen Jiang
2022-10-14 12:58 ` Jan Beulich
2022-10-24 5:37 ` Kong, Lingling
2022-10-24 5:59 ` Kong, Lingling
2022-10-24 19:25 ` H.J. Lu
2022-10-25 6:44 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 04/10] Support Intel CMPccXADD Haochen Jiang
2022-10-14 13:46 ` Jan Beulich
2022-10-14 18:27 ` H.J. Lu
2022-10-14 21:51 ` H.J. Lu
2022-10-16 6:34 ` Jan Beulich
2022-10-17 23:31 ` H.J. Lu
2022-10-16 6:25 ` Jan Beulich
2022-10-17 23:44 ` H.J. Lu
2022-10-16 6:19 ` Jan Beulich
2022-10-24 2:30 ` Jiang, Haochen
2022-10-24 19:12 ` H.J. Lu
2022-10-24 5:55 ` Jiang, Haochen
2022-10-25 6:53 ` Jan Beulich
2022-10-26 3:03 ` Jiang, Haochen
2022-10-26 8:49 ` Jan Beulich
2022-10-27 3:09 ` Jiang, Haochen
2022-10-27 6:37 ` Jan Beulich
2022-10-28 0:59 ` Jiang, Haochen
2022-10-14 9:12 ` [PATCH 05/10] Add handler for more i386_cpu_flags Haochen Jiang
2022-10-14 13:53 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 06/10] Support Intel RAO-INT Haochen Jiang
2022-10-14 14:38 ` Jan Beulich
2022-10-16 6:15 ` Jan Beulich
2022-10-24 3:12 ` Jiang, Haochen
2022-10-24 19:17 ` H.J. Lu
2022-10-24 5:56 ` Jiang, Haochen
2022-10-25 7:01 ` Jan Beulich
2022-10-26 5:16 ` Jiang, Haochen
2022-10-26 8:56 ` Jan Beulich
2022-10-27 3:50 ` Jiang, Haochen
2022-10-27 6:39 ` Jan Beulich
2022-10-27 18:46 ` H.J. Lu
2022-10-28 6:52 ` Jan Beulich
2022-10-28 8:10 ` Jiang, Haochen
2022-10-28 8:22 ` Jan Beulich
2022-10-28 8:31 ` Jiang, Haochen
2022-10-28 8:40 ` Jan Beulich
2022-10-28 16:08 ` H.J. Lu
2022-10-31 9:41 ` Jan Beulich
2022-10-31 16:49 ` H.J. Lu
2022-11-06 12:50 ` Kong, Lingling
2022-11-07 9:24 ` Jan Beulich
2022-11-07 13:37 ` Kong, Lingling
2022-11-07 20:03 ` H.J. Lu
2022-10-17 23:23 ` H.J. Lu
2022-10-18 5:38 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 07/10] Support Intel WRMSRNS Haochen Jiang
2022-10-17 7:17 ` Jan Beulich
2022-10-24 2:52 ` Jiang, Haochen
2022-10-24 5:56 ` Jiang, Haochen
2022-10-24 19:14 ` H.J. Lu
2022-10-25 7:04 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 08/10] Support Intel MSRLIST Haochen Jiang
2022-10-17 7:20 ` Jan Beulich
2022-10-24 3:03 ` Jiang, Haochen
2022-10-24 5:56 ` Jiang, Haochen
2022-10-24 19:15 ` H.J. Lu
2022-10-25 7:07 ` Jan Beulich
2022-10-14 9:12 ` [PATCH 09/10] Support Intel AMX-FP16 Haochen Jiang
2022-10-17 7:35 ` Jan Beulich
2022-10-18 9:01 ` Cui, Lili
2022-10-18 9:23 ` Jan Beulich
2022-10-18 9:33 ` Jiang, Haochen
2022-10-19 10:33 ` Cui, Lili
2022-10-19 13:35 ` Jan Beulich
2022-10-19 14:05 ` Cui, Lili
2022-10-19 14:09 ` Jan Beulich
2022-10-19 14:41 ` Cui, Lili
2022-10-19 15:04 ` Jan Beulich
2022-10-19 15:21 ` Cui, Lili
2022-10-19 14:01 ` Jiang, Haochen
2022-10-19 14:13 ` Jan Beulich
2022-10-19 14:58 ` Jiang, Haochen
2022-10-25 6:02 ` Jan Beulich
2022-10-25 13:05 ` Cui, Lili
2022-10-14 9:12 ` Haochen Jiang [this message]
2022-10-17 8:15 ` [PATCH 10/10] Support Intel PREFETCHI Jan Beulich
2022-10-25 13:03 ` Cui, Lili
2022-10-25 15:41 ` Jan Beulich
2022-10-25 15:52 ` Jan Beulich
2022-10-25 17:01 ` H.J. Lu
2022-10-26 13:42 ` Cui, Lili
2022-10-26 13:53 ` Jan Beulich
2022-10-27 6:04 ` Cui, Lili
2022-10-27 6:45 ` Jan Beulich
2022-10-27 7:01 ` Cui, Lili
2022-10-27 7:15 ` Jan Beulich
2022-10-27 7:43 ` Cui, Lili
2022-10-28 9:03 ` Cui, Lili
2022-10-28 15:54 ` H.J. Lu
2022-10-31 13:23 ` Cui, Lili
2022-10-31 14:45 ` Mike Frysinger
2022-10-31 16:25 ` H.J. Lu
2022-10-19 14:55 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions Haochen Jiang
2022-10-19 14:56 ` [PATCH 10/10] Support Intel PREFETCHI Haochen Jiang
2022-10-19 15:15 [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions (Resend) Haochen Jiang
2022-10-19 15:15 ` [PATCH 10/10] Support Intel PREFETCHI Haochen Jiang
2022-10-25 7:11 ` Jan Beulich
2022-10-25 7:49 ` Cui, Lili
2022-10-25 8:31 ` Jan Beulich
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