[PATCH 0/5] Add Xtensa ESP chips support

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* [PATCH 0/5] Add Xtensa ESP chips support
@ 2022-10-22 12:51 Alexey Lapshin
  2022-10-22 12:53 ` [PATCH 1/5] bfd: xtensa: move common code from ld and gas Alexey Lapshin
                   ` (5 more replies)
  0 siblings, 6 replies; 14+ messages in thread
From: Alexey Lapshin @ 2022-10-22 12:51 UTC (permalink / raw)
  To: binutils; +Cc: Alexey Gerenkov, Ivan Grokhotkov, Anton Maklakov

Since ESP chips are getting more and more popular for developers I
would like to suggest these patches to consider to include Xtensa ESP
chips support for binutils and gdb.

The chips support was done in a not common binutils way. There are a
few reasons for that:
As I know, the Xtensa specific code for binutils and gdb is generated
with tools from Tensilica Inc.
To build binutils and gdb with other chip presets we need to override
some related files (https://github.com/espressif/xtensa-overlays).
To make it easy to integrate new chips I did refactor the code a bit to
make a possibility to just copy and paste Tensilica-generated files and
modify a few lines in a code to make it supported in binutils and gdb.

Please consider these changes to merge, I believe this could be a
pretty improvement to extend supported CPUs without using third-party
sources patches.

Alexey Lapshin (5):
  bfd: xtensa: move common code from ld and gas
  gas: xtensa: add endianness, loops, booleans options
  ld: xtensa: use default LD command line options to specify endianness
  gas: xtensa: add esp32, esp32s2, esp32s3 isa-modules options
  gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules

 bfd/Makefile.am                               |    10 +-
 bfd/Makefile.in                               |    15 +-
 bfd/configure                                 |     4 +-
 bfd/configure.ac                              |     4 +-
 bfd/elf32-xtensa.c                            |   126 +
 ...nsa-modules.c => xtensa-default-modules.c} |     2 +-
 bfd/xtensa-esp32-modules.c                    | 19191 +++++++
 bfd/xtensa-esp32s2-modules.c                  | 11671 +++++
 bfd/xtensa-esp32s3-modules.c                  | 43674 ++++++++++++++++
 bfd/xtensa-isa.c                              |    25 +-
 gas/config/tc-xtensa.c                        |    79 +-
 gas/config/tc-xtensa.h                        |     2 +-
 gas/config/xtensa-relax.c                     |     8 +-
 gdb/Makefile.in                               |    10 +-
 gdb/configure.tgt                             |     2 +-
 ...tensa-config.c => xtensa-config-default.c} |    66 +-
 gdb/xtensa-config-esp32.c                     |   389 +
 gdb/xtensa-config-esp32s2.c                   |   271 +
 gdb/xtensa-config-esp32s3.c                   |   496 +
 gdb/xtensa-tdep.c                             |    70 +-
 gdb/xtensa-tdep.h                             |     2 +-
 include/elf/xtensa.h                          |    22 +
 include/xtensa-isa.h                          |     8 +
 ld/emultempl/xtensaelf.em                     |   169 +-
 24 files changed, 76128 insertions(+), 188 deletions(-)
 rename bfd/{xtensa-modules.c => xtensa-default-modules.c} (99%)
 create mode 100644 bfd/xtensa-esp32-modules.c
 create mode 100644 bfd/xtensa-esp32s2-modules.c
 create mode 100644 bfd/xtensa-esp32s3-modules.c
 rename gdb/{xtensa-config.c => xtensa-config-default.c} (84%)
 create mode 100644 gdb/xtensa-config-esp32.c
 create mode 100644 gdb/xtensa-config-esp32s2.c
 create mode 100644 gdb/xtensa-config-esp32s3.c

-- 
2.34.1


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH 1/5] bfd: xtensa: move common code from ld and gas
  2022-10-22 12:51 [PATCH 0/5] Add Xtensa ESP chips support Alexey Lapshin
@ 2022-10-22 12:53 ` Alexey Lapshin
  2022-10-22 12:55 ` [PATCH 2/5] gas: xtensa: add endianness, loops, booleans options Alexey Lapshin
                   ` (4 subsequent siblings)
  5 siblings, 0 replies; 14+ messages in thread
From: Alexey Lapshin @ 2022-10-22 12:53 UTC (permalink / raw)
  To: binutils; +Cc: Alexey Gerenkov, Ivan Grokhotkov, Anton Maklakov

Just refactor the common code to easy maintain.

---
 bfd/elf32-xtensa.c        | 108 +++++++++++++++++++++++++++++++++++
 gas/config/tc-xtensa.c    |   7 +--
 include/elf/xtensa.h      |  18 ++++++
 ld/emultempl/xtensaelf.em | 116 ++++++--------------------------------
 4 files changed, 144 insertions(+), 105 deletions(-)

diff --git a/bfd/elf32-xtensa.c b/bfd/elf32-xtensa.c
index cb658483ca6..77ff4d63381 100644
--- a/bfd/elf32-xtensa.c
+++ b/bfd/elf32-xtensa.c
@@ -11495,6 +11495,114 @@ xtensa_callback_required_dependence (bfd
*abfd,
   return ok;
 }
 
+static void
+xtensa_info_set_entry (char *key, int value, xtensa_info_entries
*entries)
+{
+  if (! strcmp (key, "ABI"))
+    {
+      entries->abi = value;
+    }
+  else if (! strcmp (key, "USE_ABSOLUTE_LITERALS"))
+    {
+      entries->use_absolute_literals = value;
+    }
+}
+
+static bool
+xtensa_info_parse (char *data, xtensa_info_entries *entries)
+{
+  char *d, *key;
+
+  d = data;
+  while (*d)
+    {
+      key = d;
+      d = strchr (d, '=');
+      if (! d)
+        goto error;
+
+      /* Overwrite the equal sign.  */
+      *d++ = 0;
+
+      /* Check if this is a quoted string or a number.  */
+      if (*d == '"')
+        {
+          /* No string values are currently checked by LD;
+             just skip over the quotes.  */
+          d++;
+          d = strchr (d, '"');
+          if (! d)
+            goto error;
+          /* Skip the trailing quote.  */
+          d++;
+        }
+      else if( *d >= '0' && *d <= '9' )
+        {
+          int value = strtoul (d, &d, 0);
+          xtensa_info_set_entry (key, value, entries);
+        }
+      else
+        goto error;
+
+      if (*d++ != '\n')
+        goto error;
+    }
+
+  return true;
+
+error:
+  return false;
+}
+
+bool
+read_xtensa_info (bfd *abfd, asection *info_sec, xtensa_info_entries
*entries)
+{
+  bool ret = false;
+  char *data = (char *) bfd_malloc (info_sec->size);
+
+  /* initialize values  */
+  entries->abi = XSHAL_ABI;
+  entries->use_absolute_literals = XSHAL_USE_ABSOLUTE_LITERALS;
+
+  if (! bfd_get_section_contents (abfd, info_sec, data, 0, info_sec-
>size))
+    {
+      fprintf (stderr, _("%pB: cannot read contents of section
%pA\n"),
+               abfd, info_sec);
+      goto exit;
+    }
+
+  if (! (info_sec->size > 24
+         && info_sec->size >= 24 + bfd_get_32 (abfd, data + 4)
+         && bfd_get_32 (abfd, data + 0) == XTINFO_NAMESZ
+         && bfd_get_32 (abfd, data + 8) == XTINFO_TYPE
+         && strcmp (data + 12, XTINFO_NAME) == 0
+         && xtensa_info_parse (data + 12 + XTINFO_NAMESZ, entries)
+        )
+     )
+    {
+      fprintf (stderr,
+               _("%pB: warning: cannot parse .xtensa.info section\n"),
+               abfd);
+      goto exit;
+    }
+
+  ret = true;
+
+exit:
+  free (data);
+  return ret;
+}
+
+void
+fill_xtensa_info (char **data)
+{
+  sprintf (*data,
+           "USE_ABSOLUTE_LITERALS=%d\n"
+           "ABI=%d\n",
+           XSHAL_USE_ABSOLUTE_LITERALS,
+           xtensa_abi_choice ());
+}
+
 /* The default literal sections should always be marked as "code"
(i.e.,
    SHF_EXECINSTR).  This is particularly important for the Linux
kernel
    module loader so that the literals are not placed after the text. 
*/
diff --git a/gas/config/tc-xtensa.c b/gas/config/tc-xtensa.c
index 3e3deb5dd36..df6a3cec8a1 100644
--- a/gas/config/tc-xtensa.c
+++ b/gas/config/tc-xtensa.c
@@ -8982,10 +8982,6 @@ is_local_forward_loop (const TInsn *insn, fragS
*fragP)
   return false;
 }
 
-#define XTINFO_NAME "Xtensa_Info"
-#define XTINFO_NAMESZ 12
-#define XTINFO_TYPE 1
-
 static void
 xtensa_add_config_info (void)
 {
@@ -8997,8 +8993,7 @@ xtensa_add_config_info (void)
   bfd_set_section_flags (info_sec, SEC_HAS_CONTENTS | SEC_READONLY);
 
   data = XNEWVEC (char, 100);
-  sprintf (data, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
-	   XSHAL_USE_ABSOLUTE_LITERALS, xtensa_abi_choice ());
+  fill_xtensa_info (&data);
   sz = strlen (data) + 1;
 
   /* Add enough null terminators to pad to a word boundary.  */
diff --git a/include/elf/xtensa.h b/include/elf/xtensa.h
index 542821b0dc9..6d916f8fd64 100644
--- a/include/elf/xtensa.h
+++ b/include/elf/xtensa.h
@@ -138,6 +138,18 @@ typedef struct property_table_entry_t
   flagword flags;
 } property_table_entry;
 
+/* .xtensa.info section related definitions  */
+
+#define XTINFO_NAME "Xtensa_Info"
+#define XTINFO_NAMESZ sizeof(XTINFO_NAME)
+#define XTINFO_TYPE 1
+
+typedef struct xtensa_info_entries_t
+{
+  int abi;
+  int use_absolute_literals;
+} xtensa_info_entries;
+
 /* Flags in the property tables to specify whether blocks of memory
are
    literals, instructions, data, or unreachable.  For instructions,
    blocks that begin loop targets and branch targets are designated.
@@ -228,6 +240,12 @@ xtensa_compute_fill_extra_space
(property_table_entry *entry);
 extern int
 xtensa_abi_choice (void);
 
+extern void
+fill_xtensa_info (char **data);
+
+extern bool
+read_xtensa_info (bfd *abfd, asection *info_sec, xtensa_info_entries
*entries);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/ld/emultempl/xtensaelf.em b/ld/emultempl/xtensaelf.em
index 9d527daea95..ed2945b850d 100644
--- a/ld/emultempl/xtensaelf.em
+++ b/ld/emultempl/xtensaelf.em
@@ -312,108 +312,25 @@ elf_xtensa_after_open (void)
 }
 
 
-static bool
-xt_config_info_unpack_and_check (char *data,
-				 bool *pmismatch,
-				 char **pmsg)
+static void
+check_xtensa_info (bfd *abfd, xtensa_info_entries *entries)
 {
-  char *d, *key;
-  int num;
-
-  *pmismatch = false;
-
-  d = data;
-  while (*d)
+  /* Check ABI */
+  if (elf32xtensa_abi == XTHAL_ABI_UNDEFINED)
     {
-      key = d;
-      d = strchr (d, '=');
-      if (! d)
-	goto error;
-
-      /* Overwrite the equal sign.  */
-      *d++ = 0;
-
-      /* Check if this is a quoted string or a number.  */
-      if (*d == '"')
-	{
-	  /* No string values are currently checked by LD;
-	     just skip over the quotes.  */
-	  d++;
-	  d = strchr (d, '"');
-	  if (! d)
-	    goto error;
-	  /* Overwrite the trailing quote.  */
-	  *d++ = 0;
-	}
-      else
-	{
-	  if (*d == 0)
-	    goto error;
-	  num = strtoul (d, &d, 0);
-
-	  if (! strcmp (key, "ABI"))
-	    {
-	      if (elf32xtensa_abi == XTHAL_ABI_UNDEFINED)
-		{
-		  elf32xtensa_abi = num;
-		}
-	      else if (num != elf32xtensa_abi)
-		{
-		  *pmismatch = true;
-		  *pmsg = "ABI does not match";
-		}
-	    }
-	  else if (! strcmp (key, "USE_ABSOLUTE_LITERALS"))
-	    {
-	      if (num != XSHAL_USE_ABSOLUTE_LITERALS)
-		{
-		  *pmismatch = true;
-		  *pmsg = "incompatible use of the Extended L32R
option";
-		}
-	    }
-	}
-
-      if (*d++ != '\n')
-	goto error;
+      elf32xtensa_abi = entries->abi;
     }
-
-  return true;
-
- error:
-  return false;
-}
-
-
-#define XTINFO_NAME "Xtensa_Info"
-#define XTINFO_NAMESZ 12
-#define XTINFO_TYPE 1
-
-static void
-check_xtensa_info (bfd *abfd, asection *info_sec)
-{
-  char *data, *errmsg = "";
-  bool mismatch;
-
-  data = xmalloc (info_sec->size);
-  if (! bfd_get_section_contents (abfd, info_sec, data, 0, info_sec-
>size))
-    einfo (_("%F%P: %pB: cannot read contents of section %pA\n"),
abfd, info_sec);
-
-  if (info_sec->size > 24
-      && info_sec->size >= 24 + bfd_get_32 (abfd, data + 4)
-      && bfd_get_32 (abfd, data + 0) == XTINFO_NAMESZ
-      && bfd_get_32 (abfd, data + 8) == XTINFO_TYPE
-      && strcmp (data + 12, XTINFO_NAME) == 0
-      && xt_config_info_unpack_and_check (data + 12 + XTINFO_NAMESZ,
-					  &mismatch, &errmsg))
+  else if (entries->abi != elf32xtensa_abi)
     {
-      if (mismatch)
-	einfo (_("%P: %pB: warning: incompatible Xtensa configuration
(%s)\n"),
-	       abfd, errmsg);
+      einfo (_("%P: %pB: warning: Xtensa ABI does not match\n"),
abfd);
     }
-  else
-    einfo (_("%P: %pB: warning: cannot parse .xtensa.info section\n"),
abfd);
 
-  free (data);
+  /* Check USE_ABSOLUTE_LITERALS */
+  if (entries->use_absolute_literals != XSHAL_USE_ABSOLUTE_LITERALS)
+    {
+      einfo (_("%P: %pB: warning: Xtensa incompatible use of the
Extended L32R option (%d != %d)\n"),
+             abfd, entries->use_absolute_literals,
XSHAL_USE_ABSOLUTE_LITERALS);
+    }
 }
 
 
@@ -423,6 +340,7 @@ check_xtensa_info (bfd *abfd, asection *info_sec)
 static void
 elf_xtensa_before_allocation (void)
 {
+  xtensa_info_entries xtensa_info;
   asection *info_sec, *first_info_sec;
   bfd *first_bfd;
   bool is_big_endian = XCHAL_HAVE_BE;
@@ -477,7 +395,8 @@ elf_xtensa_before_allocation (void)
 
       /* Unpack the .xtensa.info section and check it against the
current
 	 Xtensa configuration.  */
-      check_xtensa_info (f->the_bfd, info_sec);
+      if (read_xtensa_info (f->the_bfd, info_sec, &xtensa_info))
+	check_xtensa_info (f->the_bfd, &xtensa_info);
 
       /* Do not include this copy of .xtensa.info in the output.  */
       info_sec->size = 0;
@@ -504,8 +423,7 @@ elf_xtensa_before_allocation (void)
       info_sec->flags |= SEC_IN_MEMORY;
 
       data = xmalloc (100);
-      sprintf (data, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
-	       XSHAL_USE_ABSOLUTE_LITERALS, xtensa_abi_choice ());
+      fill_xtensa_info (&data);
       xtensa_info_size = strlen (data) + 1;
 
       /* Add enough null terminators to pad to a word boundary.  */
-- 
2.34.1


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH 2/5] gas: xtensa: add endianness, loops, booleans options
  2022-10-22 12:51 [PATCH 0/5] Add Xtensa ESP chips support Alexey Lapshin
  2022-10-22 12:53 ` [PATCH 1/5] bfd: xtensa: move common code from ld and gas Alexey Lapshin
@ 2022-10-22 12:55 ` Alexey Lapshin
  2022-10-22 12:56 ` [PATCH 3/5] ld: xtensa: use default LD command line options for endianness Alexey Lapshin
                   ` (3 subsequent siblings)
  5 siblings, 0 replies; 14+ messages in thread
From: Alexey Lapshin @ 2022-10-22 12:55 UTC (permalink / raw)
  To: binutils; +Cc: Alexey Gerenkov, Ivan Grokhotkov, Anton Maklakov

Added additional assembley options for a better flexibility.

---
 gas/config/tc-xtensa.c    | 53 ++++++++++++++++++++++++++++++++++++---
 gas/config/tc-xtensa.h    |  2 +-
 gas/config/xtensa-relax.c |  8 ++++--
 3 files changed, 57 insertions(+), 6 deletions(-)

diff --git a/gas/config/tc-xtensa.c b/gas/config/tc-xtensa.c
index df6a3cec8a1..630d147bf63 100644
--- a/gas/config/tc-xtensa.c
+++ b/gas/config/tc-xtensa.c
@@ -89,6 +89,9 @@ static vliw_insn cur_vinsn;
 unsigned xtensa_num_pipe_stages;
 unsigned xtensa_fetch_width;
 
+unsigned target_have_booleans = XCHAL_HAVE_LOOPS;
+unsigned target_have_loops = XCHAL_HAVE_BOOLEANS;
+
 static enum debug_info_type xt_saved_debug_type = DEBUG_NONE;
 
 /* Some functions are only valid in the front end.  This variable
@@ -746,6 +749,15 @@ enum
 
   option_abi_windowed,
   option_abi_call0,
+
+  option_eb,
+  option_el,
+
+  option_loops,
+  option_no_loops,
+
+  option_booleans,
+  option_no_booleans,
 };
 
 const char *md_shortopts = "";
@@ -830,6 +842,15 @@ struct option md_longopts[] =
   { "abi-windowed", no_argument, NULL, option_abi_windowed },
   { "abi-call0", no_argument, NULL, option_abi_call0 },
 
+  { "EL", no_argument, NULL, option_el },
+  { "EB", no_argument, NULL, option_eb },
+
+  { "loops", no_argument, NULL, option_loops },
+  { "no-loops", no_argument, NULL, option_no_loops },
+
+  { "booleans", no_argument, NULL, option_booleans },
+  { "no-booleans", no_argument, NULL, option_no_booleans },
+
   { NULL, no_argument, NULL, 0 }
 };
 
@@ -1066,6 +1087,30 @@ md_parse_option (int c, const char *arg)
       elf32xtensa_abi = XTHAL_ABI_CALL0;
       return 1;
 
+    case option_eb:
+      target_big_endian = 1;
+      return 1;
+
+    case option_el:
+      target_big_endian = 0;
+      return 1;
+
+    case option_loops:
+      target_have_loops = 1;
+      return 1;
+
+    case option_no_loops:
+      target_have_loops = 0;
+      return 1;
+
+    case option_booleans:
+      target_have_booleans = 1;
+      return 1;
+
+    case option_no_booleans:
+      target_have_booleans = 0;
+      return 1;
+
     default:
       return 0;
     }
@@ -1100,7 +1145,11 @@ Xtensa options:\n\
   --[no-]separate-prop-tables\n\
                           [Do not] place Xtensa property records into\n\
                           individual property sections for each section.\n\
-                          Default is to generate single property section.\n", stream);
+                          Default is to generate single property section.\n\
+  --EB                    Generate code for a big endian machine.\n\
+  --EL                    Generate code for a little endian machine.\n\
+  --[no-]booleans         [Do not] use boolean registers.\n\
+  --[no-]loops            [Do not] zero-overhead loops.\n", stream);
 }
 
 \f
@@ -5268,8 +5317,6 @@ md_number_to_chars (char *buf, valueT val, int n)
 static void
 xg_init_global_config (void)
 {
-  target_big_endian = XCHAL_HAVE_BE;
-
   density_supported = XCHAL_HAVE_DENSITY;
   absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS;
   xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH;
diff --git a/gas/config/tc-xtensa.h b/gas/config/tc-xtensa.h
index 1887558ecf1..914f4565c52 100644
--- a/gas/config/tc-xtensa.h
+++ b/gas/config/tc-xtensa.h
@@ -30,7 +30,7 @@ struct fix;
 #include "xtensa-isa.h"
 #include "xtensa-config.h"
 
-#define TARGET_BYTES_BIG_ENDIAN 0
+#define TARGET_BYTES_BIG_ENDIAN XCHAL_HAVE_BE
 
 
 /* Maximum number of opcode slots in a VLIW instruction.  */
diff --git a/gas/config/xtensa-relax.c b/gas/config/xtensa-relax.c
index 0682b29f815..aad9ae7d348 100644
--- a/gas/config/xtensa-relax.c
+++ b/gas/config/xtensa-relax.c
@@ -102,6 +102,10 @@
 /* Imported from bfd.  */
 extern xtensa_isa xtensa_default_isa;
 
+/* Imported from tc-xtensa.  */
+extern unsigned target_have_booleans;
+extern unsigned target_have_loops;
+
 /* The opname_list is a small list of names that we use for opcode and
    operand variable names to simplify ownership of these commonly used
    strings.  Strings entered in the table can be compared by pointer
@@ -1569,7 +1573,7 @@ transition_applies (insn_pattern *initial_insn,
 	  else if (!strcmp (option_name, "Const16"))
 	    option_available = (XCHAL_HAVE_CONST16 == 1);
 	  else if (!strcmp (option_name, "Loops"))
-	    option_available = (XCHAL_HAVE_LOOPS == 1);
+	    option_available = (target_have_loops == 1);
 	  else if (!strcmp (option_name, "WideBranches"))
 	    option_available
 	      = (XCHAL_HAVE_WIDE_BRANCHES == 1 && produce_flix == FLIX_ALL);
@@ -1578,7 +1582,7 @@ transition_applies (insn_pattern *initial_insn,
 	      = (XCHAL_HAVE_PREDICTED_BRANCHES == 1
 		 && produce_flix == FLIX_ALL);
 	  else if (!strcmp (option_name, "Booleans"))
-	    option_available = (XCHAL_HAVE_BOOLEANS == 1);
+	    option_available = (target_have_booleans == 1);
 	  else
 	    as_warn (_("invalid configuration option '%s' in transition rule '%s'"),
 		     req_or_option->option_name, from_string);
-- 
2.34.1


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH 3/5] ld: xtensa: use default LD command line options for endianness
  2022-10-22 12:51 [PATCH 0/5] Add Xtensa ESP chips support Alexey Lapshin
  2022-10-22 12:53 ` [PATCH 1/5] bfd: xtensa: move common code from ld and gas Alexey Lapshin
  2022-10-22 12:55 ` [PATCH 2/5] gas: xtensa: add endianness, loops, booleans options Alexey Lapshin
@ 2022-10-22 12:56 ` Alexey Lapshin
  2022-10-22 13:54 ` [PATCH 4/5] gas: xtensa: add esp32, esp32s2, esp32s3 isa-modules options Alexey Lapshin
                   ` (2 subsequent siblings)
  5 siblings, 0 replies; 14+ messages in thread
From: Alexey Lapshin @ 2022-10-22 12:56 UTC (permalink / raw)
  To: binutils; +Cc: Alexey Gerenkov, Ivan Grokhotkov, Anton Maklakov

Use --EB, --EL ld options instead of hardcoded macro definition.

---
 ld/emultempl/xtensaelf.em | 27 +++------------------------
 1 file changed, 3 insertions(+), 24 deletions(-)

diff --git a/ld/emultempl/xtensaelf.em b/ld/emultempl/xtensaelf.em
index ed2945b850d..f06bcb97daa 100644
--- a/ld/emultempl/xtensaelf.em
+++ b/ld/emultempl/xtensaelf.em
@@ -66,7 +66,8 @@ static char *
 elf_xtensa_choose_target (int argc ATTRIBUTE_UNUSED,
 			  char **argv ATTRIBUTE_UNUSED)
 {
-  if (XCHAL_HAVE_BE)
+  if (command_line.endian == ENDIAN_BIG ||
+      (command_line.endian == ENDIAN_UNSET && XCHAL_HAVE_BE))
     return "${BIG_OUTPUT_FORMAT}";
   else
     return "${LITTLE_OUTPUT_FORMAT}";
@@ -343,27 +344,6 @@ elf_xtensa_before_allocation (void)
   xtensa_info_entries xtensa_info;
   asection *info_sec, *first_info_sec;
   bfd *first_bfd;
-  bool is_big_endian = XCHAL_HAVE_BE;
-
-  /* Check that the output endianness matches the Xtensa
-     configuration.  The BFD library always includes both big and
-     little endian target vectors for Xtensa, but it only supports the
-     detailed instruction encode/decode operations (such as are
-     required to process relocations) for the selected Xtensa
-     configuration.  */
-
-  if (is_big_endian
-      && link_info.output_bfd->xvec->byteorder == BFD_ENDIAN_LITTLE)
-    {
-      einfo (_("%F%P: little endian output does not match "
-	       "Xtensa configuration\n"));
-    }
-  if (!is_big_endian
-      && link_info.output_bfd->xvec->byteorder == BFD_ENDIAN_BIG)
-    {
-      einfo (_("%F%P: big endian output does not match "
-	       "Xtensa configuration\n"));
-    }
 
   /* Keep track of the first input .xtensa.info section, and as a fallback,
      the first input bfd where a .xtensa.info section could be created.
@@ -378,8 +358,7 @@ elf_xtensa_before_allocation (void)
 	 The merge_private_bfd_data hook has already reported any mismatches
 	 as errors, but those errors are not fatal.  At this point, we
 	 cannot go any further if there are any mismatches.  */
-      if ((is_big_endian && f->the_bfd->xvec->byteorder == BFD_ENDIAN_LITTLE)
-	  || (!is_big_endian && f->the_bfd->xvec->byteorder == BFD_ENDIAN_BIG))
+      if (link_info.output_bfd->xvec->byteorder != f->the_bfd->xvec->byteorder)
 	einfo (_("%F%P: cross-endian linking for %pB not supported\n"),
 	       f->the_bfd);
 
-- 
2.34.1


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH 4/5] gas: xtensa: add esp32, esp32s2, esp32s3 isa-modules options
  2022-10-22 12:51 [PATCH 0/5] Add Xtensa ESP chips support Alexey Lapshin
                   ` (2 preceding siblings ...)
  2022-10-22 12:56 ` [PATCH 3/5] ld: xtensa: use default LD command line options for endianness Alexey Lapshin
@ 2022-10-22 13:54 ` Alexey Lapshin
  2022-10-22 13:56 ` [PATCH 5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules Alexey Lapshin
  2022-10-25 19:13 ` [PATCH 0/5] Add Xtensa ESP chips support Max Filippov
  5 siblings, 0 replies; 14+ messages in thread
From: Alexey Lapshin @ 2022-10-22 13:54 UTC (permalink / raw)
  To: binutils; +Cc: Alexey Gerenkov, Ivan Grokhotkov, Anton Maklakov

Add Xtensa isa-modules for ESP chips.
The isa-module information writes into .xtensa.info section.

---
 bfd/Makefile.am                               |    10 +-
 bfd/Makefile.in                               |    15 +-
 bfd/configure                                 |     4 +-
 bfd/configure.ac                              |     4 +-
 bfd/elf32-xtensa.c                            |    22 +-
 ...nsa-modules.c => xtensa-default-modules.c} |     2 +-
 bfd/xtensa-esp32-modules.c                    | 19191 +++++++
 bfd/xtensa-esp32s2-modules.c                  | 11671 +++++
 bfd/xtensa-esp32s3-modules.c                  | 43674 ++++++++++++++++
 bfd/xtensa-isa.c                              |    25 +-
 gas/config/tc-xtensa.c                        |    21 +-
 include/elf/xtensa.h                          |     4 +
 include/xtensa-isa.h                          |     8 +
 ld/emultempl/xtensaelf.em                     |    30 +
 14 files changed, 74666 insertions(+), 15 deletions(-)
 rename bfd/{xtensa-modules.c => xtensa-default-modules.c} (99%)
 create mode 100644 bfd/xtensa-esp32-modules.c
 create mode 100644 bfd/xtensa-esp32s2-modules.c
 create mode 100644 bfd/xtensa-esp32s3-modules.c

diff --git a/bfd/Makefile.am b/bfd/Makefile.am
index 670e0598f55..699cad51e1e 100644
--- a/bfd/Makefile.am
+++ b/bfd/Makefile.am
@@ -392,7 +392,10 @@ BFD32_BACKENDS = \
 	xcofflink.lo \
 	xsym.lo \
 	xtensa-isa.lo \
-	xtensa-modules.lo
+	xtensa-default-modules.lo \
+	xtensa-esp32-modules.lo \
+	xtensa-esp32s2-modules.lo \
+	xtensa-esp32s3-modules.lo
 
 BFD32_BACKENDS_CFILES = \
 	aout-cris.c \
@@ -523,7 +526,10 @@ BFD32_BACKENDS_CFILES = \
 	xcofflink.c \
 	xsym.c \
 	xtensa-isa.c \
-	xtensa-modules.c
+	xtensa-default-modules.c \
+	xtensa-esp32-modules.c \
+	xtensa-esp32s2-modules.c \
+	xtensa-esp32s3-modules.c
 
 # The .o files needed by all of the 64 bit vectors that are configured into
 # target_vector in targets.c if configured with --enable-targets=all
diff --git a/bfd/Makefile.in b/bfd/Makefile.in
index a26f74d7199..67843f6019c 100644
--- a/bfd/Makefile.in
+++ b/bfd/Makefile.in
@@ -855,7 +855,10 @@ BFD32_BACKENDS = \
 	xcofflink.lo \
 	xsym.lo \
 	xtensa-isa.lo \
-	xtensa-modules.lo
+	xtensa-default-modules.lo \
+	xtensa-esp32-modules.lo \
+	xtensa-esp32s2-modules.lo \
+	xtensa-esp32s3-modules.lo
 
 BFD32_BACKENDS_CFILES = \
 	aout-cris.c \
@@ -986,7 +989,10 @@ BFD32_BACKENDS_CFILES = \
 	xcofflink.c \
 	xsym.c \
 	xtensa-isa.c \
-	xtensa-modules.c
+	xtensa-default-modules.c \
+	xtensa-esp32-modules.c \
+	xtensa-esp32s2-modules.c \
+	xtensa-esp32s3-modules.c
 
 
 # The .o files needed by all of the 64 bit vectors that are configured into
@@ -1732,7 +1738,10 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xcofflink.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xsym.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xtensa-isa.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xtensa-modules.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xtensa-default-modules.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xtensa-esp32-modules.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xtensa-esp32s2-modules.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xtensa-esp32s3-modules.Plo@am__quote@
 
 .c.o:
 @am__fastdepCC_TRUE@	$(AM_V_CC)$(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
diff --git a/bfd/configure b/bfd/configure
index 4f591b750d8..4e05ced623b 100755
--- a/bfd/configure
+++ b/bfd/configure
@@ -13615,8 +13615,8 @@ do
     x86_64_pei_vec)		 tb="$tb pei-x86_64.lo pex64igen.lo $coff"; target_size=64 ;;
     xgate_elf32_vec)		 tb="$tb elf32-xgate.lo elf32.lo $elf" ;;
     xstormy16_elf32_vec)	 tb="$tb elf32-xstormy16.lo elf32.lo $elf" ;;
-    xtensa_elf32_be_vec)	 tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
-    xtensa_elf32_le_vec)	 tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
+    xtensa_elf32_be_vec)	 tb="$tb xtensa-isa.lo xtensa-default-modules.lo xtensa-esp32-modules.lo xtensa-esp32s2-modules.lo xtensa-esp32s3-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
+    xtensa_elf32_le_vec)	 tb="$tb xtensa-isa.lo xtensa-default-modules.lo xtensa-esp32-modules.lo xtensa-esp32s2-modules.lo xtensa-esp32s3-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
     z80_coff_vec)		 tb="$tb coff-z80.lo reloc16.lo $coffgen" ;;
     z80_elf32_vec)		 tb="$tb elf32-z80.lo elf32.lo $elf" ;;
     z8k_coff_vec)		 tb="$tb coff-z8k.lo reloc16.lo $coff" ;;
diff --git a/bfd/configure.ac b/bfd/configure.ac
index 6146efb5ae3..ac4933f5e46 100644
--- a/bfd/configure.ac
+++ b/bfd/configure.ac
@@ -672,8 +672,8 @@ do
     x86_64_pei_vec)		 tb="$tb pei-x86_64.lo pex64igen.lo $coff"; target_size=64 ;;
     xgate_elf32_vec)		 tb="$tb elf32-xgate.lo elf32.lo $elf" ;;
     xstormy16_elf32_vec)	 tb="$tb elf32-xstormy16.lo elf32.lo $elf" ;;
-    xtensa_elf32_be_vec)	 tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
-    xtensa_elf32_le_vec)	 tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
+    xtensa_elf32_be_vec)	 tb="$tb xtensa-isa.lo xtensa-default-modules.lo xtensa-esp32-modules.lo xtensa-esp32s2-modules.lo xtensa-esp32s3-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
+    xtensa_elf32_le_vec)	 tb="$tb xtensa-isa.lo xtensa-default-modules.lo xtensa-esp32-modules.lo xtensa-esp32s2-modules.lo xtensa-esp32s3-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
     z80_coff_vec)		 tb="$tb coff-z80.lo reloc16.lo $coffgen" ;;
     z80_elf32_vec)		 tb="$tb elf32-z80.lo elf32.lo $elf" ;;
     z8k_coff_vec)		 tb="$tb coff-z8k.lo reloc16.lo $coff" ;;
diff --git a/bfd/elf32-xtensa.c b/bfd/elf32-xtensa.c
index 77ff4d63381..352a9e8df3c 100644
--- a/bfd/elf32-xtensa.c
+++ b/bfd/elf32-xtensa.c
@@ -2268,6 +2268,17 @@ int xtensa_abi_choice (void)
     return elf32xtensa_abi;
 }
 
+extern void *xtensa_modules;
+int xtensa_isa_module_choice (void)
+{
+  for (int i = 0; i < xtensa_isa_modules_count; i++)
+    {
+      if (xtensa_modules == xtensa_isa_modules[i].isa_module)
+        return i;
+    }
+  return 0;
+}
+
 /* Set up an entry in the procedure linkage table.  */
 
 static bfd_vma
@@ -11506,6 +11517,10 @@ xtensa_info_set_entry (char *key, int value, xtensa_info_entries *entries)
     {
       entries->use_absolute_literals = value;
     }
+  else if (! strcmp (key, "ISA_MODULE"))
+    {
+      entries->isa_module = value;
+    }
 }
 
 static bool
@@ -11563,6 +11578,7 @@ read_xtensa_info (bfd *abfd, asection *info_sec, xtensa_info_entries *entries)
   /* initialize values  */
   entries->abi = XSHAL_ABI;
   entries->use_absolute_literals = XSHAL_USE_ABSOLUTE_LITERALS;
+  entries->isa_module = -1;
 
   if (! bfd_get_section_contents (abfd, info_sec, data, 0, info_sec->size))
     {
@@ -11598,9 +11614,11 @@ fill_xtensa_info (char **data)
 {
   sprintf (*data,
            "USE_ABSOLUTE_LITERALS=%d\n"
-           "ABI=%d\n",
+           "ABI=%d\n"
+           "ISA_MODULE=%d\n",
            XSHAL_USE_ABSOLUTE_LITERALS,
-           xtensa_abi_choice ());
+           xtensa_abi_choice (),
+           xtensa_isa_module_choice ());
 }
 
 /* The default literal sections should always be marked as "code" (i.e.,
diff --git a/bfd/xtensa-modules.c b/bfd/xtensa-default-modules.c
similarity index 99%
rename from bfd/xtensa-modules.c
rename to bfd/xtensa-default-modules.c
index 1032f5be164..04a438946d5 100644
--- a/bfd/xtensa-modules.c
+++ b/bfd/xtensa-default-modules.c
@@ -20878,7 +20878,7 @@ length_decoder (const unsigned char *insn)
 \f
 /* Top-level ISA structure.  */
 
-xtensa_isa_internal xtensa_modules = {
+xtensa_isa_internal xtensa_default_modules = {
   0 /* little-endian */,
   8 /* insn_size */, 0,
   5, formats, format_decoder, length_decoder,
diff --git a/bfd/xtensa-esp32-modules.c b/bfd/xtensa-esp32-modules.c
new file mode 100644
index 00000000000..83c05874a5f
--- /dev/null
+++ b/bfd/xtensa-esp32-modules.c
@@ -0,0 +1,19191 @@
+/* Xtensa configuration-specific ISA information.
+
+   Copyright (c) 2003-2016 Tensilica Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+#include "ansidecl.h"
+#include <xtensa-isa.h>
+#include "xtensa-isa-internal.h"
+
+\f
+/* Sysregs.  */
+
+static xtensa_sysreg_internal sysregs[] = {
+  { "LBEG", 0, 0 },
+  { "LEND", 1, 0 },
+  { "LCOUNT", 2, 0 },
+  { "BR", 4, 0 },
+  { "ACCLO", 16, 0 },
+  { "ACCHI", 17, 0 },
+  { "M0", 32, 0 },
+  { "M1", 33, 0 },
+  { "M2", 34, 0 },
+  { "M3", 35, 0 },
+  { "MMID", 89, 0 },
+  { "DDR", 104, 0 },
+  { "CONFIGID0", 176, 0 },
+  { "CONFIGID1", 208, 0 },
+  { "INTERRUPT", 226, 0 },
+  { "INTCLEAR", 227, 0 },
+  { "CCOUNT", 234, 0 },
+  { "PRID", 235, 0 },
+  { "ICOUNT", 236, 0 },
+  { "CCOMPARE0", 240, 0 },
+  { "CCOMPARE1", 241, 0 },
+  { "CCOMPARE2", 242, 0 },
+  { "VECBASE", 231, 0 },
+  { "EPC1", 177, 0 },
+  { "EPC2", 178, 0 },
+  { "EPC3", 179, 0 },
+  { "EPC4", 180, 0 },
+  { "EPC5", 181, 0 },
+  { "EPC6", 182, 0 },
+  { "EPC7", 183, 0 },
+  { "EXCSAVE1", 209, 0 },
+  { "EXCSAVE2", 210, 0 },
+  { "EXCSAVE3", 211, 0 },
+  { "EXCSAVE4", 212, 0 },
+  { "EXCSAVE5", 213, 0 },
+  { "EXCSAVE6", 214, 0 },
+  { "EXCSAVE7", 215, 0 },
+  { "EPS2", 194, 0 },
+  { "EPS3", 195, 0 },
+  { "EPS4", 196, 0 },
+  { "EPS5", 197, 0 },
+  { "EPS6", 198, 0 },
+  { "EPS7", 199, 0 },
+  { "EXCCAUSE", 232, 0 },
+  { "DEPC", 192, 0 },
+  { "EXCVADDR", 238, 0 },
+  { "WINDOWBASE", 72, 0 },
+  { "WINDOWSTART", 73, 0 },
+  { "MEMCTL", 97, 0 },
+  { "SAR", 3, 0 },
+  { "PS", 230, 0 },
+  { "MISC0", 244, 0 },
+  { "MISC1", 245, 0 },
+  { "MISC2", 246, 0 },
+  { "MISC3", 247, 0 },
+  { "INTENABLE", 228, 0 },
+  { "DBREAKA0", 144, 0 },
+  { "DBREAKC0", 160, 0 },
+  { "DBREAKA1", 145, 0 },
+  { "DBREAKC1", 161, 0 },
+  { "IBREAKA0", 128, 0 },
+  { "IBREAKA1", 129, 0 },
+  { "IBREAKENABLE", 96, 0 },
+  { "ICOUNTLEVEL", 237, 0 },
+  { "DEBUGCAUSE", 233, 0 },
+  { "CPENABLE", 224, 0 },
+  { "SCOMPARE1", 12, 0 },
+  { "ATOMCTL", 99, 0 },
+  { "THREADPTR", 231, 1 },
+  { "F64R_LO", 234, 1 },
+  { "F64R_HI", 235, 1 },
+  { "F64S", 236, 1 },
+  { "FCR", 232, 1 },
+  { "FSR", 233, 1 },
+  { "EXPSTATE", 230, 1 }
+};
+
+#define NUM_SYSREGS 75
+#define MAX_SPECIAL_REG 247
+#define MAX_USER_REG 236
+
+\f
+/* Processor states.  */
+
+static xtensa_state_internal states[] = {
+  { "LCOUNT", 32, 0 },
+  { "PC", 32, 0 },
+  { "ICOUNT", 32, 0 },
+  { "DDR", 32, 0 },
+  { "INTERRUPT", 32, 0 },
+  { "CCOUNT", 32, 0 },
+  { "XTSYNC", 1, 0 },
+  { "VECBASE", 22, 0 },
+  { "EPC1", 32, 0 },
+  { "EPC2", 32, 0 },
+  { "EPC3", 32, 0 },
+  { "EPC4", 32, 0 },
+  { "EPC5", 32, 0 },
+  { "EPC6", 32, 0 },
+  { "EPC7", 32, 0 },
+  { "EXCSAVE1", 32, 0 },
+  { "EXCSAVE2", 32, 0 },
+  { "EXCSAVE3", 32, 0 },
+  { "EXCSAVE4", 32, 0 },
+  { "EXCSAVE5", 32, 0 },
+  { "EXCSAVE6", 32, 0 },
+  { "EXCSAVE7", 32, 0 },
+  { "EPS2", 13, 0 },
+  { "EPS3", 13, 0 },
+  { "EPS4", 13, 0 },
+  { "EPS5", 13, 0 },
+  { "EPS6", 13, 0 },
+  { "EPS7", 13, 0 },
+  { "EXCCAUSE", 6, 0 },
+  { "PSINTLEVEL", 4, 0 },
+  { "PSUM", 1, 0 },
+  { "PSWOE", 1, 0 },
+  { "PSEXCM", 1, 0 },
+  { "DEPC", 32, 0 },
+  { "EXCVADDR", 32, 0 },
+  { "WindowBase", 4, 0 },
+  { "WindowStart", 16, 0 },
+  { "PSCALLINC", 2, 0 },
+  { "PSOWB", 4, 0 },
+  { "LBEG", 32, 0 },
+  { "LEND", 32, 0 },
+  { "MEMCTL", 1, 0 },
+  { "SAR", 6, 0 },
+  { "THREADPTR", 32, 0 },
+  { "MISC0", 32, 0 },
+  { "MISC1", 32, 0 },
+  { "MISC2", 32, 0 },
+  { "MISC3", 32, 0 },
+  { "ACC", 40, 0 },
+  { "InOCDMode", 1, 0 },
+  { "INTENABLE", 32, 0 },
+  { "DBREAKA0", 32, 0 },
+  { "DBREAKC0", 8, 0 },
+  { "DBREAKA1", 32, 0 },
+  { "DBREAKC1", 8, 0 },
+  { "IBREAKA0", 32, 0 },
+  { "IBREAKA1", 32, 0 },
+  { "IBREAKENABLE", 2, 0 },
+  { "ICOUNTLEVEL", 4, 0 },
+  { "DEBUGCAUSE", 6, 0 },
+  { "DBNUM", 4, 0 },
+  { "CCOMPARE0", 32, 0 },
+  { "CCOMPARE1", 32, 0 },
+  { "CCOMPARE2", 32, 0 },
+  { "CPENABLE", 8, 0 },
+  { "SCOMPARE1", 32, 0 },
+  { "ATOMCTL", 6, 0 },
+  { "ERI_RAW_INTERLOCK", 1, 0 },
+  { "F64R", 64, 0 },
+  { "F64S", 32, 0 },
+  { "RoundMode", 2, 0 },
+  { "InvalidEnable", 1, 0 },
+  { "DivZeroEnable", 1, 0 },
+  { "OverflowEnable", 1, 0 },
+  { "UnderflowEnable", 1, 0 },
+  { "InexactEnable", 1, 0 },
+  { "InvalidFlag", 1, XTENSA_STATE_IS_SHARED_OR },
+  { "DivZeroFlag", 1, XTENSA_STATE_IS_SHARED_OR },
+  { "OverflowFlag", 1, XTENSA_STATE_IS_SHARED_OR },
+  { "UnderflowFlag", 1, XTENSA_STATE_IS_SHARED_OR },
+  { "InexactFlag", 1, XTENSA_STATE_IS_SHARED_OR },
+  { "FPreserved20", 20, 0 },
+  { "FPreserved20a", 20, 0 },
+  { "FPreserved5", 5, 0 },
+  { "FPreserved7", 7, 0 },
+  { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }
+};
+
+#define NUM_STATES 86
+
+enum xtensa_state_id {
+  STATE_LCOUNT,
+  STATE_PC,
+  STATE_ICOUNT,
+  STATE_DDR,
+  STATE_INTERRUPT,
+  STATE_CCOUNT,
+  STATE_XTSYNC,
+  STATE_VECBASE,
+  STATE_EPC1,
+  STATE_EPC2,
+  STATE_EPC3,
+  STATE_EPC4,
+  STATE_EPC5,
+  STATE_EPC6,
+  STATE_EPC7,
+  STATE_EXCSAVE1,
+  STATE_EXCSAVE2,
+  STATE_EXCSAVE3,
+  STATE_EXCSAVE4,
+  STATE_EXCSAVE5,
+  STATE_EXCSAVE6,
+  STATE_EXCSAVE7,
+  STATE_EPS2,
+  STATE_EPS3,
+  STATE_EPS4,
+  STATE_EPS5,
+  STATE_EPS6,
+  STATE_EPS7,
+  STATE_EXCCAUSE,
+  STATE_PSINTLEVEL,
+  STATE_PSUM,
+  STATE_PSWOE,
+  STATE_PSEXCM,
+  STATE_DEPC,
+  STATE_EXCVADDR,
+  STATE_WindowBase,
+  STATE_WindowStart,
+  STATE_PSCALLINC,
+  STATE_PSOWB,
+  STATE_LBEG,
+  STATE_LEND,
+  STATE_MEMCTL,
+  STATE_SAR,
+  STATE_THREADPTR,
+  STATE_MISC0,
+  STATE_MISC1,
+  STATE_MISC2,
+  STATE_MISC3,
+  STATE_ACC,
+  STATE_InOCDMode,
+  STATE_INTENABLE,
+  STATE_DBREAKA0,
+  STATE_DBREAKC0,
+  STATE_DBREAKA1,
+  STATE_DBREAKC1,
+  STATE_IBREAKA0,
+  STATE_IBREAKA1,
+  STATE_IBREAKENABLE,
+  STATE_ICOUNTLEVEL,
+  STATE_DEBUGCAUSE,
+  STATE_DBNUM,
+  STATE_CCOMPARE0,
+  STATE_CCOMPARE1,
+  STATE_CCOMPARE2,
+  STATE_CPENABLE,
+  STATE_SCOMPARE1,
+  STATE_ATOMCTL,
+  STATE_ERI_RAW_INTERLOCK,
+  STATE_F64R,
+  STATE_F64S,
+  STATE_RoundMode,
+  STATE_InvalidEnable,
+  STATE_DivZeroEnable,
+  STATE_OverflowEnable,
+  STATE_UnderflowEnable,
+  STATE_InexactEnable,
+  STATE_InvalidFlag,
+  STATE_DivZeroFlag,
+  STATE_OverflowFlag,
+  STATE_UnderflowFlag,
+  STATE_InexactFlag,
+  STATE_FPreserved20,
+  STATE_FPreserved20a,
+  STATE_FPreserved5,
+  STATE_FPreserved7,
+  STATE_EXPSTATE
+};
+
+\f
+/* Field definitions.  */
+
+static unsigned
+Field_r_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+  return tie_t;
+}
+
+static void
+Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
+  return tie_t;
+}
+
+static void
+Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
+}
+
+static unsigned
+Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+  return tie_t;
+}
+
+static void
+Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_t_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_s_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_n_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+  return tie_t;
+}
+
+static void
+Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_m_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+  return tie_t;
+}
+
+static void
+Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+  tie_t = (val << 24) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_st_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+  tie_t = (val << 24) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+  return tie_t;
+}
+
+static void
+Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+  return tie_t;
+}
+
+static void
+Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+  return tie_t;
+}
+
+static void
+Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_w_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
+  return tie_t;
+}
+
+static void
+Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
+}
+
+static unsigned
+Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+  return tie_t;
+}
+
+static void
+Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_dfp_fld_op2_3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_op2_3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_dfp_fld_op1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_dfp_fld_op2_3_2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_op2_3_2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22);
+}
+
+static unsigned
+Field_dfp_fld_r_3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_r_3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_dfp_fld_op2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
+}
+
+static unsigned
+Field_dfp_fld_op2_3_1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_op2_3_1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21);
+}
+
+static unsigned
+Field_dfp_fld_s_3_1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_s_3_1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_dfp_fld_r_3_1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_r_3_1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
+}
+
+static unsigned
+Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+  return tie_t;
+}
+
+static void
+Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+  return tie_t;
+}
+
+static void
+Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+  return tie_t;
+}
+
+static void
+Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+  return tie_t;
+}
+
+static void
+Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+  return tie_t;
+}
+
+static void
+Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+  return tie_t;
+}
+
+static void
+Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+  tie_t = (val << 27) >> 31;
+  insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
+  return tie_t;
+}
+
+static void
+Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 20) >> 20;
+  insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
+  return tie_t;
+}
+
+static void
+Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 24) >> 24;
+  insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
+  return tie_t;
+}
+
+static void
+Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 24) >> 24;
+  insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
+  tie_t = (val << 20) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
+  return tie_t;
+}
+
+static void
+Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 16) >> 16;
+  insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
+}
+
+static unsigned
+Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
+  return tie_t;
+}
+
+static void
+Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 14) >> 14;
+  insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+  return tie_t;
+}
+
+static void
+Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+  return tie_t;
+}
+
+static void
+Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+  tie_t = (val << 27) >> 31;
+  insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+  tie_t = (val << 27) >> 31;
+  insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+  tie_t = (val << 27) >> 31;
+  insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+  return tie_t;
+}
+
+static void
+Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+  tie_t = (val << 27) >> 31;
+  insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+  tie_t = (val << 24) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+  tie_t = (val << 24) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+  tie_t = (val << 24) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+  tie_t = (val << 24) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+  return tie_t;
+}
+
+static void
+Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+  tie_t = (val << 28) >> 30;
+  insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+  return tie_t;
+}
+
+static void
+Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+  return tie_t;
+}
+
+static void
+Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+  return tie_t;
+}
+
+static void
+Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+  return tie_t;
+}
+
+static void
+Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+  return tie_t;
+}
+
+static void
+Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+  return tie_t;
+}
+
+static void
+Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+  tie_t = (val << 26) >> 30;
+  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+  tie_t = (val << 26) >> 30;
+  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+  tie_t = (val << 25) >> 29;
+  insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+  tie_t = (val << 25) >> 29;
+  insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
+  return tie_t;
+}
+
+static void
+Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
+}
+
+static unsigned
+Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+  return tie_t;
+}
+
+static void
+Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_y_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+  return tie_t;
+}
+
+static void
+Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_x_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
+  return tie_t;
+}
+
+static void
+Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
+}
+
+static unsigned
+Field_t2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+  return tie_t;
+}
+
+static void
+Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+  return tie_t;
+}
+
+static void
+Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+  return tie_t;
+}
+
+static void
+Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_s2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+  return tie_t;
+}
+
+static void
+Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+  return tie_t;
+}
+
+static void
+Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+  return tie_t;
+}
+
+static void
+Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_r2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
+  return tie_t;
+}
+
+static void
+Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
+}
+
+static unsigned
+Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
+  return tie_t;
+}
+
+static void
+Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
+}
+
+static unsigned
+Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
+  return tie_t;
+}
+
+static void
+Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
+}
+
+static unsigned
+Field_t4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+  return tie_t;
+}
+
+static void
+Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+  return tie_t;
+}
+
+static void
+Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+  return tie_t;
+}
+
+static void
+Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_s4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
+  return tie_t;
+}
+
+static void
+Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
+}
+
+static unsigned
+Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
+  return tie_t;
+}
+
+static void
+Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
+}
+
+static unsigned
+Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
+  return tie_t;
+}
+
+static void
+Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
+}
+
+static unsigned
+Field_r4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+  return tie_t;
+}
+
+static void
+Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+  return tie_t;
+}
+
+static void
+Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+  return tie_t;
+}
+
+static void
+Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_t8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+  return tie_t;
+}
+
+static void
+Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+  return tie_t;
+}
+
+static void
+Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+  return tie_t;
+}
+
+static void
+Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_s8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
+  return tie_t;
+}
+
+static void
+Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
+}
+
+static unsigned
+Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
+  return tie_t;
+}
+
+static void
+Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
+}
+
+static unsigned
+Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
+  return tie_t;
+}
+
+static void
+Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
+}
+
+static unsigned
+Field_r8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
+  return tie_t;
+}
+
+static void
+Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 17) >> 17;
+  insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
+  return tie_t;
+}
+
+static void
+Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 14) >> 14;
+  insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_dfp_fld_r_0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_r_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_dfp_fld_r_0_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_r_0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_dfp_fld_r_0_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_r_0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_dfp_fld_r_2_1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_r_2_1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x6000) | (tie_t << 13);
+}
+
+static unsigned
+Field_dfp_fld_r_2_1_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_r_2_1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x6000) | (tie_t << 13);
+}
+
+static unsigned
+Field_dfp_fld_r_2_1_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_r_2_1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x6000) | (tie_t << 13);
+}
+
+static unsigned
+Field_dfp_fld_r_3_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_r_3_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_dfp_fld_r_3_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_r_3_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_dfp_fld_r_3_1_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_r_3_1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
+}
+
+static unsigned
+Field_dfp_fld_r_3_1_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_r_3_1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
+}
+
+static unsigned
+Field_dfp_fld_s_0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_s_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_dfp_fld_s_0_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_s_0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_dfp_fld_s_0_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_s_0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_dfp_fld_s_3_1_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_s_3_1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_dfp_fld_s_3_1_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_s_3_1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_dfp_fld_op2_0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_op2_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_dfp_fld_op2_1_0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_op2_1_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_dfp_fld_op2_2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31);
+  return tie_t;
+}
+
+static void
+Field_dfp_fld_op2_2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x400000) | (tie_t << 22);
+}
+
+static unsigned
+Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+  tie_t = (val << 27) >> 31;
+  insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+  tie_t = (val << 27) >> 31;
+  insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+  tie_t = (val << 27) >> 31;
+  insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+  return tie_t;
+}
+
+static void
+Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+  return tie_t;
+}
+
+static void
+Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static void
+Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
+		    uint32 val ATTRIBUTE_UNUSED)
+{
+  /* Do nothing.  */
+}
+
+static unsigned
+Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static unsigned
+Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 4;
+}
+
+static unsigned
+Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 8;
+}
+
+static unsigned
+Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 12;
+}
+
+static unsigned
+Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static unsigned
+Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 1;
+}
+
+static unsigned
+Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 2;
+}
+
+static unsigned
+Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 3;
+}
+
+static unsigned
+Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static unsigned
+Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static unsigned
+Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static unsigned
+Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+enum xtensa_field_id {
+  FIELD_t,
+  FIELD_bbi4,
+  FIELD_bbi,
+  FIELD_imm12,
+  FIELD_imm8,
+  FIELD_s,
+  FIELD_imm12b,
+  FIELD_imm16,
+  FIELD_m,
+  FIELD_n,
+  FIELD_offset,
+  FIELD_op0,
+  FIELD_op1,
+  FIELD_op2,
+  FIELD_r,
+  FIELD_sa4,
+  FIELD_sae4,
+  FIELD_sae,
+  FIELD_sal,
+  FIELD_sargt,
+  FIELD_sas4,
+  FIELD_sas,
+  FIELD_sr,
+  FIELD_st,
+  FIELD_thi3,
+  FIELD_imm4,
+  FIELD_mn,
+  FIELD_i,
+  FIELD_imm6lo,
+  FIELD_imm6hi,
+  FIELD_imm7lo,
+  FIELD_imm7hi,
+  FIELD_z,
+  FIELD_imm6,
+  FIELD_imm7,
+  FIELD_r3,
+  FIELD_rbit2,
+  FIELD_rhi,
+  FIELD_t3,
+  FIELD_tbit2,
+  FIELD_tlo,
+  FIELD_w,
+  FIELD_y,
+  FIELD_x,
+  FIELD_t2,
+  FIELD_s2,
+  FIELD_r2,
+  FIELD_t4,
+  FIELD_s4,
+  FIELD_r4,
+  FIELD_t8,
+  FIELD_s8,
+  FIELD_r8,
+  FIELD_xt_wbr15_imm,
+  FIELD_xt_wbr18_imm,
+  FIELD_dfp_fld_op1,
+  FIELD_dfp_fld_op2,
+  FIELD_dfp_fld_r_0,
+  FIELD_dfp_fld_r_2_1,
+  FIELD_dfp_fld_r_3,
+  FIELD_dfp_fld_r_3_1,
+  FIELD_dfp_fld_s_0,
+  FIELD_dfp_fld_s_3_1,
+  FIELD_dfp_fld_op2_0,
+  FIELD_dfp_fld_op2_1_0,
+  FIELD_dfp_fld_op2_2,
+  FIELD_dfp_fld_op2_3,
+  FIELD_dfp_fld_op2_3_2,
+  FIELD_dfp_fld_op2_3_1,
+  FIELD_bitindex,
+  FIELD_s3to1,
+  FIELD__ar0,
+  FIELD__ar4,
+  FIELD__ar8,
+  FIELD__ar12,
+  FIELD__mr0,
+  FIELD__mr1,
+  FIELD__mr2,
+  FIELD__mr3,
+  FIELD__bt16,
+  FIELD__bs16,
+  FIELD__br16,
+  FIELD__brall
+};
+
+\f
+/* Functional units.  */
+
+#define funcUnits 0
+
+\f
+/* Register files.  */
+
+enum xtensa_regfile_id {
+  REGFILE_AR,
+  REGFILE_MR,
+  REGFILE_BR,
+  REGFILE_FR,
+  REGFILE_BR2,
+  REGFILE_BR4,
+  REGFILE_BR8,
+  REGFILE_BR16
+};
+
+static xtensa_regfile_internal regfiles[] = {
+  { "AR", "a", REGFILE_AR, 32, 64 },
+  { "MR", "m", REGFILE_MR, 32, 4 },
+  { "BR", "b", REGFILE_BR, 1, 16 },
+  { "FR", "f", REGFILE_FR, 32, 16 },
+  { "BR2", "b", REGFILE_BR, 2, 8 },
+  { "BR4", "b", REGFILE_BR, 4, 4 },
+  { "BR8", "b", REGFILE_BR, 8, 2 },
+  { "BR16", "b", REGFILE_BR, 16, 1 }
+};
+
+\f
+/* Interfaces.  */
+
+static xtensa_interface_internal interfaces[] = {
+  { "ERI_RD_Out", 14, 0, 0, 'o' },
+  { "ERI_RD_In", 32, 0, 1, 'i' },
+  { "ERI_RD_Rdy", 1, 0, 0, 'i' },
+  { "ERI_WR_Out", 46, 0, 2, 'o' },
+  { "ERI_WR_In", 1, 0, 3, 'i' },
+  { "IMPWIRE", 32, 0, 4, 'i' }
+};
+
+enum xtensa_interface_id {
+  INTERFACE_ERI_RD_Out,
+  INTERFACE_ERI_RD_In,
+  INTERFACE_ERI_RD_Rdy,
+  INTERFACE_ERI_WR_Out,
+  INTERFACE_ERI_WR_In,
+  INTERFACE_IMPWIRE
+};
+
+
+/* Constant tables.  */
+
+/* constant table ai4c */
+static const unsigned CONST_TBL_ai4c_0[] = {
+  0xffffffff,
+  0x1,
+  0x2,
+  0x3,
+  0x4,
+  0x5,
+  0x6,
+  0x7,
+  0x8,
+  0x9,
+  0xa,
+  0xb,
+  0xc,
+  0xd,
+  0xe,
+  0xf,
+  0
+};
+
+/* constant table b4c */
+static const unsigned CONST_TBL_b4c_0[] = {
+  0xffffffff,
+  0x1,
+  0x2,
+  0x3,
+  0x4,
+  0x5,
+  0x6,
+  0x7,
+  0x8,
+  0xa,
+  0xc,
+  0x10,
+  0x20,
+  0x40,
+  0x80,
+  0x100,
+  0
+};
+
+/* constant table b4cu */
+static const unsigned CONST_TBL_b4cu_0[] = {
+  0x8000,
+  0x10000,
+  0x2,
+  0x3,
+  0x4,
+  0x5,
+  0x6,
+  0x7,
+  0x8,
+  0xa,
+  0xc,
+  0x10,
+  0x20,
+  0x40,
+  0x80,
+  0x100,
+  0
+};
+
+/* constant table RECIP_Data8 */
+static const unsigned CONST_TBL_RECIP_Data8_0[] = {
+  0xff & 0xff,
+  0xfd & 0xff,
+  0xfb & 0xff,
+  0xf9 & 0xff,
+  0xf7 & 0xff,
+  0xf5 & 0xff,
+  0xf4 & 0xff,
+  0xf2 & 0xff,
+  0xf0 & 0xff,
+  0xee & 0xff,
+  0xed & 0xff,
+  0xeb & 0xff,
+  0xe9 & 0xff,
+  0xe8 & 0xff,
+  0xe6 & 0xff,
+  0xe4 & 0xff,
+  0xe3 & 0xff,
+  0xe1 & 0xff,
+  0xe0 & 0xff,
+  0xde & 0xff,
+  0xdd & 0xff,
+  0xdb & 0xff,
+  0xda & 0xff,
+  0xd8 & 0xff,
+  0xd7 & 0xff,
+  0xd5 & 0xff,
+  0xd4 & 0xff,
+  0xd3 & 0xff,
+  0xd1 & 0xff,
+  0xd0 & 0xff,
+  0xcf & 0xff,
+  0xcd & 0xff,
+  0xcc & 0xff,
+  0xcb & 0xff,
+  0xca & 0xff,
+  0xc8 & 0xff,
+  0xc7 & 0xff,
+  0xc6 & 0xff,
+  0xc5 & 0xff,
+  0xc4 & 0xff,
+  0xc2 & 0xff,
+  0xc1 & 0xff,
+  0xc0 & 0xff,
+  0xbf & 0xff,
+  0xbe & 0xff,
+  0xbd & 0xff,
+  0xbc & 0xff,
+  0xbb & 0xff,
+  0xba & 0xff,
+  0xb9 & 0xff,
+  0xb8 & 0xff,
+  0xb7 & 0xff,
+  0xb6 & 0xff,
+  0xb5 & 0xff,
+  0xb4 & 0xff,
+  0xb3 & 0xff,
+  0xb2 & 0xff,
+  0xb1 & 0xff,
+  0xb0 & 0xff,
+  0xaf & 0xff,
+  0xae & 0xff,
+  0xad & 0xff,
+  0xac & 0xff,
+  0xab & 0xff,
+  0xaa & 0xff,
+  0xa9 & 0xff,
+  0xa8 & 0xff,
+  0xa8 & 0xff,
+  0xa7 & 0xff,
+  0xa6 & 0xff,
+  0xa5 & 0xff,
+  0xa4 & 0xff,
+  0xa3 & 0xff,
+  0xa3 & 0xff,
+  0xa2 & 0xff,
+  0xa1 & 0xff,
+  0xa0 & 0xff,
+  0x9f & 0xff,
+  0x9f & 0xff,
+  0x9e & 0xff,
+  0x9d & 0xff,
+  0x9c & 0xff,
+  0x9c & 0xff,
+  0x9b & 0xff,
+  0x9a & 0xff,
+  0x99 & 0xff,
+  0x99 & 0xff,
+  0x98 & 0xff,
+  0x97 & 0xff,
+  0x97 & 0xff,
+  0x96 & 0xff,
+  0x95 & 0xff,
+  0x95 & 0xff,
+  0x94 & 0xff,
+  0x93 & 0xff,
+  0x93 & 0xff,
+  0x92 & 0xff,
+  0x91 & 0xff,
+  0x91 & 0xff,
+  0x90 & 0xff,
+  0x8f & 0xff,
+  0x8f & 0xff,
+  0x8e & 0xff,
+  0x8e & 0xff,
+  0x8d & 0xff,
+  0x8c & 0xff,
+  0x8c & 0xff,
+  0x8b & 0xff,
+  0x8b & 0xff,
+  0x8a & 0xff,
+  0x89 & 0xff,
+  0x89 & 0xff,
+  0x88 & 0xff,
+  0x88 & 0xff,
+  0x87 & 0xff,
+  0x87 & 0xff,
+  0x86 & 0xff,
+  0x85 & 0xff,
+  0x85 & 0xff,
+  0x84 & 0xff,
+  0x84 & 0xff,
+  0x83 & 0xff,
+  0x83 & 0xff,
+  0x82 & 0xff,
+  0x82 & 0xff,
+  0x81 & 0xff,
+  0x81 & 0xff,
+  0x81 & 0xff,
+  0
+};
+
+/* constant table RSQRT_Data8 */
+static const unsigned CONST_TBL_RSQRT_Data8_0[] = {
+  0xb4 & 0xff,
+  0xb3 & 0xff,
+  0xb2 & 0xff,
+  0xb0 & 0xff,
+  0xaf & 0xff,
+  0xae & 0xff,
+  0xac & 0xff,
+  0xab & 0xff,
+  0xaa & 0xff,
+  0xa9 & 0xff,
+  0xa8 & 0xff,
+  0xa7 & 0xff,
+  0xa6 & 0xff,
+  0xa5 & 0xff,
+  0xa3 & 0xff,
+  0xa2 & 0xff,
+  0xa1 & 0xff,
+  0xa0 & 0xff,
+  0x9f & 0xff,
+  0x9e & 0xff,
+  0x9e & 0xff,
+  0x9d & 0xff,
+  0x9c & 0xff,
+  0x9b & 0xff,
+  0x9a & 0xff,
+  0x99 & 0xff,
+  0x98 & 0xff,
+  0x97 & 0xff,
+  0x97 & 0xff,
+  0x96 & 0xff,
+  0x95 & 0xff,
+  0x94 & 0xff,
+  0x93 & 0xff,
+  0x93 & 0xff,
+  0x92 & 0xff,
+  0x91 & 0xff,
+  0x90 & 0xff,
+  0x90 & 0xff,
+  0x8f & 0xff,
+  0x8e & 0xff,
+  0x8e & 0xff,
+  0x8d & 0xff,
+  0x8c & 0xff,
+  0x8c & 0xff,
+  0x8b & 0xff,
+  0x8a & 0xff,
+  0x8a & 0xff,
+  0x89 & 0xff,
+  0x89 & 0xff,
+  0x88 & 0xff,
+  0x87 & 0xff,
+  0x87 & 0xff,
+  0x86 & 0xff,
+  0x86 & 0xff,
+  0x85 & 0xff,
+  0x84 & 0xff,
+  0x84 & 0xff,
+  0x83 & 0xff,
+  0x83 & 0xff,
+  0x82 & 0xff,
+  0x82 & 0xff,
+  0x81 & 0xff,
+  0x81 & 0xff,
+  0x80 & 0xff,
+  0xff & 0xff,
+  0xfd & 0xff,
+  0xfb & 0xff,
+  0xf9 & 0xff,
+  0xf7 & 0xff,
+  0xf6 & 0xff,
+  0xf4 & 0xff,
+  0xf2 & 0xff,
+  0xf1 & 0xff,
+  0xef & 0xff,
+  0xed & 0xff,
+  0xec & 0xff,
+  0xea & 0xff,
+  0xe9 & 0xff,
+  0xe7 & 0xff,
+  0xe6 & 0xff,
+  0xe4 & 0xff,
+  0xe3 & 0xff,
+  0xe1 & 0xff,
+  0xe0 & 0xff,
+  0xdf & 0xff,
+  0xdd & 0xff,
+  0xdc & 0xff,
+  0xdb & 0xff,
+  0xda & 0xff,
+  0xd8 & 0xff,
+  0xd7 & 0xff,
+  0xd6 & 0xff,
+  0xd5 & 0xff,
+  0xd4 & 0xff,
+  0xd3 & 0xff,
+  0xd2 & 0xff,
+  0xd0 & 0xff,
+  0xcf & 0xff,
+  0xce & 0xff,
+  0xcd & 0xff,
+  0xcc & 0xff,
+  0xcb & 0xff,
+  0xca & 0xff,
+  0xc9 & 0xff,
+  0xc8 & 0xff,
+  0xc7 & 0xff,
+  0xc6 & 0xff,
+  0xc6 & 0xff,
+  0xc5 & 0xff,
+  0xc4 & 0xff,
+  0xc3 & 0xff,
+  0xc2 & 0xff,
+  0xc1 & 0xff,
+  0xc0 & 0xff,
+  0xbf & 0xff,
+  0xbf & 0xff,
+  0xbe & 0xff,
+  0xbd & 0xff,
+  0xbc & 0xff,
+  0xbb & 0xff,
+  0xbb & 0xff,
+  0xba & 0xff,
+  0xb9 & 0xff,
+  0xb8 & 0xff,
+  0xb8 & 0xff,
+  0xb7 & 0xff,
+  0xb6 & 0xff,
+  0xb5 & 0xff,
+  0
+};
+
+/* constant table RECIP_Data10_2 */
+static const unsigned CONST_TBL_RECIP_Data10_2_0[] = {
+  0x3fc & 0x3ff,
+  0x3f4 & 0x3ff,
+  0x3ec & 0x3ff,
+  0x3e5 & 0x3ff,
+  0x3dd & 0x3ff,
+  0x3d6 & 0x3ff,
+  0x3cf & 0x3ff,
+  0x3c7 & 0x3ff,
+  0x3c0 & 0x3ff,
+  0x3b9 & 0x3ff,
+  0x3b2 & 0x3ff,
+  0x3ac & 0x3ff,
+  0x3a5 & 0x3ff,
+  0x39e & 0x3ff,
+  0x398 & 0x3ff,
+  0x391 & 0x3ff,
+  0x38b & 0x3ff,
+  0x385 & 0x3ff,
+  0x37f & 0x3ff,
+  0x378 & 0x3ff,
+  0x373 & 0x3ff,
+  0x36c & 0x3ff,
+  0x367 & 0x3ff,
+  0x361 & 0x3ff,
+  0x35c & 0x3ff,
+  0x356 & 0x3ff,
+  0x350 & 0x3ff,
+  0x34b & 0x3ff,
+  0x345 & 0x3ff,
+  0x340 & 0x3ff,
+  0x33b & 0x3ff,
+  0x335 & 0x3ff,
+  0x330 & 0x3ff,
+  0x32c & 0x3ff,
+  0x327 & 0x3ff,
+  0x322 & 0x3ff,
+  0x31c & 0x3ff,
+  0x318 & 0x3ff,
+  0x314 & 0x3ff,
+  0x30e & 0x3ff,
+  0x30a & 0x3ff,
+  0x306 & 0x3ff,
+  0x300 & 0x3ff,
+  0x2fc & 0x3ff,
+  0x2f8 & 0x3ff,
+  0x2f4 & 0x3ff,
+  0x2f0 & 0x3ff,
+  0x2ea & 0x3ff,
+  0x2e6 & 0x3ff,
+  0x2e2 & 0x3ff,
+  0x2de & 0x3ff,
+  0x2da & 0x3ff,
+  0x2d6 & 0x3ff,
+  0x2d2 & 0x3ff,
+  0x2ce & 0x3ff,
+  0x2ca & 0x3ff,
+  0x2c6 & 0x3ff,
+  0x2c2 & 0x3ff,
+  0x2be & 0x3ff,
+  0x2ba & 0x3ff,
+  0x2b8 & 0x3ff,
+  0x2b4 & 0x3ff,
+  0x2b0 & 0x3ff,
+  0x2ac & 0x3ff,
+  0x2a8 & 0x3ff,
+  0x2a6 & 0x3ff,
+  0x2a2 & 0x3ff,
+  0x29e & 0x3ff,
+  0x29c & 0x3ff,
+  0x298 & 0x3ff,
+  0x294 & 0x3ff,
+  0x290 & 0x3ff,
+  0x28e & 0x3ff,
+  0x28a & 0x3ff,
+  0x288 & 0x3ff,
+  0x284 & 0x3ff,
+  0x280 & 0x3ff,
+  0x27e & 0x3ff,
+  0x27a & 0x3ff,
+  0x278 & 0x3ff,
+  0x274 & 0x3ff,
+  0x272 & 0x3ff,
+  0x26e & 0x3ff,
+  0x26c & 0x3ff,
+  0x268 & 0x3ff,
+  0x266 & 0x3ff,
+  0x264 & 0x3ff,
+  0x260 & 0x3ff,
+  0x25e & 0x3ff,
+  0x25a & 0x3ff,
+  0x258 & 0x3ff,
+  0x254 & 0x3ff,
+  0x252 & 0x3ff,
+  0x250 & 0x3ff,
+  0x24c & 0x3ff,
+  0x24a & 0x3ff,
+  0x248 & 0x3ff,
+  0x246 & 0x3ff,
+  0x242 & 0x3ff,
+  0x240 & 0x3ff,
+  0x23e & 0x3ff,
+  0x23c & 0x3ff,
+  0x238 & 0x3ff,
+  0x236 & 0x3ff,
+  0x234 & 0x3ff,
+  0x232 & 0x3ff,
+  0x230 & 0x3ff,
+  0x22c & 0x3ff,
+  0x22a & 0x3ff,
+  0x228 & 0x3ff,
+  0x226 & 0x3ff,
+  0x224 & 0x3ff,
+  0x220 & 0x3ff,
+  0x21e & 0x3ff,
+  0x21c & 0x3ff,
+  0x21a & 0x3ff,
+  0x218 & 0x3ff,
+  0x216 & 0x3ff,
+  0x214 & 0x3ff,
+  0x212 & 0x3ff,
+  0x210 & 0x3ff,
+  0x20e & 0x3ff,
+  0x20c & 0x3ff,
+  0x208 & 0x3ff,
+  0x208 & 0x3ff,
+  0x204 & 0x3ff,
+  0x204 & 0x3ff,
+  0x201 & 0x3ff,
+  0
+};
+
+/* constant table RSQRT_10b_256 */
+static const unsigned CONST_TBL_RSQRT_10b_256_0[] = {
+  0x1a5 & 0x3ff,
+  0x1a0 & 0x3ff,
+  0x19a & 0x3ff,
+  0x195 & 0x3ff,
+  0x18f & 0x3ff,
+  0x18a & 0x3ff,
+  0x185 & 0x3ff,
+  0x180 & 0x3ff,
+  0x17a & 0x3ff,
+  0x175 & 0x3ff,
+  0x170 & 0x3ff,
+  0x16b & 0x3ff,
+  0x166 & 0x3ff,
+  0x161 & 0x3ff,
+  0x15d & 0x3ff,
+  0x158 & 0x3ff,
+  0x153 & 0x3ff,
+  0x14e & 0x3ff,
+  0x14a & 0x3ff,
+  0x145 & 0x3ff,
+  0x140 & 0x3ff,
+  0x13c & 0x3ff,
+  0x138 & 0x3ff,
+  0x133 & 0x3ff,
+  0x12f & 0x3ff,
+  0x12a & 0x3ff,
+  0x126 & 0x3ff,
+  0x122 & 0x3ff,
+  0x11e & 0x3ff,
+  0x11a & 0x3ff,
+  0x115 & 0x3ff,
+  0x111 & 0x3ff,
+  0x10d & 0x3ff,
+  0x109 & 0x3ff,
+  0x105 & 0x3ff,
+  0x101 & 0x3ff,
+  0xfd & 0x3ff,
+  0xfa & 0x3ff,
+  0xf6 & 0x3ff,
+  0xf2 & 0x3ff,
+  0xee & 0x3ff,
+  0xea & 0x3ff,
+  0xe7 & 0x3ff,
+  0xe3 & 0x3ff,
+  0xdf & 0x3ff,
+  0xdc & 0x3ff,
+  0xd8 & 0x3ff,
+  0xd5 & 0x3ff,
+  0xd1 & 0x3ff,
+  0xce & 0x3ff,
+  0xca & 0x3ff,
+  0xc7 & 0x3ff,
+  0xc3 & 0x3ff,
+  0xc0 & 0x3ff,
+  0xbd & 0x3ff,
+  0xb9 & 0x3ff,
+  0xb6 & 0x3ff,
+  0xb3 & 0x3ff,
+  0xb0 & 0x3ff,
+  0xad & 0x3ff,
+  0xa9 & 0x3ff,
+  0xa6 & 0x3ff,
+  0xa3 & 0x3ff,
+  0xa0 & 0x3ff,
+  0x9d & 0x3ff,
+  0x9a & 0x3ff,
+  0x97 & 0x3ff,
+  0x94 & 0x3ff,
+  0x91 & 0x3ff,
+  0x8e & 0x3ff,
+  0x8b & 0x3ff,
+  0x88 & 0x3ff,
+  0x85 & 0x3ff,
+  0x82 & 0x3ff,
+  0x7f & 0x3ff,
+  0x7d & 0x3ff,
+  0x7a & 0x3ff,
+  0x77 & 0x3ff,
+  0x74 & 0x3ff,
+  0x71 & 0x3ff,
+  0x6f & 0x3ff,
+  0x6c & 0x3ff,
+  0x69 & 0x3ff,
+  0x67 & 0x3ff,
+  0x64 & 0x3ff,
+  0x61 & 0x3ff,
+  0x5f & 0x3ff,
+  0x5c & 0x3ff,
+  0x5a & 0x3ff,
+  0x57 & 0x3ff,
+  0x54 & 0x3ff,
+  0x52 & 0x3ff,
+  0x4f & 0x3ff,
+  0x4d & 0x3ff,
+  0x4a & 0x3ff,
+  0x48 & 0x3ff,
+  0x45 & 0x3ff,
+  0x43 & 0x3ff,
+  0x41 & 0x3ff,
+  0x3e & 0x3ff,
+  0x3c & 0x3ff,
+  0x3a & 0x3ff,
+  0x37 & 0x3ff,
+  0x35 & 0x3ff,
+  0x33 & 0x3ff,
+  0x30 & 0x3ff,
+  0x2e & 0x3ff,
+  0x2c & 0x3ff,
+  0x29 & 0x3ff,
+  0x27 & 0x3ff,
+  0x25 & 0x3ff,
+  0x23 & 0x3ff,
+  0x20 & 0x3ff,
+  0x1e & 0x3ff,
+  0x1c & 0x3ff,
+  0x1a & 0x3ff,
+  0x18 & 0x3ff,
+  0x16 & 0x3ff,
+  0x14 & 0x3ff,
+  0x11 & 0x3ff,
+  0xf & 0x3ff,
+  0xd & 0x3ff,
+  0xb & 0x3ff,
+  0x9 & 0x3ff,
+  0x7 & 0x3ff,
+  0x5 & 0x3ff,
+  0x3 & 0x3ff,
+  0x1 & 0x3ff,
+  0x3fc & 0x3ff,
+  0x3f4 & 0x3ff,
+  0x3ec & 0x3ff,
+  0x3e5 & 0x3ff,
+  0x3dd & 0x3ff,
+  0x3d5 & 0x3ff,
+  0x3ce & 0x3ff,
+  0x3c7 & 0x3ff,
+  0x3bf & 0x3ff,
+  0x3b8 & 0x3ff,
+  0x3b1 & 0x3ff,
+  0x3aa & 0x3ff,
+  0x3a3 & 0x3ff,
+  0x39c & 0x3ff,
+  0x395 & 0x3ff,
+  0x38e & 0x3ff,
+  0x388 & 0x3ff,
+  0x381 & 0x3ff,
+  0x37a & 0x3ff,
+  0x374 & 0x3ff,
+  0x36d & 0x3ff,
+  0x367 & 0x3ff,
+  0x361 & 0x3ff,
+  0x35a & 0x3ff,
+  0x354 & 0x3ff,
+  0x34e & 0x3ff,
+  0x348 & 0x3ff,
+  0x342 & 0x3ff,
+  0x33c & 0x3ff,
+  0x336 & 0x3ff,
+  0x330 & 0x3ff,
+  0x32b & 0x3ff,
+  0x325 & 0x3ff,
+  0x31f & 0x3ff,
+  0x31a & 0x3ff,
+  0x314 & 0x3ff,
+  0x30f & 0x3ff,
+  0x309 & 0x3ff,
+  0x304 & 0x3ff,
+  0x2fe & 0x3ff,
+  0x2f9 & 0x3ff,
+  0x2f4 & 0x3ff,
+  0x2ee & 0x3ff,
+  0x2e9 & 0x3ff,
+  0x2e4 & 0x3ff,
+  0x2df & 0x3ff,
+  0x2da & 0x3ff,
+  0x2d5 & 0x3ff,
+  0x2d0 & 0x3ff,
+  0x2cb & 0x3ff,
+  0x2c6 & 0x3ff,
+  0x2c1 & 0x3ff,
+  0x2bd & 0x3ff,
+  0x2b8 & 0x3ff,
+  0x2b3 & 0x3ff,
+  0x2ae & 0x3ff,
+  0x2aa & 0x3ff,
+  0x2a5 & 0x3ff,
+  0x2a1 & 0x3ff,
+  0x29c & 0x3ff,
+  0x298 & 0x3ff,
+  0x293 & 0x3ff,
+  0x28f & 0x3ff,
+  0x28a & 0x3ff,
+  0x286 & 0x3ff,
+  0x282 & 0x3ff,
+  0x27d & 0x3ff,
+  0x279 & 0x3ff,
+  0x275 & 0x3ff,
+  0x271 & 0x3ff,
+  0x26d & 0x3ff,
+  0x268 & 0x3ff,
+  0x264 & 0x3ff,
+  0x260 & 0x3ff,
+  0x25c & 0x3ff,
+  0x258 & 0x3ff,
+  0x254 & 0x3ff,
+  0x250 & 0x3ff,
+  0x24c & 0x3ff,
+  0x249 & 0x3ff,
+  0x245 & 0x3ff,
+  0x241 & 0x3ff,
+  0x23d & 0x3ff,
+  0x239 & 0x3ff,
+  0x235 & 0x3ff,
+  0x232 & 0x3ff,
+  0x22e & 0x3ff,
+  0x22a & 0x3ff,
+  0x227 & 0x3ff,
+  0x223 & 0x3ff,
+  0x220 & 0x3ff,
+  0x21c & 0x3ff,
+  0x218 & 0x3ff,
+  0x215 & 0x3ff,
+  0x211 & 0x3ff,
+  0x20e & 0x3ff,
+  0x20a & 0x3ff,
+  0x207 & 0x3ff,
+  0x204 & 0x3ff,
+  0x200 & 0x3ff,
+  0x1fd & 0x3ff,
+  0x1f9 & 0x3ff,
+  0x1f6 & 0x3ff,
+  0x1f3 & 0x3ff,
+  0x1f0 & 0x3ff,
+  0x1ec & 0x3ff,
+  0x1e9 & 0x3ff,
+  0x1e6 & 0x3ff,
+  0x1e3 & 0x3ff,
+  0x1df & 0x3ff,
+  0x1dc & 0x3ff,
+  0x1d9 & 0x3ff,
+  0x1d6 & 0x3ff,
+  0x1d3 & 0x3ff,
+  0x1d0 & 0x3ff,
+  0x1cd & 0x3ff,
+  0x1ca & 0x3ff,
+  0x1c7 & 0x3ff,
+  0x1c4 & 0x3ff,
+  0x1c1 & 0x3ff,
+  0x1be & 0x3ff,
+  0x1bb & 0x3ff,
+  0x1b8 & 0x3ff,
+  0x1b5 & 0x3ff,
+  0x1b2 & 0x3ff,
+  0x1af & 0x3ff,
+  0x1ac & 0x3ff,
+  0x1aa & 0x3ff,
+  0
+};
+
+/* constant table RECIP_10b_256 */
+static const unsigned CONST_TBL_RECIP_10b_256_0[] = {
+  0x3fc & 0x3ff,
+  0x3f4 & 0x3ff,
+  0x3ec & 0x3ff,
+  0x3e4 & 0x3ff,
+  0x3dd & 0x3ff,
+  0x3d5 & 0x3ff,
+  0x3cd & 0x3ff,
+  0x3c6 & 0x3ff,
+  0x3be & 0x3ff,
+  0x3b7 & 0x3ff,
+  0x3af & 0x3ff,
+  0x3a8 & 0x3ff,
+  0x3a1 & 0x3ff,
+  0x399 & 0x3ff,
+  0x392 & 0x3ff,
+  0x38b & 0x3ff,
+  0x384 & 0x3ff,
+  0x37d & 0x3ff,
+  0x376 & 0x3ff,
+  0x36f & 0x3ff,
+  0x368 & 0x3ff,
+  0x361 & 0x3ff,
+  0x35b & 0x3ff,
+  0x354 & 0x3ff,
+  0x34d & 0x3ff,
+  0x346 & 0x3ff,
+  0x340 & 0x3ff,
+  0x339 & 0x3ff,
+  0x333 & 0x3ff,
+  0x32c & 0x3ff,
+  0x326 & 0x3ff,
+  0x320 & 0x3ff,
+  0x319 & 0x3ff,
+  0x313 & 0x3ff,
+  0x30d & 0x3ff,
+  0x307 & 0x3ff,
+  0x300 & 0x3ff,
+  0x2fa & 0x3ff,
+  0x2f4 & 0x3ff,
+  0x2ee & 0x3ff,
+  0x2e8 & 0x3ff,
+  0x2e2 & 0x3ff,
+  0x2dc & 0x3ff,
+  0x2d7 & 0x3ff,
+  0x2d1 & 0x3ff,
+  0x2cb & 0x3ff,
+  0x2c5 & 0x3ff,
+  0x2bf & 0x3ff,
+  0x2ba & 0x3ff,
+  0x2b4 & 0x3ff,
+  0x2af & 0x3ff,
+  0x2a9 & 0x3ff,
+  0x2a3 & 0x3ff,
+  0x29e & 0x3ff,
+  0x299 & 0x3ff,
+  0x293 & 0x3ff,
+  0x28e & 0x3ff,
+  0x288 & 0x3ff,
+  0x283 & 0x3ff,
+  0x27e & 0x3ff,
+  0x279 & 0x3ff,
+  0x273 & 0x3ff,
+  0x26e & 0x3ff,
+  0x269 & 0x3ff,
+  0x264 & 0x3ff,
+  0x25f & 0x3ff,
+  0x25a & 0x3ff,
+  0x255 & 0x3ff,
+  0x250 & 0x3ff,
+  0x24b & 0x3ff,
+  0x246 & 0x3ff,
+  0x241 & 0x3ff,
+  0x23c & 0x3ff,
+  0x237 & 0x3ff,
+  0x232 & 0x3ff,
+  0x22e & 0x3ff,
+  0x229 & 0x3ff,
+  0x224 & 0x3ff,
+  0x21f & 0x3ff,
+  0x21b & 0x3ff,
+  0x216 & 0x3ff,
+  0x211 & 0x3ff,
+  0x20d & 0x3ff,
+  0x208 & 0x3ff,
+  0x204 & 0x3ff,
+  0x1ff & 0x3ff,
+  0x1fb & 0x3ff,
+  0x1f6 & 0x3ff,
+  0x1f2 & 0x3ff,
+  0x1ed & 0x3ff,
+  0x1e9 & 0x3ff,
+  0x1e5 & 0x3ff,
+  0x1e0 & 0x3ff,
+  0x1dc & 0x3ff,
+  0x1d8 & 0x3ff,
+  0x1d4 & 0x3ff,
+  0x1cf & 0x3ff,
+  0x1cb & 0x3ff,
+  0x1c7 & 0x3ff,
+  0x1c3 & 0x3ff,
+  0x1bf & 0x3ff,
+  0x1bb & 0x3ff,
+  0x1b6 & 0x3ff,
+  0x1b2 & 0x3ff,
+  0x1ae & 0x3ff,
+  0x1aa & 0x3ff,
+  0x1a6 & 0x3ff,
+  0x1a2 & 0x3ff,
+  0x19e & 0x3ff,
+  0x19a & 0x3ff,
+  0x197 & 0x3ff,
+  0x193 & 0x3ff,
+  0x18f & 0x3ff,
+  0x18b & 0x3ff,
+  0x187 & 0x3ff,
+  0x183 & 0x3ff,
+  0x17f & 0x3ff,
+  0x17c & 0x3ff,
+  0x178 & 0x3ff,
+  0x174 & 0x3ff,
+  0x171 & 0x3ff,
+  0x16d & 0x3ff,
+  0x169 & 0x3ff,
+  0x166 & 0x3ff,
+  0x162 & 0x3ff,
+  0x15e & 0x3ff,
+  0x15b & 0x3ff,
+  0x157 & 0x3ff,
+  0x154 & 0x3ff,
+  0x150 & 0x3ff,
+  0x14d & 0x3ff,
+  0x149 & 0x3ff,
+  0x146 & 0x3ff,
+  0x142 & 0x3ff,
+  0x13f & 0x3ff,
+  0x13b & 0x3ff,
+  0x138 & 0x3ff,
+  0x134 & 0x3ff,
+  0x131 & 0x3ff,
+  0x12e & 0x3ff,
+  0x12a & 0x3ff,
+  0x127 & 0x3ff,
+  0x124 & 0x3ff,
+  0x120 & 0x3ff,
+  0x11d & 0x3ff,
+  0x11a & 0x3ff,
+  0x117 & 0x3ff,
+  0x113 & 0x3ff,
+  0x110 & 0x3ff,
+  0x10d & 0x3ff,
+  0x10a & 0x3ff,
+  0x107 & 0x3ff,
+  0x103 & 0x3ff,
+  0x100 & 0x3ff,
+  0xfd & 0x3ff,
+  0xfa & 0x3ff,
+  0xf7 & 0x3ff,
+  0xf4 & 0x3ff,
+  0xf1 & 0x3ff,
+  0xee & 0x3ff,
+  0xeb & 0x3ff,
+  0xe8 & 0x3ff,
+  0xe5 & 0x3ff,
+  0xe2 & 0x3ff,
+  0xdf & 0x3ff,
+  0xdc & 0x3ff,
+  0xd9 & 0x3ff,
+  0xd6 & 0x3ff,
+  0xd3 & 0x3ff,
+  0xd0 & 0x3ff,
+  0xcd & 0x3ff,
+  0xca & 0x3ff,
+  0xc8 & 0x3ff,
+  0xc5 & 0x3ff,
+  0xc2 & 0x3ff,
+  0xbf & 0x3ff,
+  0xbc & 0x3ff,
+  0xb9 & 0x3ff,
+  0xb7 & 0x3ff,
+  0xb4 & 0x3ff,
+  0xb1 & 0x3ff,
+  0xae & 0x3ff,
+  0xac & 0x3ff,
+  0xa9 & 0x3ff,
+  0xa6 & 0x3ff,
+  0xa4 & 0x3ff,
+  0xa1 & 0x3ff,
+  0x9e & 0x3ff,
+  0x9c & 0x3ff,
+  0x99 & 0x3ff,
+  0x96 & 0x3ff,
+  0x94 & 0x3ff,
+  0x91 & 0x3ff,
+  0x8e & 0x3ff,
+  0x8c & 0x3ff,
+  0x89 & 0x3ff,
+  0x87 & 0x3ff,
+  0x84 & 0x3ff,
+  0x82 & 0x3ff,
+  0x7f & 0x3ff,
+  0x7c & 0x3ff,
+  0x7a & 0x3ff,
+  0x77 & 0x3ff,
+  0x75 & 0x3ff,
+  0x73 & 0x3ff,
+  0x70 & 0x3ff,
+  0x6e & 0x3ff,
+  0x6b & 0x3ff,
+  0x69 & 0x3ff,
+  0x66 & 0x3ff,
+  0x64 & 0x3ff,
+  0x61 & 0x3ff,
+  0x5f & 0x3ff,
+  0x5d & 0x3ff,
+  0x5a & 0x3ff,
+  0x58 & 0x3ff,
+  0x56 & 0x3ff,
+  0x53 & 0x3ff,
+  0x51 & 0x3ff,
+  0x4f & 0x3ff,
+  0x4c & 0x3ff,
+  0x4a & 0x3ff,
+  0x48 & 0x3ff,
+  0x45 & 0x3ff,
+  0x43 & 0x3ff,
+  0x41 & 0x3ff,
+  0x3f & 0x3ff,
+  0x3c & 0x3ff,
+  0x3a & 0x3ff,
+  0x38 & 0x3ff,
+  0x36 & 0x3ff,
+  0x33 & 0x3ff,
+  0x31 & 0x3ff,
+  0x2f & 0x3ff,
+  0x2d & 0x3ff,
+  0x2b & 0x3ff,
+  0x29 & 0x3ff,
+  0x26 & 0x3ff,
+  0x24 & 0x3ff,
+  0x22 & 0x3ff,
+  0x20 & 0x3ff,
+  0x1e & 0x3ff,
+  0x1c & 0x3ff,
+  0x1a & 0x3ff,
+  0x18 & 0x3ff,
+  0x15 & 0x3ff,
+  0x13 & 0x3ff,
+  0x11 & 0x3ff,
+  0xf & 0x3ff,
+  0xd & 0x3ff,
+  0xb & 0x3ff,
+  0x9 & 0x3ff,
+  0x7 & 0x3ff,
+  0x5 & 0x3ff,
+  0x3 & 0x3ff,
+  0x1 & 0x3ff,
+  0
+};
+
+\f
+/* Instruction operands.  */
+
+static int
+OperandSem_opnd_sem_MR_0_decode (uint32 *valp)
+{
+  *valp += 2;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_0_encode (uint32 *valp)
+{
+  int error;
+  error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
+  *valp = *valp & 1;
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp)
+{
+  unsigned soffsetx4_out_0;
+  unsigned soffsetx4_in_0;
+  soffsetx4_in_0 = *valp & 0x3ffff;
+  soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
+  *valp = soffsetx4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp)
+{
+  unsigned soffsetx4_in_0;
+  unsigned soffsetx4_out_0;
+  soffsetx4_out_0 = *valp;
+  soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
+  *valp = soffsetx4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp)
+{
+  unsigned uimm12x8_out_0;
+  unsigned uimm12x8_in_0;
+  uimm12x8_in_0 = *valp & 0xfff;
+  uimm12x8_out_0 = uimm12x8_in_0 << 3;
+  *valp = uimm12x8_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp)
+{
+  unsigned uimm12x8_in_0;
+  unsigned uimm12x8_out_0;
+  uimm12x8_out_0 = *valp;
+  uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
+  *valp = uimm12x8_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm4_decode (uint32 *valp)
+{
+  unsigned simm4_out_0;
+  unsigned simm4_in_0;
+  simm4_in_0 = *valp & 0xf;
+  simm4_out_0 = ((int) simm4_in_0 << 28) >> 28;
+  *valp = simm4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm4_encode (uint32 *valp)
+{
+  unsigned simm4_in_0;
+  unsigned simm4_out_0;
+  simm4_out_0 = *valp;
+  simm4_in_0 = (simm4_out_0 & 0xf);
+  *valp = simm4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 64);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_0_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 64);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_1_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 64);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_2_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 64);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_3_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 64);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_4_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 64);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_immrx4_decode (uint32 *valp)
+{
+  unsigned immrx4_out_0;
+  unsigned immrx4_in_0;
+  immrx4_in_0 = *valp & 0xf;
+  immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
+  *valp = immrx4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_immrx4_encode (uint32 *valp)
+{
+  unsigned immrx4_in_0;
+  unsigned immrx4_out_0;
+  immrx4_out_0 = *valp;
+  immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
+  *valp = immrx4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp)
+{
+  unsigned lsi4x4_out_0;
+  unsigned lsi4x4_in_0;
+  lsi4x4_in_0 = *valp & 0xf;
+  lsi4x4_out_0 = lsi4x4_in_0 << 2;
+  *valp = lsi4x4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp)
+{
+  unsigned lsi4x4_in_0;
+  unsigned lsi4x4_out_0;
+  lsi4x4_out_0 = *valp;
+  lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
+  *valp = lsi4x4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm7_decode (uint32 *valp)
+{
+  unsigned simm7_out_0;
+  unsigned simm7_in_0;
+  simm7_in_0 = *valp & 0x7f;
+  simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0;
+  *valp = simm7_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm7_encode (uint32 *valp)
+{
+  unsigned simm7_in_0;
+  unsigned simm7_out_0;
+  simm7_out_0 = *valp;
+  simm7_in_0 = (simm7_out_0 & 0x7f);
+  *valp = simm7_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm6_decode (uint32 *valp)
+{
+  unsigned uimm6_out_0;
+  unsigned uimm6_in_0;
+  uimm6_in_0 = *valp & 0x3f;
+  uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
+  *valp = uimm6_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm6_encode (uint32 *valp)
+{
+  unsigned uimm6_in_0;
+  unsigned uimm6_out_0;
+  uimm6_out_0 = *valp;
+  uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
+  *valp = uimm6_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_ai4const_decode (uint32 *valp)
+{
+  unsigned ai4const_out_0;
+  unsigned ai4const_in_0;
+  ai4const_in_0 = *valp & 0xf;
+  ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
+  *valp = ai4const_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_ai4const_encode (uint32 *valp)
+{
+  unsigned ai4const_in_0;
+  unsigned ai4const_out_0;
+  ai4const_out_0 = *valp;
+  switch (ai4const_out_0)
+    {
+    case 0xffffffff: ai4const_in_0 = 0; break;
+    case 0x1: ai4const_in_0 = 0x1; break;
+    case 0x2: ai4const_in_0 = 0x2; break;
+    case 0x3: ai4const_in_0 = 0x3; break;
+    case 0x4: ai4const_in_0 = 0x4; break;
+    case 0x5: ai4const_in_0 = 0x5; break;
+    case 0x6: ai4const_in_0 = 0x6; break;
+    case 0x7: ai4const_in_0 = 0x7; break;
+    case 0x8: ai4const_in_0 = 0x8; break;
+    case 0x9: ai4const_in_0 = 0x9; break;
+    case 0xa: ai4const_in_0 = 0xa; break;
+    case 0xb: ai4const_in_0 = 0xb; break;
+    case 0xc: ai4const_in_0 = 0xc; break;
+    case 0xd: ai4const_in_0 = 0xd; break;
+    case 0xe: ai4const_in_0 = 0xe; break;
+    default: ai4const_in_0 = 0xf; break;
+    }
+  *valp = ai4const_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4const_decode (uint32 *valp)
+{
+  unsigned b4const_out_0;
+  unsigned b4const_in_0;
+  b4const_in_0 = *valp & 0xf;
+  b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
+  *valp = b4const_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4const_encode (uint32 *valp)
+{
+  unsigned b4const_in_0;
+  unsigned b4const_out_0;
+  b4const_out_0 = *valp;
+  switch (b4const_out_0)
+    {
+    case 0xffffffff: b4const_in_0 = 0; break;
+    case 0x1: b4const_in_0 = 0x1; break;
+    case 0x2: b4const_in_0 = 0x2; break;
+    case 0x3: b4const_in_0 = 0x3; break;
+    case 0x4: b4const_in_0 = 0x4; break;
+    case 0x5: b4const_in_0 = 0x5; break;
+    case 0x6: b4const_in_0 = 0x6; break;
+    case 0x7: b4const_in_0 = 0x7; break;
+    case 0x8: b4const_in_0 = 0x8; break;
+    case 0xa: b4const_in_0 = 0x9; break;
+    case 0xc: b4const_in_0 = 0xa; break;
+    case 0x10: b4const_in_0 = 0xb; break;
+    case 0x20: b4const_in_0 = 0xc; break;
+    case 0x40: b4const_in_0 = 0xd; break;
+    case 0x80: b4const_in_0 = 0xe; break;
+    default: b4const_in_0 = 0xf; break;
+    }
+  *valp = b4const_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4constu_decode (uint32 *valp)
+{
+  unsigned b4constu_out_0;
+  unsigned b4constu_in_0;
+  b4constu_in_0 = *valp & 0xf;
+  b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
+  *valp = b4constu_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4constu_encode (uint32 *valp)
+{
+  unsigned b4constu_in_0;
+  unsigned b4constu_out_0;
+  b4constu_out_0 = *valp;
+  switch (b4constu_out_0)
+    {
+    case 0x8000: b4constu_in_0 = 0; break;
+    case 0x10000: b4constu_in_0 = 0x1; break;
+    case 0x2: b4constu_in_0 = 0x2; break;
+    case 0x3: b4constu_in_0 = 0x3; break;
+    case 0x4: b4constu_in_0 = 0x4; break;
+    case 0x5: b4constu_in_0 = 0x5; break;
+    case 0x6: b4constu_in_0 = 0x6; break;
+    case 0x7: b4constu_in_0 = 0x7; break;
+    case 0x8: b4constu_in_0 = 0x8; break;
+    case 0xa: b4constu_in_0 = 0x9; break;
+    case 0xc: b4constu_in_0 = 0xa; break;
+    case 0x10: b4constu_in_0 = 0xb; break;
+    case 0x20: b4constu_in_0 = 0xc; break;
+    case 0x40: b4constu_in_0 = 0xd; break;
+    case 0x80: b4constu_in_0 = 0xe; break;
+    default: b4constu_in_0 = 0xf; break;
+    }
+  *valp = b4constu_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8_decode (uint32 *valp)
+{
+  unsigned uimm8_out_0;
+  unsigned uimm8_in_0;
+  uimm8_in_0 = *valp & 0xff;
+  uimm8_out_0 = uimm8_in_0;
+  *valp = uimm8_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8_encode (uint32 *valp)
+{
+  unsigned uimm8_in_0;
+  unsigned uimm8_out_0;
+  uimm8_out_0 = *valp;
+  uimm8_in_0 = (uimm8_out_0 & 0xff);
+  *valp = uimm8_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp)
+{
+  unsigned uimm8x2_out_0;
+  unsigned uimm8x2_in_0;
+  uimm8x2_in_0 = *valp & 0xff;
+  uimm8x2_out_0 = uimm8x2_in_0 << 1;
+  *valp = uimm8x2_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp)
+{
+  unsigned uimm8x2_in_0;
+  unsigned uimm8x2_out_0;
+  uimm8x2_out_0 = *valp;
+  uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
+  *valp = uimm8x2_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp)
+{
+  unsigned uimm8x4_out_0;
+  unsigned uimm8x4_in_0;
+  uimm8x4_in_0 = *valp & 0xff;
+  uimm8x4_out_0 = uimm8x4_in_0 << 2;
+  *valp = uimm8x4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp)
+{
+  unsigned uimm8x4_in_0;
+  unsigned uimm8x4_out_0;
+  uimm8x4_out_0 = *valp;
+  uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
+  *valp = uimm8x4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp)
+{
+  unsigned uimm4x16_out_0;
+  unsigned uimm4x16_in_0;
+  uimm4x16_in_0 = *valp & 0xf;
+  uimm4x16_out_0 = uimm4x16_in_0 << 4;
+  *valp = uimm4x16_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp)
+{
+  unsigned uimm4x16_in_0;
+  unsigned uimm4x16_out_0;
+  uimm4x16_out_0 = *valp;
+  uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
+  *valp = uimm4x16_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8_decode (uint32 *valp)
+{
+  unsigned simm8_out_0;
+  unsigned simm8_in_0;
+  simm8_in_0 = *valp & 0xff;
+  simm8_out_0 = ((int) simm8_in_0 << 24) >> 24;
+  *valp = simm8_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8_encode (uint32 *valp)
+{
+  unsigned simm8_in_0;
+  unsigned simm8_out_0;
+  simm8_out_0 = *valp;
+  simm8_in_0 = (simm8_out_0 & 0xff);
+  *valp = simm8_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8x256_decode (uint32 *valp)
+{
+  unsigned simm8x256_out_0;
+  unsigned simm8x256_in_0;
+  simm8x256_in_0 = *valp & 0xff;
+  simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8;
+  *valp = simm8x256_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8x256_encode (uint32 *valp)
+{
+  unsigned simm8x256_in_0;
+  unsigned simm8x256_out_0;
+  simm8x256_out_0 = *valp;
+  simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
+  *valp = simm8x256_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm12b_decode (uint32 *valp)
+{
+  unsigned simm12b_out_0;
+  unsigned simm12b_in_0;
+  simm12b_in_0 = *valp & 0xfff;
+  simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20;
+  *valp = simm12b_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm12b_encode (uint32 *valp)
+{
+  unsigned simm12b_in_0;
+  unsigned simm12b_out_0;
+  simm12b_out_0 = *valp;
+  simm12b_in_0 = (simm12b_out_0 & 0xfff);
+  *valp = simm12b_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_msalp32_decode (uint32 *valp)
+{
+  unsigned msalp32_out_0;
+  unsigned msalp32_in_0;
+  msalp32_in_0 = *valp & 0x1f;
+  msalp32_out_0 = 0x20 - msalp32_in_0;
+  *valp = msalp32_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_msalp32_encode (uint32 *valp)
+{
+  unsigned msalp32_in_0;
+  unsigned msalp32_out_0;
+  msalp32_out_0 = *valp;
+  msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
+  *valp = msalp32_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_op2p1_decode (uint32 *valp)
+{
+  unsigned op2p1_out_0;
+  unsigned op2p1_in_0;
+  op2p1_in_0 = *valp & 0xf;
+  op2p1_out_0 = op2p1_in_0 + 0x1;
+  *valp = op2p1_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_op2p1_encode (uint32 *valp)
+{
+  unsigned op2p1_in_0;
+  unsigned op2p1_out_0;
+  op2p1_out_0 = *valp;
+  op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
+  *valp = op2p1_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_label8_decode (uint32 *valp)
+{
+  unsigned label8_out_0;
+  unsigned label8_in_0;
+  label8_in_0 = *valp & 0xff;
+  label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
+  *valp = label8_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_label8_encode (uint32 *valp)
+{
+  unsigned label8_in_0;
+  unsigned label8_out_0;
+  label8_out_0 = *valp;
+  label8_in_0 = (label8_out_0 - 0x4) & 0xff;
+  *valp = label8_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_ulabel8_decode (uint32 *valp)
+{
+  unsigned ulabel8_out_0;
+  unsigned ulabel8_in_0;
+  ulabel8_in_0 = *valp & 0xff;
+  ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0);
+  *valp = ulabel8_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_ulabel8_encode (uint32 *valp)
+{
+  unsigned ulabel8_in_0;
+  unsigned ulabel8_out_0;
+  ulabel8_out_0 = *valp;
+  ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff;
+  *valp = ulabel8_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_label12_decode (uint32 *valp)
+{
+  unsigned label12_out_0;
+  unsigned label12_in_0;
+  label12_in_0 = *valp & 0xfff;
+  label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
+  *valp = label12_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_label12_encode (uint32 *valp)
+{
+  unsigned label12_in_0;
+  unsigned label12_out_0;
+  label12_out_0 = *valp;
+  label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
+  *valp = label12_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffset_decode (uint32 *valp)
+{
+  unsigned soffset_out_0;
+  unsigned soffset_in_0;
+  soffset_in_0 = *valp & 0x3ffff;
+  soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
+  *valp = soffset_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffset_encode (uint32 *valp)
+{
+  unsigned soffset_in_0;
+  unsigned soffset_out_0;
+  soffset_out_0 = *valp;
+  soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
+  *valp = soffset_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp)
+{
+  unsigned uimm16x4_out_0;
+  unsigned uimm16x4_in_0;
+  uimm16x4_in_0 = *valp & 0xffff;
+  uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
+  *valp = uimm16x4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp)
+{
+  unsigned uimm16x4_in_0;
+  unsigned uimm16x4_out_0;
+  uimm16x4_out_0 = *valp;
+  uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
+  *valp = uimm16x4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_bbi_decode (uint32 *valp)
+{
+  unsigned bbi_out_0;
+  unsigned bbi_in_0;
+  bbi_in_0 = *valp & 0x1f;
+  bbi_out_0 = (0 << 5) | bbi_in_0;
+  *valp = bbi_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_bbi_encode (uint32 *valp)
+{
+  unsigned bbi_in_0;
+  unsigned bbi_out_0;
+  bbi_out_0 = *valp;
+  bbi_in_0 = (bbi_out_0 & 0x1f);
+  *valp = bbi_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_s_decode (uint32 *valp)
+{
+  unsigned s_out_0;
+  unsigned s_in_0;
+  s_in_0 = *valp & 0xf;
+  s_out_0 = (0 << 4) | s_in_0;
+  *valp = s_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_s_encode (uint32 *valp)
+{
+  unsigned s_in_0;
+  unsigned s_out_0;
+  s_out_0 = *valp;
+  s_in_0 = (s_out_0 & 0xf);
+  *valp = s_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 4);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_MR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_1_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 4);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_MR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_2_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 4);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_MR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_3_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 4);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_MR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_4_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 4);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_MR_5_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_5_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 4);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_immt_decode (uint32 *valp)
+{
+  unsigned immt_out_0;
+  unsigned immt_in_0;
+  immt_in_0 = *valp & 0xf;
+  immt_out_0 = immt_in_0;
+  *valp = immt_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_immt_encode (uint32 *valp)
+{
+  unsigned immt_in_0;
+  unsigned immt_out_0;
+  immt_out_0 = *valp;
+  immt_in_0 = immt_out_0 & 0xf;
+  *valp = immt_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 16);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_BR2_decode (uint32 *valp)
+{
+  *valp = *valp << 1;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR2_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 16) || ((*valp & 1) != 0);
+  *valp = *valp >> 1;
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_BR4_decode (uint32 *valp)
+{
+  *valp = *valp << 2;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR4_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 16) || ((*valp & 3) != 0);
+  *valp = *valp >> 2;
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_BR8_decode (uint32 *valp)
+{
+  *valp = *valp << 3;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR8_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 16) || ((*valp & 7) != 0);
+  *valp = *valp >> 3;
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_BR16_decode (uint32 *valp)
+{
+  *valp = *valp << 4;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR16_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 16) || ((*valp & 15) != 0);
+  *valp = *valp >> 4;
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_tp7_decode (uint32 *valp)
+{
+  unsigned tp7_out_0;
+  unsigned tp7_in_0;
+  tp7_in_0 = *valp & 0xf;
+  tp7_out_0 = tp7_in_0 + 0x7;
+  *valp = tp7_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_tp7_encode (uint32 *valp)
+{
+  unsigned tp7_in_0;
+  unsigned tp7_out_0;
+  tp7_out_0 = *valp;
+  tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
+  *valp = tp7_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp)
+{
+  unsigned xt_wbr15_label_out_0;
+  unsigned xt_wbr15_label_in_0;
+  xt_wbr15_label_in_0 = *valp & 0x7fff;
+  xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
+  *valp = xt_wbr15_label_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp)
+{
+  unsigned xt_wbr15_label_in_0;
+  unsigned xt_wbr15_label_out_0;
+  xt_wbr15_label_out_0 = *valp;
+  xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
+  *valp = xt_wbr15_label_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_dfp_fld_op2_2_decode (uint32 *valp)
+{
+  unsigned dfp_fld_op2_2_out_0;
+  unsigned dfp_fld_op2_2_in_0;
+  dfp_fld_op2_2_in_0 = *valp & 0x1;
+  dfp_fld_op2_2_out_0 = (0 << 1) | dfp_fld_op2_2_in_0;
+  *valp = dfp_fld_op2_2_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_dfp_fld_op2_2_encode (uint32 *valp)
+{
+  unsigned dfp_fld_op2_2_in_0;
+  unsigned dfp_fld_op2_2_out_0;
+  dfp_fld_op2_2_out_0 = *valp;
+  dfp_fld_op2_2_in_0 = (((dfp_fld_op2_2_out_0 >> 0) & 1)) & 0x1;
+  *valp = dfp_fld_op2_2_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_dfp_fld_op2_1_0_decode (uint32 *valp)
+{
+  unsigned dfp_fld_op2_1_0_out_0;
+  unsigned dfp_fld_op2_1_0_in_0;
+  dfp_fld_op2_1_0_in_0 = *valp & 0x3;
+  dfp_fld_op2_1_0_out_0 = (0 << 2) | dfp_fld_op2_1_0_in_0;
+  *valp = dfp_fld_op2_1_0_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_dfp_fld_op2_1_0_encode (uint32 *valp)
+{
+  unsigned dfp_fld_op2_1_0_in_0;
+  unsigned dfp_fld_op2_1_0_out_0;
+  dfp_fld_op2_1_0_out_0 = *valp;
+  dfp_fld_op2_1_0_in_0 = (dfp_fld_op2_1_0_out_0 & 0x3);
+  *valp = dfp_fld_op2_1_0_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_FR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_FR_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 16);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_imm8x4_decode (uint32 *valp)
+{
+  unsigned imm8x4_out_0;
+  unsigned imm8x4_in_0;
+  imm8x4_in_0 = *valp & 0xff;
+  imm8x4_out_0 = (0 << 10) | (imm8x4_in_0 << 2) | 0;
+  *valp = imm8x4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_imm8x4_encode (uint32 *valp)
+{
+  unsigned imm8x4_in_0;
+  unsigned imm8x4_out_0;
+  imm8x4_out_0 = *valp;
+  imm8x4_in_0 = ((imm8x4_out_0 >> 2) & 0xff);
+  *valp = imm8x4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_imm8x8_decode (uint32 *valp)
+{
+  unsigned imm8x8_out_0;
+  unsigned imm8x8_in_0;
+  imm8x8_in_0 = *valp & 0xff;
+  imm8x8_out_0 = (0 << 11) | (imm8x8_in_0 << 3) | 0;
+  *valp = imm8x8_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_imm8x8_encode (uint32 *valp)
+{
+  unsigned imm8x8_in_0;
+  unsigned imm8x8_out_0;
+  imm8x8_out_0 = *valp;
+  imm8x8_in_0 = ((imm8x8_out_0 >> 3) & 0xff);
+  *valp = imm8x8_in_0;
+  return 0;
+}
+
+static int
+Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= (pc & ~0x3);
+  return 0;
+}
+
+static int
+Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += (pc & ~0x3);
+  return 0;
+}
+
+static int
+Operand_uimm6_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= pc;
+  return 0;
+}
+
+static int
+Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += pc;
+  return 0;
+}
+
+static int
+Operand_label8_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= pc;
+  return 0;
+}
+
+static int
+Operand_label8_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += pc;
+  return 0;
+}
+
+static int
+Operand_ulabel8_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= pc;
+  return 0;
+}
+
+static int
+Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += pc;
+  return 0;
+}
+
+static int
+Operand_label12_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= pc;
+  return 0;
+}
+
+static int
+Operand_label12_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += pc;
+  return 0;
+}
+
+static int
+Operand_soffset_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= pc;
+  return 0;
+}
+
+static int
+Operand_soffset_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += pc;
+  return 0;
+}
+
+static int
+Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= ((pc + 3) & ~0x3);
+  return 0;
+}
+
+static int
+Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += ((pc + 3) & ~0x3);
+  return 0;
+}
+
+static int
+Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= pc;
+  return 0;
+}
+
+static int
+Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += pc;
+  return 0;
+}
+
+static int
+Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= pc;
+  return 0;
+}
+
+static int
+Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += pc;
+  return 0;
+}
+
+static xtensa_operand_internal operands[] = {
+  { "soffsetx4", FIELD_offset, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode,
+    Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
+  { "uimm12x8", FIELD_imm12, -1, 0,
+    0,
+    OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode,
+    0, 0 },
+  { "simm4", FIELD_mn, -1, 0,
+    0,
+    OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode,
+    0, 0 },
+  { "arr", FIELD_r, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "ars", FIELD_s, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "art", FIELD_t, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "ar0", FIELD__ar0, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+    OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode,
+    0, 0 },
+  { "ar4", FIELD__ar4, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+    OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode,
+    0, 0 },
+  { "ar8", FIELD__ar8, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+    OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode,
+    0, 0 },
+  { "ar12", FIELD__ar12, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+    OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode,
+    0, 0 },
+  { "ars_entry", FIELD_s, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode,
+    0, 0 },
+  { "immrx4", FIELD_r, -1, 0,
+    0,
+    OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode,
+    0, 0 },
+  { "lsi4x4", FIELD_r, -1, 0,
+    0,
+    OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
+    0, 0 },
+  { "simm7", FIELD_imm7, -1, 0,
+    0,
+    OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode,
+    0, 0 },
+  { "uimm6", FIELD_imm6, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode,
+    Operand_uimm6_ator, Operand_uimm6_rtoa },
+  { "ai4const", FIELD_t, -1, 0,
+    0,
+    OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode,
+    0, 0 },
+  { "b4const", FIELD_r, -1, 0,
+    0,
+    OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode,
+    0, 0 },
+  { "b4constu", FIELD_r, -1, 0,
+    0,
+    OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode,
+    0, 0 },
+  { "uimm8", FIELD_imm8, -1, 0,
+    0,
+    OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode,
+    0, 0 },
+  { "uimm8x2", FIELD_imm8, -1, 0,
+    0,
+    OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode,
+    0, 0 },
+  { "uimm8x4", FIELD_imm8, -1, 0,
+    0,
+    OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode,
+    0, 0 },
+  { "uimm4x16", FIELD_op2, -1, 0,
+    0,
+    OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode,
+    0, 0 },
+  { "uimmrx4", FIELD_r, -1, 0,
+    0,
+    OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
+    0, 0 },
+  { "simm8", FIELD_imm8, -1, 0,
+    0,
+    OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode,
+    0, 0 },
+  { "simm8x256", FIELD_imm8, -1, 0,
+    0,
+    OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode,
+    0, 0 },
+  { "simm12b", FIELD_imm12b, -1, 0,
+    0,
+    OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode,
+    0, 0 },
+  { "msalp32", FIELD_sal, -1, 0,
+    0,
+    OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode,
+    0, 0 },
+  { "op2p1", FIELD_op2, -1, 0,
+    0,
+    OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode,
+    0, 0 },
+  { "label8", FIELD_imm8, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode,
+    Operand_label8_ator, Operand_label8_rtoa },
+  { "ulabel8", FIELD_imm8, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode,
+    Operand_ulabel8_ator, Operand_ulabel8_rtoa },
+  { "label12", FIELD_imm12, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode,
+    Operand_label12_ator, Operand_label12_rtoa },
+  { "soffset", FIELD_offset, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
+    Operand_soffset_ator, Operand_soffset_rtoa },
+  { "uimm16x4", FIELD_imm16, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode,
+    Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
+  { "bbi", FIELD_bbi, -1, 0,
+    0,
+    OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+    0, 0 },
+  { "sae", FIELD_sae, -1, 0,
+    0,
+    OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+    0, 0 },
+  { "sas", FIELD_sas, -1, 0,
+    0,
+    OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+    0, 0 },
+  { "sargt", FIELD_sargt, -1, 0,
+    0,
+    OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+    0, 0 },
+  { "s", FIELD_s, -1, 0,
+    0,
+    OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
+    0, 0 },
+  { "mx", FIELD_x, REGFILE_MR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
+    OperandSem_opnd_sem_MR_encode, OperandSem_opnd_sem_MR_decode,
+    0, 0 },
+  { "my", FIELD_y, REGFILE_MR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
+    OperandSem_opnd_sem_MR_0_encode, OperandSem_opnd_sem_MR_0_decode,
+    0, 0 },
+  { "mw", FIELD_w, REGFILE_MR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_MR_1_encode, OperandSem_opnd_sem_MR_1_decode,
+    0, 0 },
+  { "mr0", FIELD__mr0, REGFILE_MR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+    OperandSem_opnd_sem_MR_2_encode, OperandSem_opnd_sem_MR_2_decode,
+    0, 0 },
+  { "mr1", FIELD__mr1, REGFILE_MR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+    OperandSem_opnd_sem_MR_3_encode, OperandSem_opnd_sem_MR_3_decode,
+    0, 0 },
+  { "mr2", FIELD__mr2, REGFILE_MR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+    OperandSem_opnd_sem_MR_4_encode, OperandSem_opnd_sem_MR_4_decode,
+    0, 0 },
+  { "mr3", FIELD__mr3, REGFILE_MR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+    OperandSem_opnd_sem_MR_5_encode, OperandSem_opnd_sem_MR_5_decode,
+    0, 0 },
+  { "immt", FIELD_t, -1, 0,
+    0,
+    OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
+    0, 0 },
+  { "imms", FIELD_s, -1, 0,
+    0,
+    OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
+    0, 0 },
+  { "bt", FIELD_t, REGFILE_BR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
+    0, 0 },
+  { "bs", FIELD_s, REGFILE_BR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
+    0, 0 },
+  { "br", FIELD_r, REGFILE_BR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
+    0, 0 },
+  { "bt2", FIELD_t2, REGFILE_BR, 2,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
+    0, 0 },
+  { "bs2", FIELD_s2, REGFILE_BR, 2,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
+    0, 0 },
+  { "br2", FIELD_r2, REGFILE_BR, 2,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
+    0, 0 },
+  { "bt4", FIELD_t4, REGFILE_BR, 4,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
+    0, 0 },
+  { "bs4", FIELD_s4, REGFILE_BR, 4,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
+    0, 0 },
+  { "br4", FIELD_r4, REGFILE_BR, 4,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
+    0, 0 },
+  { "bt8", FIELD_t8, REGFILE_BR, 8,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
+    0, 0 },
+  { "bs8", FIELD_s8, REGFILE_BR, 8,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
+    0, 0 },
+  { "br8", FIELD_r8, REGFILE_BR, 8,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
+    0, 0 },
+  { "bt16", FIELD__bt16, REGFILE_BR, 16,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
+    0, 0 },
+  { "bs16", FIELD__bs16, REGFILE_BR, 16,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
+    0, 0 },
+  { "br16", FIELD__br16, REGFILE_BR, 16,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
+    0, 0 },
+  { "brall", FIELD__brall, REGFILE_BR, 16,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+    OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
+    0, 0 },
+  { "tp7", FIELD_t, -1, 0,
+    0,
+    OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode,
+    0, 0 },
+  { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode,
+    Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
+  { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
+    Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
+  { "dfp_fld_op2_2", FIELD_dfp_fld_op2_2, -1, 0,
+    0,
+    OperandSem_opnd_sem_dfp_fld_op2_2_encode, OperandSem_opnd_sem_dfp_fld_op2_2_decode,
+    0, 0 },
+  { "dfp_fld_op2_1_0", FIELD_dfp_fld_op2_1_0, -1, 0,
+    0,
+    OperandSem_opnd_sem_dfp_fld_op2_1_0_encode, OperandSem_opnd_sem_dfp_fld_op2_1_0_decode,
+    0, 0 },
+  { "dfp_fld_r_0", FIELD_dfp_fld_r_0, -1, 0,
+    0,
+    OperandSem_opnd_sem_dfp_fld_op2_2_encode, OperandSem_opnd_sem_dfp_fld_op2_2_decode,
+    0, 0 },
+  { "dfp_fld_r_2_1", FIELD_dfp_fld_r_2_1, -1, 0,
+    0,
+    OperandSem_opnd_sem_dfp_fld_op2_1_0_encode, OperandSem_opnd_sem_dfp_fld_op2_1_0_decode,
+    0, 0 },
+  { "dfp_fld_op2", FIELD_dfp_fld_op2, -1, 0,
+    0,
+    OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
+    0, 0 },
+  { "dfp_fld_op2_0", FIELD_dfp_fld_op2_0, -1, 0,
+    0,
+    OperandSem_opnd_sem_dfp_fld_op2_2_encode, OperandSem_opnd_sem_dfp_fld_op2_2_decode,
+    0, 0 },
+  { "dfp_fld_s_0", FIELD_dfp_fld_s_0, -1, 0,
+    0,
+    OperandSem_opnd_sem_dfp_fld_op2_2_encode, OperandSem_opnd_sem_dfp_fld_op2_2_decode,
+    0, 0 },
+  { "frr", FIELD_r, REGFILE_FR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode,
+    0, 0 },
+  { "frs", FIELD_s, REGFILE_FR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode,
+    0, 0 },
+  { "frt", FIELD_t, REGFILE_FR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode,
+    0, 0 },
+  { "imm_t", FIELD_t, -1, 0,
+    0,
+    OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
+    0, 0 },
+  { "imm_s", FIELD_s, -1, 0,
+    0,
+    OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
+    0, 0 },
+  { "imm8x4", FIELD_imm8, -1, 0,
+    0,
+    OperandSem_opnd_sem_imm8x4_encode, OperandSem_opnd_sem_imm8x4_decode,
+    0, 0 },
+  { "imm8x8", FIELD_imm8, -1, 0,
+    0,
+    OperandSem_opnd_sem_imm8x8_encode, OperandSem_opnd_sem_imm8x8_decode,
+    0, 0 },
+  { "bitindex", FIELD_bitindex, -1, 0,
+    0,
+    OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+    0, 0 },
+  { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
+  { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
+  { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
+  { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
+  { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
+  { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
+  { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
+  { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
+  { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
+  { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
+  { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
+  { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
+  { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
+  { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
+  { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
+  { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
+  { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
+  { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
+  { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
+  { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 },
+  { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 },
+  { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 },
+  { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 },
+  { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 },
+  { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 },
+  { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 },
+  { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 },
+  { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 },
+  { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 },
+  { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 },
+  { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 },
+  { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 },
+  { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 },
+  { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 },
+  { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 },
+  { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 },
+  { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 },
+  { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
+  { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
+  { "dfp_fld_op1", FIELD_dfp_fld_op1, -1, 0, 0, 0, 0, 0, 0 },
+  { "dfp_fld_r_3", FIELD_dfp_fld_r_3, -1, 0, 0, 0, 0, 0, 0 },
+  { "dfp_fld_r_3_1", FIELD_dfp_fld_r_3_1, -1, 0, 0, 0, 0, 0, 0 },
+  { "dfp_fld_s_3_1", FIELD_dfp_fld_s_3_1, -1, 0, 0, 0, 0, 0, 0 },
+  { "dfp_fld_op2_3", FIELD_dfp_fld_op2_3, -1, 0, 0, 0, 0, 0, 0 },
+  { "dfp_fld_op2_3_2", FIELD_dfp_fld_op2_3_2, -1, 0, 0, 0, 0, 0, 0 },
+  { "dfp_fld_op2_3_1", FIELD_dfp_fld_op2_3_1, -1, 0, 0, 0, 0, 0, 0 },
+  { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }
+};
+
+enum xtensa_operand_id {
+  OPERAND_soffsetx4,
+  OPERAND_uimm12x8,
+  OPERAND_simm4,
+  OPERAND_arr,
+  OPERAND_ars,
+  OPERAND__ars_invisible,
+  OPERAND_art,
+  OPERAND_ar0,
+  OPERAND_ar4,
+  OPERAND_ar8,
+  OPERAND_ar12,
+  OPERAND_ars_entry,
+  OPERAND_immrx4,
+  OPERAND_lsi4x4,
+  OPERAND_simm7,
+  OPERAND_uimm6,
+  OPERAND_ai4const,
+  OPERAND_b4const,
+  OPERAND_b4constu,
+  OPERAND_uimm8,
+  OPERAND_uimm8x2,
+  OPERAND_uimm8x4,
+  OPERAND_uimm4x16,
+  OPERAND_uimmrx4,
+  OPERAND_simm8,
+  OPERAND_simm8x256,
+  OPERAND_simm12b,
+  OPERAND_msalp32,
+  OPERAND_op2p1,
+  OPERAND_label8,
+  OPERAND_ulabel8,
+  OPERAND_label12,
+  OPERAND_soffset,
+  OPERAND_uimm16x4,
+  OPERAND_bbi,
+  OPERAND_sae,
+  OPERAND_sas,
+  OPERAND_sargt,
+  OPERAND_s,
+  OPERAND_mx,
+  OPERAND_my,
+  OPERAND_mw,
+  OPERAND_mr0,
+  OPERAND_mr1,
+  OPERAND_mr2,
+  OPERAND_mr3,
+  OPERAND_immt,
+  OPERAND_imms,
+  OPERAND_bt,
+  OPERAND_bs,
+  OPERAND_br,
+  OPERAND_bt2,
+  OPERAND_bs2,
+  OPERAND_br2,
+  OPERAND_bt4,
+  OPERAND_bs4,
+  OPERAND_br4,
+  OPERAND_bt8,
+  OPERAND_bs8,
+  OPERAND_br8,
+  OPERAND_bt16,
+  OPERAND_bs16,
+  OPERAND_br16,
+  OPERAND_brall,
+  OPERAND_tp7,
+  OPERAND_xt_wbr15_label,
+  OPERAND_xt_wbr18_label,
+  OPERAND_dfp_fld_op2_2,
+  OPERAND_dfp_fld_op2_1_0,
+  OPERAND_dfp_fld_r_0,
+  OPERAND_dfp_fld_r_2_1,
+  OPERAND_dfp_fld_op2,
+  OPERAND_dfp_fld_op2_0,
+  OPERAND_dfp_fld_s_0,
+  OPERAND_frr,
+  OPERAND_frs,
+  OPERAND_frt,
+  OPERAND_imm_t,
+  OPERAND_imm_s,
+  OPERAND_imm8x4,
+  OPERAND_imm8x8,
+  OPERAND_bitindex,
+  OPERAND_t,
+  OPERAND_bbi4,
+  OPERAND_imm12,
+  OPERAND_imm8,
+  OPERAND_imm12b,
+  OPERAND_imm16,
+  OPERAND_m,
+  OPERAND_n,
+  OPERAND_offset,
+  OPERAND_op0,
+  OPERAND_op1,
+  OPERAND_op2,
+  OPERAND_r,
+  OPERAND_sa4,
+  OPERAND_sae4,
+  OPERAND_sal,
+  OPERAND_sas4,
+  OPERAND_sr,
+  OPERAND_st,
+  OPERAND_thi3,
+  OPERAND_imm4,
+  OPERAND_mn,
+  OPERAND_i,
+  OPERAND_imm6lo,
+  OPERAND_imm6hi,
+  OPERAND_imm7lo,
+  OPERAND_imm7hi,
+  OPERAND_z,
+  OPERAND_imm6,
+  OPERAND_imm7,
+  OPERAND_r3,
+  OPERAND_rbit2,
+  OPERAND_rhi,
+  OPERAND_t3,
+  OPERAND_tbit2,
+  OPERAND_tlo,
+  OPERAND_w,
+  OPERAND_y,
+  OPERAND_x,
+  OPERAND_t2,
+  OPERAND_s2,
+  OPERAND_r2,
+  OPERAND_t4,
+  OPERAND_s4,
+  OPERAND_r4,
+  OPERAND_t8,
+  OPERAND_s8,
+  OPERAND_r8,
+  OPERAND_xt_wbr15_imm,
+  OPERAND_xt_wbr18_imm,
+  OPERAND_dfp_fld_op1,
+  OPERAND_dfp_fld_r_3,
+  OPERAND_dfp_fld_r_3_1,
+  OPERAND_dfp_fld_s_3_1,
+  OPERAND_dfp_fld_op2_3,
+  OPERAND_dfp_fld_op2_3_2,
+  OPERAND_dfp_fld_op2_3_1,
+  OPERAND_s3to1
+};
+
+\f
+/* Iclass table.  */
+
+static xtensa_arg_internal Iclass_LSI_args[] = {
+  { { OPERAND_frt }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_imm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_LSI_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_LSIP_args[] = {
+  { { OPERAND_frt }, 'o' },
+  { { OPERAND_ars }, 'm' },
+  { { OPERAND_imm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_LSIP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_LSX_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_LSX_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_LSXP_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_ars }, 'm' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_LSXP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_SSI_args[] = {
+  { { OPERAND_frt }, 'i' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_imm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_SSI_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_SSIP_args[] = {
+  { { OPERAND_frt }, 'i' },
+  { { OPERAND_ars }, 'm' },
+  { { OPERAND_imm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_SSIP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_SSX_args[] = {
+  { { OPERAND_frr }, 'i' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_SSX_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_SSXP_args[] = {
+  { { OPERAND_frr }, 'i' },
+  { { OPERAND_ars }, 'm' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_SSXP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ABS_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ABS_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_NEG_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_NEG_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOV_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOV_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOVEQZ_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOVEQZ_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOVNEZ_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOVNEZ_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOVLTZ_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOVLTZ_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOVGEZ_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOVGEZ_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOVF_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_bt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOVF_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOVT_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_bt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOVT_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_WFR_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_WFR_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_RFR_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_RFR_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ROUND_S_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_imm_t }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ROUND_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_CEIL_S_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_imm_t }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_CEIL_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_FLOOR_S_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_imm_t }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_FLOOR_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_TRUNC_S_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_imm_t }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_TRUNC_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_UTRUNC_S_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_imm_t }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_UTRUNC_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_FLOAT_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_imm_t }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_FLOAT_S_stateArgs[] = {
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_RoundMode }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_UFLOAT_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_imm_t }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_UFLOAT_S_stateArgs[] = {
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_RoundMode }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_UN_S_args[] = {
+  { { OPERAND_br }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_UN_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ULT_S_args[] = {
+  { { OPERAND_br }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ULT_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ULE_S_args[] = {
+  { { OPERAND_br }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ULE_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_UEQ_S_args[] = {
+  { { OPERAND_br }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_UEQ_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_OLT_S_args[] = {
+  { { OPERAND_br }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_OLT_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_OLE_S_args[] = {
+  { { OPERAND_br }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_OLE_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_OEQ_S_args[] = {
+  { { OPERAND_br }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_OEQ_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ADD_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ADD_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_OverflowFlag }, 'm' },
+  { { STATE_UnderflowFlag }, 'm' },
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_RoundMode }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_SUB_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_SUB_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_OverflowFlag }, 'm' },
+  { { STATE_UnderflowFlag }, 'm' },
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_RoundMode }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MUL_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MUL_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_OverflowFlag }, 'm' },
+  { { STATE_UnderflowFlag }, 'm' },
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_RoundMode }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MADD_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MADD_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_OverflowFlag }, 'm' },
+  { { STATE_UnderflowFlag }, 'm' },
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_RoundMode }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MSUB_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MSUB_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_OverflowFlag }, 'm' },
+  { { STATE_UnderflowFlag }, 'm' },
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_RoundMode }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_SQRT0_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_SQRT0_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_DIV0_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_DIV0_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_RECIP0_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_RECIP0_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_DivZeroFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_RSQRT0_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_RSQRT0_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_DivZeroFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MADDN_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MADDN_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_DIVN_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_DIVN_S_stateArgs[] = {
+  { { STATE_OverflowFlag }, 'm' },
+  { { STATE_UnderflowFlag }, 'm' },
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_RoundMode }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_CONST_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_imm_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_CONST_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_NEXP01_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_NEXP01_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ADDEXP_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ADDEXP_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ADDEXPM_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ADDEXPM_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MKDADJ_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MKDADJ_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_DivZeroFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MKSADJ_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MKSADJ_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
+  { { STATE_PSEXCM }, 'o' },
+  { { STATE_EPC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
+  { { STATE_DEPC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
+  { { OPERAND_soffsetx4 }, 'i' },
+  { { OPERAND_ar12 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
+  { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
+  { { OPERAND_soffsetx4 }, 'i' },
+  { { OPERAND_ar8 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
+  { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
+  { { OPERAND_soffsetx4 }, 'i' },
+  { { OPERAND_ar4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
+  { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_ar12 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
+  { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_ar8 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
+  { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_ar4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
+  { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
+  { { OPERAND_ars_entry }, 's' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm12x8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
+  { { STATE_PSCALLINC }, 'i' },
+  { { STATE_PSEXCM }, 'i' },
+  { { STATE_PSWOE }, 'i' },
+  { { STATE_WindowBase }, 'm' },
+  { { STATE_WindowStart }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
+  { { STATE_WindowBase }, 'i' },
+  { { STATE_WindowStart }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
+  { { OPERAND_simm4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
+  { { STATE_WindowBase }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
+  { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
+  { { STATE_WindowBase }, 'm' },
+  { { STATE_WindowStart }, 'm' },
+  { { STATE_PSCALLINC }, 'o' },
+  { { STATE_PSEXCM }, 'i' },
+  { { STATE_PSWOE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
+  { { STATE_EPC1 }, 'i' },
+  { { STATE_PSEXCM }, 'o' },
+  { { STATE_WindowBase }, 'm' },
+  { { STATE_WindowStart }, 'm' },
+  { { STATE_PSOWB }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_immrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_immrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
+  { { STATE_WindowBase }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
+  { { STATE_WindowBase }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
+  { { STATE_WindowBase }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
+  { { STATE_WindowStart }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
+  { { STATE_WindowStart }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
+  { { STATE_WindowStart }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_ai4const }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_lsi4x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
+  { { OPERAND_ars }, 'o' },
+  { { OPERAND_simm7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
+  { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_lsi4x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
+  { { STATE_THREADPTR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
+  { { STATE_THREADPTR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_simm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_simm8x256 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_b4const }, 'i' },
+  { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_bbi }, 'i' },
+  { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_b4constu }, 'i' },
+  { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_label12 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
+  { { OPERAND_soffsetx4 }, 'i' },
+  { { OPERAND_ar0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_ar0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_sae }, 'i' },
+  { { OPERAND_op2p1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
+  { { OPERAND_soffset }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_uimm16x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_ulabel8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
+  { { STATE_LBEG }, 'o' },
+  { { STATE_LEND }, 'o' },
+  { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_ulabel8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
+  { { STATE_LBEG }, 'o' },
+  { { STATE_LEND }, 'o' },
+  { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_simm12b }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
+  { { OPERAND_arr }, 'm' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
+  { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimmrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
+  { { STATE_SAR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
+  { { OPERAND_sas }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
+  { { STATE_SAR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
+  { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
+  { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
+  { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_msalp32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_sargt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
+  { { STATE_XTSYNC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
+  { { STATE_PSWOE }, 'i' },
+  { { STATE_PSCALLINC }, 'i' },
+  { { STATE_PSOWB }, 'i' },
+  { { STATE_PSUM }, 'i' },
+  { { STATE_PSEXCM }, 'i' },
+  { { STATE_PSINTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
+  { { STATE_LEND }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
+  { { STATE_LEND }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
+  { { STATE_LEND }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
+  { { STATE_LCOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_LCOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
+  { { STATE_LBEG }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
+  { { STATE_LBEG }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
+  { { STATE_LBEG }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
+  { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
+  { { STATE_SAR }, 'o' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
+  { { STATE_SAR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_stateArgs[] = {
+  { { STATE_MEMCTL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_stateArgs[] = {
+  { { STATE_MEMCTL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_stateArgs[] = {
+  { { STATE_MEMCTL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
+  { { STATE_PSWOE }, 'i' },
+  { { STATE_PSCALLINC }, 'i' },
+  { { STATE_PSOWB }, 'i' },
+  { { STATE_PSUM }, 'i' },
+  { { STATE_PSEXCM }, 'i' },
+  { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
+  { { STATE_PSWOE }, 'o' },
+  { { STATE_PSCALLINC }, 'o' },
+  { { STATE_PSOWB }, 'o' },
+  { { STATE_PSUM }, 'o' },
+  { { STATE_PSEXCM }, 'o' },
+  { { STATE_PSINTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
+  { { STATE_PSWOE }, 'm' },
+  { { STATE_PSCALLINC }, 'm' },
+  { { STATE_PSOWB }, 'm' },
+  { { STATE_PSUM }, 'm' },
+  { { STATE_PSEXCM }, 'm' },
+  { { STATE_PSINTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
+  { { STATE_EPC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
+  { { STATE_EPC1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
+  { { STATE_EPC1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
+  { { STATE_EXCSAVE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
+  { { STATE_EXCSAVE1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
+  { { STATE_EXCSAVE1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
+  { { STATE_EPC2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
+  { { STATE_EPC2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
+  { { STATE_EPC2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
+  { { STATE_EXCSAVE2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
+  { { STATE_EXCSAVE2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
+  { { STATE_EXCSAVE2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
+  { { STATE_EPC3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
+  { { STATE_EPC3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
+  { { STATE_EPC3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
+  { { STATE_EXCSAVE3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
+  { { STATE_EXCSAVE3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
+  { { STATE_EXCSAVE3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
+  { { STATE_EPC4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
+  { { STATE_EPC4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
+  { { STATE_EPC4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
+  { { STATE_EXCSAVE4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
+  { { STATE_EXCSAVE4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
+  { { STATE_EXCSAVE4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
+  { { STATE_EPC5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
+  { { STATE_EPC5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
+  { { STATE_EPC5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
+  { { STATE_EXCSAVE5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
+  { { STATE_EXCSAVE5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
+  { { STATE_EXCSAVE5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
+  { { STATE_EPC6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
+  { { STATE_EPC6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
+  { { STATE_EPC6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
+  { { STATE_EXCSAVE6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
+  { { STATE_EXCSAVE6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
+  { { STATE_EXCSAVE6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
+  { { STATE_EPC7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
+  { { STATE_EPC7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
+  { { STATE_EPC7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
+  { { STATE_EXCSAVE7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
+  { { STATE_EXCSAVE7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
+  { { STATE_EXCSAVE7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
+  { { STATE_EPS2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
+  { { STATE_EPS2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
+  { { STATE_EPS2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
+  { { STATE_EPS3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
+  { { STATE_EPS3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
+  { { STATE_EPS3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
+  { { STATE_EPS4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
+  { { STATE_EPS4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
+  { { STATE_EPS4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
+  { { STATE_EPS5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
+  { { STATE_EPS5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
+  { { STATE_EPS5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
+  { { STATE_EPS6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
+  { { STATE_EPS6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
+  { { STATE_EPS6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
+  { { STATE_EPS7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
+  { { STATE_EPS7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
+  { { STATE_EPS7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
+  { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
+  { { STATE_EXCVADDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
+  { { STATE_EXCVADDR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
+  { { STATE_DEPC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
+  { { STATE_DEPC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
+  { { STATE_DEPC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
+  { { STATE_EXCCAUSE }, 'i' },
+  { { STATE_XTSYNC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
+  { { STATE_EXCCAUSE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
+  { { STATE_EXCCAUSE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
+  { { STATE_MISC0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
+  { { STATE_MISC0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
+  { { STATE_MISC0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
+  { { STATE_MISC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
+  { { STATE_MISC1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
+  { { STATE_MISC1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_stateArgs[] = {
+  { { STATE_MISC2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_stateArgs[] = {
+  { { STATE_MISC2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_stateArgs[] = {
+  { { STATE_MISC2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_stateArgs[] = {
+  { { STATE_MISC3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_stateArgs[] = {
+  { { STATE_MISC3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_stateArgs[] = {
+  { { STATE_MISC3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
+  { { STATE_VECBASE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
+  { { STATE_VECBASE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
+  { { STATE_VECBASE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul16_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul32_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul32h_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
+  { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
+  { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
+  { { OPERAND_mx }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
+  { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
+  { { OPERAND_mx }, 'i' },
+  { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
+  { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
+  { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
+  { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
+  { { OPERAND_mx }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
+  { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
+  { { OPERAND_mx }, 'i' },
+  { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
+  { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
+  { { OPERAND_mw }, 'o' },
+  { { OPERAND_ars }, 'm' },
+  { { OPERAND_mx }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
+  { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
+  { { OPERAND_mw }, 'o' },
+  { { OPERAND_ars }, 'm' },
+  { { OPERAND_mx }, 'i' },
+  { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
+  { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
+  { { OPERAND_mw }, 'o' },
+  { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_mr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_mr0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
+  { { OPERAND_art }, 'm' },
+  { { OPERAND_mr0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_mr1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_mr1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
+  { { OPERAND_art }, 'm' },
+  { { OPERAND_mr1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_mr2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_mr2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
+  { { OPERAND_art }, 'm' },
+  { { OPERAND_mr2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_mr3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_mr3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
+  { { OPERAND_art }, 'm' },
+  { { OPERAND_mr3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
+  { { STATE_ACC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
+  { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
+  { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
+  { { STATE_ACC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
+  { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
+  { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
+  { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
+  { { STATE_PSWOE }, 'o' },
+  { { STATE_PSCALLINC }, 'o' },
+  { { STATE_PSOWB }, 'o' },
+  { { STATE_PSUM }, 'o' },
+  { { STATE_PSEXCM }, 'o' },
+  { { STATE_PSINTLEVEL }, 'o' },
+  { { STATE_EPC1 }, 'i' },
+  { { STATE_EPC2 }, 'i' },
+  { { STATE_EPC3 }, 'i' },
+  { { STATE_EPC4 }, 'i' },
+  { { STATE_EPC5 }, 'i' },
+  { { STATE_EPC6 }, 'i' },
+  { { STATE_EPC7 }, 'i' },
+  { { STATE_EPS2 }, 'i' },
+  { { STATE_EPS3 }, 'i' },
+  { { STATE_EPS4 }, 'i' },
+  { { STATE_EPS5 }, 'i' },
+  { { STATE_EPS6 }, 'i' },
+  { { STATE_EPS7 }, 'i' },
+  { { STATE_InOCDMode }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
+  { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
+  { { STATE_PSINTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
+  { { STATE_INTERRUPT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
+  { { STATE_INTENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
+  { { STATE_INTENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
+  { { STATE_INTENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
+  { { OPERAND_imms }, 'i' },
+  { { OPERAND_immt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
+  { { STATE_PSEXCM }, 'i' },
+  { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
+  { { OPERAND_imms }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
+  { { STATE_PSEXCM }, 'i' },
+  { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
+  { { STATE_DBREAKA0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
+  { { STATE_DBREAKA0 }, 'o' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
+  { { STATE_DBREAKA0 }, 'm' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
+  { { STATE_DBREAKC0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
+  { { STATE_DBREAKC0 }, 'o' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
+  { { STATE_DBREAKC0 }, 'm' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
+  { { STATE_DBREAKA1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
+  { { STATE_DBREAKA1 }, 'o' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
+  { { STATE_DBREAKA1 }, 'm' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
+  { { STATE_DBREAKC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
+  { { STATE_DBREAKC1 }, 'o' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
+  { { STATE_DBREAKC1 }, 'm' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
+  { { STATE_IBREAKA0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
+  { { STATE_IBREAKA0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
+  { { STATE_IBREAKA0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
+  { { STATE_IBREAKA1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
+  { { STATE_IBREAKA1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
+  { { STATE_IBREAKA1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
+  { { STATE_IBREAKENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
+  { { STATE_IBREAKENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
+  { { STATE_IBREAKENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
+  { { STATE_DEBUGCAUSE }, 'i' },
+  { { STATE_DBNUM }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
+  { { STATE_DEBUGCAUSE }, 'o' },
+  { { STATE_DBNUM }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
+  { { STATE_DEBUGCAUSE }, 'm' },
+  { { STATE_DBNUM }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
+  { { STATE_ICOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_ICOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_ICOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
+  { { STATE_ICOUNTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
+  { { STATE_ICOUNTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
+  { { STATE_ICOUNTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
+  { { STATE_DDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_DDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_DDR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = {
+  { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_InOCDMode }, 'i' },
+  { { STATE_DDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = {
+  { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = {
+  { { STATE_InOCDMode }, 'i' },
+  { { STATE_DDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
+  { { OPERAND_imms }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
+  { { STATE_InOCDMode }, 'm' },
+  { { STATE_EPC6 }, 'i' },
+  { { STATE_PSWOE }, 'o' },
+  { { STATE_PSCALLINC }, 'o' },
+  { { STATE_PSOWB }, 'o' },
+  { { STATE_PSUM }, 'o' },
+  { { STATE_PSEXCM }, 'o' },
+  { { STATE_PSINTLEVEL }, 'o' },
+  { { STATE_EPS6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
+  { { STATE_InOCDMode }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = {
+  { { OPERAND_br }, 'o' },
+  { { OPERAND_bs }, 'i' },
+  { { OPERAND_bt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = {
+  { { OPERAND_bt }, 'o' },
+  { { OPERAND_bs4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = {
+  { { OPERAND_bt }, 'o' },
+  { { OPERAND_bs8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = {
+  { { OPERAND_bs }, 'i' },
+  { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = {
+  { { OPERAND_arr }, 'm' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_bt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_brall }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_brall }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = {
+  { { OPERAND_art }, 'm' },
+  { { OPERAND_brall }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
+  { { STATE_CCOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_CCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_CCOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
+  { { STATE_CCOMPARE0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
+  { { STATE_CCOMPARE0 }, 'o' },
+  { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
+  { { STATE_CCOMPARE0 }, 'm' },
+  { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
+  { { STATE_CCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
+  { { STATE_CCOMPARE1 }, 'o' },
+  { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
+  { { STATE_CCOMPARE1 }, 'm' },
+  { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
+  { { STATE_CCOMPARE2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
+  { { STATE_CCOMPARE2 }, 'o' },
+  { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
+  { { STATE_CCOMPARE2 }, 'm' },
+  { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
+  { { STATE_CPENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
+  { { STATE_CPENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_tp7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_tp7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
+  { { OPERAND_art }, 'm' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
+  { { STATE_SCOMPARE1 }, 'i' },
+  { { STATE_XTSYNC }, 'i' },
+  { { STATE_SCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
+  { { STATE_SCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
+  { { STATE_SCOMPARE1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
+  { { STATE_SCOMPARE1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = {
+  { { STATE_ATOMCTL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = {
+  { { STATE_ATOMCTL }, 'o' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = {
+  { { STATE_ATOMCTL }, 'm' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = {
+  { { STATE_ERI_RAW_INTERLOCK }, 'i' }
+};
+
+static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = {
+  INTERFACE_ERI_RD_In,
+  INTERFACE_ERI_RD_Out
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = {
+  { { STATE_ERI_RAW_INTERLOCK }, 'o' }
+};
+
+static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = {
+  INTERFACE_ERI_WR_In,
+  INTERFACE_ERI_WR_Out
+};
+
+static xtensa_arg_internal Iclass_iclass_F64ITER_args[] = {
+  { { OPERAND_arr }, 'm' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_dfp_fld_op2_1_0 }, 'i' },
+  { { OPERAND_dfp_fld_op2_2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_F64ITER_stateArgs[] = {
+  { { STATE_F64R }, 'm' },
+  { { STATE_F64S }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_iclass_F64RND_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_dfp_fld_op2_1_0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_F64RND_stateArgs[] = {
+  { { STATE_F64R }, 'm' },
+  { { STATE_F64S }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_F64ADDC_F64SUBC_args[] = {
+  { { OPERAND_art }, 'm' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_dfp_fld_r_2_1 }, 'i' },
+  { { OPERAND_dfp_fld_r_0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_F64ADDC_F64SUBC_stateArgs[] = {
+  { { STATE_F64S }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_iclass_F64SIG_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_F64CMPL_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_F64CMPL_stateArgs[] = {
+  { { STATE_F64S }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_iclass_F64CMPH_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_dfp_fld_op2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_F64CMPH_stateArgs[] = {
+  { { STATE_SAR }, 'o' },
+  { { STATE_F64R }, 'o' },
+  { { STATE_F64S }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_iclass_F64NORM_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_dfp_fld_op2_0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_F64NORM_stateArgs[] = {
+  { { STATE_SAR }, 'o' },
+  { { STATE_F64S }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_iclass_F64SEXP_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_RF64R_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_dfp_fld_s_0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_RF64R_stateArgs[] = {
+  { { STATE_F64R }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_WF64R_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_dfp_fld_r_0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_WF64R_stateArgs[] = {
+  { { STATE_F64R }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_f64r_lo_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_f64r_lo_stateArgs[] = {
+  { { STATE_F64R }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_f64r_lo_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_f64r_lo_stateArgs[] = {
+  { { STATE_F64R }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_rur_f64r_hi_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_f64r_hi_stateArgs[] = {
+  { { STATE_F64R }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_f64r_hi_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_f64r_hi_stateArgs[] = {
+  { { STATE_F64R }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_rur_f64s_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_f64s_stateArgs[] = {
+  { { STATE_F64S }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_f64s_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_f64s_stateArgs[] = {
+  { { STATE_F64S }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_fcr_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_fcr_stateArgs[] = {
+  { { STATE_RoundMode }, 'i' },
+  { { STATE_InvalidEnable }, 'i' },
+  { { STATE_DivZeroEnable }, 'i' },
+  { { STATE_OverflowEnable }, 'i' },
+  { { STATE_UnderflowEnable }, 'i' },
+  { { STATE_InexactEnable }, 'i' },
+  { { STATE_FPreserved20 }, 'i' },
+  { { STATE_FPreserved5 }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_fcr_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_fcr_stateArgs[] = {
+  { { STATE_RoundMode }, 'o' },
+  { { STATE_InvalidEnable }, 'o' },
+  { { STATE_DivZeroEnable }, 'o' },
+  { { STATE_OverflowEnable }, 'o' },
+  { { STATE_UnderflowEnable }, 'o' },
+  { { STATE_InexactEnable }, 'o' },
+  { { STATE_FPreserved20 }, 'o' },
+  { { STATE_FPreserved5 }, 'o' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_fsr_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_fsr_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'i' },
+  { { STATE_DivZeroFlag }, 'i' },
+  { { STATE_OverflowFlag }, 'i' },
+  { { STATE_UnderflowFlag }, 'i' },
+  { { STATE_InexactFlag }, 'i' },
+  { { STATE_FPreserved20a }, 'i' },
+  { { STATE_FPreserved7 }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_fsr_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_fsr_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'o' },
+  { { STATE_DivZeroFlag }, 'o' },
+  { { STATE_OverflowFlag }, 'o' },
+  { { STATE_UnderflowFlag }, 'o' },
+  { { STATE_InexactFlag }, 'o' },
+  { { STATE_FPreserved20a }, 'o' },
+  { { STATE_FPreserved7 }, 'o' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_expstate_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = {
+  { { STATE_EXPSTATE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_expstate_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = {
+  { { STATE_EXPSTATE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = {
+  INTERFACE_IMPWIRE
+};
+
+static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = {
+  { { OPERAND_bitindex }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = {
+  { { STATE_EXPSTATE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = {
+  { { OPERAND_bitindex }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = {
+  { { STATE_EXPSTATE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = {
+  { { STATE_EXPSTATE }, 'm' }
+};
+
+static xtensa_iclass_internal iclasses[] = {
+  { 3, Iclass_LSI_args,
+    1, Iclass_LSI_stateArgs, 0, 0 },
+  { 3, Iclass_LSIP_args,
+    1, Iclass_LSIP_stateArgs, 0, 0 },
+  { 3, Iclass_LSX_args,
+    1, Iclass_LSX_stateArgs, 0, 0 },
+  { 3, Iclass_LSXP_args,
+    1, Iclass_LSXP_stateArgs, 0, 0 },
+  { 3, Iclass_SSI_args,
+    1, Iclass_SSI_stateArgs, 0, 0 },
+  { 3, Iclass_SSIP_args,
+    1, Iclass_SSIP_stateArgs, 0, 0 },
+  { 3, Iclass_SSX_args,
+    1, Iclass_SSX_stateArgs, 0, 0 },
+  { 3, Iclass_SSXP_args,
+    1, Iclass_SSXP_stateArgs, 0, 0 },
+  { 2, Iclass_ABS_S_args,
+    1, Iclass_ABS_S_stateArgs, 0, 0 },
+  { 2, Iclass_NEG_S_args,
+    1, Iclass_NEG_S_stateArgs, 0, 0 },
+  { 2, Iclass_MOV_S_args,
+    1, Iclass_MOV_S_stateArgs, 0, 0 },
+  { 3, Iclass_MOVEQZ_S_args,
+    1, Iclass_MOVEQZ_S_stateArgs, 0, 0 },
+  { 3, Iclass_MOVNEZ_S_args,
+    1, Iclass_MOVNEZ_S_stateArgs, 0, 0 },
+  { 3, Iclass_MOVLTZ_S_args,
+    1, Iclass_MOVLTZ_S_stateArgs, 0, 0 },
+  { 3, Iclass_MOVGEZ_S_args,
+    1, Iclass_MOVGEZ_S_stateArgs, 0, 0 },
+  { 3, Iclass_MOVF_S_args,
+    1, Iclass_MOVF_S_stateArgs, 0, 0 },
+  { 3, Iclass_MOVT_S_args,
+    1, Iclass_MOVT_S_stateArgs, 0, 0 },
+  { 2, Iclass_WFR_args,
+    1, Iclass_WFR_stateArgs, 0, 0 },
+  { 2, Iclass_RFR_args,
+    1, Iclass_RFR_stateArgs, 0, 0 },
+  { 3, Iclass_ROUND_S_args,
+    3, Iclass_ROUND_S_stateArgs, 0, 0 },
+  { 3, Iclass_CEIL_S_args,
+    3, Iclass_CEIL_S_stateArgs, 0, 0 },
+  { 3, Iclass_FLOOR_S_args,
+    3, Iclass_FLOOR_S_stateArgs, 0, 0 },
+  { 3, Iclass_TRUNC_S_args,
+    3, Iclass_TRUNC_S_stateArgs, 0, 0 },
+  { 3, Iclass_UTRUNC_S_args,
+    3, Iclass_UTRUNC_S_stateArgs, 0, 0 },
+  { 3, Iclass_FLOAT_S_args,
+    3, Iclass_FLOAT_S_stateArgs, 0, 0 },
+  { 3, Iclass_UFLOAT_S_args,
+    3, Iclass_UFLOAT_S_stateArgs, 0, 0 },
+  { 3, Iclass_UN_S_args,
+    2, Iclass_UN_S_stateArgs, 0, 0 },
+  { 3, Iclass_ULT_S_args,
+    2, Iclass_ULT_S_stateArgs, 0, 0 },
+  { 3, Iclass_ULE_S_args,
+    2, Iclass_ULE_S_stateArgs, 0, 0 },
+  { 3, Iclass_UEQ_S_args,
+    2, Iclass_UEQ_S_stateArgs, 0, 0 },
+  { 3, Iclass_OLT_S_args,
+    2, Iclass_OLT_S_stateArgs, 0, 0 },
+  { 3, Iclass_OLE_S_args,
+    2, Iclass_OLE_S_stateArgs, 0, 0 },
+  { 3, Iclass_OEQ_S_args,
+    2, Iclass_OEQ_S_stateArgs, 0, 0 },
+  { 3, Iclass_ADD_S_args,
+    6, Iclass_ADD_S_stateArgs, 0, 0 },
+  { 3, Iclass_SUB_S_args,
+    6, Iclass_SUB_S_stateArgs, 0, 0 },
+  { 3, Iclass_MUL_S_args,
+    6, Iclass_MUL_S_stateArgs, 0, 0 },
+  { 3, Iclass_MADD_S_args,
+    6, Iclass_MADD_S_stateArgs, 0, 0 },
+  { 3, Iclass_MSUB_S_args,
+    6, Iclass_MSUB_S_stateArgs, 0, 0 },
+  { 2, Iclass_SQRT0_S_args,
+    1, Iclass_SQRT0_S_stateArgs, 0, 0 },
+  { 2, Iclass_DIV0_S_args,
+    1, Iclass_DIV0_S_stateArgs, 0, 0 },
+  { 2, Iclass_RECIP0_S_args,
+    3, Iclass_RECIP0_S_stateArgs, 0, 0 },
+  { 2, Iclass_RSQRT0_S_args,
+    3, Iclass_RSQRT0_S_stateArgs, 0, 0 },
+  { 3, Iclass_MADDN_S_args,
+    1, Iclass_MADDN_S_stateArgs, 0, 0 },
+  { 3, Iclass_DIVN_S_args,
+    5, Iclass_DIVN_S_stateArgs, 0, 0 },
+  { 2, Iclass_CONST_S_args,
+    1, Iclass_CONST_S_stateArgs, 0, 0 },
+  { 2, Iclass_NEXP01_S_args,
+    1, Iclass_NEXP01_S_stateArgs, 0, 0 },
+  { 2, Iclass_ADDEXP_S_args,
+    1, Iclass_ADDEXP_S_stateArgs, 0, 0 },
+  { 2, Iclass_ADDEXPM_S_args,
+    1, Iclass_ADDEXPM_S_stateArgs, 0, 0 },
+  { 2, Iclass_MKDADJ_S_args,
+    3, Iclass_MKDADJ_S_stateArgs, 0, 0 },
+  { 2, Iclass_MKSADJ_S_args,
+    2, Iclass_MKSADJ_S_stateArgs, 0, 0 },
+  { 0, 0 /* xt_iclass_excw */,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_rfe */,
+    2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
+  { 0, 0 /* xt_iclass_rfde */,
+    1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
+  { 0, 0 /* xt_iclass_syscall */,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_call12_args,
+    1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_call8_args,
+    1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_call4_args,
+    1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_callx12_args,
+    1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_callx8_args,
+    1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_callx4_args,
+    1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_entry_args,
+    5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_movsp_args,
+    2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rotw_args,
+    1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_retw_args,
+    5, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
+  { 0, 0 /* xt_iclass_rfwou */,
+    5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_l32e_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_s32e_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_windowbase_args,
+    1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_windowbase_args,
+    1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_windowbase_args,
+    1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_windowstart_args,
+    1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_windowstart_args,
+    1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_windowstart_args,
+    1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_add_n_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_addi_n_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_bz6_args,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_ill_n */,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_loadi4_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_mov_n_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_movi_n_args,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_nopn */,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_retn_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_storei4_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_rur_threadptr_args,
+    1, Iclass_rur_threadptr_stateArgs, 0, 0 },
+  { 1, Iclass_wur_threadptr_args,
+    1, Iclass_wur_threadptr_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_addi_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_addmi_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_addsub_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_bit_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_bsi8_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_bsi8b_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_bsi8u_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_bst8_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_bsz12_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_call0_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_callx0_args,
+    0, 0, 0, 0 },
+  { 4, Iclass_xt_iclass_exti_args,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_ill */,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_jump_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_jumpx_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_l16ui_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_l16si_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_l32i_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_l32r_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_l8i_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_loop_args,
+    3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_loopz_args,
+    3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_movi_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_movz_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_neg_args,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_nop */,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_return_args,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_simcall */,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_s16i_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_s32i_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_s32nb_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_s8i_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_sar_args,
+    1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_sari_args,
+    1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_shifts_args,
+    1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_shiftst_args,
+    1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_shiftt_args,
+    1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_slli_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_srai_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_srli_args,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_memw */,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_extw */,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_isync */,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_sync */,
+    1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_rsil_args,
+    6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_lend_args,
+    1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_lend_args,
+    1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_lend_args,
+    1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_lcount_args,
+    1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_lcount_args,
+    2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_lcount_args,
+    2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_lbeg_args,
+    1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_lbeg_args,
+    1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_lbeg_args,
+    1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_sar_args,
+    1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_sar_args,
+    2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_sar_args,
+    1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_memctl_args,
+    1, Iclass_xt_iclass_rsr_memctl_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_memctl_args,
+    1, Iclass_xt_iclass_wsr_memctl_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_memctl_args,
+    1, Iclass_xt_iclass_xsr_memctl_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_litbase_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_litbase_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_litbase_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_configid0_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_configid0_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_configid1_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ps_args,
+    6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ps_args,
+    6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ps_args,
+    6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_epc1_args,
+    1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_epc1_args,
+    1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_epc1_args,
+    1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_excsave1_args,
+    1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_excsave1_args,
+    1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_excsave1_args,
+    1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_epc2_args,
+    1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_epc2_args,
+    1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_epc2_args,
+    1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_excsave2_args,
+    1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_excsave2_args,
+    1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_excsave2_args,
+    1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_epc3_args,
+    1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_epc3_args,
+    1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_epc3_args,
+    1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_excsave3_args,
+    1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_excsave3_args,
+    1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_excsave3_args,
+    1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_epc4_args,
+    1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_epc4_args,
+    1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_epc4_args,
+    1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_excsave4_args,
+    1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_excsave4_args,
+    1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_excsave4_args,
+    1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_epc5_args,
+    1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_epc5_args,
+    1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_epc5_args,
+    1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_excsave5_args,
+    1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_excsave5_args,
+    1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_excsave5_args,
+    1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_epc6_args,
+    1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_epc6_args,
+    1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_epc6_args,
+    1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_excsave6_args,
+    1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_excsave6_args,
+    1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_excsave6_args,
+    1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_epc7_args,
+    1, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_epc7_args,
+    1, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_epc7_args,
+    1, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_excsave7_args,
+    1, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_excsave7_args,
+    1, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_excsave7_args,
+    1, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_eps2_args,
+    1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_eps2_args,
+    1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_eps2_args,
+    1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_eps3_args,
+    1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_eps3_args,
+    1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_eps3_args,
+    1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_eps4_args,
+    1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_eps4_args,
+    1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_eps4_args,
+    1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_eps5_args,
+    1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_eps5_args,
+    1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_eps5_args,
+    1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_eps6_args,
+    1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_eps6_args,
+    1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_eps6_args,
+    1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_eps7_args,
+    1, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_eps7_args,
+    1, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_eps7_args,
+    1, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_excvaddr_args,
+    1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_excvaddr_args,
+    1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_excvaddr_args,
+    1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_depc_args,
+    1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_depc_args,
+    1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_depc_args,
+    1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_exccause_args,
+    2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_exccause_args,
+    1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_exccause_args,
+    1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_misc0_args,
+    1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_misc0_args,
+    1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_misc0_args,
+    1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_misc1_args,
+    1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_misc1_args,
+    1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_misc1_args,
+    1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_misc2_args,
+    1, Iclass_xt_iclass_rsr_misc2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_misc2_args,
+    1, Iclass_xt_iclass_wsr_misc2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_misc2_args,
+    1, Iclass_xt_iclass_xsr_misc2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_misc3_args,
+    1, Iclass_xt_iclass_rsr_misc3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_misc3_args,
+    1, Iclass_xt_iclass_wsr_misc3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_misc3_args,
+    1, Iclass_xt_iclass_xsr_misc3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_prid_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_vecbase_args,
+    1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_vecbase_args,
+    1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_vecbase_args,
+    1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
+  { 3, Iclass_xt_mul16_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_mul32_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_mul32h_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_mac16_aa_args,
+    1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_mac16_ad_args,
+    1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_mac16_da_args,
+    1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_mac16_dd_args,
+    1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_mac16a_aa_args,
+    1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_mac16a_ad_args,
+    1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_mac16a_da_args,
+    1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_mac16a_dd_args,
+    1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
+  { 4, Iclass_xt_iclass_mac16al_da_args,
+    1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
+  { 4, Iclass_xt_iclass_mac16al_dd_args,
+    1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_mac16_l_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_rsr_m0_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_wsr_m0_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_xsr_m0_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_rsr_m1_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_wsr_m1_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_xsr_m1_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_rsr_m2_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_wsr_m2_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_xsr_m2_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_rsr_m3_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_wsr_m3_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_xsr_m3_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_acclo_args,
+    1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_acclo_args,
+    1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_acclo_args,
+    1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_acchi_args,
+    1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_acchi_args,
+    1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_acchi_args,
+    1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rfi_args,
+    20, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wait_args,
+    1, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_interrupt_args,
+    1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_intset_args,
+    2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_intclear_args,
+    2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_intenable_args,
+    1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_intenable_args,
+    1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_intenable_args,
+    1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_break_args,
+    2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_break_n_args,
+    2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
+    1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
+    2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
+    2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
+    1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
+    2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
+    2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
+    1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
+    2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
+    2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
+    1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
+    2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
+    2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
+    1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
+    1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
+    1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
+    1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
+    1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
+    1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
+    1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
+    1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
+    1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_debugcause_args,
+    2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_debugcause_args,
+    2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_debugcause_args,
+    2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_icount_args,
+    1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_icount_args,
+    2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_icount_args,
+    2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_icountlevel_args,
+    1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_icountlevel_args,
+    1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_icountlevel_args,
+    1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ddr_args,
+    1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ddr_args,
+    2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ddr_args,
+    2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_lddr32_p_args,
+    3, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_sddr32_p_args,
+    2, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rfdo_args,
+    9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
+  { 0, 0 /* xt_iclass_rfdd */,
+    1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_mmid_args,
+    1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_bbool1_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_bbool4_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_bbool8_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_bbranch_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_bmove_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_RSR_BR_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_WSR_BR_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_XSR_BR_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ccount_args,
+    1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ccount_args,
+    2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ccount_args,
+    2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ccompare0_args,
+    1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ccompare0_args,
+    2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ccompare0_args,
+    2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ccompare1_args,
+    1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ccompare1_args,
+    2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ccompare1_args,
+    2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ccompare2_args,
+    1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ccompare2_args,
+    2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ccompare2_args,
+    2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_idtlb_args,
+    1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_rdtlb_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_wdtlb_args,
+    1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_iitlb_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_ritlb_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_witlb_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_cpenable_args,
+    1, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_cpenable_args,
+    1, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_cpenable_args,
+    1, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_clamp_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_minmax_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_nsa_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_sx_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_l32ai_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_s32ri_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_s32c1i_args,
+    3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_scompare1_args,
+    1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_scompare1_args,
+    1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_scompare1_args,
+    1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_atomctl_args,
+    1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_atomctl_args,
+    2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_atomctl_args,
+    2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_div_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_rer_args,
+    1, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs },
+  { 2, Iclass_xt_iclass_wer_args,
+    1, Iclass_xt_iclass_wer_stateArgs, 2, Iclass_xt_iclass_wer_intfArgs },
+  { 5, Iclass_iclass_F64ITER_args,
+    2, Iclass_iclass_F64ITER_stateArgs, 0, 0 },
+  { 4, Iclass_iclass_F64RND_args,
+    2, Iclass_iclass_F64RND_stateArgs, 0, 0 },
+  { 4, Iclass_iclass_F64ADDC_F64SUBC_args,
+    1, Iclass_iclass_F64ADDC_F64SUBC_stateArgs, 0, 0 },
+  { 2, Iclass_iclass_F64SIG_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_iclass_F64CMPL_args,
+    1, Iclass_iclass_F64CMPL_stateArgs, 0, 0 },
+  { 4, Iclass_iclass_F64CMPH_args,
+    3, Iclass_iclass_F64CMPH_stateArgs, 0, 0 },
+  { 4, Iclass_iclass_F64NORM_args,
+    2, Iclass_iclass_F64NORM_stateArgs, 0, 0 },
+  { 3, Iclass_iclass_F64SEXP_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_iclass_RF64R_args,
+    1, Iclass_iclass_RF64R_stateArgs, 0, 0 },
+  { 3, Iclass_iclass_WF64R_args,
+    1, Iclass_iclass_WF64R_stateArgs, 0, 0 },
+  { 1, Iclass_rur_f64r_lo_args,
+    1, Iclass_rur_f64r_lo_stateArgs, 0, 0 },
+  { 1, Iclass_wur_f64r_lo_args,
+    1, Iclass_wur_f64r_lo_stateArgs, 0, 0 },
+  { 1, Iclass_rur_f64r_hi_args,
+    1, Iclass_rur_f64r_hi_stateArgs, 0, 0 },
+  { 1, Iclass_wur_f64r_hi_args,
+    1, Iclass_wur_f64r_hi_stateArgs, 0, 0 },
+  { 1, Iclass_rur_f64s_args,
+    1, Iclass_rur_f64s_stateArgs, 0, 0 },
+  { 1, Iclass_wur_f64s_args,
+    1, Iclass_wur_f64s_stateArgs, 0, 0 },
+  { 1, Iclass_rur_fcr_args,
+    9, Iclass_rur_fcr_stateArgs, 0, 0 },
+  { 1, Iclass_wur_fcr_args,
+    9, Iclass_wur_fcr_stateArgs, 0, 0 },
+  { 1, Iclass_rur_fsr_args,
+    8, Iclass_rur_fsr_stateArgs, 0, 0 },
+  { 1, Iclass_wur_fsr_args,
+    8, Iclass_wur_fsr_stateArgs, 0, 0 },
+  { 1, Iclass_rur_expstate_args,
+    1, Iclass_rur_expstate_stateArgs, 0, 0 },
+  { 1, Iclass_wur_expstate_args,
+    1, Iclass_wur_expstate_stateArgs, 0, 0 },
+  { 1, Iclass_iclass_READ_IMPWIRE_args,
+    0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs },
+  { 1, Iclass_iclass_SETB_EXPSTATE_args,
+    1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
+  { 1, Iclass_iclass_CLRB_EXPSTATE_args,
+    1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
+  { 2, Iclass_iclass_WRMSK_EXPSTATE_args,
+    1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }
+};
+
+enum xtensa_iclass_id {
+  ICLASS_LSI,
+  ICLASS_LSIP,
+  ICLASS_LSX,
+  ICLASS_LSXP,
+  ICLASS_SSI,
+  ICLASS_SSIP,
+  ICLASS_SSX,
+  ICLASS_SSXP,
+  ICLASS_ABS_S,
+  ICLASS_NEG_S,
+  ICLASS_MOV_S,
+  ICLASS_MOVEQZ_S,
+  ICLASS_MOVNEZ_S,
+  ICLASS_MOVLTZ_S,
+  ICLASS_MOVGEZ_S,
+  ICLASS_MOVF_S,
+  ICLASS_MOVT_S,
+  ICLASS_WFR,
+  ICLASS_RFR,
+  ICLASS_ROUND_S,
+  ICLASS_CEIL_S,
+  ICLASS_FLOOR_S,
+  ICLASS_TRUNC_S,
+  ICLASS_UTRUNC_S,
+  ICLASS_FLOAT_S,
+  ICLASS_UFLOAT_S,
+  ICLASS_UN_S,
+  ICLASS_ULT_S,
+  ICLASS_ULE_S,
+  ICLASS_UEQ_S,
+  ICLASS_OLT_S,
+  ICLASS_OLE_S,
+  ICLASS_OEQ_S,
+  ICLASS_ADD_S,
+  ICLASS_SUB_S,
+  ICLASS_MUL_S,
+  ICLASS_MADD_S,
+  ICLASS_MSUB_S,
+  ICLASS_SQRT0_S,
+  ICLASS_DIV0_S,
+  ICLASS_RECIP0_S,
+  ICLASS_RSQRT0_S,
+  ICLASS_MADDN_S,
+  ICLASS_DIVN_S,
+  ICLASS_CONST_S,
+  ICLASS_NEXP01_S,
+  ICLASS_ADDEXP_S,
+  ICLASS_ADDEXPM_S,
+  ICLASS_MKDADJ_S,
+  ICLASS_MKSADJ_S,
+  ICLASS_xt_iclass_excw,
+  ICLASS_xt_iclass_rfe,
+  ICLASS_xt_iclass_rfde,
+  ICLASS_xt_iclass_syscall,
+  ICLASS_xt_iclass_call12,
+  ICLASS_xt_iclass_call8,
+  ICLASS_xt_iclass_call4,
+  ICLASS_xt_iclass_callx12,
+  ICLASS_xt_iclass_callx8,
+  ICLASS_xt_iclass_callx4,
+  ICLASS_xt_iclass_entry,
+  ICLASS_xt_iclass_movsp,
+  ICLASS_xt_iclass_rotw,
+  ICLASS_xt_iclass_retw,
+  ICLASS_xt_iclass_rfwou,
+  ICLASS_xt_iclass_l32e,
+  ICLASS_xt_iclass_s32e,
+  ICLASS_xt_iclass_rsr_windowbase,
+  ICLASS_xt_iclass_wsr_windowbase,
+  ICLASS_xt_iclass_xsr_windowbase,
+  ICLASS_xt_iclass_rsr_windowstart,
+  ICLASS_xt_iclass_wsr_windowstart,
+  ICLASS_xt_iclass_xsr_windowstart,
+  ICLASS_xt_iclass_add_n,
+  ICLASS_xt_iclass_addi_n,
+  ICLASS_xt_iclass_bz6,
+  ICLASS_xt_iclass_ill_n,
+  ICLASS_xt_iclass_loadi4,
+  ICLASS_xt_iclass_mov_n,
+  ICLASS_xt_iclass_movi_n,
+  ICLASS_xt_iclass_nopn,
+  ICLASS_xt_iclass_retn,
+  ICLASS_xt_iclass_storei4,
+  ICLASS_rur_threadptr,
+  ICLASS_wur_threadptr,
+  ICLASS_xt_iclass_addi,
+  ICLASS_xt_iclass_addmi,
+  ICLASS_xt_iclass_addsub,
+  ICLASS_xt_iclass_bit,
+  ICLASS_xt_iclass_bsi8,
+  ICLASS_xt_iclass_bsi8b,
+  ICLASS_xt_iclass_bsi8u,
+  ICLASS_xt_iclass_bst8,
+  ICLASS_xt_iclass_bsz12,
+  ICLASS_xt_iclass_call0,
+  ICLASS_xt_iclass_callx0,
+  ICLASS_xt_iclass_exti,
+  ICLASS_xt_iclass_ill,
+  ICLASS_xt_iclass_jump,
+  ICLASS_xt_iclass_jumpx,
+  ICLASS_xt_iclass_l16ui,
+  ICLASS_xt_iclass_l16si,
+  ICLASS_xt_iclass_l32i,
+  ICLASS_xt_iclass_l32r,
+  ICLASS_xt_iclass_l8i,
+  ICLASS_xt_iclass_loop,
+  ICLASS_xt_iclass_loopz,
+  ICLASS_xt_iclass_movi,
+  ICLASS_xt_iclass_movz,
+  ICLASS_xt_iclass_neg,
+  ICLASS_xt_iclass_nop,
+  ICLASS_xt_iclass_return,
+  ICLASS_xt_iclass_simcall,
+  ICLASS_xt_iclass_s16i,
+  ICLASS_xt_iclass_s32i,
+  ICLASS_xt_iclass_s32nb,
+  ICLASS_xt_iclass_s8i,
+  ICLASS_xt_iclass_sar,
+  ICLASS_xt_iclass_sari,
+  ICLASS_xt_iclass_shifts,
+  ICLASS_xt_iclass_shiftst,
+  ICLASS_xt_iclass_shiftt,
+  ICLASS_xt_iclass_slli,
+  ICLASS_xt_iclass_srai,
+  ICLASS_xt_iclass_srli,
+  ICLASS_xt_iclass_memw,
+  ICLASS_xt_iclass_extw,
+  ICLASS_xt_iclass_isync,
+  ICLASS_xt_iclass_sync,
+  ICLASS_xt_iclass_rsil,
+  ICLASS_xt_iclass_rsr_lend,
+  ICLASS_xt_iclass_wsr_lend,
+  ICLASS_xt_iclass_xsr_lend,
+  ICLASS_xt_iclass_rsr_lcount,
+  ICLASS_xt_iclass_wsr_lcount,
+  ICLASS_xt_iclass_xsr_lcount,
+  ICLASS_xt_iclass_rsr_lbeg,
+  ICLASS_xt_iclass_wsr_lbeg,
+  ICLASS_xt_iclass_xsr_lbeg,
+  ICLASS_xt_iclass_rsr_sar,
+  ICLASS_xt_iclass_wsr_sar,
+  ICLASS_xt_iclass_xsr_sar,
+  ICLASS_xt_iclass_rsr_memctl,
+  ICLASS_xt_iclass_wsr_memctl,
+  ICLASS_xt_iclass_xsr_memctl,
+  ICLASS_xt_iclass_rsr_litbase,
+  ICLASS_xt_iclass_wsr_litbase,
+  ICLASS_xt_iclass_xsr_litbase,
+  ICLASS_xt_iclass_rsr_configid0,
+  ICLASS_xt_iclass_wsr_configid0,
+  ICLASS_xt_iclass_rsr_configid1,
+  ICLASS_xt_iclass_rsr_ps,
+  ICLASS_xt_iclass_wsr_ps,
+  ICLASS_xt_iclass_xsr_ps,
+  ICLASS_xt_iclass_rsr_epc1,
+  ICLASS_xt_iclass_wsr_epc1,
+  ICLASS_xt_iclass_xsr_epc1,
+  ICLASS_xt_iclass_rsr_excsave1,
+  ICLASS_xt_iclass_wsr_excsave1,
+  ICLASS_xt_iclass_xsr_excsave1,
+  ICLASS_xt_iclass_rsr_epc2,
+  ICLASS_xt_iclass_wsr_epc2,
+  ICLASS_xt_iclass_xsr_epc2,
+  ICLASS_xt_iclass_rsr_excsave2,
+  ICLASS_xt_iclass_wsr_excsave2,
+  ICLASS_xt_iclass_xsr_excsave2,
+  ICLASS_xt_iclass_rsr_epc3,
+  ICLASS_xt_iclass_wsr_epc3,
+  ICLASS_xt_iclass_xsr_epc3,
+  ICLASS_xt_iclass_rsr_excsave3,
+  ICLASS_xt_iclass_wsr_excsave3,
+  ICLASS_xt_iclass_xsr_excsave3,
+  ICLASS_xt_iclass_rsr_epc4,
+  ICLASS_xt_iclass_wsr_epc4,
+  ICLASS_xt_iclass_xsr_epc4,
+  ICLASS_xt_iclass_rsr_excsave4,
+  ICLASS_xt_iclass_wsr_excsave4,
+  ICLASS_xt_iclass_xsr_excsave4,
+  ICLASS_xt_iclass_rsr_epc5,
+  ICLASS_xt_iclass_wsr_epc5,
+  ICLASS_xt_iclass_xsr_epc5,
+  ICLASS_xt_iclass_rsr_excsave5,
+  ICLASS_xt_iclass_wsr_excsave5,
+  ICLASS_xt_iclass_xsr_excsave5,
+  ICLASS_xt_iclass_rsr_epc6,
+  ICLASS_xt_iclass_wsr_epc6,
+  ICLASS_xt_iclass_xsr_epc6,
+  ICLASS_xt_iclass_rsr_excsave6,
+  ICLASS_xt_iclass_wsr_excsave6,
+  ICLASS_xt_iclass_xsr_excsave6,
+  ICLASS_xt_iclass_rsr_epc7,
+  ICLASS_xt_iclass_wsr_epc7,
+  ICLASS_xt_iclass_xsr_epc7,
+  ICLASS_xt_iclass_rsr_excsave7,
+  ICLASS_xt_iclass_wsr_excsave7,
+  ICLASS_xt_iclass_xsr_excsave7,
+  ICLASS_xt_iclass_rsr_eps2,
+  ICLASS_xt_iclass_wsr_eps2,
+  ICLASS_xt_iclass_xsr_eps2,
+  ICLASS_xt_iclass_rsr_eps3,
+  ICLASS_xt_iclass_wsr_eps3,
+  ICLASS_xt_iclass_xsr_eps3,
+  ICLASS_xt_iclass_rsr_eps4,
+  ICLASS_xt_iclass_wsr_eps4,
+  ICLASS_xt_iclass_xsr_eps4,
+  ICLASS_xt_iclass_rsr_eps5,
+  ICLASS_xt_iclass_wsr_eps5,
+  ICLASS_xt_iclass_xsr_eps5,
+  ICLASS_xt_iclass_rsr_eps6,
+  ICLASS_xt_iclass_wsr_eps6,
+  ICLASS_xt_iclass_xsr_eps6,
+  ICLASS_xt_iclass_rsr_eps7,
+  ICLASS_xt_iclass_wsr_eps7,
+  ICLASS_xt_iclass_xsr_eps7,
+  ICLASS_xt_iclass_rsr_excvaddr,
+  ICLASS_xt_iclass_wsr_excvaddr,
+  ICLASS_xt_iclass_xsr_excvaddr,
+  ICLASS_xt_iclass_rsr_depc,
+  ICLASS_xt_iclass_wsr_depc,
+  ICLASS_xt_iclass_xsr_depc,
+  ICLASS_xt_iclass_rsr_exccause,
+  ICLASS_xt_iclass_wsr_exccause,
+  ICLASS_xt_iclass_xsr_exccause,
+  ICLASS_xt_iclass_rsr_misc0,
+  ICLASS_xt_iclass_wsr_misc0,
+  ICLASS_xt_iclass_xsr_misc0,
+  ICLASS_xt_iclass_rsr_misc1,
+  ICLASS_xt_iclass_wsr_misc1,
+  ICLASS_xt_iclass_xsr_misc1,
+  ICLASS_xt_iclass_rsr_misc2,
+  ICLASS_xt_iclass_wsr_misc2,
+  ICLASS_xt_iclass_xsr_misc2,
+  ICLASS_xt_iclass_rsr_misc3,
+  ICLASS_xt_iclass_wsr_misc3,
+  ICLASS_xt_iclass_xsr_misc3,
+  ICLASS_xt_iclass_rsr_prid,
+  ICLASS_xt_iclass_rsr_vecbase,
+  ICLASS_xt_iclass_wsr_vecbase,
+  ICLASS_xt_iclass_xsr_vecbase,
+  ICLASS_xt_mul16,
+  ICLASS_xt_mul32,
+  ICLASS_xt_mul32h,
+  ICLASS_xt_iclass_mac16_aa,
+  ICLASS_xt_iclass_mac16_ad,
+  ICLASS_xt_iclass_mac16_da,
+  ICLASS_xt_iclass_mac16_dd,
+  ICLASS_xt_iclass_mac16a_aa,
+  ICLASS_xt_iclass_mac16a_ad,
+  ICLASS_xt_iclass_mac16a_da,
+  ICLASS_xt_iclass_mac16a_dd,
+  ICLASS_xt_iclass_mac16al_da,
+  ICLASS_xt_iclass_mac16al_dd,
+  ICLASS_xt_iclass_mac16_l,
+  ICLASS_xt_iclass_rsr_m0,
+  ICLASS_xt_iclass_wsr_m0,
+  ICLASS_xt_iclass_xsr_m0,
+  ICLASS_xt_iclass_rsr_m1,
+  ICLASS_xt_iclass_wsr_m1,
+  ICLASS_xt_iclass_xsr_m1,
+  ICLASS_xt_iclass_rsr_m2,
+  ICLASS_xt_iclass_wsr_m2,
+  ICLASS_xt_iclass_xsr_m2,
+  ICLASS_xt_iclass_rsr_m3,
+  ICLASS_xt_iclass_wsr_m3,
+  ICLASS_xt_iclass_xsr_m3,
+  ICLASS_xt_iclass_rsr_acclo,
+  ICLASS_xt_iclass_wsr_acclo,
+  ICLASS_xt_iclass_xsr_acclo,
+  ICLASS_xt_iclass_rsr_acchi,
+  ICLASS_xt_iclass_wsr_acchi,
+  ICLASS_xt_iclass_xsr_acchi,
+  ICLASS_xt_iclass_rfi,
+  ICLASS_xt_iclass_wait,
+  ICLASS_xt_iclass_rsr_interrupt,
+  ICLASS_xt_iclass_wsr_intset,
+  ICLASS_xt_iclass_wsr_intclear,
+  ICLASS_xt_iclass_rsr_intenable,
+  ICLASS_xt_iclass_wsr_intenable,
+  ICLASS_xt_iclass_xsr_intenable,
+  ICLASS_xt_iclass_break,
+  ICLASS_xt_iclass_break_n,
+  ICLASS_xt_iclass_rsr_dbreaka0,
+  ICLASS_xt_iclass_wsr_dbreaka0,
+  ICLASS_xt_iclass_xsr_dbreaka0,
+  ICLASS_xt_iclass_rsr_dbreakc0,
+  ICLASS_xt_iclass_wsr_dbreakc0,
+  ICLASS_xt_iclass_xsr_dbreakc0,
+  ICLASS_xt_iclass_rsr_dbreaka1,
+  ICLASS_xt_iclass_wsr_dbreaka1,
+  ICLASS_xt_iclass_xsr_dbreaka1,
+  ICLASS_xt_iclass_rsr_dbreakc1,
+  ICLASS_xt_iclass_wsr_dbreakc1,
+  ICLASS_xt_iclass_xsr_dbreakc1,
+  ICLASS_xt_iclass_rsr_ibreaka0,
+  ICLASS_xt_iclass_wsr_ibreaka0,
+  ICLASS_xt_iclass_xsr_ibreaka0,
+  ICLASS_xt_iclass_rsr_ibreaka1,
+  ICLASS_xt_iclass_wsr_ibreaka1,
+  ICLASS_xt_iclass_xsr_ibreaka1,
+  ICLASS_xt_iclass_rsr_ibreakenable,
+  ICLASS_xt_iclass_wsr_ibreakenable,
+  ICLASS_xt_iclass_xsr_ibreakenable,
+  ICLASS_xt_iclass_rsr_debugcause,
+  ICLASS_xt_iclass_wsr_debugcause,
+  ICLASS_xt_iclass_xsr_debugcause,
+  ICLASS_xt_iclass_rsr_icount,
+  ICLASS_xt_iclass_wsr_icount,
+  ICLASS_xt_iclass_xsr_icount,
+  ICLASS_xt_iclass_rsr_icountlevel,
+  ICLASS_xt_iclass_wsr_icountlevel,
+  ICLASS_xt_iclass_xsr_icountlevel,
+  ICLASS_xt_iclass_rsr_ddr,
+  ICLASS_xt_iclass_wsr_ddr,
+  ICLASS_xt_iclass_xsr_ddr,
+  ICLASS_xt_iclass_lddr32_p,
+  ICLASS_xt_iclass_sddr32_p,
+  ICLASS_xt_iclass_rfdo,
+  ICLASS_xt_iclass_rfdd,
+  ICLASS_xt_iclass_wsr_mmid,
+  ICLASS_xt_iclass_bbool1,
+  ICLASS_xt_iclass_bbool4,
+  ICLASS_xt_iclass_bbool8,
+  ICLASS_xt_iclass_bbranch,
+  ICLASS_xt_iclass_bmove,
+  ICLASS_xt_iclass_RSR_BR,
+  ICLASS_xt_iclass_WSR_BR,
+  ICLASS_xt_iclass_XSR_BR,
+  ICLASS_xt_iclass_rsr_ccount,
+  ICLASS_xt_iclass_wsr_ccount,
+  ICLASS_xt_iclass_xsr_ccount,
+  ICLASS_xt_iclass_rsr_ccompare0,
+  ICLASS_xt_iclass_wsr_ccompare0,
+  ICLASS_xt_iclass_xsr_ccompare0,
+  ICLASS_xt_iclass_rsr_ccompare1,
+  ICLASS_xt_iclass_wsr_ccompare1,
+  ICLASS_xt_iclass_xsr_ccompare1,
+  ICLASS_xt_iclass_rsr_ccompare2,
+  ICLASS_xt_iclass_wsr_ccompare2,
+  ICLASS_xt_iclass_xsr_ccompare2,
+  ICLASS_xt_iclass_idtlb,
+  ICLASS_xt_iclass_rdtlb,
+  ICLASS_xt_iclass_wdtlb,
+  ICLASS_xt_iclass_iitlb,
+  ICLASS_xt_iclass_ritlb,
+  ICLASS_xt_iclass_witlb,
+  ICLASS_xt_iclass_rsr_cpenable,
+  ICLASS_xt_iclass_wsr_cpenable,
+  ICLASS_xt_iclass_xsr_cpenable,
+  ICLASS_xt_iclass_clamp,
+  ICLASS_xt_iclass_minmax,
+  ICLASS_xt_iclass_nsa,
+  ICLASS_xt_iclass_sx,
+  ICLASS_xt_iclass_l32ai,
+  ICLASS_xt_iclass_s32ri,
+  ICLASS_xt_iclass_s32c1i,
+  ICLASS_xt_iclass_rsr_scompare1,
+  ICLASS_xt_iclass_wsr_scompare1,
+  ICLASS_xt_iclass_xsr_scompare1,
+  ICLASS_xt_iclass_rsr_atomctl,
+  ICLASS_xt_iclass_wsr_atomctl,
+  ICLASS_xt_iclass_xsr_atomctl,
+  ICLASS_xt_iclass_div,
+  ICLASS_xt_iclass_rer,
+  ICLASS_xt_iclass_wer,
+  ICLASS_iclass_F64ITER,
+  ICLASS_iclass_F64RND,
+  ICLASS_iclass_F64ADDC_F64SUBC,
+  ICLASS_iclass_F64SIG,
+  ICLASS_iclass_F64CMPL,
+  ICLASS_iclass_F64CMPH,
+  ICLASS_iclass_F64NORM,
+  ICLASS_iclass_F64SEXP,
+  ICLASS_iclass_RF64R,
+  ICLASS_iclass_WF64R,
+  ICLASS_rur_f64r_lo,
+  ICLASS_wur_f64r_lo,
+  ICLASS_rur_f64r_hi,
+  ICLASS_wur_f64r_hi,
+  ICLASS_rur_f64s,
+  ICLASS_wur_f64s,
+  ICLASS_rur_fcr,
+  ICLASS_wur_fcr,
+  ICLASS_rur_fsr,
+  ICLASS_wur_fsr,
+  ICLASS_rur_expstate,
+  ICLASS_wur_expstate,
+  ICLASS_iclass_READ_IMPWIRE,
+  ICLASS_iclass_SETB_EXPSTATE,
+  ICLASS_iclass_CLRB_EXPSTATE,
+  ICLASS_iclass_WRMSK_EXPSTATE
+};
+
+\f
+/*  Opcode encodings.  */
+
+static void
+Opcode_lsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3;
+}
+
+static void
+Opcode_lsip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8003;
+}
+
+static void
+Opcode_lsx_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x80000;
+}
+
+static void
+Opcode_lsxp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x180000;
+}
+
+static void
+Opcode_ssi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x4003;
+}
+
+static void
+Opcode_ssip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc003;
+}
+
+static void
+Opcode_ssx_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x480000;
+}
+
+static void
+Opcode_ssxp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x580000;
+}
+
+static void
+Opcode_abs_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa0010;
+}
+
+static void
+Opcode_neg_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa0060;
+}
+
+static void
+Opcode_mov_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa0000;
+}
+
+static void
+Opcode_moveqz_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8b0000;
+}
+
+static void
+Opcode_movnez_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x9b0000;
+}
+
+static void
+Opcode_movltz_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xab0000;
+}
+
+static void
+Opcode_movgez_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xbb0000;
+}
+
+static void
+Opcode_movf_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcb0000;
+}
+
+static void
+Opcode_movt_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xdb0000;
+}
+
+static void
+Opcode_wfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa0050;
+}
+
+static void
+Opcode_rfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa0040;
+}
+
+static void
+Opcode_round_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8a0000;
+}
+
+static void
+Opcode_ceil_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xba0000;
+}
+
+static void
+Opcode_floor_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xaa0000;
+}
+
+static void
+Opcode_trunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x9a0000;
+}
+
+static void
+Opcode_utrunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xea0000;
+}
+
+static void
+Opcode_float_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xca0000;
+}
+
+static void
+Opcode_ufloat_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xda0000;
+}
+
+static void
+Opcode_un_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1b0000;
+}
+
+static void
+Opcode_ult_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x5b0000;
+}
+
+static void
+Opcode_ule_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x7b0000;
+}
+
+static void
+Opcode_ueq_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b0000;
+}
+
+static void
+Opcode_olt_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x4b0000;
+}
+
+static void
+Opcode_ole_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6b0000;
+}
+
+static void
+Opcode_oeq_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2b0000;
+}
+
+static void
+Opcode_add_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa0000;
+}
+
+static void
+Opcode_sub_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1a0000;
+}
+
+static void
+Opcode_mul_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2a0000;
+}
+
+static void
+Opcode_madd_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x4a0000;
+}
+
+static void
+Opcode_msub_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x5a0000;
+}
+
+static void
+Opcode_sqrt0_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa0090;
+}
+
+static void
+Opcode_div0_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa0070;
+}
+
+static void
+Opcode_recip0_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa0080;
+}
+
+static void
+Opcode_rsqrt0_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa00a0;
+}
+
+static void
+Opcode_maddn_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6a0000;
+}
+
+static void
+Opcode_divn_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x7a0000;
+}
+
+static void
+Opcode_const_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa0030;
+}
+
+static void
+Opcode_nexp01_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa00b0;
+}
+
+static void
+Opcode_addexp_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa00e0;
+}
+
+static void
+Opcode_addexpm_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa00f0;
+}
+
+static void
+Opcode_mkdadj_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa00d0;
+}
+
+static void
+Opcode_mksadj_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa00c0;
+}
+
+static void
+Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2080;
+}
+
+static void
+Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3000;
+}
+
+static void
+Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3200;
+}
+
+static void
+Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x5000;
+}
+
+static void
+Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x35;
+}
+
+static void
+Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x25;
+}
+
+static void
+Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x15;
+}
+
+static void
+Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf0;
+}
+
+static void
+Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe0;
+}
+
+static void
+Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd0;
+}
+
+static void
+Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x36;
+}
+
+static void
+Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1000;
+}
+
+static void
+Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x408000;
+}
+
+static void
+Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x90;
+}
+
+static void
+Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf01d;
+}
+
+static void
+Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3400;
+}
+
+static void
+Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3500;
+}
+
+static void
+Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x90000;
+}
+
+static void
+Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x490000;
+}
+
+static void
+Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x34800;
+}
+
+static void
+Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x134800;
+}
+
+static void
+Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x614800;
+}
+
+static void
+Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x34900;
+}
+
+static void
+Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x134900;
+}
+
+static void
+Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x614900;
+}
+
+static void
+Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa;
+}
+
+static void
+Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb;
+}
+
+static void
+Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8c;
+}
+
+static void
+Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcc;
+}
+
+static void
+Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf06d;
+}
+
+static void
+Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8;
+}
+
+static void
+Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd;
+}
+
+static void
+Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc;
+}
+
+static void
+Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf03d;
+}
+
+static void
+Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf00d;
+}
+
+static void
+Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x9;
+}
+
+static void
+Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe30e70;
+}
+
+static void
+Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf3e700;
+}
+
+static void
+Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc002;
+}
+
+static void
+Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd002;
+}
+
+static void
+Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x800000;
+}
+
+static void
+Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc00000;
+}
+
+static void
+Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x900000;
+}
+
+static void
+Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa00000;
+}
+
+static void
+Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb00000;
+}
+
+static void
+Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd00000;
+}
+
+static void
+Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe00000;
+}
+
+static void
+Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf00000;
+}
+
+static void
+Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x100000;
+}
+
+static void
+Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x200000;
+}
+
+static void
+Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x300000;
+}
+
+static void
+Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x26;
+}
+
+static void
+Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x66;
+}
+
+static void
+Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe6;
+}
+
+static void
+Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa6;
+}
+
+static void
+Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6007;
+}
+
+static void
+Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe007;
+}
+
+static void
+Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf6;
+}
+
+static void
+Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb6;
+}
+
+static void
+Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1007;
+}
+
+static void
+Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x9007;
+}
+
+static void
+Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa007;
+}
+
+static void
+Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2007;
+}
+
+static void
+Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb007;
+}
+
+static void
+Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3007;
+}
+
+static void
+Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8007;
+}
+
+static void
+Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x7;
+}
+
+static void
+Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x4007;
+}
+
+static void
+Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc007;
+}
+
+static void
+Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x5007;
+}
+
+static void
+Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd007;
+}
+
+static void
+Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x16;
+}
+
+static void
+Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x56;
+}
+
+static void
+Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd6;
+}
+
+static void
+Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x96;
+}
+
+static void
+Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x5;
+}
+
+static void
+Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc0;
+}
+
+static void
+Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x40000;
+}
+
+static void
+Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0;
+}
+
+static void
+Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6;
+}
+
+static void
+Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa0;
+}
+
+static void
+Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1002;
+}
+
+static void
+Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x9002;
+}
+
+static void
+Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2002;
+}
+
+static void
+Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1;
+}
+
+static void
+Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2;
+}
+
+static void
+Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8076;
+}
+
+static void
+Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x9076;
+}
+
+static void
+Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa076;
+}
+
+static void
+Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa002;
+}
+
+static void
+Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x830000;
+}
+
+static void
+Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x930000;
+}
+
+static void
+Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa30000;
+}
+
+static void
+Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb30000;
+}
+
+static void
+Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x600000;
+}
+
+static void
+Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x600100;
+}
+
+static void
+Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x20f0;
+}
+
+static void
+Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x80;
+}
+
+static void
+Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x5100;
+}
+
+static void
+Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x5002;
+}
+
+static void
+Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6002;
+}
+
+static void
+Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x590000;
+}
+
+static void
+Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x4002;
+}
+
+static void
+Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x400000;
+}
+
+static void
+Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x401000;
+}
+
+static void
+Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x402000;
+}
+
+static void
+Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x403000;
+}
+
+static void
+Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x404000;
+}
+
+static void
+Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa10000;
+}
+
+static void
+Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x810000;
+}
+
+static void
+Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x910000;
+}
+
+static void
+Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb10000;
+}
+
+static void
+Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x10000;
+}
+
+static void
+Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x210000;
+}
+
+static void
+Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x410000;
+}
+
+static void
+Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x20c0;
+}
+
+static void
+Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x20d0;
+}
+
+static void
+Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2000;
+}
+
+static void
+Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2010;
+}
+
+static void
+Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2020;
+}
+
+static void
+Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2030;
+}
+
+static void
+Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6000;
+}
+
+static void
+Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x30100;
+}
+
+static void
+Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x130100;
+}
+
+static void
+Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x610100;
+}
+
+static void
+Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x30200;
+}
+
+static void
+Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x130200;
+}
+
+static void
+Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x610200;
+}
+
+static void
+Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x30000;
+}
+
+static void
+Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x130000;
+}
+
+static void
+Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x610000;
+}
+
+static void
+Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x30300;
+}
+
+static void
+Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x130300;
+}
+
+static void
+Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x610300;
+}
+
+static void
+Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x36100;
+}
+
+static void
+Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x136100;
+}
+
+static void
+Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x616100;
+}
+
+static void
+Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x30500;
+}
+
+static void
+Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x130500;
+}
+
+static void
+Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x610500;
+}
+
+static void
+Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b000;
+}
+
+static void
+Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13b000;
+}
+
+static void
+Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d000;
+}
+
+static void
+Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3e600;
+}
+
+static void
+Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13e600;
+}
+
+static void
+Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61e600;
+}
+
+static void
+Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b100;
+}
+
+static void
+Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13b100;
+}
+
+static void
+Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61b100;
+}
+
+static void
+Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d100;
+}
+
+static void
+Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13d100;
+}
+
+static void
+Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61d100;
+}
+
+static void
+Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b200;
+}
+
+static void
+Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13b200;
+}
+
+static void
+Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61b200;
+}
+
+static void
+Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d200;
+}
+
+static void
+Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13d200;
+}
+
+static void
+Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61d200;
+}
+
+static void
+Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b300;
+}
+
+static void
+Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13b300;
+}
+
+static void
+Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61b300;
+}
+
+static void
+Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d300;
+}
+
+static void
+Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13d300;
+}
+
+static void
+Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61d300;
+}
+
+static void
+Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b400;
+}
+
+static void
+Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13b400;
+}
+
+static void
+Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61b400;
+}
+
+static void
+Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d400;
+}
+
+static void
+Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13d400;
+}
+
+static void
+Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61d400;
+}
+
+static void
+Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b500;
+}
+
+static void
+Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13b500;
+}
+
+static void
+Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61b500;
+}
+
+static void
+Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d500;
+}
+
+static void
+Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13d500;
+}
+
+static void
+Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61d500;
+}
+
+static void
+Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b600;
+}
+
+static void
+Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13b600;
+}
+
+static void
+Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61b600;
+}
+
+static void
+Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d600;
+}
+
+static void
+Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13d600;
+}
+
+static void
+Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61d600;
+}
+
+static void
+Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b700;
+}
+
+static void
+Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13b700;
+}
+
+static void
+Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61b700;
+}
+
+static void
+Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d700;
+}
+
+static void
+Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13d700;
+}
+
+static void
+Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61d700;
+}
+
+static void
+Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3c200;
+}
+
+static void
+Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13c200;
+}
+
+static void
+Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61c200;
+}
+
+static void
+Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3c300;
+}
+
+static void
+Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13c300;
+}
+
+static void
+Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61c300;
+}
+
+static void
+Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3c400;
+}
+
+static void
+Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13c400;
+}
+
+static void
+Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61c400;
+}
+
+static void
+Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3c500;
+}
+
+static void
+Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13c500;
+}
+
+static void
+Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61c500;
+}
+
+static void
+Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3c600;
+}
+
+static void
+Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13c600;
+}
+
+static void
+Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61c600;
+}
+
+static void
+Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3c700;
+}
+
+static void
+Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13c700;
+}
+
+static void
+Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61c700;
+}
+
+static void
+Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3ee00;
+}
+
+static void
+Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13ee00;
+}
+
+static void
+Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61ee00;
+}
+
+static void
+Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3c000;
+}
+
+static void
+Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13c000;
+}
+
+static void
+Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61c000;
+}
+
+static void
+Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3e800;
+}
+
+static void
+Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13e800;
+}
+
+static void
+Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61e800;
+}
+
+static void
+Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3f400;
+}
+
+static void
+Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13f400;
+}
+
+static void
+Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61f400;
+}
+
+static void
+Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3f500;
+}
+
+static void
+Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13f500;
+}
+
+static void
+Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61f500;
+}
+
+static void
+Opcode_rsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3f600;
+}
+
+static void
+Opcode_wsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13f600;
+}
+
+static void
+Opcode_xsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61f600;
+}
+
+static void
+Opcode_rsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3f700;
+}
+
+static void
+Opcode_wsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13f700;
+}
+
+static void
+Opcode_xsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61f700;
+}
+
+static void
+Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3eb00;
+}
+
+static void
+Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3e700;
+}
+
+static void
+Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13e700;
+}
+
+static void
+Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61e700;
+}
+
+static void
+Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc10000;
+}
+
+static void
+Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd10000;
+}
+
+static void
+Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x820000;
+}
+
+static void
+Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa20000;
+}
+
+static void
+Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb20000;
+}
+
+static void
+Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x740004;
+}
+
+static void
+Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x750004;
+}
+
+static void
+Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x760004;
+}
+
+static void
+Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x770004;
+}
+
+static void
+Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x700004;
+}
+
+static void
+Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x710004;
+}
+
+static void
+Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x720004;
+}
+
+static void
+Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x730004;
+}
+
+static void
+Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x340004;
+}
+
+static void
+Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x350004;
+}
+
+static void
+Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x360004;
+}
+
+static void
+Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x370004;
+}
+
+static void
+Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x640004;
+}
+
+static void
+Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x650004;
+}
+
+static void
+Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x660004;
+}
+
+static void
+Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x670004;
+}
+
+static void
+Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x240004;
+}
+
+static void
+Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x250004;
+}
+
+static void
+Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x260004;
+}
+
+static void
+Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x270004;
+}
+
+static void
+Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x780004;
+}
+
+static void
+Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x790004;
+}
+
+static void
+Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x7a0004;
+}
+
+static void
+Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x7b0004;
+}
+
+static void
+Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x7c0004;
+}
+
+static void
+Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x7d0004;
+}
+
+static void
+Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x7e0004;
+}
+
+static void
+Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x7f0004;
+}
+
+static void
+Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x380004;
+}
+
+static void
+Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x390004;
+}
+
+static void
+Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3a0004;
+}
+
+static void
+Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b0004;
+}
+
+static void
+Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3c0004;
+}
+
+static void
+Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d0004;
+}
+
+static void
+Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3e0004;
+}
+
+static void
+Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3f0004;
+}
+
+static void
+Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x680004;
+}
+
+static void
+Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x690004;
+}
+
+static void
+Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6a0004;
+}
+
+static void
+Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6b0004;
+}
+
+static void
+Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6c0004;
+}
+
+static void
+Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6d0004;
+}
+
+static void
+Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6e0004;
+}
+
+static void
+Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6f0004;
+}
+
+static void
+Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x280004;
+}
+
+static void
+Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x290004;
+}
+
+static void
+Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2a0004;
+}
+
+static void
+Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2b0004;
+}
+
+static void
+Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2c0004;
+}
+
+static void
+Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2d0004;
+}
+
+static void
+Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2e0004;
+}
+
+static void
+Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2f0004;
+}
+
+static void
+Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x580004;
+}
+
+static void
+Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x480004;
+}
+
+static void
+Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x590004;
+}
+
+static void
+Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x490004;
+}
+
+static void
+Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x5a0004;
+}
+
+static void
+Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x4a0004;
+}
+
+static void
+Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x5b0004;
+}
+
+static void
+Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x4b0004;
+}
+
+static void
+Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x180004;
+}
+
+static void
+Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x80004;
+}
+
+static void
+Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x190004;
+}
+
+static void
+Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x90004;
+}
+
+static void
+Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1a0004;
+}
+
+static void
+Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa0004;
+}
+
+static void
+Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1b0004;
+}
+
+static void
+Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb0004;
+}
+
+static void
+Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x900004;
+}
+
+static void
+Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x800004;
+}
+
+static void
+Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x32000;
+}
+
+static void
+Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x132000;
+}
+
+static void
+Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x612000;
+}
+
+static void
+Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x32100;
+}
+
+static void
+Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x132100;
+}
+
+static void
+Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x612100;
+}
+
+static void
+Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x32200;
+}
+
+static void
+Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x132200;
+}
+
+static void
+Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x612200;
+}
+
+static void
+Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x32300;
+}
+
+static void
+Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x132300;
+}
+
+static void
+Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x612300;
+}
+
+static void
+Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x31000;
+}
+
+static void
+Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x131000;
+}
+
+static void
+Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x611000;
+}
+
+static void
+Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x31100;
+}
+
+static void
+Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x131100;
+}
+
+static void
+Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x611100;
+}
+
+static void
+Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3010;
+}
+
+static void
+Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x7000;
+}
+
+static void
+Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3e200;
+}
+
+static void
+Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13e200;
+}
+
+static void
+Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13e300;
+}
+
+static void
+Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3e400;
+}
+
+static void
+Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13e400;
+}
+
+static void
+Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61e400;
+}
+
+static void
+Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x4000;
+}
+
+static void
+Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf02d;
+}
+
+static void
+Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x39000;
+}
+
+static void
+Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x139000;
+}
+
+static void
+Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x619000;
+}
+
+static void
+Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3a000;
+}
+
+static void
+Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13a000;
+}
+
+static void
+Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61a000;
+}
+
+static void
+Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x39100;
+}
+
+static void
+Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x139100;
+}
+
+static void
+Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x619100;
+}
+
+static void
+Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3a100;
+}
+
+static void
+Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13a100;
+}
+
+static void
+Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61a100;
+}
+
+static void
+Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x38000;
+}
+
+static void
+Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x138000;
+}
+
+static void
+Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x618000;
+}
+
+static void
+Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x38100;
+}
+
+static void
+Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x138100;
+}
+
+static void
+Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x618100;
+}
+
+static void
+Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x36000;
+}
+
+static void
+Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x136000;
+}
+
+static void
+Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x616000;
+}
+
+static void
+Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3e900;
+}
+
+static void
+Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13e900;
+}
+
+static void
+Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61e900;
+}
+
+static void
+Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3ec00;
+}
+
+static void
+Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13ec00;
+}
+
+static void
+Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61ec00;
+}
+
+static void
+Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3ed00;
+}
+
+static void
+Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13ed00;
+}
+
+static void
+Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61ed00;
+}
+
+static void
+Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x36800;
+}
+
+static void
+Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x136800;
+}
+
+static void
+Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x616800;
+}
+
+static void
+Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x70e0;
+}
+
+static void
+Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x70f0;
+}
+
+static void
+Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf1e000;
+}
+
+static void
+Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf1e010;
+}
+
+static void
+Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x135900;
+}
+
+static void
+Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x20000;
+}
+
+static void
+Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x120000;
+}
+
+static void
+Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x220000;
+}
+
+static void
+Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x320000;
+}
+
+static void
+Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x420000;
+}
+
+static void
+Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8000;
+}
+
+static void
+Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x9000;
+}
+
+static void
+Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa000;
+}
+
+static void
+Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb000;
+}
+
+static void
+Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x76;
+}
+
+static void
+Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1076;
+}
+
+static void
+Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc30000;
+}
+
+static void
+Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd30000;
+}
+
+static void
+Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x30400;
+}
+
+static void
+Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x130400;
+}
+
+static void
+Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x610400;
+}
+
+static void
+Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3ea00;
+}
+
+static void
+Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13ea00;
+}
+
+static void
+Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61ea00;
+}
+
+static void
+Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3f000;
+}
+
+static void
+Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13f000;
+}
+
+static void
+Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61f000;
+}
+
+static void
+Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3f100;
+}
+
+static void
+Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13f100;
+}
+
+static void
+Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61f100;
+}
+
+static void
+Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3f200;
+}
+
+static void
+Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13f200;
+}
+
+static void
+Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61f200;
+}
+
+static void
+Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x50c000;
+}
+
+static void
+Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x50d000;
+}
+
+static void
+Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x50b000;
+}
+
+static void
+Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x50f000;
+}
+
+static void
+Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x50e000;
+}
+
+static void
+Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x504000;
+}
+
+static void
+Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x505000;
+}
+
+static void
+Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x503000;
+}
+
+static void
+Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x507000;
+}
+
+static void
+Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x506000;
+}
+
+static void
+Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3e000;
+}
+
+static void
+Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13e000;
+}
+
+static void
+Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61e000;
+}
+
+static void
+Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x330000;
+}
+
+static void
+Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x430000;
+}
+
+static void
+Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x530000;
+}
+
+static void
+Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x630000;
+}
+
+static void
+Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x730000;
+}
+
+static void
+Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x40e000;
+}
+
+static void
+Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x40f000;
+}
+
+static void
+Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x230000;
+}
+
+static void
+Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb002;
+}
+
+static void
+Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf002;
+}
+
+static void
+Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe002;
+}
+
+static void
+Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x30c00;
+}
+
+static void
+Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x130c00;
+}
+
+static void
+Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x610c00;
+}
+
+static void
+Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x36300;
+}
+
+static void
+Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x136300;
+}
+
+static void
+Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x616300;
+}
+
+static void
+Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc20000;
+}
+
+static void
+Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd20000;
+}
+
+static void
+Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe20000;
+}
+
+static void
+Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf20000;
+}
+
+static void
+Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x406000;
+}
+
+static void
+Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x407000;
+}
+
+static void
+Opcode_f64iter_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e0000;
+}
+
+static void
+Opcode_f64rnd_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x4e0000;
+}
+
+static void
+Opcode_f64addc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfb0000;
+}
+
+static void
+Opcode_f64subc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfb8000;
+}
+
+static void
+Opcode_f64sig_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xed000;
+}
+
+static void
+Opcode_f64cmpl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xeb0000;
+}
+
+static void
+Opcode_f64cmph_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf0000;
+}
+
+static void
+Opcode_f64norm_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2e0000;
+}
+
+static void
+Opcode_f64sexp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1e0000;
+}
+
+static void
+Opcode_rf64r_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xbce00;
+}
+
+static void
+Opcode_wf64r_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xbe000;
+}
+
+static void
+Opcode_rur_f64r_lo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe30ea0;
+}
+
+static void
+Opcode_wur_f64r_lo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf3ea00;
+}
+
+static void
+Opcode_rur_f64r_hi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe30eb0;
+}
+
+static void
+Opcode_wur_f64r_hi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf3eb00;
+}
+
+static void
+Opcode_rur_f64s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe30ec0;
+}
+
+static void
+Opcode_wur_f64s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf3ec00;
+}
+
+static void
+Opcode_rur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe30e80;
+}
+
+static void
+Opcode_wur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf3e800;
+}
+
+static void
+Opcode_rur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe30e90;
+}
+
+static void
+Opcode_wur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf3e900;
+}
+
+static void
+Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe30e60;
+}
+
+static void
+Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf3e600;
+}
+
+static void
+Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe0000;
+}
+
+static void
+Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe1000;
+}
+
+static void
+Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe1200;
+}
+
+static void
+Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe2000;
+}
+
+static const xtensa_opcode_encode_fn Opcode_lsi_encode_fns[] = {
+  Opcode_lsi_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_lsip_encode_fns[] = {
+  Opcode_lsip_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_lsx_encode_fns[] = {
+  Opcode_lsx_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_lsxp_encode_fns[] = {
+  Opcode_lsxp_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ssi_encode_fns[] = {
+  Opcode_ssi_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ssip_encode_fns[] = {
+  Opcode_ssip_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ssx_encode_fns[] = {
+  Opcode_ssx_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ssxp_encode_fns[] = {
+  Opcode_ssxp_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_abs_s_encode_fns[] = {
+  Opcode_abs_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_neg_s_encode_fns[] = {
+  Opcode_neg_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mov_s_encode_fns[] = {
+  Opcode_mov_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_moveqz_s_encode_fns[] = {
+  Opcode_moveqz_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movnez_s_encode_fns[] = {
+  Opcode_movnez_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movltz_s_encode_fns[] = {
+  Opcode_movltz_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movgez_s_encode_fns[] = {
+  Opcode_movgez_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movf_s_encode_fns[] = {
+  Opcode_movf_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movt_s_encode_fns[] = {
+  Opcode_movt_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wfr_encode_fns[] = {
+  Opcode_wfr_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rfr_encode_fns[] = {
+  Opcode_rfr_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_round_s_encode_fns[] = {
+  Opcode_round_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ceil_s_encode_fns[] = {
+  Opcode_ceil_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_floor_s_encode_fns[] = {
+  Opcode_floor_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_trunc_s_encode_fns[] = {
+  Opcode_trunc_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_utrunc_s_encode_fns[] = {
+  Opcode_utrunc_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_float_s_encode_fns[] = {
+  Opcode_float_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ufloat_s_encode_fns[] = {
+  Opcode_ufloat_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_un_s_encode_fns[] = {
+  Opcode_un_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ult_s_encode_fns[] = {
+  Opcode_ult_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ule_s_encode_fns[] = {
+  Opcode_ule_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ueq_s_encode_fns[] = {
+  Opcode_ueq_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_olt_s_encode_fns[] = {
+  Opcode_olt_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ole_s_encode_fns[] = {
+  Opcode_ole_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_oeq_s_encode_fns[] = {
+  Opcode_oeq_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_add_s_encode_fns[] = {
+  Opcode_add_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_sub_s_encode_fns[] = {
+  Opcode_sub_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_s_encode_fns[] = {
+  Opcode_mul_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_madd_s_encode_fns[] = {
+  Opcode_madd_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_msub_s_encode_fns[] = {
+  Opcode_msub_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_sqrt0_s_encode_fns[] = {
+  Opcode_sqrt0_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_div0_s_encode_fns[] = {
+  Opcode_div0_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_recip0_s_encode_fns[] = {
+  Opcode_recip0_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsqrt0_s_encode_fns[] = {
+  Opcode_rsqrt0_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_maddn_s_encode_fns[] = {
+  Opcode_maddn_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_divn_s_encode_fns[] = {
+  Opcode_divn_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_const_s_encode_fns[] = {
+  Opcode_const_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_nexp01_s_encode_fns[] = {
+  Opcode_nexp01_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_addexp_s_encode_fns[] = {
+  Opcode_addexp_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_addexpm_s_encode_fns[] = {
+  Opcode_addexpm_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mkdadj_s_encode_fns[] = {
+  Opcode_mkdadj_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mksadj_s_encode_fns[] = {
+  Opcode_mksadj_s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
+  Opcode_excw_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
+  Opcode_rfe_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
+  Opcode_rfde_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
+  Opcode_syscall_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
+  Opcode_call12_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
+  Opcode_call8_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
+  Opcode_call4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
+  Opcode_callx12_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
+  Opcode_callx8_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
+  Opcode_callx4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
+  Opcode_entry_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
+  Opcode_movsp_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
+  Opcode_rotw_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
+  Opcode_retw_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
+  0, 0, Opcode_retw_n_Slot_inst16b_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
+  Opcode_rfwo_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
+  Opcode_rfwu_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
+  Opcode_l32e_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
+  Opcode_s32e_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
+  Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
+  Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
+  Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
+  Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
+  Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
+  Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
+  0, Opcode_add_n_Slot_inst16a_encode, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
+  0, Opcode_addi_n_Slot_inst16a_encode, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
+  0, 0, Opcode_beqz_n_Slot_inst16b_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
+  0, 0, Opcode_bnez_n_Slot_inst16b_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
+  0, 0, Opcode_ill_n_Slot_inst16b_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
+  0, Opcode_l32i_n_Slot_inst16a_encode, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
+  0, 0, Opcode_mov_n_Slot_inst16b_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
+  0, 0, Opcode_movi_n_Slot_inst16b_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
+  0, 0, Opcode_nop_n_Slot_inst16b_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
+  0, 0, Opcode_ret_n_Slot_inst16b_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
+  0, Opcode_s32i_n_Slot_inst16a_encode, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
+  Opcode_rur_threadptr_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
+  Opcode_wur_threadptr_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
+  Opcode_addi_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
+  Opcode_addmi_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
+  Opcode_add_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
+  Opcode_sub_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
+  Opcode_addx2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
+  Opcode_addx4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
+  Opcode_addx8_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
+  Opcode_subx2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
+  Opcode_subx4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
+  Opcode_subx8_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
+  Opcode_and_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
+  Opcode_or_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
+  Opcode_xor_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
+  Opcode_beqi_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
+  Opcode_bnei_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
+  Opcode_bgei_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
+  Opcode_blti_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
+  Opcode_bbci_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
+  Opcode_bbsi_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
+  Opcode_bgeui_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
+  Opcode_bltui_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
+  Opcode_beq_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
+  Opcode_bne_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
+  Opcode_bge_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
+  Opcode_blt_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
+  Opcode_bgeu_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
+  Opcode_bltu_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
+  Opcode_bany_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
+  Opcode_bnone_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
+  Opcode_ball_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
+  Opcode_bnall_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
+  Opcode_bbc_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
+  Opcode_bbs_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
+  Opcode_beqz_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
+  Opcode_bnez_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
+  Opcode_bgez_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
+  Opcode_bltz_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
+  Opcode_call0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
+  Opcode_callx0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
+  Opcode_extui_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
+  Opcode_ill_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
+  Opcode_j_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
+  Opcode_jx_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
+  Opcode_l16ui_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
+  Opcode_l16si_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
+  Opcode_l32i_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
+  Opcode_l32r_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
+  Opcode_l8ui_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
+  Opcode_loop_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
+  Opcode_loopnez_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
+  Opcode_loopgtz_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
+  Opcode_movi_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
+  Opcode_moveqz_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
+  Opcode_movnez_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
+  Opcode_movltz_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
+  Opcode_movgez_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
+  Opcode_neg_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
+  Opcode_abs_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
+  Opcode_nop_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
+  Opcode_ret_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
+  Opcode_simcall_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
+  Opcode_s16i_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
+  Opcode_s32i_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = {
+  Opcode_s32nb_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
+  Opcode_s8i_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
+  Opcode_ssr_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
+  Opcode_ssl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
+  Opcode_ssa8l_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
+  Opcode_ssa8b_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
+  Opcode_ssai_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
+  Opcode_sll_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
+  Opcode_src_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
+  Opcode_srl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
+  Opcode_sra_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
+  Opcode_slli_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
+  Opcode_srai_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
+  Opcode_srli_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
+  Opcode_memw_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
+  Opcode_extw_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
+  Opcode_isync_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
+  Opcode_rsync_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
+  Opcode_esync_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
+  Opcode_dsync_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
+  Opcode_rsil_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
+  Opcode_rsr_lend_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
+  Opcode_wsr_lend_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
+  Opcode_xsr_lend_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
+  Opcode_rsr_lcount_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
+  Opcode_wsr_lcount_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
+  Opcode_xsr_lcount_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
+  Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
+  Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
+  Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
+  Opcode_rsr_sar_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
+  Opcode_wsr_sar_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
+  Opcode_xsr_sar_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = {
+  Opcode_rsr_memctl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = {
+  Opcode_wsr_memctl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = {
+  Opcode_xsr_memctl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
+  Opcode_rsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
+  Opcode_wsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
+  Opcode_xsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = {
+  Opcode_rsr_configid0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = {
+  Opcode_wsr_configid0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = {
+  Opcode_rsr_configid1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
+  Opcode_rsr_ps_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
+  Opcode_wsr_ps_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
+  Opcode_xsr_ps_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
+  Opcode_rsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
+  Opcode_wsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
+  Opcode_xsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
+  Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
+  Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
+  Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
+  Opcode_rsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
+  Opcode_wsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
+  Opcode_xsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
+  Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
+  Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
+  Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
+  Opcode_rsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
+  Opcode_wsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
+  Opcode_xsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
+  Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
+  Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
+  Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
+  Opcode_rsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
+  Opcode_wsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
+  Opcode_xsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
+  Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
+  Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
+  Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
+  Opcode_rsr_epc5_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
+  Opcode_wsr_epc5_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
+  Opcode_xsr_epc5_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
+  Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
+  Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
+  Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
+  Opcode_rsr_epc6_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
+  Opcode_wsr_epc6_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
+  Opcode_xsr_epc6_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
+  Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
+  Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
+  Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
+  Opcode_rsr_epc7_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
+  Opcode_wsr_epc7_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
+  Opcode_xsr_epc7_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
+  Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
+  Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
+  Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
+  Opcode_rsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
+  Opcode_wsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
+  Opcode_xsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
+  Opcode_rsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
+  Opcode_wsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
+  Opcode_xsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
+  Opcode_rsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
+  Opcode_wsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
+  Opcode_xsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
+  Opcode_rsr_eps5_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
+  Opcode_wsr_eps5_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
+  Opcode_xsr_eps5_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
+  Opcode_rsr_eps6_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
+  Opcode_wsr_eps6_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
+  Opcode_xsr_eps6_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
+  Opcode_rsr_eps7_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
+  Opcode_wsr_eps7_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
+  Opcode_xsr_eps7_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
+  Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
+  Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
+  Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
+  Opcode_rsr_depc_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
+  Opcode_wsr_depc_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
+  Opcode_xsr_depc_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
+  Opcode_rsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
+  Opcode_wsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
+  Opcode_xsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
+  Opcode_rsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
+  Opcode_wsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
+  Opcode_xsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
+  Opcode_rsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
+  Opcode_wsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
+  Opcode_xsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_misc2_encode_fns[] = {
+  Opcode_rsr_misc2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_misc2_encode_fns[] = {
+  Opcode_wsr_misc2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_misc2_encode_fns[] = {
+  Opcode_xsr_misc2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_misc3_encode_fns[] = {
+  Opcode_rsr_misc3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_misc3_encode_fns[] = {
+  Opcode_wsr_misc3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_misc3_encode_fns[] = {
+  Opcode_xsr_misc3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
+  Opcode_rsr_prid_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
+  Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
+  Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
+  Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
+  Opcode_mul16u_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
+  Opcode_mul16s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
+  Opcode_mull_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = {
+  Opcode_muluh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = {
+  Opcode_mulsh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
+  Opcode_mul_aa_ll_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
+  Opcode_mul_aa_hl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
+  Opcode_mul_aa_lh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
+  Opcode_mul_aa_hh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
+  Opcode_umul_aa_ll_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
+  Opcode_umul_aa_hl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
+  Opcode_umul_aa_lh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
+  Opcode_umul_aa_hh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
+  Opcode_mul_ad_ll_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
+  Opcode_mul_ad_hl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
+  Opcode_mul_ad_lh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
+  Opcode_mul_ad_hh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
+  Opcode_mul_da_ll_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
+  Opcode_mul_da_hl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
+  Opcode_mul_da_lh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
+  Opcode_mul_da_hh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
+  Opcode_mul_dd_ll_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
+  Opcode_mul_dd_hl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
+  Opcode_mul_dd_lh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
+  Opcode_mul_dd_hh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
+  Opcode_mula_aa_ll_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
+  Opcode_mula_aa_hl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
+  Opcode_mula_aa_lh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
+  Opcode_mula_aa_hh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
+  Opcode_muls_aa_ll_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
+  Opcode_muls_aa_hl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
+  Opcode_muls_aa_lh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
+  Opcode_muls_aa_hh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
+  Opcode_mula_ad_ll_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
+  Opcode_mula_ad_hl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
+  Opcode_mula_ad_lh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
+  Opcode_mula_ad_hh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
+  Opcode_muls_ad_ll_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
+  Opcode_muls_ad_hl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
+  Opcode_muls_ad_lh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
+  Opcode_muls_ad_hh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
+  Opcode_mula_da_ll_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
+  Opcode_mula_da_hl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
+  Opcode_mula_da_lh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
+  Opcode_mula_da_hh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
+  Opcode_muls_da_ll_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
+  Opcode_muls_da_hl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
+  Opcode_muls_da_lh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
+  Opcode_muls_da_hh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
+  Opcode_mula_dd_ll_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
+  Opcode_mula_dd_hl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
+  Opcode_mula_dd_lh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
+  Opcode_mula_dd_hh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
+  Opcode_muls_dd_ll_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
+  Opcode_muls_dd_hl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
+  Opcode_muls_dd_lh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
+  Opcode_muls_dd_hh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
+  Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
+  Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
+  Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
+  Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
+  Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
+  Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
+  Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
+  Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
+  Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
+  Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
+  Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
+  Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
+  Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
+  Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
+  Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
+  Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
+  Opcode_lddec_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
+  Opcode_ldinc_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
+  Opcode_rsr_m0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
+  Opcode_wsr_m0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
+  Opcode_xsr_m0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
+  Opcode_rsr_m1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
+  Opcode_wsr_m1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
+  Opcode_xsr_m1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
+  Opcode_rsr_m2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
+  Opcode_wsr_m2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
+  Opcode_xsr_m2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
+  Opcode_rsr_m3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
+  Opcode_wsr_m3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
+  Opcode_xsr_m3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
+  Opcode_rsr_acclo_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
+  Opcode_wsr_acclo_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
+  Opcode_xsr_acclo_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
+  Opcode_rsr_acchi_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
+  Opcode_wsr_acchi_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
+  Opcode_xsr_acchi_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
+  Opcode_rfi_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
+  Opcode_waiti_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
+  Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
+  Opcode_wsr_intset_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
+  Opcode_wsr_intclear_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
+  Opcode_rsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
+  Opcode_wsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
+  Opcode_xsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
+  Opcode_break_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
+  0, 0, Opcode_break_n_Slot_inst16b_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
+  Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
+  Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
+  Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
+  Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
+  Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
+  Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
+  Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
+  Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
+  Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
+  Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
+  Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
+  Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
+  Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
+  Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
+  Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
+  Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
+  Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
+  Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
+  Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
+  Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
+  Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
+  Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
+  Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
+  Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
+  Opcode_rsr_icount_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
+  Opcode_wsr_icount_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
+  Opcode_xsr_icount_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
+  Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
+  Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
+  Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
+  Opcode_rsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
+  Opcode_wsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
+  Opcode_xsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = {
+  Opcode_lddr32_p_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = {
+  Opcode_sddr32_p_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
+  Opcode_rfdo_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
+  Opcode_rfdd_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
+  Opcode_wsr_mmid_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = {
+  Opcode_andb_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = {
+  Opcode_andbc_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = {
+  Opcode_orb_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = {
+  Opcode_orbc_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = {
+  Opcode_xorb_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = {
+  Opcode_any4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = {
+  Opcode_all4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = {
+  Opcode_any8_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = {
+  Opcode_all8_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = {
+  Opcode_bf_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = {
+  Opcode_bt_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = {
+  Opcode_movf_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = {
+  Opcode_movt_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = {
+  Opcode_rsr_br_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = {
+  Opcode_wsr_br_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = {
+  Opcode_xsr_br_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
+  Opcode_rsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
+  Opcode_wsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
+  Opcode_xsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
+  Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
+  Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
+  Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
+  Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
+  Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
+  Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
+  Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
+  Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
+  Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
+  Opcode_idtlb_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
+  Opcode_pdtlb_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
+  Opcode_rdtlb0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
+  Opcode_rdtlb1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
+  Opcode_wdtlb_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
+  Opcode_iitlb_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
+  Opcode_pitlb_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
+  Opcode_ritlb0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
+  Opcode_ritlb1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
+  Opcode_witlb_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
+  Opcode_rsr_cpenable_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
+  Opcode_wsr_cpenable_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
+  Opcode_xsr_cpenable_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
+  Opcode_clamps_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
+  Opcode_min_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
+  Opcode_max_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
+  Opcode_minu_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
+  Opcode_maxu_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
+  Opcode_nsa_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
+  Opcode_nsau_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
+  Opcode_sext_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
+  Opcode_l32ai_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
+  Opcode_s32ri_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
+  Opcode_s32c1i_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
+  Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
+  Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
+  Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = {
+  Opcode_rsr_atomctl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = {
+  Opcode_wsr_atomctl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = {
+  Opcode_xsr_atomctl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
+  Opcode_quou_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
+  Opcode_quos_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
+  Opcode_remu_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
+  Opcode_rems_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = {
+  Opcode_rer_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = {
+  Opcode_wer_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_f64iter_encode_fns[] = {
+  Opcode_f64iter_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_f64rnd_encode_fns[] = {
+  Opcode_f64rnd_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_f64addc_encode_fns[] = {
+  Opcode_f64addc_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_f64subc_encode_fns[] = {
+  Opcode_f64subc_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_f64sig_encode_fns[] = {
+  Opcode_f64sig_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_f64cmpl_encode_fns[] = {
+  Opcode_f64cmpl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_f64cmph_encode_fns[] = {
+  Opcode_f64cmph_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_f64norm_encode_fns[] = {
+  Opcode_f64norm_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_f64sexp_encode_fns[] = {
+  Opcode_f64sexp_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rf64r_encode_fns[] = {
+  Opcode_rf64r_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wf64r_encode_fns[] = {
+  Opcode_wf64r_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_f64r_lo_encode_fns[] = {
+  Opcode_rur_f64r_lo_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_f64r_lo_encode_fns[] = {
+  Opcode_wur_f64r_lo_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_f64r_hi_encode_fns[] = {
+  Opcode_rur_f64r_hi_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_f64r_hi_encode_fns[] = {
+  Opcode_wur_f64r_hi_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_f64s_encode_fns[] = {
+  Opcode_rur_f64s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_f64s_encode_fns[] = {
+  Opcode_wur_f64s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_fcr_encode_fns[] = {
+  Opcode_rur_fcr_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_fcr_encode_fns[] = {
+  Opcode_wur_fcr_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_fsr_encode_fns[] = {
+  Opcode_rur_fsr_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_fsr_encode_fns[] = {
+  Opcode_wur_fsr_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = {
+  Opcode_rur_expstate_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = {
+  Opcode_wur_expstate_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = {
+  Opcode_read_impwire_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = {
+  Opcode_setb_expstate_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = {
+  Opcode_clrb_expstate_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = {
+  Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0
+};
+
+\f
+/* Opcode table.  */
+
+static xtensa_opcode_internal opcodes[] = {
+  { "lsi", ICLASS_LSI,
+    0,
+    Opcode_lsi_encode_fns, 0, 0 },
+  { "lsip", ICLASS_LSIP,
+    0,
+    Opcode_lsip_encode_fns, 0, 0 },
+  { "lsx", ICLASS_LSX,
+    0,
+    Opcode_lsx_encode_fns, 0, 0 },
+  { "lsxp", ICLASS_LSXP,
+    0,
+    Opcode_lsxp_encode_fns, 0, 0 },
+  { "ssi", ICLASS_SSI,
+    0,
+    Opcode_ssi_encode_fns, 0, 0 },
+  { "ssip", ICLASS_SSIP,
+    0,
+    Opcode_ssip_encode_fns, 0, 0 },
+  { "ssx", ICLASS_SSX,
+    0,
+    Opcode_ssx_encode_fns, 0, 0 },
+  { "ssxp", ICLASS_SSXP,
+    0,
+    Opcode_ssxp_encode_fns, 0, 0 },
+  { "abs.s", ICLASS_ABS_S,
+    0,
+    Opcode_abs_s_encode_fns, 0, 0 },
+  { "neg.s", ICLASS_NEG_S,
+    0,
+    Opcode_neg_s_encode_fns, 0, 0 },
+  { "mov.s", ICLASS_MOV_S,
+    0,
+    Opcode_mov_s_encode_fns, 0, 0 },
+  { "moveqz.s", ICLASS_MOVEQZ_S,
+    0,
+    Opcode_moveqz_s_encode_fns, 0, 0 },
+  { "movnez.s", ICLASS_MOVNEZ_S,
+    0,
+    Opcode_movnez_s_encode_fns, 0, 0 },
+  { "movltz.s", ICLASS_MOVLTZ_S,
+    0,
+    Opcode_movltz_s_encode_fns, 0, 0 },
+  { "movgez.s", ICLASS_MOVGEZ_S,
+    0,
+    Opcode_movgez_s_encode_fns, 0, 0 },
+  { "movf.s", ICLASS_MOVF_S,
+    0,
+    Opcode_movf_s_encode_fns, 0, 0 },
+  { "movt.s", ICLASS_MOVT_S,
+    0,
+    Opcode_movt_s_encode_fns, 0, 0 },
+  { "wfr", ICLASS_WFR,
+    0,
+    Opcode_wfr_encode_fns, 0, 0 },
+  { "rfr", ICLASS_RFR,
+    0,
+    Opcode_rfr_encode_fns, 0, 0 },
+  { "round.s", ICLASS_ROUND_S,
+    0,
+    Opcode_round_s_encode_fns, 0, 0 },
+  { "ceil.s", ICLASS_CEIL_S,
+    0,
+    Opcode_ceil_s_encode_fns, 0, 0 },
+  { "floor.s", ICLASS_FLOOR_S,
+    0,
+    Opcode_floor_s_encode_fns, 0, 0 },
+  { "trunc.s", ICLASS_TRUNC_S,
+    0,
+    Opcode_trunc_s_encode_fns, 0, 0 },
+  { "utrunc.s", ICLASS_UTRUNC_S,
+    0,
+    Opcode_utrunc_s_encode_fns, 0, 0 },
+  { "float.s", ICLASS_FLOAT_S,
+    0,
+    Opcode_float_s_encode_fns, 0, 0 },
+  { "ufloat.s", ICLASS_UFLOAT_S,
+    0,
+    Opcode_ufloat_s_encode_fns, 0, 0 },
+  { "un.s", ICLASS_UN_S,
+    0,
+    Opcode_un_s_encode_fns, 0, 0 },
+  { "ult.s", ICLASS_ULT_S,
+    0,
+    Opcode_ult_s_encode_fns, 0, 0 },
+  { "ule.s", ICLASS_ULE_S,
+    0,
+    Opcode_ule_s_encode_fns, 0, 0 },
+  { "ueq.s", ICLASS_UEQ_S,
+    0,
+    Opcode_ueq_s_encode_fns, 0, 0 },
+  { "olt.s", ICLASS_OLT_S,
+    0,
+    Opcode_olt_s_encode_fns, 0, 0 },
+  { "ole.s", ICLASS_OLE_S,
+    0,
+    Opcode_ole_s_encode_fns, 0, 0 },
+  { "oeq.s", ICLASS_OEQ_S,
+    0,
+    Opcode_oeq_s_encode_fns, 0, 0 },
+  { "add.s", ICLASS_ADD_S,
+    0,
+    Opcode_add_s_encode_fns, 0, 0 },
+  { "sub.s", ICLASS_SUB_S,
+    0,
+    Opcode_sub_s_encode_fns, 0, 0 },
+  { "mul.s", ICLASS_MUL_S,
+    0,
+    Opcode_mul_s_encode_fns, 0, 0 },
+  { "madd.s", ICLASS_MADD_S,
+    0,
+    Opcode_madd_s_encode_fns, 0, 0 },
+  { "msub.s", ICLASS_MSUB_S,
+    0,
+    Opcode_msub_s_encode_fns, 0, 0 },
+  { "sqrt0.s", ICLASS_SQRT0_S,
+    0,
+    Opcode_sqrt0_s_encode_fns, 0, 0 },
+  { "div0.s", ICLASS_DIV0_S,
+    0,
+    Opcode_div0_s_encode_fns, 0, 0 },
+  { "recip0.s", ICLASS_RECIP0_S,
+    0,
+    Opcode_recip0_s_encode_fns, 0, 0 },
+  { "rsqrt0.s", ICLASS_RSQRT0_S,
+    0,
+    Opcode_rsqrt0_s_encode_fns, 0, 0 },
+  { "maddn.s", ICLASS_MADDN_S,
+    0,
+    Opcode_maddn_s_encode_fns, 0, 0 },
+  { "divn.s", ICLASS_DIVN_S,
+    0,
+    Opcode_divn_s_encode_fns, 0, 0 },
+  { "const.s", ICLASS_CONST_S,
+    0,
+    Opcode_const_s_encode_fns, 0, 0 },
+  { "nexp01.s", ICLASS_NEXP01_S,
+    0,
+    Opcode_nexp01_s_encode_fns, 0, 0 },
+  { "addexp.s", ICLASS_ADDEXP_S,
+    0,
+    Opcode_addexp_s_encode_fns, 0, 0 },
+  { "addexpm.s", ICLASS_ADDEXPM_S,
+    0,
+    Opcode_addexpm_s_encode_fns, 0, 0 },
+  { "mkdadj.s", ICLASS_MKDADJ_S,
+    0,
+    Opcode_mkdadj_s_encode_fns, 0, 0 },
+  { "mksadj.s", ICLASS_MKSADJ_S,
+    0,
+    Opcode_mksadj_s_encode_fns, 0, 0 },
+  { "excw", ICLASS_xt_iclass_excw,
+    0,
+    Opcode_excw_encode_fns, 0, 0 },
+  { "rfe", ICLASS_xt_iclass_rfe,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_rfe_encode_fns, 0, 0 },
+  { "rfde", ICLASS_xt_iclass_rfde,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_rfde_encode_fns, 0, 0 },
+  { "syscall", ICLASS_xt_iclass_syscall,
+    0,
+    Opcode_syscall_encode_fns, 0, 0 },
+  { "call12", ICLASS_xt_iclass_call12,
+    XTENSA_OPCODE_IS_CALL,
+    Opcode_call12_encode_fns, 0, 0 },
+  { "call8", ICLASS_xt_iclass_call8,
+    XTENSA_OPCODE_IS_CALL,
+    Opcode_call8_encode_fns, 0, 0 },
+  { "call4", ICLASS_xt_iclass_call4,
+    XTENSA_OPCODE_IS_CALL,
+    Opcode_call4_encode_fns, 0, 0 },
+  { "callx12", ICLASS_xt_iclass_callx12,
+    XTENSA_OPCODE_IS_CALL,
+    Opcode_callx12_encode_fns, 0, 0 },
+  { "callx8", ICLASS_xt_iclass_callx8,
+    XTENSA_OPCODE_IS_CALL,
+    Opcode_callx8_encode_fns, 0, 0 },
+  { "callx4", ICLASS_xt_iclass_callx4,
+    XTENSA_OPCODE_IS_CALL,
+    Opcode_callx4_encode_fns, 0, 0 },
+  { "entry", ICLASS_xt_iclass_entry,
+    0,
+    Opcode_entry_encode_fns, 0, 0 },
+  { "movsp", ICLASS_xt_iclass_movsp,
+    0,
+    Opcode_movsp_encode_fns, 0, 0 },
+  { "rotw", ICLASS_xt_iclass_rotw,
+    0,
+    Opcode_rotw_encode_fns, 0, 0 },
+  { "retw", ICLASS_xt_iclass_retw,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_retw_encode_fns, 0, 0 },
+  { "retw.n", ICLASS_xt_iclass_retw,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_retw_n_encode_fns, 0, 0 },
+  { "rfwo", ICLASS_xt_iclass_rfwou,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_rfwo_encode_fns, 0, 0 },
+  { "rfwu", ICLASS_xt_iclass_rfwou,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_rfwu_encode_fns, 0, 0 },
+  { "l32e", ICLASS_xt_iclass_l32e,
+    0,
+    Opcode_l32e_encode_fns, 0, 0 },
+  { "s32e", ICLASS_xt_iclass_s32e,
+    0,
+    Opcode_s32e_encode_fns, 0, 0 },
+  { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase,
+    0,
+    Opcode_rsr_windowbase_encode_fns, 0, 0 },
+  { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase,
+    0,
+    Opcode_wsr_windowbase_encode_fns, 0, 0 },
+  { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase,
+    0,
+    Opcode_xsr_windowbase_encode_fns, 0, 0 },
+  { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart,
+    0,
+    Opcode_rsr_windowstart_encode_fns, 0, 0 },
+  { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart,
+    0,
+    Opcode_wsr_windowstart_encode_fns, 0, 0 },
+  { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart,
+    0,
+    Opcode_xsr_windowstart_encode_fns, 0, 0 },
+  { "add.n", ICLASS_xt_iclass_add_n,
+    0,
+    Opcode_add_n_encode_fns, 0, 0 },
+  { "addi.n", ICLASS_xt_iclass_addi_n,
+    0,
+    Opcode_addi_n_encode_fns, 0, 0 },
+  { "beqz.n", ICLASS_xt_iclass_bz6,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_beqz_n_encode_fns, 0, 0 },
+  { "bnez.n", ICLASS_xt_iclass_bz6,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bnez_n_encode_fns, 0, 0 },
+  { "ill.n", ICLASS_xt_iclass_ill_n,
+    0,
+    Opcode_ill_n_encode_fns, 0, 0 },
+  { "l32i.n", ICLASS_xt_iclass_loadi4,
+    0,
+    Opcode_l32i_n_encode_fns, 0, 0 },
+  { "mov.n", ICLASS_xt_iclass_mov_n,
+    0,
+    Opcode_mov_n_encode_fns, 0, 0 },
+  { "movi.n", ICLASS_xt_iclass_movi_n,
+    0,
+    Opcode_movi_n_encode_fns, 0, 0 },
+  { "nop.n", ICLASS_xt_iclass_nopn,
+    0,
+    Opcode_nop_n_encode_fns, 0, 0 },
+  { "ret.n", ICLASS_xt_iclass_retn,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_ret_n_encode_fns, 0, 0 },
+  { "s32i.n", ICLASS_xt_iclass_storei4,
+    0,
+    Opcode_s32i_n_encode_fns, 0, 0 },
+  { "rur.threadptr", ICLASS_rur_threadptr,
+    0,
+    Opcode_rur_threadptr_encode_fns, 0, 0 },
+  { "wur.threadptr", ICLASS_wur_threadptr,
+    0,
+    Opcode_wur_threadptr_encode_fns, 0, 0 },
+  { "addi", ICLASS_xt_iclass_addi,
+    0,
+    Opcode_addi_encode_fns, 0, 0 },
+  { "addmi", ICLASS_xt_iclass_addmi,
+    0,
+    Opcode_addmi_encode_fns, 0, 0 },
+  { "add", ICLASS_xt_iclass_addsub,
+    0,
+    Opcode_add_encode_fns, 0, 0 },
+  { "sub", ICLASS_xt_iclass_addsub,
+    0,
+    Opcode_sub_encode_fns, 0, 0 },
+  { "addx2", ICLASS_xt_iclass_addsub,
+    0,
+    Opcode_addx2_encode_fns, 0, 0 },
+  { "addx4", ICLASS_xt_iclass_addsub,
+    0,
+    Opcode_addx4_encode_fns, 0, 0 },
+  { "addx8", ICLASS_xt_iclass_addsub,
+    0,
+    Opcode_addx8_encode_fns, 0, 0 },
+  { "subx2", ICLASS_xt_iclass_addsub,
+    0,
+    Opcode_subx2_encode_fns, 0, 0 },
+  { "subx4", ICLASS_xt_iclass_addsub,
+    0,
+    Opcode_subx4_encode_fns, 0, 0 },
+  { "subx8", ICLASS_xt_iclass_addsub,
+    0,
+    Opcode_subx8_encode_fns, 0, 0 },
+  { "and", ICLASS_xt_iclass_bit,
+    0,
+    Opcode_and_encode_fns, 0, 0 },
+  { "or", ICLASS_xt_iclass_bit,
+    0,
+    Opcode_or_encode_fns, 0, 0 },
+  { "xor", ICLASS_xt_iclass_bit,
+    0,
+    Opcode_xor_encode_fns, 0, 0 },
+  { "beqi", ICLASS_xt_iclass_bsi8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_beqi_encode_fns, 0, 0 },
+  { "bnei", ICLASS_xt_iclass_bsi8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bnei_encode_fns, 0, 0 },
+  { "bgei", ICLASS_xt_iclass_bsi8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bgei_encode_fns, 0, 0 },
+  { "blti", ICLASS_xt_iclass_bsi8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_blti_encode_fns, 0, 0 },
+  { "bbci", ICLASS_xt_iclass_bsi8b,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bbci_encode_fns, 0, 0 },
+  { "bbsi", ICLASS_xt_iclass_bsi8b,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bbsi_encode_fns, 0, 0 },
+  { "bgeui", ICLASS_xt_iclass_bsi8u,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bgeui_encode_fns, 0, 0 },
+  { "bltui", ICLASS_xt_iclass_bsi8u,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bltui_encode_fns, 0, 0 },
+  { "beq", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_beq_encode_fns, 0, 0 },
+  { "bne", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bne_encode_fns, 0, 0 },
+  { "bge", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bge_encode_fns, 0, 0 },
+  { "blt", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_blt_encode_fns, 0, 0 },
+  { "bgeu", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bgeu_encode_fns, 0, 0 },
+  { "bltu", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bltu_encode_fns, 0, 0 },
+  { "bany", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bany_encode_fns, 0, 0 },
+  { "bnone", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bnone_encode_fns, 0, 0 },
+  { "ball", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_ball_encode_fns, 0, 0 },
+  { "bnall", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bnall_encode_fns, 0, 0 },
+  { "bbc", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bbc_encode_fns, 0, 0 },
+  { "bbs", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bbs_encode_fns, 0, 0 },
+  { "beqz", ICLASS_xt_iclass_bsz12,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_beqz_encode_fns, 0, 0 },
+  { "bnez", ICLASS_xt_iclass_bsz12,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bnez_encode_fns, 0, 0 },
+  { "bgez", ICLASS_xt_iclass_bsz12,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bgez_encode_fns, 0, 0 },
+  { "bltz", ICLASS_xt_iclass_bsz12,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bltz_encode_fns, 0, 0 },
+  { "call0", ICLASS_xt_iclass_call0,
+    XTENSA_OPCODE_IS_CALL,
+    Opcode_call0_encode_fns, 0, 0 },
+  { "callx0", ICLASS_xt_iclass_callx0,
+    XTENSA_OPCODE_IS_CALL,
+    Opcode_callx0_encode_fns, 0, 0 },
+  { "extui", ICLASS_xt_iclass_exti,
+    0,
+    Opcode_extui_encode_fns, 0, 0 },
+  { "ill", ICLASS_xt_iclass_ill,
+    0,
+    Opcode_ill_encode_fns, 0, 0 },
+  { "j", ICLASS_xt_iclass_jump,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_j_encode_fns, 0, 0 },
+  { "jx", ICLASS_xt_iclass_jumpx,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_jx_encode_fns, 0, 0 },
+  { "l16ui", ICLASS_xt_iclass_l16ui,
+    0,
+    Opcode_l16ui_encode_fns, 0, 0 },
+  { "l16si", ICLASS_xt_iclass_l16si,
+    0,
+    Opcode_l16si_encode_fns, 0, 0 },
+  { "l32i", ICLASS_xt_iclass_l32i,
+    0,
+    Opcode_l32i_encode_fns, 0, 0 },
+  { "l32r", ICLASS_xt_iclass_l32r,
+    0,
+    Opcode_l32r_encode_fns, 0, 0 },
+  { "l8ui", ICLASS_xt_iclass_l8i,
+    0,
+    Opcode_l8ui_encode_fns, 0, 0 },
+  { "loop", ICLASS_xt_iclass_loop,
+    XTENSA_OPCODE_IS_LOOP,
+    Opcode_loop_encode_fns, 0, 0 },
+  { "loopnez", ICLASS_xt_iclass_loopz,
+    XTENSA_OPCODE_IS_LOOP,
+    Opcode_loopnez_encode_fns, 0, 0 },
+  { "loopgtz", ICLASS_xt_iclass_loopz,
+    XTENSA_OPCODE_IS_LOOP,
+    Opcode_loopgtz_encode_fns, 0, 0 },
+  { "movi", ICLASS_xt_iclass_movi,
+    0,
+    Opcode_movi_encode_fns, 0, 0 },
+  { "moveqz", ICLASS_xt_iclass_movz,
+    0,
+    Opcode_moveqz_encode_fns, 0, 0 },
+  { "movnez", ICLASS_xt_iclass_movz,
+    0,
+    Opcode_movnez_encode_fns, 0, 0 },
+  { "movltz", ICLASS_xt_iclass_movz,
+    0,
+    Opcode_movltz_encode_fns, 0, 0 },
+  { "movgez", ICLASS_xt_iclass_movz,
+    0,
+    Opcode_movgez_encode_fns, 0, 0 },
+  { "neg", ICLASS_xt_iclass_neg,
+    0,
+    Opcode_neg_encode_fns, 0, 0 },
+  { "abs", ICLASS_xt_iclass_neg,
+    0,
+    Opcode_abs_encode_fns, 0, 0 },
+  { "nop", ICLASS_xt_iclass_nop,
+    0,
+    Opcode_nop_encode_fns, 0, 0 },
+  { "ret", ICLASS_xt_iclass_return,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_ret_encode_fns, 0, 0 },
+  { "simcall", ICLASS_xt_iclass_simcall,
+    0,
+    Opcode_simcall_encode_fns, 0, 0 },
+  { "s16i", ICLASS_xt_iclass_s16i,
+    0,
+    Opcode_s16i_encode_fns, 0, 0 },
+  { "s32i", ICLASS_xt_iclass_s32i,
+    0,
+    Opcode_s32i_encode_fns, 0, 0 },
+  { "s32nb", ICLASS_xt_iclass_s32nb,
+    0,
+    Opcode_s32nb_encode_fns, 0, 0 },
+  { "s8i", ICLASS_xt_iclass_s8i,
+    0,
+    Opcode_s8i_encode_fns, 0, 0 },
+  { "ssr", ICLASS_xt_iclass_sar,
+    0,
+    Opcode_ssr_encode_fns, 0, 0 },
+  { "ssl", ICLASS_xt_iclass_sar,
+    0,
+    Opcode_ssl_encode_fns, 0, 0 },
+  { "ssa8l", ICLASS_xt_iclass_sar,
+    0,
+    Opcode_ssa8l_encode_fns, 0, 0 },
+  { "ssa8b", ICLASS_xt_iclass_sar,
+    0,
+    Opcode_ssa8b_encode_fns, 0, 0 },
+  { "ssai", ICLASS_xt_iclass_sari,
+    0,
+    Opcode_ssai_encode_fns, 0, 0 },
+  { "sll", ICLASS_xt_iclass_shifts,
+    0,
+    Opcode_sll_encode_fns, 0, 0 },
+  { "src", ICLASS_xt_iclass_shiftst,
+    0,
+    Opcode_src_encode_fns, 0, 0 },
+  { "srl", ICLASS_xt_iclass_shiftt,
+    0,
+    Opcode_srl_encode_fns, 0, 0 },
+  { "sra", ICLASS_xt_iclass_shiftt,
+    0,
+    Opcode_sra_encode_fns, 0, 0 },
+  { "slli", ICLASS_xt_iclass_slli,
+    0,
+    Opcode_slli_encode_fns, 0, 0 },
+  { "srai", ICLASS_xt_iclass_srai,
+    0,
+    Opcode_srai_encode_fns, 0, 0 },
+  { "srli", ICLASS_xt_iclass_srli,
+    0,
+    Opcode_srli_encode_fns, 0, 0 },
+  { "memw", ICLASS_xt_iclass_memw,
+    0,
+    Opcode_memw_encode_fns, 0, 0 },
+  { "extw", ICLASS_xt_iclass_extw,
+    0,
+    Opcode_extw_encode_fns, 0, 0 },
+  { "isync", ICLASS_xt_iclass_isync,
+    0,
+    Opcode_isync_encode_fns, 0, 0 },
+  { "rsync", ICLASS_xt_iclass_sync,
+    0,
+    Opcode_rsync_encode_fns, 0, 0 },
+  { "esync", ICLASS_xt_iclass_sync,
+    0,
+    Opcode_esync_encode_fns, 0, 0 },
+  { "dsync", ICLASS_xt_iclass_sync,
+    0,
+    Opcode_dsync_encode_fns, 0, 0 },
+  { "rsil", ICLASS_xt_iclass_rsil,
+    0,
+    Opcode_rsil_encode_fns, 0, 0 },
+  { "rsr.lend", ICLASS_xt_iclass_rsr_lend,
+    0,
+    Opcode_rsr_lend_encode_fns, 0, 0 },
+  { "wsr.lend", ICLASS_xt_iclass_wsr_lend,
+    0,
+    Opcode_wsr_lend_encode_fns, 0, 0 },
+  { "xsr.lend", ICLASS_xt_iclass_xsr_lend,
+    0,
+    Opcode_xsr_lend_encode_fns, 0, 0 },
+  { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount,
+    0,
+    Opcode_rsr_lcount_encode_fns, 0, 0 },
+  { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount,
+    0,
+    Opcode_wsr_lcount_encode_fns, 0, 0 },
+  { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount,
+    0,
+    Opcode_xsr_lcount_encode_fns, 0, 0 },
+  { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg,
+    0,
+    Opcode_rsr_lbeg_encode_fns, 0, 0 },
+  { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg,
+    0,
+    Opcode_wsr_lbeg_encode_fns, 0, 0 },
+  { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg,
+    0,
+    Opcode_xsr_lbeg_encode_fns, 0, 0 },
+  { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
+    0,
+    Opcode_rsr_sar_encode_fns, 0, 0 },
+  { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
+    0,
+    Opcode_wsr_sar_encode_fns, 0, 0 },
+  { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
+    0,
+    Opcode_xsr_sar_encode_fns, 0, 0 },
+  { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl,
+    0,
+    Opcode_rsr_memctl_encode_fns, 0, 0 },
+  { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl,
+    0,
+    Opcode_wsr_memctl_encode_fns, 0, 0 },
+  { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl,
+    0,
+    Opcode_xsr_memctl_encode_fns, 0, 0 },
+  { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase,
+    0,
+    Opcode_rsr_litbase_encode_fns, 0, 0 },
+  { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase,
+    0,
+    Opcode_wsr_litbase_encode_fns, 0, 0 },
+  { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
+    0,
+    Opcode_xsr_litbase_encode_fns, 0, 0 },
+  { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0,
+    0,
+    Opcode_rsr_configid0_encode_fns, 0, 0 },
+  { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0,
+    0,
+    Opcode_wsr_configid0_encode_fns, 0, 0 },
+  { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1,
+    0,
+    Opcode_rsr_configid1_encode_fns, 0, 0 },
+  { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
+    0,
+    Opcode_rsr_ps_encode_fns, 0, 0 },
+  { "wsr.ps", ICLASS_xt_iclass_wsr_ps,
+    0,
+    Opcode_wsr_ps_encode_fns, 0, 0 },
+  { "xsr.ps", ICLASS_xt_iclass_xsr_ps,
+    0,
+    Opcode_xsr_ps_encode_fns, 0, 0 },
+  { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
+    0,
+    Opcode_rsr_epc1_encode_fns, 0, 0 },
+  { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
+    0,
+    Opcode_wsr_epc1_encode_fns, 0, 0 },
+  { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
+    0,
+    Opcode_xsr_epc1_encode_fns, 0, 0 },
+  { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
+    0,
+    Opcode_rsr_excsave1_encode_fns, 0, 0 },
+  { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
+    0,
+    Opcode_wsr_excsave1_encode_fns, 0, 0 },
+  { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
+    0,
+    Opcode_xsr_excsave1_encode_fns, 0, 0 },
+  { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
+    0,
+    Opcode_rsr_epc2_encode_fns, 0, 0 },
+  { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
+    0,
+    Opcode_wsr_epc2_encode_fns, 0, 0 },
+  { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
+    0,
+    Opcode_xsr_epc2_encode_fns, 0, 0 },
+  { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
+    0,
+    Opcode_rsr_excsave2_encode_fns, 0, 0 },
+  { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
+    0,
+    Opcode_wsr_excsave2_encode_fns, 0, 0 },
+  { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
+    0,
+    Opcode_xsr_excsave2_encode_fns, 0, 0 },
+  { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3,
+    0,
+    Opcode_rsr_epc3_encode_fns, 0, 0 },
+  { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3,
+    0,
+    Opcode_wsr_epc3_encode_fns, 0, 0 },
+  { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3,
+    0,
+    Opcode_xsr_epc3_encode_fns, 0, 0 },
+  { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3,
+    0,
+    Opcode_rsr_excsave3_encode_fns, 0, 0 },
+  { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3,
+    0,
+    Opcode_wsr_excsave3_encode_fns, 0, 0 },
+  { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3,
+    0,
+    Opcode_xsr_excsave3_encode_fns, 0, 0 },
+  { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4,
+    0,
+    Opcode_rsr_epc4_encode_fns, 0, 0 },
+  { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4,
+    0,
+    Opcode_wsr_epc4_encode_fns, 0, 0 },
+  { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4,
+    0,
+    Opcode_xsr_epc4_encode_fns, 0, 0 },
+  { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4,
+    0,
+    Opcode_rsr_excsave4_encode_fns, 0, 0 },
+  { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4,
+    0,
+    Opcode_wsr_excsave4_encode_fns, 0, 0 },
+  { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4,
+    0,
+    Opcode_xsr_excsave4_encode_fns, 0, 0 },
+  { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5,
+    0,
+    Opcode_rsr_epc5_encode_fns, 0, 0 },
+  { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5,
+    0,
+    Opcode_wsr_epc5_encode_fns, 0, 0 },
+  { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5,
+    0,
+    Opcode_xsr_epc5_encode_fns, 0, 0 },
+  { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5,
+    0,
+    Opcode_rsr_excsave5_encode_fns, 0, 0 },
+  { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5,
+    0,
+    Opcode_wsr_excsave5_encode_fns, 0, 0 },
+  { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5,
+    0,
+    Opcode_xsr_excsave5_encode_fns, 0, 0 },
+  { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6,
+    0,
+    Opcode_rsr_epc6_encode_fns, 0, 0 },
+  { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6,
+    0,
+    Opcode_wsr_epc6_encode_fns, 0, 0 },
+  { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6,
+    0,
+    Opcode_xsr_epc6_encode_fns, 0, 0 },
+  { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6,
+    0,
+    Opcode_rsr_excsave6_encode_fns, 0, 0 },
+  { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6,
+    0,
+    Opcode_wsr_excsave6_encode_fns, 0, 0 },
+  { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6,
+    0,
+    Opcode_xsr_excsave6_encode_fns, 0, 0 },
+  { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7,
+    0,
+    Opcode_rsr_epc7_encode_fns, 0, 0 },
+  { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7,
+    0,
+    Opcode_wsr_epc7_encode_fns, 0, 0 },
+  { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7,
+    0,
+    Opcode_xsr_epc7_encode_fns, 0, 0 },
+  { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7,
+    0,
+    Opcode_rsr_excsave7_encode_fns, 0, 0 },
+  { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7,
+    0,
+    Opcode_wsr_excsave7_encode_fns, 0, 0 },
+  { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7,
+    0,
+    Opcode_xsr_excsave7_encode_fns, 0, 0 },
+  { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
+    0,
+    Opcode_rsr_eps2_encode_fns, 0, 0 },
+  { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
+    0,
+    Opcode_wsr_eps2_encode_fns, 0, 0 },
+  { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
+    0,
+    Opcode_xsr_eps2_encode_fns, 0, 0 },
+  { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3,
+    0,
+    Opcode_rsr_eps3_encode_fns, 0, 0 },
+  { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3,
+    0,
+    Opcode_wsr_eps3_encode_fns, 0, 0 },
+  { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3,
+    0,
+    Opcode_xsr_eps3_encode_fns, 0, 0 },
+  { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4,
+    0,
+    Opcode_rsr_eps4_encode_fns, 0, 0 },
+  { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4,
+    0,
+    Opcode_wsr_eps4_encode_fns, 0, 0 },
+  { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4,
+    0,
+    Opcode_xsr_eps4_encode_fns, 0, 0 },
+  { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5,
+    0,
+    Opcode_rsr_eps5_encode_fns, 0, 0 },
+  { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5,
+    0,
+    Opcode_wsr_eps5_encode_fns, 0, 0 },
+  { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5,
+    0,
+    Opcode_xsr_eps5_encode_fns, 0, 0 },
+  { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6,
+    0,
+    Opcode_rsr_eps6_encode_fns, 0, 0 },
+  { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6,
+    0,
+    Opcode_wsr_eps6_encode_fns, 0, 0 },
+  { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6,
+    0,
+    Opcode_xsr_eps6_encode_fns, 0, 0 },
+  { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7,
+    0,
+    Opcode_rsr_eps7_encode_fns, 0, 0 },
+  { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7,
+    0,
+    Opcode_wsr_eps7_encode_fns, 0, 0 },
+  { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7,
+    0,
+    Opcode_xsr_eps7_encode_fns, 0, 0 },
+  { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
+    0,
+    Opcode_rsr_excvaddr_encode_fns, 0, 0 },
+  { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
+    0,
+    Opcode_wsr_excvaddr_encode_fns, 0, 0 },
+  { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
+    0,
+    Opcode_xsr_excvaddr_encode_fns, 0, 0 },
+  { "rsr.depc", ICLASS_xt_iclass_rsr_depc,
+    0,
+    Opcode_rsr_depc_encode_fns, 0, 0 },
+  { "wsr.depc", ICLASS_xt_iclass_wsr_depc,
+    0,
+    Opcode_wsr_depc_encode_fns, 0, 0 },
+  { "xsr.depc", ICLASS_xt_iclass_xsr_depc,
+    0,
+    Opcode_xsr_depc_encode_fns, 0, 0 },
+  { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
+    0,
+    Opcode_rsr_exccause_encode_fns, 0, 0 },
+  { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
+    0,
+    Opcode_wsr_exccause_encode_fns, 0, 0 },
+  { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
+    0,
+    Opcode_xsr_exccause_encode_fns, 0, 0 },
+  { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0,
+    0,
+    Opcode_rsr_misc0_encode_fns, 0, 0 },
+  { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0,
+    0,
+    Opcode_wsr_misc0_encode_fns, 0, 0 },
+  { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0,
+    0,
+    Opcode_xsr_misc0_encode_fns, 0, 0 },
+  { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
+    0,
+    Opcode_rsr_misc1_encode_fns, 0, 0 },
+  { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
+    0,
+    Opcode_wsr_misc1_encode_fns, 0, 0 },
+  { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
+    0,
+    Opcode_xsr_misc1_encode_fns, 0, 0 },
+  { "rsr.misc2", ICLASS_xt_iclass_rsr_misc2,
+    0,
+    Opcode_rsr_misc2_encode_fns, 0, 0 },
+  { "wsr.misc2", ICLASS_xt_iclass_wsr_misc2,
+    0,
+    Opcode_wsr_misc2_encode_fns, 0, 0 },
+  { "xsr.misc2", ICLASS_xt_iclass_xsr_misc2,
+    0,
+    Opcode_xsr_misc2_encode_fns, 0, 0 },
+  { "rsr.misc3", ICLASS_xt_iclass_rsr_misc3,
+    0,
+    Opcode_rsr_misc3_encode_fns, 0, 0 },
+  { "wsr.misc3", ICLASS_xt_iclass_wsr_misc3,
+    0,
+    Opcode_wsr_misc3_encode_fns, 0, 0 },
+  { "xsr.misc3", ICLASS_xt_iclass_xsr_misc3,
+    0,
+    Opcode_xsr_misc3_encode_fns, 0, 0 },
+  { "rsr.prid", ICLASS_xt_iclass_rsr_prid,
+    0,
+    Opcode_rsr_prid_encode_fns, 0, 0 },
+  { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
+    0,
+    Opcode_rsr_vecbase_encode_fns, 0, 0 },
+  { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
+    0,
+    Opcode_wsr_vecbase_encode_fns, 0, 0 },
+  { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
+    0,
+    Opcode_xsr_vecbase_encode_fns, 0, 0 },
+  { "mul16u", ICLASS_xt_mul16,
+    0,
+    Opcode_mul16u_encode_fns, 0, 0 },
+  { "mul16s", ICLASS_xt_mul16,
+    0,
+    Opcode_mul16s_encode_fns, 0, 0 },
+  { "mull", ICLASS_xt_mul32,
+    0,
+    Opcode_mull_encode_fns, 0, 0 },
+  { "muluh", ICLASS_xt_mul32h,
+    0,
+    Opcode_muluh_encode_fns, 0, 0 },
+  { "mulsh", ICLASS_xt_mul32h,
+    0,
+    Opcode_mulsh_encode_fns, 0, 0 },
+  { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa,
+    0,
+    Opcode_mul_aa_ll_encode_fns, 0, 0 },
+  { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa,
+    0,
+    Opcode_mul_aa_hl_encode_fns, 0, 0 },
+  { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa,
+    0,
+    Opcode_mul_aa_lh_encode_fns, 0, 0 },
+  { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa,
+    0,
+    Opcode_mul_aa_hh_encode_fns, 0, 0 },
+  { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa,
+    0,
+    Opcode_umul_aa_ll_encode_fns, 0, 0 },
+  { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa,
+    0,
+    Opcode_umul_aa_hl_encode_fns, 0, 0 },
+  { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa,
+    0,
+    Opcode_umul_aa_lh_encode_fns, 0, 0 },
+  { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa,
+    0,
+    Opcode_umul_aa_hh_encode_fns, 0, 0 },
+  { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad,
+    0,
+    Opcode_mul_ad_ll_encode_fns, 0, 0 },
+  { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad,
+    0,
+    Opcode_mul_ad_hl_encode_fns, 0, 0 },
+  { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad,
+    0,
+    Opcode_mul_ad_lh_encode_fns, 0, 0 },
+  { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad,
+    0,
+    Opcode_mul_ad_hh_encode_fns, 0, 0 },
+  { "mul.da.ll", ICLASS_xt_iclass_mac16_da,
+    0,
+    Opcode_mul_da_ll_encode_fns, 0, 0 },
+  { "mul.da.hl", ICLASS_xt_iclass_mac16_da,
+    0,
+    Opcode_mul_da_hl_encode_fns, 0, 0 },
+  { "mul.da.lh", ICLASS_xt_iclass_mac16_da,
+    0,
+    Opcode_mul_da_lh_encode_fns, 0, 0 },
+  { "mul.da.hh", ICLASS_xt_iclass_mac16_da,
+    0,
+    Opcode_mul_da_hh_encode_fns, 0, 0 },
+  { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd,
+    0,
+    Opcode_mul_dd_ll_encode_fns, 0, 0 },
+  { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd,
+    0,
+    Opcode_mul_dd_hl_encode_fns, 0, 0 },
+  { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd,
+    0,
+    Opcode_mul_dd_lh_encode_fns, 0, 0 },
+  { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd,
+    0,
+    Opcode_mul_dd_hh_encode_fns, 0, 0 },
+  { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa,
+    0,
+    Opcode_mula_aa_ll_encode_fns, 0, 0 },
+  { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa,
+    0,
+    Opcode_mula_aa_hl_encode_fns, 0, 0 },
+  { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa,
+    0,
+    Opcode_mula_aa_lh_encode_fns, 0, 0 },
+  { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa,
+    0,
+    Opcode_mula_aa_hh_encode_fns, 0, 0 },
+  { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa,
+    0,
+    Opcode_muls_aa_ll_encode_fns, 0, 0 },
+  { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa,
+    0,
+    Opcode_muls_aa_hl_encode_fns, 0, 0 },
+  { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa,
+    0,
+    Opcode_muls_aa_lh_encode_fns, 0, 0 },
+  { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa,
+    0,
+    Opcode_muls_aa_hh_encode_fns, 0, 0 },
+  { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad,
+    0,
+    Opcode_mula_ad_ll_encode_fns, 0, 0 },
+  { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad,
+    0,
+    Opcode_mula_ad_hl_encode_fns, 0, 0 },
+  { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad,
+    0,
+    Opcode_mula_ad_lh_encode_fns, 0, 0 },
+  { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad,
+    0,
+    Opcode_mula_ad_hh_encode_fns, 0, 0 },
+  { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad,
+    0,
+    Opcode_muls_ad_ll_encode_fns, 0, 0 },
+  { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad,
+    0,
+    Opcode_muls_ad_hl_encode_fns, 0, 0 },
+  { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad,
+    0,
+    Opcode_muls_ad_lh_encode_fns, 0, 0 },
+  { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad,
+    0,
+    Opcode_muls_ad_hh_encode_fns, 0, 0 },
+  { "mula.da.ll", ICLASS_xt_iclass_mac16a_da,
+    0,
+    Opcode_mula_da_ll_encode_fns, 0, 0 },
+  { "mula.da.hl", ICLASS_xt_iclass_mac16a_da,
+    0,
+    Opcode_mula_da_hl_encode_fns, 0, 0 },
+  { "mula.da.lh", ICLASS_xt_iclass_mac16a_da,
+    0,
+    Opcode_mula_da_lh_encode_fns, 0, 0 },
+  { "mula.da.hh", ICLASS_xt_iclass_mac16a_da,
+    0,
+    Opcode_mula_da_hh_encode_fns, 0, 0 },
+  { "muls.da.ll", ICLASS_xt_iclass_mac16a_da,
+    0,
+    Opcode_muls_da_ll_encode_fns, 0, 0 },
+  { "muls.da.hl", ICLASS_xt_iclass_mac16a_da,
+    0,
+    Opcode_muls_da_hl_encode_fns, 0, 0 },
+  { "muls.da.lh", ICLASS_xt_iclass_mac16a_da,
+    0,
+    Opcode_muls_da_lh_encode_fns, 0, 0 },
+  { "muls.da.hh", ICLASS_xt_iclass_mac16a_da,
+    0,
+    Opcode_muls_da_hh_encode_fns, 0, 0 },
+  { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd,
+    0,
+    Opcode_mula_dd_ll_encode_fns, 0, 0 },
+  { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd,
+    0,
+    Opcode_mula_dd_hl_encode_fns, 0, 0 },
+  { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd,
+    0,
+    Opcode_mula_dd_lh_encode_fns, 0, 0 },
+  { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd,
+    0,
+    Opcode_mula_dd_hh_encode_fns, 0, 0 },
+  { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd,
+    0,
+    Opcode_muls_dd_ll_encode_fns, 0, 0 },
+  { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd,
+    0,
+    Opcode_muls_dd_hl_encode_fns, 0, 0 },
+  { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd,
+    0,
+    Opcode_muls_dd_lh_encode_fns, 0, 0 },
+  { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd,
+    0,
+    Opcode_muls_dd_hh_encode_fns, 0, 0 },
+  { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da,
+    0,
+    Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
+  { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da,
+    0,
+    Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
+  { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da,
+    0,
+    Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
+  { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da,
+    0,
+    Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
+  { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da,
+    0,
+    Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
+  { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da,
+    0,
+    Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
+  { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da,
+    0,
+    Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
+  { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da,
+    0,
+    Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
+  { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd,
+    0,
+    Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
+  { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd,
+    0,
+    Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
+  { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd,
+    0,
+    Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
+  { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd,
+    0,
+    Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
+  { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd,
+    0,
+    Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
+  { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd,
+    0,
+    Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
+  { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd,
+    0,
+    Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
+  { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd,
+    0,
+    Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
+  { "lddec", ICLASS_xt_iclass_mac16_l,
+    0,
+    Opcode_lddec_encode_fns, 0, 0 },
+  { "ldinc", ICLASS_xt_iclass_mac16_l,
+    0,
+    Opcode_ldinc_encode_fns, 0, 0 },
+  { "rsr.m0", ICLASS_xt_iclass_rsr_m0,
+    0,
+    Opcode_rsr_m0_encode_fns, 0, 0 },
+  { "wsr.m0", ICLASS_xt_iclass_wsr_m0,
+    0,
+    Opcode_wsr_m0_encode_fns, 0, 0 },
+  { "xsr.m0", ICLASS_xt_iclass_xsr_m0,
+    0,
+    Opcode_xsr_m0_encode_fns, 0, 0 },
+  { "rsr.m1", ICLASS_xt_iclass_rsr_m1,
+    0,
+    Opcode_rsr_m1_encode_fns, 0, 0 },
+  { "wsr.m1", ICLASS_xt_iclass_wsr_m1,
+    0,
+    Opcode_wsr_m1_encode_fns, 0, 0 },
+  { "xsr.m1", ICLASS_xt_iclass_xsr_m1,
+    0,
+    Opcode_xsr_m1_encode_fns, 0, 0 },
+  { "rsr.m2", ICLASS_xt_iclass_rsr_m2,
+    0,
+    Opcode_rsr_m2_encode_fns, 0, 0 },
+  { "wsr.m2", ICLASS_xt_iclass_wsr_m2,
+    0,
+    Opcode_wsr_m2_encode_fns, 0, 0 },
+  { "xsr.m2", ICLASS_xt_iclass_xsr_m2,
+    0,
+    Opcode_xsr_m2_encode_fns, 0, 0 },
+  { "rsr.m3", ICLASS_xt_iclass_rsr_m3,
+    0,
+    Opcode_rsr_m3_encode_fns, 0, 0 },
+  { "wsr.m3", ICLASS_xt_iclass_wsr_m3,
+    0,
+    Opcode_wsr_m3_encode_fns, 0, 0 },
+  { "xsr.m3", ICLASS_xt_iclass_xsr_m3,
+    0,
+    Opcode_xsr_m3_encode_fns, 0, 0 },
+  { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo,
+    0,
+    Opcode_rsr_acclo_encode_fns, 0, 0 },
+  { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo,
+    0,
+    Opcode_wsr_acclo_encode_fns, 0, 0 },
+  { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo,
+    0,
+    Opcode_xsr_acclo_encode_fns, 0, 0 },
+  { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi,
+    0,
+    Opcode_rsr_acchi_encode_fns, 0, 0 },
+  { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi,
+    0,
+    Opcode_wsr_acchi_encode_fns, 0, 0 },
+  { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi,
+    0,
+    Opcode_xsr_acchi_encode_fns, 0, 0 },
+  { "rfi", ICLASS_xt_iclass_rfi,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_rfi_encode_fns, 0, 0 },
+  { "waiti", ICLASS_xt_iclass_wait,
+    0,
+    Opcode_waiti_encode_fns, 0, 0 },
+  { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
+    0,
+    Opcode_rsr_interrupt_encode_fns, 0, 0 },
+  { "wsr.intset", ICLASS_xt_iclass_wsr_intset,
+    0,
+    Opcode_wsr_intset_encode_fns, 0, 0 },
+  { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
+    0,
+    Opcode_wsr_intclear_encode_fns, 0, 0 },
+  { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
+    0,
+    Opcode_rsr_intenable_encode_fns, 0, 0 },
+  { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
+    0,
+    Opcode_wsr_intenable_encode_fns, 0, 0 },
+  { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
+    0,
+    Opcode_xsr_intenable_encode_fns, 0, 0 },
+  { "break", ICLASS_xt_iclass_break,
+    0,
+    Opcode_break_encode_fns, 0, 0 },
+  { "break.n", ICLASS_xt_iclass_break_n,
+    0,
+    Opcode_break_n_encode_fns, 0, 0 },
+  { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0,
+    0,
+    Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
+  { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0,
+    0,
+    Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
+  { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0,
+    0,
+    Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
+  { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0,
+    0,
+    Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
+  { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0,
+    0,
+    Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
+  { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0,
+    0,
+    Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
+  { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1,
+    0,
+    Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
+  { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1,
+    0,
+    Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
+  { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1,
+    0,
+    Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
+  { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1,
+    0,
+    Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
+  { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1,
+    0,
+    Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
+  { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1,
+    0,
+    Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
+  { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0,
+    0,
+    Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
+  { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0,
+    0,
+    Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
+  { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0,
+    0,
+    Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
+  { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1,
+    0,
+    Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
+  { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1,
+    0,
+    Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
+  { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1,
+    0,
+    Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
+  { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable,
+    0,
+    Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
+  { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable,
+    0,
+    Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
+  { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable,
+    0,
+    Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
+  { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
+    0,
+    Opcode_rsr_debugcause_encode_fns, 0, 0 },
+  { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
+    0,
+    Opcode_wsr_debugcause_encode_fns, 0, 0 },
+  { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
+    0,
+    Opcode_xsr_debugcause_encode_fns, 0, 0 },
+  { "rsr.icount", ICLASS_xt_iclass_rsr_icount,
+    0,
+    Opcode_rsr_icount_encode_fns, 0, 0 },
+  { "wsr.icount", ICLASS_xt_iclass_wsr_icount,
+    0,
+    Opcode_wsr_icount_encode_fns, 0, 0 },
+  { "xsr.icount", ICLASS_xt_iclass_xsr_icount,
+    0,
+    Opcode_xsr_icount_encode_fns, 0, 0 },
+  { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
+    0,
+    Opcode_rsr_icountlevel_encode_fns, 0, 0 },
+  { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
+    0,
+    Opcode_wsr_icountlevel_encode_fns, 0, 0 },
+  { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
+    0,
+    Opcode_xsr_icountlevel_encode_fns, 0, 0 },
+  { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
+    0,
+    Opcode_rsr_ddr_encode_fns, 0, 0 },
+  { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
+    0,
+    Opcode_wsr_ddr_encode_fns, 0, 0 },
+  { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
+    0,
+    Opcode_xsr_ddr_encode_fns, 0, 0 },
+  { "lddr32.p", ICLASS_xt_iclass_lddr32_p,
+    0,
+    Opcode_lddr32_p_encode_fns, 0, 0 },
+  { "sddr32.p", ICLASS_xt_iclass_sddr32_p,
+    0,
+    Opcode_sddr32_p_encode_fns, 0, 0 },
+  { "rfdo", ICLASS_xt_iclass_rfdo,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_rfdo_encode_fns, 0, 0 },
+  { "rfdd", ICLASS_xt_iclass_rfdd,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_rfdd_encode_fns, 0, 0 },
+  { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid,
+    0,
+    Opcode_wsr_mmid_encode_fns, 0, 0 },
+  { "andb", ICLASS_xt_iclass_bbool1,
+    0,
+    Opcode_andb_encode_fns, 0, 0 },
+  { "andbc", ICLASS_xt_iclass_bbool1,
+    0,
+    Opcode_andbc_encode_fns, 0, 0 },
+  { "orb", ICLASS_xt_iclass_bbool1,
+    0,
+    Opcode_orb_encode_fns, 0, 0 },
+  { "orbc", ICLASS_xt_iclass_bbool1,
+    0,
+    Opcode_orbc_encode_fns, 0, 0 },
+  { "xorb", ICLASS_xt_iclass_bbool1,
+    0,
+    Opcode_xorb_encode_fns, 0, 0 },
+  { "any4", ICLASS_xt_iclass_bbool4,
+    0,
+    Opcode_any4_encode_fns, 0, 0 },
+  { "all4", ICLASS_xt_iclass_bbool4,
+    0,
+    Opcode_all4_encode_fns, 0, 0 },
+  { "any8", ICLASS_xt_iclass_bbool8,
+    0,
+    Opcode_any8_encode_fns, 0, 0 },
+  { "all8", ICLASS_xt_iclass_bbool8,
+    0,
+    Opcode_all8_encode_fns, 0, 0 },
+  { "bf", ICLASS_xt_iclass_bbranch,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bf_encode_fns, 0, 0 },
+  { "bt", ICLASS_xt_iclass_bbranch,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bt_encode_fns, 0, 0 },
+  { "movf", ICLASS_xt_iclass_bmove,
+    0,
+    Opcode_movf_encode_fns, 0, 0 },
+  { "movt", ICLASS_xt_iclass_bmove,
+    0,
+    Opcode_movt_encode_fns, 0, 0 },
+  { "rsr.br", ICLASS_xt_iclass_RSR_BR,
+    0,
+    Opcode_rsr_br_encode_fns, 0, 0 },
+  { "wsr.br", ICLASS_xt_iclass_WSR_BR,
+    0,
+    Opcode_wsr_br_encode_fns, 0, 0 },
+  { "xsr.br", ICLASS_xt_iclass_XSR_BR,
+    0,
+    Opcode_xsr_br_encode_fns, 0, 0 },
+  { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
+    0,
+    Opcode_rsr_ccount_encode_fns, 0, 0 },
+  { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
+    0,
+    Opcode_wsr_ccount_encode_fns, 0, 0 },
+  { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
+    0,
+    Opcode_xsr_ccount_encode_fns, 0, 0 },
+  { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
+    0,
+    Opcode_rsr_ccompare0_encode_fns, 0, 0 },
+  { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
+    0,
+    Opcode_wsr_ccompare0_encode_fns, 0, 0 },
+  { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
+    0,
+    Opcode_xsr_ccompare0_encode_fns, 0, 0 },
+  { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1,
+    0,
+    Opcode_rsr_ccompare1_encode_fns, 0, 0 },
+  { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1,
+    0,
+    Opcode_wsr_ccompare1_encode_fns, 0, 0 },
+  { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1,
+    0,
+    Opcode_xsr_ccompare1_encode_fns, 0, 0 },
+  { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2,
+    0,
+    Opcode_rsr_ccompare2_encode_fns, 0, 0 },
+  { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2,
+    0,
+    Opcode_wsr_ccompare2_encode_fns, 0, 0 },
+  { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2,
+    0,
+    Opcode_xsr_ccompare2_encode_fns, 0, 0 },
+  { "idtlb", ICLASS_xt_iclass_idtlb,
+    0,
+    Opcode_idtlb_encode_fns, 0, 0 },
+  { "pdtlb", ICLASS_xt_iclass_rdtlb,
+    0,
+    Opcode_pdtlb_encode_fns, 0, 0 },
+  { "rdtlb0", ICLASS_xt_iclass_rdtlb,
+    0,
+    Opcode_rdtlb0_encode_fns, 0, 0 },
+  { "rdtlb1", ICLASS_xt_iclass_rdtlb,
+    0,
+    Opcode_rdtlb1_encode_fns, 0, 0 },
+  { "wdtlb", ICLASS_xt_iclass_wdtlb,
+    0,
+    Opcode_wdtlb_encode_fns, 0, 0 },
+  { "iitlb", ICLASS_xt_iclass_iitlb,
+    0,
+    Opcode_iitlb_encode_fns, 0, 0 },
+  { "pitlb", ICLASS_xt_iclass_ritlb,
+    0,
+    Opcode_pitlb_encode_fns, 0, 0 },
+  { "ritlb0", ICLASS_xt_iclass_ritlb,
+    0,
+    Opcode_ritlb0_encode_fns, 0, 0 },
+  { "ritlb1", ICLASS_xt_iclass_ritlb,
+    0,
+    Opcode_ritlb1_encode_fns, 0, 0 },
+  { "witlb", ICLASS_xt_iclass_witlb,
+    0,
+    Opcode_witlb_encode_fns, 0, 0 },
+  { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable,
+    0,
+    Opcode_rsr_cpenable_encode_fns, 0, 0 },
+  { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable,
+    0,
+    Opcode_wsr_cpenable_encode_fns, 0, 0 },
+  { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable,
+    0,
+    Opcode_xsr_cpenable_encode_fns, 0, 0 },
+  { "clamps", ICLASS_xt_iclass_clamp,
+    0,
+    Opcode_clamps_encode_fns, 0, 0 },
+  { "min", ICLASS_xt_iclass_minmax,
+    0,
+    Opcode_min_encode_fns, 0, 0 },
+  { "max", ICLASS_xt_iclass_minmax,
+    0,
+    Opcode_max_encode_fns, 0, 0 },
+  { "minu", ICLASS_xt_iclass_minmax,
+    0,
+    Opcode_minu_encode_fns, 0, 0 },
+  { "maxu", ICLASS_xt_iclass_minmax,
+    0,
+    Opcode_maxu_encode_fns, 0, 0 },
+  { "nsa", ICLASS_xt_iclass_nsa,
+    0,
+    Opcode_nsa_encode_fns, 0, 0 },
+  { "nsau", ICLASS_xt_iclass_nsa,
+    0,
+    Opcode_nsau_encode_fns, 0, 0 },
+  { "sext", ICLASS_xt_iclass_sx,
+    0,
+    Opcode_sext_encode_fns, 0, 0 },
+  { "l32ai", ICLASS_xt_iclass_l32ai,
+    0,
+    Opcode_l32ai_encode_fns, 0, 0 },
+  { "s32ri", ICLASS_xt_iclass_s32ri,
+    0,
+    Opcode_s32ri_encode_fns, 0, 0 },
+  { "s32c1i", ICLASS_xt_iclass_s32c1i,
+    0,
+    Opcode_s32c1i_encode_fns, 0, 0 },
+  { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1,
+    0,
+    Opcode_rsr_scompare1_encode_fns, 0, 0 },
+  { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1,
+    0,
+    Opcode_wsr_scompare1_encode_fns, 0, 0 },
+  { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1,
+    0,
+    Opcode_xsr_scompare1_encode_fns, 0, 0 },
+  { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl,
+    0,
+    Opcode_rsr_atomctl_encode_fns, 0, 0 },
+  { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl,
+    0,
+    Opcode_wsr_atomctl_encode_fns, 0, 0 },
+  { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl,
+    0,
+    Opcode_xsr_atomctl_encode_fns, 0, 0 },
+  { "quou", ICLASS_xt_iclass_div,
+    0,
+    Opcode_quou_encode_fns, 0, 0 },
+  { "quos", ICLASS_xt_iclass_div,
+    0,
+    Opcode_quos_encode_fns, 0, 0 },
+  { "remu", ICLASS_xt_iclass_div,
+    0,
+    Opcode_remu_encode_fns, 0, 0 },
+  { "rems", ICLASS_xt_iclass_div,
+    0,
+    Opcode_rems_encode_fns, 0, 0 },
+  { "rer", ICLASS_xt_iclass_rer,
+    0,
+    Opcode_rer_encode_fns, 0, 0 },
+  { "wer", ICLASS_xt_iclass_wer,
+    0,
+    Opcode_wer_encode_fns, 0, 0 },
+  { "f64iter", ICLASS_iclass_F64ITER,
+    0,
+    Opcode_f64iter_encode_fns, 0, 0 },
+  { "f64rnd", ICLASS_iclass_F64RND,
+    0,
+    Opcode_f64rnd_encode_fns, 0, 0 },
+  { "f64addc", ICLASS_iclass_F64ADDC_F64SUBC,
+    0,
+    Opcode_f64addc_encode_fns, 0, 0 },
+  { "f64subc", ICLASS_iclass_F64ADDC_F64SUBC,
+    0,
+    Opcode_f64subc_encode_fns, 0, 0 },
+  { "f64sig", ICLASS_iclass_F64SIG,
+    0,
+    Opcode_f64sig_encode_fns, 0, 0 },
+  { "f64cmpl", ICLASS_iclass_F64CMPL,
+    0,
+    Opcode_f64cmpl_encode_fns, 0, 0 },
+  { "f64cmph", ICLASS_iclass_F64CMPH,
+    0,
+    Opcode_f64cmph_encode_fns, 0, 0 },
+  { "f64norm", ICLASS_iclass_F64NORM,
+    0,
+    Opcode_f64norm_encode_fns, 0, 0 },
+  { "f64sexp", ICLASS_iclass_F64SEXP,
+    0,
+    Opcode_f64sexp_encode_fns, 0, 0 },
+  { "rf64r", ICLASS_iclass_RF64R,
+    0,
+    Opcode_rf64r_encode_fns, 0, 0 },
+  { "wf64r", ICLASS_iclass_WF64R,
+    0,
+    Opcode_wf64r_encode_fns, 0, 0 },
+  { "rur.f64r_lo", ICLASS_rur_f64r_lo,
+    0,
+    Opcode_rur_f64r_lo_encode_fns, 0, 0 },
+  { "wur.f64r_lo", ICLASS_wur_f64r_lo,
+    0,
+    Opcode_wur_f64r_lo_encode_fns, 0, 0 },
+  { "rur.f64r_hi", ICLASS_rur_f64r_hi,
+    0,
+    Opcode_rur_f64r_hi_encode_fns, 0, 0 },
+  { "wur.f64r_hi", ICLASS_wur_f64r_hi,
+    0,
+    Opcode_wur_f64r_hi_encode_fns, 0, 0 },
+  { "rur.f64s", ICLASS_rur_f64s,
+    0,
+    Opcode_rur_f64s_encode_fns, 0, 0 },
+  { "wur.f64s", ICLASS_wur_f64s,
+    0,
+    Opcode_wur_f64s_encode_fns, 0, 0 },
+  { "rur.fcr", ICLASS_rur_fcr,
+    0,
+    Opcode_rur_fcr_encode_fns, 0, 0 },
+  { "wur.fcr", ICLASS_wur_fcr,
+    0,
+    Opcode_wur_fcr_encode_fns, 0, 0 },
+  { "rur.fsr", ICLASS_rur_fsr,
+    0,
+    Opcode_rur_fsr_encode_fns, 0, 0 },
+  { "wur.fsr", ICLASS_wur_fsr,
+    0,
+    Opcode_wur_fsr_encode_fns, 0, 0 },
+  { "rur.expstate", ICLASS_rur_expstate,
+    0,
+    Opcode_rur_expstate_encode_fns, 0, 0 },
+  { "wur.expstate", ICLASS_wur_expstate,
+    0,
+    Opcode_wur_expstate_encode_fns, 0, 0 },
+  { "read_impwire", ICLASS_iclass_READ_IMPWIRE,
+    0,
+    Opcode_read_impwire_encode_fns, 0, 0 },
+  { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE,
+    0,
+    Opcode_setb_expstate_encode_fns, 0, 0 },
+  { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE,
+    0,
+    Opcode_clrb_expstate_encode_fns, 0, 0 },
+  { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE,
+    0,
+    Opcode_wrmsk_expstate_encode_fns, 0, 0 }
+};
+
+enum xtensa_opcode_id {
+  OPCODE_LSI,
+  OPCODE_LSIP,
+  OPCODE_LSX,
+  OPCODE_LSXP,
+  OPCODE_SSI,
+  OPCODE_SSIP,
+  OPCODE_SSX,
+  OPCODE_SSXP,
+  OPCODE_ABS_S,
+  OPCODE_NEG_S,
+  OPCODE_MOV_S,
+  OPCODE_MOVEQZ_S,
+  OPCODE_MOVNEZ_S,
+  OPCODE_MOVLTZ_S,
+  OPCODE_MOVGEZ_S,
+  OPCODE_MOVF_S,
+  OPCODE_MOVT_S,
+  OPCODE_WFR,
+  OPCODE_RFR,
+  OPCODE_ROUND_S,
+  OPCODE_CEIL_S,
+  OPCODE_FLOOR_S,
+  OPCODE_TRUNC_S,
+  OPCODE_UTRUNC_S,
+  OPCODE_FLOAT_S,
+  OPCODE_UFLOAT_S,
+  OPCODE_UN_S,
+  OPCODE_ULT_S,
+  OPCODE_ULE_S,
+  OPCODE_UEQ_S,
+  OPCODE_OLT_S,
+  OPCODE_OLE_S,
+  OPCODE_OEQ_S,
+  OPCODE_ADD_S,
+  OPCODE_SUB_S,
+  OPCODE_MUL_S,
+  OPCODE_MADD_S,
+  OPCODE_MSUB_S,
+  OPCODE_SQRT0_S,
+  OPCODE_DIV0_S,
+  OPCODE_RECIP0_S,
+  OPCODE_RSQRT0_S,
+  OPCODE_MADDN_S,
+  OPCODE_DIVN_S,
+  OPCODE_CONST_S,
+  OPCODE_NEXP01_S,
+  OPCODE_ADDEXP_S,
+  OPCODE_ADDEXPM_S,
+  OPCODE_MKDADJ_S,
+  OPCODE_MKSADJ_S,
+  OPCODE_EXCW,
+  OPCODE_RFE,
+  OPCODE_RFDE,
+  OPCODE_SYSCALL,
+  OPCODE_CALL12,
+  OPCODE_CALL8,
+  OPCODE_CALL4,
+  OPCODE_CALLX12,
+  OPCODE_CALLX8,
+  OPCODE_CALLX4,
+  OPCODE_ENTRY,
+  OPCODE_MOVSP,
+  OPCODE_ROTW,
+  OPCODE_RETW,
+  OPCODE_RETW_N,
+  OPCODE_RFWO,
+  OPCODE_RFWU,
+  OPCODE_L32E,
+  OPCODE_S32E,
+  OPCODE_RSR_WINDOWBASE,
+  OPCODE_WSR_WINDOWBASE,
+  OPCODE_XSR_WINDOWBASE,
+  OPCODE_RSR_WINDOWSTART,
+  OPCODE_WSR_WINDOWSTART,
+  OPCODE_XSR_WINDOWSTART,
+  OPCODE_ADD_N,
+  OPCODE_ADDI_N,
+  OPCODE_BEQZ_N,
+  OPCODE_BNEZ_N,
+  OPCODE_ILL_N,
+  OPCODE_L32I_N,
+  OPCODE_MOV_N,
+  OPCODE_MOVI_N,
+  OPCODE_NOP_N,
+  OPCODE_RET_N,
+  OPCODE_S32I_N,
+  OPCODE_RUR_THREADPTR,
+  OPCODE_WUR_THREADPTR,
+  OPCODE_ADDI,
+  OPCODE_ADDMI,
+  OPCODE_ADD,
+  OPCODE_SUB,
+  OPCODE_ADDX2,
+  OPCODE_ADDX4,
+  OPCODE_ADDX8,
+  OPCODE_SUBX2,
+  OPCODE_SUBX4,
+  OPCODE_SUBX8,
+  OPCODE_AND,
+  OPCODE_OR,
+  OPCODE_XOR,
+  OPCODE_BEQI,
+  OPCODE_BNEI,
+  OPCODE_BGEI,
+  OPCODE_BLTI,
+  OPCODE_BBCI,
+  OPCODE_BBSI,
+  OPCODE_BGEUI,
+  OPCODE_BLTUI,
+  OPCODE_BEQ,
+  OPCODE_BNE,
+  OPCODE_BGE,
+  OPCODE_BLT,
+  OPCODE_BGEU,
+  OPCODE_BLTU,
+  OPCODE_BANY,
+  OPCODE_BNONE,
+  OPCODE_BALL,
+  OPCODE_BNALL,
+  OPCODE_BBC,
+  OPCODE_BBS,
+  OPCODE_BEQZ,
+  OPCODE_BNEZ,
+  OPCODE_BGEZ,
+  OPCODE_BLTZ,
+  OPCODE_CALL0,
+  OPCODE_CALLX0,
+  OPCODE_EXTUI,
+  OPCODE_ILL,
+  OPCODE_J,
+  OPCODE_JX,
+  OPCODE_L16UI,
+  OPCODE_L16SI,
+  OPCODE_L32I,
+  OPCODE_L32R,
+  OPCODE_L8UI,
+  OPCODE_LOOP,
+  OPCODE_LOOPNEZ,
+  OPCODE_LOOPGTZ,
+  OPCODE_MOVI,
+  OPCODE_MOVEQZ,
+  OPCODE_MOVNEZ,
+  OPCODE_MOVLTZ,
+  OPCODE_MOVGEZ,
+  OPCODE_NEG,
+  OPCODE_ABS,
+  OPCODE_NOP,
+  OPCODE_RET,
+  OPCODE_SIMCALL,
+  OPCODE_S16I,
+  OPCODE_S32I,
+  OPCODE_S32NB,
+  OPCODE_S8I,
+  OPCODE_SSR,
+  OPCODE_SSL,
+  OPCODE_SSA8L,
+  OPCODE_SSA8B,
+  OPCODE_SSAI,
+  OPCODE_SLL,
+  OPCODE_SRC,
+  OPCODE_SRL,
+  OPCODE_SRA,
+  OPCODE_SLLI,
+  OPCODE_SRAI,
+  OPCODE_SRLI,
+  OPCODE_MEMW,
+  OPCODE_EXTW,
+  OPCODE_ISYNC,
+  OPCODE_RSYNC,
+  OPCODE_ESYNC,
+  OPCODE_DSYNC,
+  OPCODE_RSIL,
+  OPCODE_RSR_LEND,
+  OPCODE_WSR_LEND,
+  OPCODE_XSR_LEND,
+  OPCODE_RSR_LCOUNT,
+  OPCODE_WSR_LCOUNT,
+  OPCODE_XSR_LCOUNT,
+  OPCODE_RSR_LBEG,
+  OPCODE_WSR_LBEG,
+  OPCODE_XSR_LBEG,
+  OPCODE_RSR_SAR,
+  OPCODE_WSR_SAR,
+  OPCODE_XSR_SAR,
+  OPCODE_RSR_MEMCTL,
+  OPCODE_WSR_MEMCTL,
+  OPCODE_XSR_MEMCTL,
+  OPCODE_RSR_LITBASE,
+  OPCODE_WSR_LITBASE,
+  OPCODE_XSR_LITBASE,
+  OPCODE_RSR_CONFIGID0,
+  OPCODE_WSR_CONFIGID0,
+  OPCODE_RSR_CONFIGID1,
+  OPCODE_RSR_PS,
+  OPCODE_WSR_PS,
+  OPCODE_XSR_PS,
+  OPCODE_RSR_EPC1,
+  OPCODE_WSR_EPC1,
+  OPCODE_XSR_EPC1,
+  OPCODE_RSR_EXCSAVE1,
+  OPCODE_WSR_EXCSAVE1,
+  OPCODE_XSR_EXCSAVE1,
+  OPCODE_RSR_EPC2,
+  OPCODE_WSR_EPC2,
+  OPCODE_XSR_EPC2,
+  OPCODE_RSR_EXCSAVE2,
+  OPCODE_WSR_EXCSAVE2,
+  OPCODE_XSR_EXCSAVE2,
+  OPCODE_RSR_EPC3,
+  OPCODE_WSR_EPC3,
+  OPCODE_XSR_EPC3,
+  OPCODE_RSR_EXCSAVE3,
+  OPCODE_WSR_EXCSAVE3,
+  OPCODE_XSR_EXCSAVE3,
+  OPCODE_RSR_EPC4,
+  OPCODE_WSR_EPC4,
+  OPCODE_XSR_EPC4,
+  OPCODE_RSR_EXCSAVE4,
+  OPCODE_WSR_EXCSAVE4,
+  OPCODE_XSR_EXCSAVE4,
+  OPCODE_RSR_EPC5,
+  OPCODE_WSR_EPC5,
+  OPCODE_XSR_EPC5,
+  OPCODE_RSR_EXCSAVE5,
+  OPCODE_WSR_EXCSAVE5,
+  OPCODE_XSR_EXCSAVE5,
+  OPCODE_RSR_EPC6,
+  OPCODE_WSR_EPC6,
+  OPCODE_XSR_EPC6,
+  OPCODE_RSR_EXCSAVE6,
+  OPCODE_WSR_EXCSAVE6,
+  OPCODE_XSR_EXCSAVE6,
+  OPCODE_RSR_EPC7,
+  OPCODE_WSR_EPC7,
+  OPCODE_XSR_EPC7,
+  OPCODE_RSR_EXCSAVE7,
+  OPCODE_WSR_EXCSAVE7,
+  OPCODE_XSR_EXCSAVE7,
+  OPCODE_RSR_EPS2,
+  OPCODE_WSR_EPS2,
+  OPCODE_XSR_EPS2,
+  OPCODE_RSR_EPS3,
+  OPCODE_WSR_EPS3,
+  OPCODE_XSR_EPS3,
+  OPCODE_RSR_EPS4,
+  OPCODE_WSR_EPS4,
+  OPCODE_XSR_EPS4,
+  OPCODE_RSR_EPS5,
+  OPCODE_WSR_EPS5,
+  OPCODE_XSR_EPS5,
+  OPCODE_RSR_EPS6,
+  OPCODE_WSR_EPS6,
+  OPCODE_XSR_EPS6,
+  OPCODE_RSR_EPS7,
+  OPCODE_WSR_EPS7,
+  OPCODE_XSR_EPS7,
+  OPCODE_RSR_EXCVADDR,
+  OPCODE_WSR_EXCVADDR,
+  OPCODE_XSR_EXCVADDR,
+  OPCODE_RSR_DEPC,
+  OPCODE_WSR_DEPC,
+  OPCODE_XSR_DEPC,
+  OPCODE_RSR_EXCCAUSE,
+  OPCODE_WSR_EXCCAUSE,
+  OPCODE_XSR_EXCCAUSE,
+  OPCODE_RSR_MISC0,
+  OPCODE_WSR_MISC0,
+  OPCODE_XSR_MISC0,
+  OPCODE_RSR_MISC1,
+  OPCODE_WSR_MISC1,
+  OPCODE_XSR_MISC1,
+  OPCODE_RSR_MISC2,
+  OPCODE_WSR_MISC2,
+  OPCODE_XSR_MISC2,
+  OPCODE_RSR_MISC3,
+  OPCODE_WSR_MISC3,
+  OPCODE_XSR_MISC3,
+  OPCODE_RSR_PRID,
+  OPCODE_RSR_VECBASE,
+  OPCODE_WSR_VECBASE,
+  OPCODE_XSR_VECBASE,
+  OPCODE_MUL16U,
+  OPCODE_MUL16S,
+  OPCODE_MULL,
+  OPCODE_MULUH,
+  OPCODE_MULSH,
+  OPCODE_MUL_AA_LL,
+  OPCODE_MUL_AA_HL,
+  OPCODE_MUL_AA_LH,
+  OPCODE_MUL_AA_HH,
+  OPCODE_UMUL_AA_LL,
+  OPCODE_UMUL_AA_HL,
+  OPCODE_UMUL_AA_LH,
+  OPCODE_UMUL_AA_HH,
+  OPCODE_MUL_AD_LL,
+  OPCODE_MUL_AD_HL,
+  OPCODE_MUL_AD_LH,
+  OPCODE_MUL_AD_HH,
+  OPCODE_MUL_DA_LL,
+  OPCODE_MUL_DA_HL,
+  OPCODE_MUL_DA_LH,
+  OPCODE_MUL_DA_HH,
+  OPCODE_MUL_DD_LL,
+  OPCODE_MUL_DD_HL,
+  OPCODE_MUL_DD_LH,
+  OPCODE_MUL_DD_HH,
+  OPCODE_MULA_AA_LL,
+  OPCODE_MULA_AA_HL,
+  OPCODE_MULA_AA_LH,
+  OPCODE_MULA_AA_HH,
+  OPCODE_MULS_AA_LL,
+  OPCODE_MULS_AA_HL,
+  OPCODE_MULS_AA_LH,
+  OPCODE_MULS_AA_HH,
+  OPCODE_MULA_AD_LL,
+  OPCODE_MULA_AD_HL,
+  OPCODE_MULA_AD_LH,
+  OPCODE_MULA_AD_HH,
+  OPCODE_MULS_AD_LL,
+  OPCODE_MULS_AD_HL,
+  OPCODE_MULS_AD_LH,
+  OPCODE_MULS_AD_HH,
+  OPCODE_MULA_DA_LL,
+  OPCODE_MULA_DA_HL,
+  OPCODE_MULA_DA_LH,
+  OPCODE_MULA_DA_HH,
+  OPCODE_MULS_DA_LL,
+  OPCODE_MULS_DA_HL,
+  OPCODE_MULS_DA_LH,
+  OPCODE_MULS_DA_HH,
+  OPCODE_MULA_DD_LL,
+  OPCODE_MULA_DD_HL,
+  OPCODE_MULA_DD_LH,
+  OPCODE_MULA_DD_HH,
+  OPCODE_MULS_DD_LL,
+  OPCODE_MULS_DD_HL,
+  OPCODE_MULS_DD_LH,
+  OPCODE_MULS_DD_HH,
+  OPCODE_MULA_DA_LL_LDDEC,
+  OPCODE_MULA_DA_LL_LDINC,
+  OPCODE_MULA_DA_HL_LDDEC,
+  OPCODE_MULA_DA_HL_LDINC,
+  OPCODE_MULA_DA_LH_LDDEC,
+  OPCODE_MULA_DA_LH_LDINC,
+  OPCODE_MULA_DA_HH_LDDEC,
+  OPCODE_MULA_DA_HH_LDINC,
+  OPCODE_MULA_DD_LL_LDDEC,
+  OPCODE_MULA_DD_LL_LDINC,
+  OPCODE_MULA_DD_HL_LDDEC,
+  OPCODE_MULA_DD_HL_LDINC,
+  OPCODE_MULA_DD_LH_LDDEC,
+  OPCODE_MULA_DD_LH_LDINC,
+  OPCODE_MULA_DD_HH_LDDEC,
+  OPCODE_MULA_DD_HH_LDINC,
+  OPCODE_LDDEC,
+  OPCODE_LDINC,
+  OPCODE_RSR_M0,
+  OPCODE_WSR_M0,
+  OPCODE_XSR_M0,
+  OPCODE_RSR_M1,
+  OPCODE_WSR_M1,
+  OPCODE_XSR_M1,
+  OPCODE_RSR_M2,
+  OPCODE_WSR_M2,
+  OPCODE_XSR_M2,
+  OPCODE_RSR_M3,
+  OPCODE_WSR_M3,
+  OPCODE_XSR_M3,
+  OPCODE_RSR_ACCLO,
+  OPCODE_WSR_ACCLO,
+  OPCODE_XSR_ACCLO,
+  OPCODE_RSR_ACCHI,
+  OPCODE_WSR_ACCHI,
+  OPCODE_XSR_ACCHI,
+  OPCODE_RFI,
+  OPCODE_WAITI,
+  OPCODE_RSR_INTERRUPT,
+  OPCODE_WSR_INTSET,
+  OPCODE_WSR_INTCLEAR,
+  OPCODE_RSR_INTENABLE,
+  OPCODE_WSR_INTENABLE,
+  OPCODE_XSR_INTENABLE,
+  OPCODE_BREAK,
+  OPCODE_BREAK_N,
+  OPCODE_RSR_DBREAKA0,
+  OPCODE_WSR_DBREAKA0,
+  OPCODE_XSR_DBREAKA0,
+  OPCODE_RSR_DBREAKC0,
+  OPCODE_WSR_DBREAKC0,
+  OPCODE_XSR_DBREAKC0,
+  OPCODE_RSR_DBREAKA1,
+  OPCODE_WSR_DBREAKA1,
+  OPCODE_XSR_DBREAKA1,
+  OPCODE_RSR_DBREAKC1,
+  OPCODE_WSR_DBREAKC1,
+  OPCODE_XSR_DBREAKC1,
+  OPCODE_RSR_IBREAKA0,
+  OPCODE_WSR_IBREAKA0,
+  OPCODE_XSR_IBREAKA0,
+  OPCODE_RSR_IBREAKA1,
+  OPCODE_WSR_IBREAKA1,
+  OPCODE_XSR_IBREAKA1,
+  OPCODE_RSR_IBREAKENABLE,
+  OPCODE_WSR_IBREAKENABLE,
+  OPCODE_XSR_IBREAKENABLE,
+  OPCODE_RSR_DEBUGCAUSE,
+  OPCODE_WSR_DEBUGCAUSE,
+  OPCODE_XSR_DEBUGCAUSE,
+  OPCODE_RSR_ICOUNT,
+  OPCODE_WSR_ICOUNT,
+  OPCODE_XSR_ICOUNT,
+  OPCODE_RSR_ICOUNTLEVEL,
+  OPCODE_WSR_ICOUNTLEVEL,
+  OPCODE_XSR_ICOUNTLEVEL,
+  OPCODE_RSR_DDR,
+  OPCODE_WSR_DDR,
+  OPCODE_XSR_DDR,
+  OPCODE_LDDR32_P,
+  OPCODE_SDDR32_P,
+  OPCODE_RFDO,
+  OPCODE_RFDD,
+  OPCODE_WSR_MMID,
+  OPCODE_ANDB,
+  OPCODE_ANDBC,
+  OPCODE_ORB,
+  OPCODE_ORBC,
+  OPCODE_XORB,
+  OPCODE_ANY4,
+  OPCODE_ALL4,
+  OPCODE_ANY8,
+  OPCODE_ALL8,
+  OPCODE_BF,
+  OPCODE_BT,
+  OPCODE_MOVF,
+  OPCODE_MOVT,
+  OPCODE_RSR_BR,
+  OPCODE_WSR_BR,
+  OPCODE_XSR_BR,
+  OPCODE_RSR_CCOUNT,
+  OPCODE_WSR_CCOUNT,
+  OPCODE_XSR_CCOUNT,
+  OPCODE_RSR_CCOMPARE0,
+  OPCODE_WSR_CCOMPARE0,
+  OPCODE_XSR_CCOMPARE0,
+  OPCODE_RSR_CCOMPARE1,
+  OPCODE_WSR_CCOMPARE1,
+  OPCODE_XSR_CCOMPARE1,
+  OPCODE_RSR_CCOMPARE2,
+  OPCODE_WSR_CCOMPARE2,
+  OPCODE_XSR_CCOMPARE2,
+  OPCODE_IDTLB,
+  OPCODE_PDTLB,
+  OPCODE_RDTLB0,
+  OPCODE_RDTLB1,
+  OPCODE_WDTLB,
+  OPCODE_IITLB,
+  OPCODE_PITLB,
+  OPCODE_RITLB0,
+  OPCODE_RITLB1,
+  OPCODE_WITLB,
+  OPCODE_RSR_CPENABLE,
+  OPCODE_WSR_CPENABLE,
+  OPCODE_XSR_CPENABLE,
+  OPCODE_CLAMPS,
+  OPCODE_MIN,
+  OPCODE_MAX,
+  OPCODE_MINU,
+  OPCODE_MAXU,
+  OPCODE_NSA,
+  OPCODE_NSAU,
+  OPCODE_SEXT,
+  OPCODE_L32AI,
+  OPCODE_S32RI,
+  OPCODE_S32C1I,
+  OPCODE_RSR_SCOMPARE1,
+  OPCODE_WSR_SCOMPARE1,
+  OPCODE_XSR_SCOMPARE1,
+  OPCODE_RSR_ATOMCTL,
+  OPCODE_WSR_ATOMCTL,
+  OPCODE_XSR_ATOMCTL,
+  OPCODE_QUOU,
+  OPCODE_QUOS,
+  OPCODE_REMU,
+  OPCODE_REMS,
+  OPCODE_RER,
+  OPCODE_WER,
+  OPCODE_F64ITER,
+  OPCODE_F64RND,
+  OPCODE_F64ADDC,
+  OPCODE_F64SUBC,
+  OPCODE_F64SIG,
+  OPCODE_F64CMPL,
+  OPCODE_F64CMPH,
+  OPCODE_F64NORM,
+  OPCODE_F64SEXP,
+  OPCODE_RF64R,
+  OPCODE_WF64R,
+  OPCODE_RUR_F64R_LO,
+  OPCODE_WUR_F64R_LO,
+  OPCODE_RUR_F64R_HI,
+  OPCODE_WUR_F64R_HI,
+  OPCODE_RUR_F64S,
+  OPCODE_WUR_F64S,
+  OPCODE_RUR_FCR,
+  OPCODE_WUR_FCR,
+  OPCODE_RUR_FSR,
+  OPCODE_WUR_FSR,
+  OPCODE_RUR_EXPSTATE,
+  OPCODE_WUR_EXPSTATE,
+  OPCODE_READ_IMPWIRE,
+  OPCODE_SETB_EXPSTATE,
+  OPCODE_CLRB_EXPSTATE,
+  OPCODE_WRMSK_EXPSTATE
+};
+
+\f
+/* Slot-specific opcode decode functions.  */
+
+static int
+Slot_inst_decode (const xtensa_insnbuf insn)
+{
+  if (Field_op0_Slot_inst_get (insn) == 0)
+    {
+      if (Field_op1_Slot_inst_get (insn) == 0)
+	{
+	  if (Field_op2_Slot_inst_get (insn) == 0)
+	    {
+	      if (Field_r_Slot_inst_get (insn) == 0)
+		{
+		  if (Field_m_Slot_inst_get (insn) == 0 &&
+		      Field_s_Slot_inst_get (insn) == 0 &&
+		      Field_n_Slot_inst_get (insn) == 0)
+		    return OPCODE_ILL;
+		  if (Field_m_Slot_inst_get (insn) == 2)
+		    {
+		      if (Field_n_Slot_inst_get (insn) == 0)
+			return OPCODE_RET;
+		      if (Field_n_Slot_inst_get (insn) == 1)
+			return OPCODE_RETW;
+		      if (Field_n_Slot_inst_get (insn) == 2)
+			return OPCODE_JX;
+		    }
+		  if (Field_m_Slot_inst_get (insn) == 3)
+		    {
+		      if (Field_n_Slot_inst_get (insn) == 0)
+			return OPCODE_CALLX0;
+		      if (Field_n_Slot_inst_get (insn) == 1)
+			return OPCODE_CALLX4;
+		      if (Field_n_Slot_inst_get (insn) == 2)
+			return OPCODE_CALLX8;
+		      if (Field_n_Slot_inst_get (insn) == 3)
+			return OPCODE_CALLX12;
+		    }
+		}
+	      if (Field_r_Slot_inst_get (insn) == 1)
+		return OPCODE_MOVSP;
+	      if (Field_r_Slot_inst_get (insn) == 2)
+		{
+		  if (Field_s_Slot_inst_get (insn) == 0)
+		    {
+		      if (Field_t_Slot_inst_get (insn) == 0)
+			return OPCODE_ISYNC;
+		      if (Field_t_Slot_inst_get (insn) == 1)
+			return OPCODE_RSYNC;
+		      if (Field_t_Slot_inst_get (insn) == 2)
+			return OPCODE_ESYNC;
+		      if (Field_t_Slot_inst_get (insn) == 3)
+			return OPCODE_DSYNC;
+		      if (Field_t_Slot_inst_get (insn) == 8)
+			return OPCODE_EXCW;
+		      if (Field_t_Slot_inst_get (insn) == 12)
+			return OPCODE_MEMW;
+		      if (Field_t_Slot_inst_get (insn) == 13)
+			return OPCODE_EXTW;
+		      if (Field_t_Slot_inst_get (insn) == 15)
+			return OPCODE_NOP;
+		    }
+		}
+	      if (Field_r_Slot_inst_get (insn) == 3)
+		{
+		  if (Field_t_Slot_inst_get (insn) == 0)
+		    {
+		      if (Field_s_Slot_inst_get (insn) == 0)
+			return OPCODE_RFE;
+		      if (Field_s_Slot_inst_get (insn) == 2)
+			return OPCODE_RFDE;
+		      if (Field_s_Slot_inst_get (insn) == 4)
+			return OPCODE_RFWO;
+		      if (Field_s_Slot_inst_get (insn) == 5)
+			return OPCODE_RFWU;
+		    }
+		  if (Field_t_Slot_inst_get (insn) == 1)
+		    return OPCODE_RFI;
+		}
+	      if (Field_r_Slot_inst_get (insn) == 4)
+		return OPCODE_BREAK;
+	      if (Field_r_Slot_inst_get (insn) == 5)
+		{
+		  if (Field_s_Slot_inst_get (insn) == 0 &&
+		      Field_t_Slot_inst_get (insn) == 0)
+		    return OPCODE_SYSCALL;
+		  if (Field_s_Slot_inst_get (insn) == 1 &&
+		      Field_t_Slot_inst_get (insn) == 0)
+		    return OPCODE_SIMCALL;
+		}
+	      if (Field_r_Slot_inst_get (insn) == 6)
+		return OPCODE_RSIL;
+	      if (Field_r_Slot_inst_get (insn) == 7 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_WAITI;
+	      if (Field_r_Slot_inst_get (insn) == 7)
+		{
+		  if (Field_t_Slot_inst_get (insn) == 14)
+		    return OPCODE_LDDR32_P;
+		  if (Field_t_Slot_inst_get (insn) == 15)
+		    return OPCODE_SDDR32_P;
+		}
+	      if (Field_r_Slot_inst_get (insn) == 8)
+		return OPCODE_ANY4;
+	      if (Field_r_Slot_inst_get (insn) == 9)
+		return OPCODE_ALL4;
+	      if (Field_r_Slot_inst_get (insn) == 10)
+		return OPCODE_ANY8;
+	      if (Field_r_Slot_inst_get (insn) == 11)
+		return OPCODE_ALL8;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 1)
+	    return OPCODE_AND;
+	  if (Field_op2_Slot_inst_get (insn) == 2)
+	    return OPCODE_OR;
+	  if (Field_op2_Slot_inst_get (insn) == 3)
+	    return OPCODE_XOR;
+	  if (Field_op2_Slot_inst_get (insn) == 4)
+	    {
+	      if (Field_r_Slot_inst_get (insn) == 0 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_SSR;
+	      if (Field_r_Slot_inst_get (insn) == 1 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_SSL;
+	      if (Field_r_Slot_inst_get (insn) == 2 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_SSA8L;
+	      if (Field_r_Slot_inst_get (insn) == 3 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_SSA8B;
+	      if (Field_r_Slot_inst_get (insn) == 4 &&
+		  Field_thi3_Slot_inst_get (insn) == 0)
+		return OPCODE_SSAI;
+	      if (Field_r_Slot_inst_get (insn) == 6)
+		return OPCODE_RER;
+	      if (Field_r_Slot_inst_get (insn) == 7)
+		return OPCODE_WER;
+	      if (Field_r_Slot_inst_get (insn) == 8 &&
+		  Field_s_Slot_inst_get (insn) == 0)
+		return OPCODE_ROTW;
+	      if (Field_r_Slot_inst_get (insn) == 14)
+		return OPCODE_NSA;
+	      if (Field_r_Slot_inst_get (insn) == 15)
+		return OPCODE_NSAU;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 5)
+	    {
+	      if (Field_r_Slot_inst_get (insn) == 3)
+		return OPCODE_RITLB0;
+	      if (Field_r_Slot_inst_get (insn) == 4 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_IITLB;
+	      if (Field_r_Slot_inst_get (insn) == 5)
+		return OPCODE_PITLB;
+	      if (Field_r_Slot_inst_get (insn) == 6)
+		return OPCODE_WITLB;
+	      if (Field_r_Slot_inst_get (insn) == 7)
+		return OPCODE_RITLB1;
+	      if (Field_r_Slot_inst_get (insn) == 11)
+		return OPCODE_RDTLB0;
+	      if (Field_r_Slot_inst_get (insn) == 12 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_IDTLB;
+	      if (Field_r_Slot_inst_get (insn) == 13)
+		return OPCODE_PDTLB;
+	      if (Field_r_Slot_inst_get (insn) == 14)
+		return OPCODE_WDTLB;
+	      if (Field_r_Slot_inst_get (insn) == 15)
+		return OPCODE_RDTLB1;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 6)
+	    {
+	      if (Field_s_Slot_inst_get (insn) == 0)
+		return OPCODE_NEG;
+	      if (Field_s_Slot_inst_get (insn) == 1)
+		return OPCODE_ABS;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 8)
+	    return OPCODE_ADD;
+	  if (Field_op2_Slot_inst_get (insn) == 9)
+	    return OPCODE_ADDX2;
+	  if (Field_op2_Slot_inst_get (insn) == 10)
+	    return OPCODE_ADDX4;
+	  if (Field_op2_Slot_inst_get (insn) == 11)
+	    return OPCODE_ADDX8;
+	  if (Field_op2_Slot_inst_get (insn) == 12)
+	    return OPCODE_SUB;
+	  if (Field_op2_Slot_inst_get (insn) == 13)
+	    return OPCODE_SUBX2;
+	  if (Field_op2_Slot_inst_get (insn) == 14)
+	    return OPCODE_SUBX4;
+	  if (Field_op2_Slot_inst_get (insn) == 15)
+	    return OPCODE_SUBX8;
+	}
+      if (Field_op1_Slot_inst_get (insn) == 1)
+	{
+	  if ((Field_op2_Slot_inst_get (insn) == 0 ||
+	       Field_op2_Slot_inst_get (insn) == 1))
+	    return OPCODE_SLLI;
+	  if ((Field_op2_Slot_inst_get (insn) == 2 ||
+	       Field_op2_Slot_inst_get (insn) == 3))
+	    return OPCODE_SRAI;
+	  if (Field_op2_Slot_inst_get (insn) == 4)
+	    return OPCODE_SRLI;
+	  if (Field_op2_Slot_inst_get (insn) == 6)
+	    {
+	      if (Field_sr_Slot_inst_get (insn) == 0)
+		return OPCODE_XSR_LBEG;
+	      if (Field_sr_Slot_inst_get (insn) == 1)
+		return OPCODE_XSR_LEND;
+	      if (Field_sr_Slot_inst_get (insn) == 2)
+		return OPCODE_XSR_LCOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 3)
+		return OPCODE_XSR_SAR;
+	      if (Field_sr_Slot_inst_get (insn) == 4)
+		return OPCODE_XSR_BR;
+	      if (Field_sr_Slot_inst_get (insn) == 5)
+		return OPCODE_XSR_LITBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 12)
+		return OPCODE_XSR_SCOMPARE1;
+	      if (Field_sr_Slot_inst_get (insn) == 16)
+		return OPCODE_XSR_ACCLO;
+	      if (Field_sr_Slot_inst_get (insn) == 17)
+		return OPCODE_XSR_ACCHI;
+	      if (Field_sr_Slot_inst_get (insn) == 32)
+		return OPCODE_XSR_M0;
+	      if (Field_sr_Slot_inst_get (insn) == 33)
+		return OPCODE_XSR_M1;
+	      if (Field_sr_Slot_inst_get (insn) == 34)
+		return OPCODE_XSR_M2;
+	      if (Field_sr_Slot_inst_get (insn) == 35)
+		return OPCODE_XSR_M3;
+	      if (Field_sr_Slot_inst_get (insn) == 72)
+		return OPCODE_XSR_WINDOWBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 73)
+		return OPCODE_XSR_WINDOWSTART;
+	      if (Field_sr_Slot_inst_get (insn) == 96)
+		return OPCODE_XSR_IBREAKENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 97)
+		return OPCODE_XSR_MEMCTL;
+	      if (Field_sr_Slot_inst_get (insn) == 99)
+		return OPCODE_XSR_ATOMCTL;
+	      if (Field_sr_Slot_inst_get (insn) == 104)
+		return OPCODE_XSR_DDR;
+	      if (Field_sr_Slot_inst_get (insn) == 128)
+		return OPCODE_XSR_IBREAKA0;
+	      if (Field_sr_Slot_inst_get (insn) == 129)
+		return OPCODE_XSR_IBREAKA1;
+	      if (Field_sr_Slot_inst_get (insn) == 144)
+		return OPCODE_XSR_DBREAKA0;
+	      if (Field_sr_Slot_inst_get (insn) == 145)
+		return OPCODE_XSR_DBREAKA1;
+	      if (Field_sr_Slot_inst_get (insn) == 160)
+		return OPCODE_XSR_DBREAKC0;
+	      if (Field_sr_Slot_inst_get (insn) == 161)
+		return OPCODE_XSR_DBREAKC1;
+	      if (Field_sr_Slot_inst_get (insn) == 177)
+		return OPCODE_XSR_EPC1;
+	      if (Field_sr_Slot_inst_get (insn) == 178)
+		return OPCODE_XSR_EPC2;
+	      if (Field_sr_Slot_inst_get (insn) == 179)
+		return OPCODE_XSR_EPC3;
+	      if (Field_sr_Slot_inst_get (insn) == 180)
+		return OPCODE_XSR_EPC4;
+	      if (Field_sr_Slot_inst_get (insn) == 181)
+		return OPCODE_XSR_EPC5;
+	      if (Field_sr_Slot_inst_get (insn) == 182)
+		return OPCODE_XSR_EPC6;
+	      if (Field_sr_Slot_inst_get (insn) == 183)
+		return OPCODE_XSR_EPC7;
+	      if (Field_sr_Slot_inst_get (insn) == 192)
+		return OPCODE_XSR_DEPC;
+	      if (Field_sr_Slot_inst_get (insn) == 194)
+		return OPCODE_XSR_EPS2;
+	      if (Field_sr_Slot_inst_get (insn) == 195)
+		return OPCODE_XSR_EPS3;
+	      if (Field_sr_Slot_inst_get (insn) == 196)
+		return OPCODE_XSR_EPS4;
+	      if (Field_sr_Slot_inst_get (insn) == 197)
+		return OPCODE_XSR_EPS5;
+	      if (Field_sr_Slot_inst_get (insn) == 198)
+		return OPCODE_XSR_EPS6;
+	      if (Field_sr_Slot_inst_get (insn) == 199)
+		return OPCODE_XSR_EPS7;
+	      if (Field_sr_Slot_inst_get (insn) == 209)
+		return OPCODE_XSR_EXCSAVE1;
+	      if (Field_sr_Slot_inst_get (insn) == 210)
+		return OPCODE_XSR_EXCSAVE2;
+	      if (Field_sr_Slot_inst_get (insn) == 211)
+		return OPCODE_XSR_EXCSAVE3;
+	      if (Field_sr_Slot_inst_get (insn) == 212)
+		return OPCODE_XSR_EXCSAVE4;
+	      if (Field_sr_Slot_inst_get (insn) == 213)
+		return OPCODE_XSR_EXCSAVE5;
+	      if (Field_sr_Slot_inst_get (insn) == 214)
+		return OPCODE_XSR_EXCSAVE6;
+	      if (Field_sr_Slot_inst_get (insn) == 215)
+		return OPCODE_XSR_EXCSAVE7;
+	      if (Field_sr_Slot_inst_get (insn) == 224)
+		return OPCODE_XSR_CPENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 228)
+		return OPCODE_XSR_INTENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 230)
+		return OPCODE_XSR_PS;
+	      if (Field_sr_Slot_inst_get (insn) == 231)
+		return OPCODE_XSR_VECBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 232)
+		return OPCODE_XSR_EXCCAUSE;
+	      if (Field_sr_Slot_inst_get (insn) == 233)
+		return OPCODE_XSR_DEBUGCAUSE;
+	      if (Field_sr_Slot_inst_get (insn) == 234)
+		return OPCODE_XSR_CCOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 236)
+		return OPCODE_XSR_ICOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 237)
+		return OPCODE_XSR_ICOUNTLEVEL;
+	      if (Field_sr_Slot_inst_get (insn) == 238)
+		return OPCODE_XSR_EXCVADDR;
+	      if (Field_sr_Slot_inst_get (insn) == 240)
+		return OPCODE_XSR_CCOMPARE0;
+	      if (Field_sr_Slot_inst_get (insn) == 241)
+		return OPCODE_XSR_CCOMPARE1;
+	      if (Field_sr_Slot_inst_get (insn) == 242)
+		return OPCODE_XSR_CCOMPARE2;
+	      if (Field_sr_Slot_inst_get (insn) == 244)
+		return OPCODE_XSR_MISC0;
+	      if (Field_sr_Slot_inst_get (insn) == 245)
+		return OPCODE_XSR_MISC1;
+	      if (Field_sr_Slot_inst_get (insn) == 246)
+		return OPCODE_XSR_MISC2;
+	      if (Field_sr_Slot_inst_get (insn) == 247)
+		return OPCODE_XSR_MISC3;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 8)
+	    return OPCODE_SRC;
+	  if (Field_op2_Slot_inst_get (insn) == 9 &&
+	      Field_s_Slot_inst_get (insn) == 0)
+	    return OPCODE_SRL;
+	  if (Field_op2_Slot_inst_get (insn) == 10 &&
+	      Field_t_Slot_inst_get (insn) == 0)
+	    return OPCODE_SLL;
+	  if (Field_op2_Slot_inst_get (insn) == 11 &&
+	      Field_s_Slot_inst_get (insn) == 0)
+	    return OPCODE_SRA;
+	  if (Field_op2_Slot_inst_get (insn) == 12)
+	    return OPCODE_MUL16U;
+	  if (Field_op2_Slot_inst_get (insn) == 13)
+	    return OPCODE_MUL16S;
+	  if (Field_op2_Slot_inst_get (insn) == 15)
+	    {
+	      if (Field_r_Slot_inst_get (insn) == 14 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_RFDO;
+	      if (Field_r_Slot_inst_get (insn) == 14 &&
+		  Field_t_Slot_inst_get (insn) == 1)
+		return OPCODE_RFDD;
+	    }
+	}
+      if (Field_op1_Slot_inst_get (insn) == 2)
+	{
+	  if (Field_op2_Slot_inst_get (insn) == 0)
+	    return OPCODE_ANDB;
+	  if (Field_op2_Slot_inst_get (insn) == 1)
+	    return OPCODE_ANDBC;
+	  if (Field_op2_Slot_inst_get (insn) == 2)
+	    return OPCODE_ORB;
+	  if (Field_op2_Slot_inst_get (insn) == 3)
+	    return OPCODE_ORBC;
+	  if (Field_op2_Slot_inst_get (insn) == 4)
+	    return OPCODE_XORB;
+	  if (Field_op2_Slot_inst_get (insn) == 8)
+	    return OPCODE_MULL;
+	  if (Field_op2_Slot_inst_get (insn) == 10)
+	    return OPCODE_MULUH;
+	  if (Field_op2_Slot_inst_get (insn) == 11)
+	    return OPCODE_MULSH;
+	  if (Field_op2_Slot_inst_get (insn) == 12)
+	    return OPCODE_QUOU;
+	  if (Field_op2_Slot_inst_get (insn) == 13)
+	    return OPCODE_QUOS;
+	  if (Field_op2_Slot_inst_get (insn) == 14)
+	    return OPCODE_REMU;
+	  if (Field_op2_Slot_inst_get (insn) == 15)
+	    return OPCODE_REMS;
+	}
+      if (Field_op1_Slot_inst_get (insn) == 3)
+	{
+	  if (Field_op2_Slot_inst_get (insn) == 0)
+	    {
+	      if (Field_sr_Slot_inst_get (insn) == 0)
+		return OPCODE_RSR_LBEG;
+	      if (Field_sr_Slot_inst_get (insn) == 1)
+		return OPCODE_RSR_LEND;
+	      if (Field_sr_Slot_inst_get (insn) == 2)
+		return OPCODE_RSR_LCOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 3)
+		return OPCODE_RSR_SAR;
+	      if (Field_sr_Slot_inst_get (insn) == 4)
+		return OPCODE_RSR_BR;
+	      if (Field_sr_Slot_inst_get (insn) == 5)
+		return OPCODE_RSR_LITBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 12)
+		return OPCODE_RSR_SCOMPARE1;
+	      if (Field_sr_Slot_inst_get (insn) == 16)
+		return OPCODE_RSR_ACCLO;
+	      if (Field_sr_Slot_inst_get (insn) == 17)
+		return OPCODE_RSR_ACCHI;
+	      if (Field_sr_Slot_inst_get (insn) == 32)
+		return OPCODE_RSR_M0;
+	      if (Field_sr_Slot_inst_get (insn) == 33)
+		return OPCODE_RSR_M1;
+	      if (Field_sr_Slot_inst_get (insn) == 34)
+		return OPCODE_RSR_M2;
+	      if (Field_sr_Slot_inst_get (insn) == 35)
+		return OPCODE_RSR_M3;
+	      if (Field_sr_Slot_inst_get (insn) == 72)
+		return OPCODE_RSR_WINDOWBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 73)
+		return OPCODE_RSR_WINDOWSTART;
+	      if (Field_sr_Slot_inst_get (insn) == 96)
+		return OPCODE_RSR_IBREAKENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 97)
+		return OPCODE_RSR_MEMCTL;
+	      if (Field_sr_Slot_inst_get (insn) == 99)
+		return OPCODE_RSR_ATOMCTL;
+	      if (Field_sr_Slot_inst_get (insn) == 104)
+		return OPCODE_RSR_DDR;
+	      if (Field_sr_Slot_inst_get (insn) == 128)
+		return OPCODE_RSR_IBREAKA0;
+	      if (Field_sr_Slot_inst_get (insn) == 129)
+		return OPCODE_RSR_IBREAKA1;
+	      if (Field_sr_Slot_inst_get (insn) == 144)
+		return OPCODE_RSR_DBREAKA0;
+	      if (Field_sr_Slot_inst_get (insn) == 145)
+		return OPCODE_RSR_DBREAKA1;
+	      if (Field_sr_Slot_inst_get (insn) == 160)
+		return OPCODE_RSR_DBREAKC0;
+	      if (Field_sr_Slot_inst_get (insn) == 161)
+		return OPCODE_RSR_DBREAKC1;
+	      if (Field_sr_Slot_inst_get (insn) == 176)
+		return OPCODE_RSR_CONFIGID0;
+	      if (Field_sr_Slot_inst_get (insn) == 177)
+		return OPCODE_RSR_EPC1;
+	      if (Field_sr_Slot_inst_get (insn) == 178)
+		return OPCODE_RSR_EPC2;
+	      if (Field_sr_Slot_inst_get (insn) == 179)
+		return OPCODE_RSR_EPC3;
+	      if (Field_sr_Slot_inst_get (insn) == 180)
+		return OPCODE_RSR_EPC4;
+	      if (Field_sr_Slot_inst_get (insn) == 181)
+		return OPCODE_RSR_EPC5;
+	      if (Field_sr_Slot_inst_get (insn) == 182)
+		return OPCODE_RSR_EPC6;
+	      if (Field_sr_Slot_inst_get (insn) == 183)
+		return OPCODE_RSR_EPC7;
+	      if (Field_sr_Slot_inst_get (insn) == 192)
+		return OPCODE_RSR_DEPC;
+	      if (Field_sr_Slot_inst_get (insn) == 194)
+		return OPCODE_RSR_EPS2;
+	      if (Field_sr_Slot_inst_get (insn) == 195)
+		return OPCODE_RSR_EPS3;
+	      if (Field_sr_Slot_inst_get (insn) == 196)
+		return OPCODE_RSR_EPS4;
+	      if (Field_sr_Slot_inst_get (insn) == 197)
+		return OPCODE_RSR_EPS5;
+	      if (Field_sr_Slot_inst_get (insn) == 198)
+		return OPCODE_RSR_EPS6;
+	      if (Field_sr_Slot_inst_get (insn) == 199)
+		return OPCODE_RSR_EPS7;
+	      if (Field_sr_Slot_inst_get (insn) == 208)
+		return OPCODE_RSR_CONFIGID1;
+	      if (Field_sr_Slot_inst_get (insn) == 209)
+		return OPCODE_RSR_EXCSAVE1;
+	      if (Field_sr_Slot_inst_get (insn) == 210)
+		return OPCODE_RSR_EXCSAVE2;
+	      if (Field_sr_Slot_inst_get (insn) == 211)
+		return OPCODE_RSR_EXCSAVE3;
+	      if (Field_sr_Slot_inst_get (insn) == 212)
+		return OPCODE_RSR_EXCSAVE4;
+	      if (Field_sr_Slot_inst_get (insn) == 213)
+		return OPCODE_RSR_EXCSAVE5;
+	      if (Field_sr_Slot_inst_get (insn) == 214)
+		return OPCODE_RSR_EXCSAVE6;
+	      if (Field_sr_Slot_inst_get (insn) == 215)
+		return OPCODE_RSR_EXCSAVE7;
+	      if (Field_sr_Slot_inst_get (insn) == 224)
+		return OPCODE_RSR_CPENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 226)
+		return OPCODE_RSR_INTERRUPT;
+	      if (Field_sr_Slot_inst_get (insn) == 228)
+		return OPCODE_RSR_INTENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 230)
+		return OPCODE_RSR_PS;
+	      if (Field_sr_Slot_inst_get (insn) == 231)
+		return OPCODE_RSR_VECBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 232)
+		return OPCODE_RSR_EXCCAUSE;
+	      if (Field_sr_Slot_inst_get (insn) == 233)
+		return OPCODE_RSR_DEBUGCAUSE;
+	      if (Field_sr_Slot_inst_get (insn) == 234)
+		return OPCODE_RSR_CCOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 235)
+		return OPCODE_RSR_PRID;
+	      if (Field_sr_Slot_inst_get (insn) == 236)
+		return OPCODE_RSR_ICOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 237)
+		return OPCODE_RSR_ICOUNTLEVEL;
+	      if (Field_sr_Slot_inst_get (insn) == 238)
+		return OPCODE_RSR_EXCVADDR;
+	      if (Field_sr_Slot_inst_get (insn) == 240)
+		return OPCODE_RSR_CCOMPARE0;
+	      if (Field_sr_Slot_inst_get (insn) == 241)
+		return OPCODE_RSR_CCOMPARE1;
+	      if (Field_sr_Slot_inst_get (insn) == 242)
+		return OPCODE_RSR_CCOMPARE2;
+	      if (Field_sr_Slot_inst_get (insn) == 244)
+		return OPCODE_RSR_MISC0;
+	      if (Field_sr_Slot_inst_get (insn) == 245)
+		return OPCODE_RSR_MISC1;
+	      if (Field_sr_Slot_inst_get (insn) == 246)
+		return OPCODE_RSR_MISC2;
+	      if (Field_sr_Slot_inst_get (insn) == 247)
+		return OPCODE_RSR_MISC3;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 1)
+	    {
+	      if (Field_sr_Slot_inst_get (insn) == 0)
+		return OPCODE_WSR_LBEG;
+	      if (Field_sr_Slot_inst_get (insn) == 1)
+		return OPCODE_WSR_LEND;
+	      if (Field_sr_Slot_inst_get (insn) == 2)
+		return OPCODE_WSR_LCOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 3)
+		return OPCODE_WSR_SAR;
+	      if (Field_sr_Slot_inst_get (insn) == 4)
+		return OPCODE_WSR_BR;
+	      if (Field_sr_Slot_inst_get (insn) == 5)
+		return OPCODE_WSR_LITBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 12)
+		return OPCODE_WSR_SCOMPARE1;
+	      if (Field_sr_Slot_inst_get (insn) == 16)
+		return OPCODE_WSR_ACCLO;
+	      if (Field_sr_Slot_inst_get (insn) == 17)
+		return OPCODE_WSR_ACCHI;
+	      if (Field_sr_Slot_inst_get (insn) == 32)
+		return OPCODE_WSR_M0;
+	      if (Field_sr_Slot_inst_get (insn) == 33)
+		return OPCODE_WSR_M1;
+	      if (Field_sr_Slot_inst_get (insn) == 34)
+		return OPCODE_WSR_M2;
+	      if (Field_sr_Slot_inst_get (insn) == 35)
+		return OPCODE_WSR_M3;
+	      if (Field_sr_Slot_inst_get (insn) == 72)
+		return OPCODE_WSR_WINDOWBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 73)
+		return OPCODE_WSR_WINDOWSTART;
+	      if (Field_sr_Slot_inst_get (insn) == 89)
+		return OPCODE_WSR_MMID;
+	      if (Field_sr_Slot_inst_get (insn) == 96)
+		return OPCODE_WSR_IBREAKENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 97)
+		return OPCODE_WSR_MEMCTL;
+	      if (Field_sr_Slot_inst_get (insn) == 99)
+		return OPCODE_WSR_ATOMCTL;
+	      if (Field_sr_Slot_inst_get (insn) == 104)
+		return OPCODE_WSR_DDR;
+	      if (Field_sr_Slot_inst_get (insn) == 128)
+		return OPCODE_WSR_IBREAKA0;
+	      if (Field_sr_Slot_inst_get (insn) == 129)
+		return OPCODE_WSR_IBREAKA1;
+	      if (Field_sr_Slot_inst_get (insn) == 144)
+		return OPCODE_WSR_DBREAKA0;
+	      if (Field_sr_Slot_inst_get (insn) == 145)
+		return OPCODE_WSR_DBREAKA1;
+	      if (Field_sr_Slot_inst_get (insn) == 160)
+		return OPCODE_WSR_DBREAKC0;
+	      if (Field_sr_Slot_inst_get (insn) == 161)
+		return OPCODE_WSR_DBREAKC1;
+	      if (Field_sr_Slot_inst_get (insn) == 176)
+		return OPCODE_WSR_CONFIGID0;
+	      if (Field_sr_Slot_inst_get (insn) == 177)
+		return OPCODE_WSR_EPC1;
+	      if (Field_sr_Slot_inst_get (insn) == 178)
+		return OPCODE_WSR_EPC2;
+	      if (Field_sr_Slot_inst_get (insn) == 179)
+		return OPCODE_WSR_EPC3;
+	      if (Field_sr_Slot_inst_get (insn) == 180)
+		return OPCODE_WSR_EPC4;
+	      if (Field_sr_Slot_inst_get (insn) == 181)
+		return OPCODE_WSR_EPC5;
+	      if (Field_sr_Slot_inst_get (insn) == 182)
+		return OPCODE_WSR_EPC6;
+	      if (Field_sr_Slot_inst_get (insn) == 183)
+		return OPCODE_WSR_EPC7;
+	      if (Field_sr_Slot_inst_get (insn) == 192)
+		return OPCODE_WSR_DEPC;
+	      if (Field_sr_Slot_inst_get (insn) == 194)
+		return OPCODE_WSR_EPS2;
+	      if (Field_sr_Slot_inst_get (insn) == 195)
+		return OPCODE_WSR_EPS3;
+	      if (Field_sr_Slot_inst_get (insn) == 196)
+		return OPCODE_WSR_EPS4;
+	      if (Field_sr_Slot_inst_get (insn) == 197)
+		return OPCODE_WSR_EPS5;
+	      if (Field_sr_Slot_inst_get (insn) == 198)
+		return OPCODE_WSR_EPS6;
+	      if (Field_sr_Slot_inst_get (insn) == 199)
+		return OPCODE_WSR_EPS7;
+	      if (Field_sr_Slot_inst_get (insn) == 209)
+		return OPCODE_WSR_EXCSAVE1;
+	      if (Field_sr_Slot_inst_get (insn) == 210)
+		return OPCODE_WSR_EXCSAVE2;
+	      if (Field_sr_Slot_inst_get (insn) == 211)
+		return OPCODE_WSR_EXCSAVE3;
+	      if (Field_sr_Slot_inst_get (insn) == 212)
+		return OPCODE_WSR_EXCSAVE4;
+	      if (Field_sr_Slot_inst_get (insn) == 213)
+		return OPCODE_WSR_EXCSAVE5;
+	      if (Field_sr_Slot_inst_get (insn) == 214)
+		return OPCODE_WSR_EXCSAVE6;
+	      if (Field_sr_Slot_inst_get (insn) == 215)
+		return OPCODE_WSR_EXCSAVE7;
+	      if (Field_sr_Slot_inst_get (insn) == 224)
+		return OPCODE_WSR_CPENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 226)
+		return OPCODE_WSR_INTSET;
+	      if (Field_sr_Slot_inst_get (insn) == 227)
+		return OPCODE_WSR_INTCLEAR;
+	      if (Field_sr_Slot_inst_get (insn) == 228)
+		return OPCODE_WSR_INTENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 230)
+		return OPCODE_WSR_PS;
+	      if (Field_sr_Slot_inst_get (insn) == 231)
+		return OPCODE_WSR_VECBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 232)
+		return OPCODE_WSR_EXCCAUSE;
+	      if (Field_sr_Slot_inst_get (insn) == 233)
+		return OPCODE_WSR_DEBUGCAUSE;
+	      if (Field_sr_Slot_inst_get (insn) == 234)
+		return OPCODE_WSR_CCOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 236)
+		return OPCODE_WSR_ICOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 237)
+		return OPCODE_WSR_ICOUNTLEVEL;
+	      if (Field_sr_Slot_inst_get (insn) == 238)
+		return OPCODE_WSR_EXCVADDR;
+	      if (Field_sr_Slot_inst_get (insn) == 240)
+		return OPCODE_WSR_CCOMPARE0;
+	      if (Field_sr_Slot_inst_get (insn) == 241)
+		return OPCODE_WSR_CCOMPARE1;
+	      if (Field_sr_Slot_inst_get (insn) == 242)
+		return OPCODE_WSR_CCOMPARE2;
+	      if (Field_sr_Slot_inst_get (insn) == 244)
+		return OPCODE_WSR_MISC0;
+	      if (Field_sr_Slot_inst_get (insn) == 245)
+		return OPCODE_WSR_MISC1;
+	      if (Field_sr_Slot_inst_get (insn) == 246)
+		return OPCODE_WSR_MISC2;
+	      if (Field_sr_Slot_inst_get (insn) == 247)
+		return OPCODE_WSR_MISC3;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 2)
+	    return OPCODE_SEXT;
+	  if (Field_op2_Slot_inst_get (insn) == 3)
+	    return OPCODE_CLAMPS;
+	  if (Field_op2_Slot_inst_get (insn) == 4)
+	    return OPCODE_MIN;
+	  if (Field_op2_Slot_inst_get (insn) == 5)
+	    return OPCODE_MAX;
+	  if (Field_op2_Slot_inst_get (insn) == 6)
+	    return OPCODE_MINU;
+	  if (Field_op2_Slot_inst_get (insn) == 7)
+	    return OPCODE_MAXU;
+	  if (Field_op2_Slot_inst_get (insn) == 8)
+	    return OPCODE_MOVEQZ;
+	  if (Field_op2_Slot_inst_get (insn) == 9)
+	    return OPCODE_MOVNEZ;
+	  if (Field_op2_Slot_inst_get (insn) == 10)
+	    return OPCODE_MOVLTZ;
+	  if (Field_op2_Slot_inst_get (insn) == 11)
+	    return OPCODE_MOVGEZ;
+	  if (Field_op2_Slot_inst_get (insn) == 12)
+	    return OPCODE_MOVF;
+	  if (Field_op2_Slot_inst_get (insn) == 13)
+	    return OPCODE_MOVT;
+	  if (Field_op2_Slot_inst_get (insn) == 14)
+	    {
+	      if (Field_st_Slot_inst_get (insn) == 230)
+		return OPCODE_RUR_EXPSTATE;
+	      if (Field_st_Slot_inst_get (insn) == 231)
+		return OPCODE_RUR_THREADPTR;
+	      if (Field_st_Slot_inst_get (insn) == 232)
+		return OPCODE_RUR_FCR;
+	      if (Field_st_Slot_inst_get (insn) == 233)
+		return OPCODE_RUR_FSR;
+	      if (Field_st_Slot_inst_get (insn) == 234)
+		return OPCODE_RUR_F64R_LO;
+	      if (Field_st_Slot_inst_get (insn) == 235)
+		return OPCODE_RUR_F64R_HI;
+	      if (Field_st_Slot_inst_get (insn) == 236)
+		return OPCODE_RUR_F64S;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 15)
+	    {
+	      if (Field_sr_Slot_inst_get (insn) == 230)
+		return OPCODE_WUR_EXPSTATE;
+	      if (Field_sr_Slot_inst_get (insn) == 231)
+		return OPCODE_WUR_THREADPTR;
+	      if (Field_sr_Slot_inst_get (insn) == 232)
+		return OPCODE_WUR_FCR;
+	      if (Field_sr_Slot_inst_get (insn) == 233)
+		return OPCODE_WUR_FSR;
+	      if (Field_sr_Slot_inst_get (insn) == 234)
+		return OPCODE_WUR_F64R_LO;
+	      if (Field_sr_Slot_inst_get (insn) == 235)
+		return OPCODE_WUR_F64R_HI;
+	      if (Field_sr_Slot_inst_get (insn) == 236)
+		return OPCODE_WUR_F64S;
+	    }
+	}
+      if ((Field_op1_Slot_inst_get (insn) == 4 ||
+	   Field_op1_Slot_inst_get (insn) == 5))
+	return OPCODE_EXTUI;
+      if (Field_op1_Slot_inst_get (insn) == 8)
+	{
+	  if (Field_op2_Slot_inst_get (insn) == 0)
+	    return OPCODE_LSX;
+	  if (Field_op2_Slot_inst_get (insn) == 1)
+	    return OPCODE_LSXP;
+	  if (Field_op2_Slot_inst_get (insn) == 4)
+	    return OPCODE_SSX;
+	  if (Field_op2_Slot_inst_get (insn) == 5)
+	    return OPCODE_SSXP;
+	}
+      if (Field_op1_Slot_inst_get (insn) == 9)
+	{
+	  if (Field_op2_Slot_inst_get (insn) == 0)
+	    return OPCODE_L32E;
+	  if (Field_op2_Slot_inst_get (insn) == 4)
+	    return OPCODE_S32E;
+	  if (Field_op2_Slot_inst_get (insn) == 5)
+	    return OPCODE_S32NB;
+	}
+      if (Field_op1_Slot_inst_get (insn) == 10)
+	{
+	  if (Field_op2_Slot_inst_get (insn) == 0)
+	    return OPCODE_ADD_S;
+	  if (Field_op2_Slot_inst_get (insn) == 1)
+	    return OPCODE_SUB_S;
+	  if (Field_op2_Slot_inst_get (insn) == 2)
+	    return OPCODE_MUL_S;
+	  if (Field_op2_Slot_inst_get (insn) == 4)
+	    return OPCODE_MADD_S;
+	  if (Field_op2_Slot_inst_get (insn) == 5)
+	    return OPCODE_MSUB_S;
+	  if (Field_op2_Slot_inst_get (insn) == 6)
+	    return OPCODE_MADDN_S;
+	  if (Field_op2_Slot_inst_get (insn) == 7)
+	    return OPCODE_DIVN_S;
+	  if (Field_op2_Slot_inst_get (insn) == 8)
+	    return OPCODE_ROUND_S;
+	  if (Field_op2_Slot_inst_get (insn) == 9)
+	    return OPCODE_TRUNC_S;
+	  if (Field_op2_Slot_inst_get (insn) == 10)
+	    return OPCODE_FLOOR_S;
+	  if (Field_op2_Slot_inst_get (insn) == 11)
+	    return OPCODE_CEIL_S;
+	  if (Field_op2_Slot_inst_get (insn) == 12)
+	    return OPCODE_FLOAT_S;
+	  if (Field_op2_Slot_inst_get (insn) == 13)
+	    return OPCODE_UFLOAT_S;
+	  if (Field_op2_Slot_inst_get (insn) == 14)
+	    return OPCODE_UTRUNC_S;
+	  if (Field_op2_Slot_inst_get (insn) == 15)
+	    {
+	      if (Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_MOV_S;
+	      if (Field_t_Slot_inst_get (insn) == 1)
+		return OPCODE_ABS_S;
+	      if (Field_t_Slot_inst_get (insn) == 3)
+		return OPCODE_CONST_S;
+	      if (Field_t_Slot_inst_get (insn) == 4)
+		return OPCODE_RFR;
+	      if (Field_t_Slot_inst_get (insn) == 5)
+		return OPCODE_WFR;
+	      if (Field_t_Slot_inst_get (insn) == 6)
+		return OPCODE_NEG_S;
+	      if (Field_t_Slot_inst_get (insn) == 7)
+		return OPCODE_DIV0_S;
+	      if (Field_t_Slot_inst_get (insn) == 8)
+		return OPCODE_RECIP0_S;
+	      if (Field_t_Slot_inst_get (insn) == 9)
+		return OPCODE_SQRT0_S;
+	      if (Field_t_Slot_inst_get (insn) == 10)
+		return OPCODE_RSQRT0_S;
+	      if (Field_t_Slot_inst_get (insn) == 11)
+		return OPCODE_NEXP01_S;
+	      if (Field_t_Slot_inst_get (insn) == 12)
+		return OPCODE_MKSADJ_S;
+	      if (Field_t_Slot_inst_get (insn) == 13)
+		return OPCODE_MKDADJ_S;
+	      if (Field_t_Slot_inst_get (insn) == 14)
+		return OPCODE_ADDEXP_S;
+	      if (Field_t_Slot_inst_get (insn) == 15)
+		return OPCODE_ADDEXPM_S;
+	    }
+	}
+      if (Field_op1_Slot_inst_get (insn) == 11)
+	{
+	  if (Field_op2_Slot_inst_get (insn) == 1)
+	    return OPCODE_UN_S;
+	  if (Field_op2_Slot_inst_get (insn) == 2)
+	    return OPCODE_OEQ_S;
+	  if (Field_op2_Slot_inst_get (insn) == 3)
+	    return OPCODE_UEQ_S;
+	  if (Field_op2_Slot_inst_get (insn) == 4)
+	    return OPCODE_OLT_S;
+	  if (Field_op2_Slot_inst_get (insn) == 5)
+	    return OPCODE_ULT_S;
+	  if (Field_op2_Slot_inst_get (insn) == 6)
+	    return OPCODE_OLE_S;
+	  if (Field_op2_Slot_inst_get (insn) == 7)
+	    return OPCODE_ULE_S;
+	  if (Field_op2_Slot_inst_get (insn) == 8)
+	    return OPCODE_MOVEQZ_S;
+	  if (Field_op2_Slot_inst_get (insn) == 9)
+	    return OPCODE_MOVNEZ_S;
+	  if (Field_op2_Slot_inst_get (insn) == 10)
+	    return OPCODE_MOVLTZ_S;
+	  if (Field_op2_Slot_inst_get (insn) == 11)
+	    return OPCODE_MOVGEZ_S;
+	  if (Field_op2_Slot_inst_get (insn) == 12)
+	    return OPCODE_MOVF_S;
+	  if (Field_op2_Slot_inst_get (insn) == 13)
+	    return OPCODE_MOVT_S;
+	}
+      if (Field_r_Slot_inst_get (insn) == 0 &&
+	  Field_s_Slot_inst_get (insn) == 0 &&
+	  Field_op2_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 14)
+	return OPCODE_READ_IMPWIRE;
+      if (Field_r_Slot_inst_get (insn) == 1 &&
+	  Field_s3to1_Slot_inst_get (insn) == 0 &&
+	  Field_op2_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 14)
+	return OPCODE_SETB_EXPSTATE;
+      if (Field_r_Slot_inst_get (insn) == 1 &&
+	  Field_s3to1_Slot_inst_get (insn) == 1 &&
+	  Field_op2_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 14)
+	return OPCODE_CLRB_EXPSTATE;
+      if (Field_r_Slot_inst_get (insn) == 2 &&
+	  Field_op2_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 14)
+	return OPCODE_WRMSK_EXPSTATE;
+    }
+  if (Field_op0_Slot_inst_get (insn) == 0)
+    {
+      if (Field_dfp_fld_op1_Slot_inst_get (insn) == 11)
+	{
+	  if (Field_dfp_fld_op2_Slot_inst_get (insn) == 0)
+	    {
+	      if (Field_dfp_fld_r_3_1_Slot_inst_get (insn) == 7)
+		return OPCODE_WF64R;
+	      if (Field_dfp_fld_s_3_1_Slot_inst_get (insn) == 7 &&
+		  Field_r_Slot_inst_get (insn) == 12)
+		return OPCODE_RF64R;
+	    }
+	  if (Field_dfp_fld_op2_Slot_inst_get (insn) == 14)
+	    {
+	      return OPCODE_F64CMPL;
+	    }
+	  if (Field_dfp_fld_op2_Slot_inst_get (insn) == 15)
+	    {
+	      if (Field_dfp_fld_r_3_Slot_inst_get (insn) == 0)
+		return OPCODE_F64ADDC;
+	      if (Field_dfp_fld_r_3_Slot_inst_get (insn) == 1)
+		return OPCODE_F64SUBC;
+	    }
+	}
+      if (Field_dfp_fld_op1_Slot_inst_get (insn) == 14)
+	{
+	  if (Field_dfp_fld_op2_Slot_inst_get (insn) == 0)
+	    {
+	      if (Field_r_Slot_inst_get (insn) == 13)
+		return OPCODE_F64SIG;
+	    }
+	  if (Field_dfp_fld_op2_Slot_inst_get (insn) == 1)
+	    {
+	      return OPCODE_F64SEXP;
+	    }
+	  if (Field_dfp_fld_op2_3_Slot_inst_get (insn) == 1)
+	    return OPCODE_F64ITER;
+	  if (Field_dfp_fld_op2_3_1_Slot_inst_get (insn) == 1)
+	    return OPCODE_F64NORM;
+	  if (Field_dfp_fld_op2_3_2_Slot_inst_get (insn) == 1)
+	    return OPCODE_F64RND;
+	}
+      if (Field_dfp_fld_op1_Slot_inst_get (insn) == 15)
+	{
+	  return OPCODE_F64CMPH;
+	}
+    }
+  if (Field_op0_Slot_inst_get (insn) == 1)
+    return OPCODE_L32R;
+  if (Field_op0_Slot_inst_get (insn) == 2)
+    {
+      if (Field_r_Slot_inst_get (insn) == 0)
+	return OPCODE_L8UI;
+      if (Field_r_Slot_inst_get (insn) == 1)
+	return OPCODE_L16UI;
+      if (Field_r_Slot_inst_get (insn) == 2)
+	return OPCODE_L32I;
+      if (Field_r_Slot_inst_get (insn) == 4)
+	return OPCODE_S8I;
+      if (Field_r_Slot_inst_get (insn) == 5)
+	return OPCODE_S16I;
+      if (Field_r_Slot_inst_get (insn) == 6)
+	return OPCODE_S32I;
+      if (Field_r_Slot_inst_get (insn) == 9)
+	return OPCODE_L16SI;
+      if (Field_r_Slot_inst_get (insn) == 10)
+	return OPCODE_MOVI;
+      if (Field_r_Slot_inst_get (insn) == 11)
+	return OPCODE_L32AI;
+      if (Field_r_Slot_inst_get (insn) == 12)
+	return OPCODE_ADDI;
+      if (Field_r_Slot_inst_get (insn) == 13)
+	return OPCODE_ADDMI;
+      if (Field_r_Slot_inst_get (insn) == 14)
+	return OPCODE_S32C1I;
+      if (Field_r_Slot_inst_get (insn) == 15)
+	return OPCODE_S32RI;
+    }
+  if (Field_op0_Slot_inst_get (insn) == 3)
+    {
+      if (Field_r_Slot_inst_get (insn) == 0)
+	return OPCODE_LSI;
+      if (Field_r_Slot_inst_get (insn) == 4)
+	return OPCODE_SSI;
+      if (Field_r_Slot_inst_get (insn) == 8)
+	return OPCODE_LSIP;
+      if (Field_r_Slot_inst_get (insn) == 12)
+	return OPCODE_SSIP;
+    }
+  if (Field_op0_Slot_inst_get (insn) == 4)
+    {
+      if (Field_op2_Slot_inst_get (insn) == 0)
+	{
+	  if (Field_op1_Slot_inst_get (insn) == 8 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DD_LL_LDINC;
+	  if (Field_op1_Slot_inst_get (insn) == 9 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DD_HL_LDINC;
+	  if (Field_op1_Slot_inst_get (insn) == 10 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DD_LH_LDINC;
+	  if (Field_op1_Slot_inst_get (insn) == 11 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DD_HH_LDINC;
+	}
+      if (Field_op2_Slot_inst_get (insn) == 1)
+	{
+	  if (Field_op1_Slot_inst_get (insn) == 8 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DD_LL_LDDEC;
+	  if (Field_op1_Slot_inst_get (insn) == 9 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DD_HL_LDDEC;
+	  if (Field_op1_Slot_inst_get (insn) == 10 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DD_LH_LDDEC;
+	  if (Field_op1_Slot_inst_get (insn) == 11 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DD_HH_LDDEC;
+	}
+      if (Field_op2_Slot_inst_get (insn) == 2)
+	{
+	  if (Field_op1_Slot_inst_get (insn) == 4 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_DD_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 5 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_DD_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 6 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_DD_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 7 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_DD_HH;
+	  if (Field_op1_Slot_inst_get (insn) == 8 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DD_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 9 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DD_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 10 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DD_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 11 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DD_HH;
+	  if (Field_op1_Slot_inst_get (insn) == 12 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_DD_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 13 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_DD_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 14 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_DD_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 15 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_DD_HH;
+	}
+      if (Field_op2_Slot_inst_get (insn) == 3)
+	{
+	  if (Field_op1_Slot_inst_get (insn) == 4 &&
+	      Field_r_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_AD_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 5 &&
+	      Field_r_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_AD_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 6 &&
+	      Field_r_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_AD_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 7 &&
+	      Field_r_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_AD_HH;
+	  if (Field_op1_Slot_inst_get (insn) == 8 &&
+	      Field_r_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_AD_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 9 &&
+	      Field_r_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_AD_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 10 &&
+	      Field_r_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_AD_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 11 &&
+	      Field_r_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_AD_HH;
+	  if (Field_op1_Slot_inst_get (insn) == 12 &&
+	      Field_r_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_AD_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 13 &&
+	      Field_r_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_AD_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 14 &&
+	      Field_r_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_AD_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 15 &&
+	      Field_r_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_AD_HH;
+	}
+      if (Field_op2_Slot_inst_get (insn) == 4)
+	{
+	  if (Field_op1_Slot_inst_get (insn) == 8 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DA_LL_LDINC;
+	  if (Field_op1_Slot_inst_get (insn) == 9 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DA_HL_LDINC;
+	  if (Field_op1_Slot_inst_get (insn) == 10 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DA_LH_LDINC;
+	  if (Field_op1_Slot_inst_get (insn) == 11 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DA_HH_LDINC;
+	}
+      if (Field_op2_Slot_inst_get (insn) == 5)
+	{
+	  if (Field_op1_Slot_inst_get (insn) == 8 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DA_LL_LDDEC;
+	  if (Field_op1_Slot_inst_get (insn) == 9 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DA_HL_LDDEC;
+	  if (Field_op1_Slot_inst_get (insn) == 10 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DA_LH_LDDEC;
+	  if (Field_op1_Slot_inst_get (insn) == 11 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DA_HH_LDDEC;
+	}
+      if (Field_op2_Slot_inst_get (insn) == 6)
+	{
+	  if (Field_op1_Slot_inst_get (insn) == 4 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_DA_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 5 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_DA_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 6 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_DA_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 7 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_DA_HH;
+	  if (Field_op1_Slot_inst_get (insn) == 8 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DA_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 9 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DA_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 10 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DA_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 11 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DA_HH;
+	  if (Field_op1_Slot_inst_get (insn) == 12 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_DA_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 13 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_DA_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 14 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_DA_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 15 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_DA_HH;
+	}
+      if (Field_op2_Slot_inst_get (insn) == 7)
+	{
+	  if (Field_op1_Slot_inst_get (insn) == 0 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_UMUL_AA_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 1 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_UMUL_AA_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 2 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_UMUL_AA_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 3 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_UMUL_AA_HH;
+	  if (Field_op1_Slot_inst_get (insn) == 4 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_AA_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 5 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_AA_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 6 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_AA_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 7 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_AA_HH;
+	  if (Field_op1_Slot_inst_get (insn) == 8 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_AA_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 9 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_AA_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 10 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_AA_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 11 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_AA_HH;
+	  if (Field_op1_Slot_inst_get (insn) == 12 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_AA_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 13 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_AA_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 14 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_AA_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 15 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_AA_HH;
+	}
+      if (Field_op2_Slot_inst_get (insn) == 8)
+	{
+	  if (Field_op1_Slot_inst_get (insn) == 0 &&
+	      Field_t_Slot_inst_get (insn) == 0 &&
+	      Field_rhi_Slot_inst_get (insn) == 0)
+	    return OPCODE_LDINC;
+	}
+      if (Field_op2_Slot_inst_get (insn) == 9)
+	{
+	  if (Field_op1_Slot_inst_get (insn) == 0 &&
+	      Field_t_Slot_inst_get (insn) == 0 &&
+	      Field_rhi_Slot_inst_get (insn) == 0)
+	    return OPCODE_LDDEC;
+	}
+    }
+  if (Field_op0_Slot_inst_get (insn) == 5)
+    {
+      if (Field_n_Slot_inst_get (insn) == 0)
+	return OPCODE_CALL0;
+      if (Field_n_Slot_inst_get (insn) == 1)
+	return OPCODE_CALL4;
+      if (Field_n_Slot_inst_get (insn) == 2)
+	return OPCODE_CALL8;
+      if (Field_n_Slot_inst_get (insn) == 3)
+	return OPCODE_CALL12;
+    }
+  if (Field_op0_Slot_inst_get (insn) == 6)
+    {
+      if (Field_n_Slot_inst_get (insn) == 0)
+	return OPCODE_J;
+      if (Field_n_Slot_inst_get (insn) == 1)
+	{
+	  if (Field_m_Slot_inst_get (insn) == 0)
+	    return OPCODE_BEQZ;
+	  if (Field_m_Slot_inst_get (insn) == 1)
+	    return OPCODE_BNEZ;
+	  if (Field_m_Slot_inst_get (insn) == 2)
+	    return OPCODE_BLTZ;
+	  if (Field_m_Slot_inst_get (insn) == 3)
+	    return OPCODE_BGEZ;
+	}
+      if (Field_n_Slot_inst_get (insn) == 2)
+	{
+	  if (Field_m_Slot_inst_get (insn) == 0)
+	    return OPCODE_BEQI;
+	  if (Field_m_Slot_inst_get (insn) == 1)
+	    return OPCODE_BNEI;
+	  if (Field_m_Slot_inst_get (insn) == 2)
+	    return OPCODE_BLTI;
+	  if (Field_m_Slot_inst_get (insn) == 3)
+	    return OPCODE_BGEI;
+	}
+      if (Field_n_Slot_inst_get (insn) == 3)
+	{
+	  if (Field_m_Slot_inst_get (insn) == 0)
+	    return OPCODE_ENTRY;
+	  if (Field_m_Slot_inst_get (insn) == 1)
+	    {
+	      if (Field_r_Slot_inst_get (insn) == 0)
+		return OPCODE_BF;
+	      if (Field_r_Slot_inst_get (insn) == 1)
+		return OPCODE_BT;
+	      if (Field_r_Slot_inst_get (insn) == 8)
+		return OPCODE_LOOP;
+	      if (Field_r_Slot_inst_get (insn) == 9)
+		return OPCODE_LOOPNEZ;
+	      if (Field_r_Slot_inst_get (insn) == 10)
+		return OPCODE_LOOPGTZ;
+	    }
+	  if (Field_m_Slot_inst_get (insn) == 2)
+	    return OPCODE_BLTUI;
+	  if (Field_m_Slot_inst_get (insn) == 3)
+	    return OPCODE_BGEUI;
+	}
+    }
+  if (Field_op0_Slot_inst_get (insn) == 7)
+    {
+      if (Field_r_Slot_inst_get (insn) == 0)
+	return OPCODE_BNONE;
+      if (Field_r_Slot_inst_get (insn) == 1)
+	return OPCODE_BEQ;
+      if (Field_r_Slot_inst_get (insn) == 2)
+	return OPCODE_BLT;
+      if (Field_r_Slot_inst_get (insn) == 3)
+	return OPCODE_BLTU;
+      if (Field_r_Slot_inst_get (insn) == 4)
+	return OPCODE_BALL;
+      if (Field_r_Slot_inst_get (insn) == 5)
+	return OPCODE_BBC;
+      if ((Field_r_Slot_inst_get (insn) == 6 ||
+	   Field_r_Slot_inst_get (insn) == 7))
+	return OPCODE_BBCI;
+      if (Field_r_Slot_inst_get (insn) == 8)
+	return OPCODE_BANY;
+      if (Field_r_Slot_inst_get (insn) == 9)
+	return OPCODE_BNE;
+      if (Field_r_Slot_inst_get (insn) == 10)
+	return OPCODE_BGE;
+      if (Field_r_Slot_inst_get (insn) == 11)
+	return OPCODE_BGEU;
+      if (Field_r_Slot_inst_get (insn) == 12)
+	return OPCODE_BNALL;
+      if (Field_r_Slot_inst_get (insn) == 13)
+	return OPCODE_BBS;
+      if ((Field_r_Slot_inst_get (insn) == 14 ||
+	   Field_r_Slot_inst_get (insn) == 15))
+	return OPCODE_BBSI;
+    }
+  return 0;
+}
+
+static int
+Slot_inst16b_decode (const xtensa_insnbuf insn)
+{
+  if (Field_op0_Slot_inst16b_get (insn) == 12)
+    {
+      if (Field_i_Slot_inst16b_get (insn) == 0)
+	return OPCODE_MOVI_N;
+      if (Field_i_Slot_inst16b_get (insn) == 1)
+	{
+	  if (Field_z_Slot_inst16b_get (insn) == 0)
+	    return OPCODE_BEQZ_N;
+	  if (Field_z_Slot_inst16b_get (insn) == 1)
+	    return OPCODE_BNEZ_N;
+	}
+    }
+  if (Field_op0_Slot_inst16b_get (insn) == 13)
+    {
+      if (Field_r_Slot_inst16b_get (insn) == 0)
+	return OPCODE_MOV_N;
+      if (Field_r_Slot_inst16b_get (insn) == 15)
+	{
+	  if (Field_t_Slot_inst16b_get (insn) == 0)
+	    return OPCODE_RET_N;
+	  if (Field_t_Slot_inst16b_get (insn) == 1)
+	    return OPCODE_RETW_N;
+	  if (Field_t_Slot_inst16b_get (insn) == 2)
+	    return OPCODE_BREAK_N;
+	  if (Field_t_Slot_inst16b_get (insn) == 3 &&
+	      Field_s_Slot_inst16b_get (insn) == 0)
+	    return OPCODE_NOP_N;
+	  if (Field_t_Slot_inst16b_get (insn) == 6 &&
+	      Field_s_Slot_inst16b_get (insn) == 0)
+	    return OPCODE_ILL_N;
+	}
+    }
+  return 0;
+}
+
+static int
+Slot_inst16a_decode (const xtensa_insnbuf insn)
+{
+  if (Field_op0_Slot_inst16a_get (insn) == 8)
+    return OPCODE_L32I_N;
+  if (Field_op0_Slot_inst16a_get (insn) == 9)
+    return OPCODE_S32I_N;
+  if (Field_op0_Slot_inst16a_get (insn) == 10)
+    return OPCODE_ADD_N;
+  if (Field_op0_Slot_inst16a_get (insn) == 11)
+    return OPCODE_ADDI_N;
+  return 0;
+}
+
+\f
+/* Instruction slots.  */
+
+static void
+Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
+			    xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = (insn[0] & 0xffffff);
+}
+
+static void
+Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
+			    const xtensa_insnbuf slotbuf)
+{
+  insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
+}
+
+static void
+Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
+				xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = (insn[0] & 0xffff);
+}
+
+static void
+Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
+				const xtensa_insnbuf slotbuf)
+{
+  insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
+}
+
+static void
+Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
+				xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = (insn[0] & 0xffff);
+}
+
+static void
+Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
+				const xtensa_insnbuf slotbuf)
+{
+  insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
+}
+
+static xtensa_get_field_fn
+Slot_inst_get_field_fns[] = {
+  Field_t_Slot_inst_get,
+  Field_bbi4_Slot_inst_get,
+  Field_bbi_Slot_inst_get,
+  Field_imm12_Slot_inst_get,
+  Field_imm8_Slot_inst_get,
+  Field_s_Slot_inst_get,
+  Field_imm12b_Slot_inst_get,
+  Field_imm16_Slot_inst_get,
+  Field_m_Slot_inst_get,
+  Field_n_Slot_inst_get,
+  Field_offset_Slot_inst_get,
+  Field_op0_Slot_inst_get,
+  Field_op1_Slot_inst_get,
+  Field_op2_Slot_inst_get,
+  Field_r_Slot_inst_get,
+  Field_sa4_Slot_inst_get,
+  Field_sae4_Slot_inst_get,
+  Field_sae_Slot_inst_get,
+  Field_sal_Slot_inst_get,
+  Field_sargt_Slot_inst_get,
+  Field_sas4_Slot_inst_get,
+  Field_sas_Slot_inst_get,
+  Field_sr_Slot_inst_get,
+  Field_st_Slot_inst_get,
+  Field_thi3_Slot_inst_get,
+  Field_imm4_Slot_inst_get,
+  Field_mn_Slot_inst_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_r3_Slot_inst_get,
+  Field_rbit2_Slot_inst_get,
+  Field_rhi_Slot_inst_get,
+  Field_t3_Slot_inst_get,
+  Field_tbit2_Slot_inst_get,
+  Field_tlo_Slot_inst_get,
+  Field_w_Slot_inst_get,
+  Field_y_Slot_inst_get,
+  Field_x_Slot_inst_get,
+  Field_t2_Slot_inst_get,
+  Field_s2_Slot_inst_get,
+  Field_r2_Slot_inst_get,
+  Field_t4_Slot_inst_get,
+  Field_s4_Slot_inst_get,
+  Field_r4_Slot_inst_get,
+  Field_t8_Slot_inst_get,
+  Field_s8_Slot_inst_get,
+  Field_r8_Slot_inst_get,
+  Field_xt_wbr15_imm_Slot_inst_get,
+  Field_xt_wbr18_imm_Slot_inst_get,
+  Field_dfp_fld_op1_Slot_inst_get,
+  Field_dfp_fld_op2_Slot_inst_get,
+  Field_dfp_fld_r_0_Slot_inst_get,
+  Field_dfp_fld_r_2_1_Slot_inst_get,
+  Field_dfp_fld_r_3_Slot_inst_get,
+  Field_dfp_fld_r_3_1_Slot_inst_get,
+  Field_dfp_fld_s_0_Slot_inst_get,
+  Field_dfp_fld_s_3_1_Slot_inst_get,
+  Field_dfp_fld_op2_0_Slot_inst_get,
+  Field_dfp_fld_op2_1_0_Slot_inst_get,
+  Field_dfp_fld_op2_2_Slot_inst_get,
+  Field_dfp_fld_op2_3_Slot_inst_get,
+  Field_dfp_fld_op2_3_2_Slot_inst_get,
+  Field_dfp_fld_op2_3_1_Slot_inst_get,
+  Field_bitindex_Slot_inst_get,
+  Field_s3to1_Slot_inst_get,
+  Implicit_Field_ar0_get,
+  Implicit_Field_ar4_get,
+  Implicit_Field_ar8_get,
+  Implicit_Field_ar12_get,
+  Implicit_Field_mr0_get,
+  Implicit_Field_mr1_get,
+  Implicit_Field_mr2_get,
+  Implicit_Field_mr3_get,
+  Implicit_Field_bt16_get,
+  Implicit_Field_bs16_get,
+  Implicit_Field_br16_get,
+  Implicit_Field_brall_get
+};
+
+static xtensa_set_field_fn
+Slot_inst_set_field_fns[] = {
+  Field_t_Slot_inst_set,
+  Field_bbi4_Slot_inst_set,
+  Field_bbi_Slot_inst_set,
+  Field_imm12_Slot_inst_set,
+  Field_imm8_Slot_inst_set,
+  Field_s_Slot_inst_set,
+  Field_imm12b_Slot_inst_set,
+  Field_imm16_Slot_inst_set,
+  Field_m_Slot_inst_set,
+  Field_n_Slot_inst_set,
+  Field_offset_Slot_inst_set,
+  Field_op0_Slot_inst_set,
+  Field_op1_Slot_inst_set,
+  Field_op2_Slot_inst_set,
+  Field_r_Slot_inst_set,
+  Field_sa4_Slot_inst_set,
+  Field_sae4_Slot_inst_set,
+  Field_sae_Slot_inst_set,
+  Field_sal_Slot_inst_set,
+  Field_sargt_Slot_inst_set,
+  Field_sas4_Slot_inst_set,
+  Field_sas_Slot_inst_set,
+  Field_sr_Slot_inst_set,
+  Field_st_Slot_inst_set,
+  Field_thi3_Slot_inst_set,
+  Field_imm4_Slot_inst_set,
+  Field_mn_Slot_inst_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_r3_Slot_inst_set,
+  Field_rbit2_Slot_inst_set,
+  Field_rhi_Slot_inst_set,
+  Field_t3_Slot_inst_set,
+  Field_tbit2_Slot_inst_set,
+  Field_tlo_Slot_inst_set,
+  Field_w_Slot_inst_set,
+  Field_y_Slot_inst_set,
+  Field_x_Slot_inst_set,
+  Field_t2_Slot_inst_set,
+  Field_s2_Slot_inst_set,
+  Field_r2_Slot_inst_set,
+  Field_t4_Slot_inst_set,
+  Field_s4_Slot_inst_set,
+  Field_r4_Slot_inst_set,
+  Field_t8_Slot_inst_set,
+  Field_s8_Slot_inst_set,
+  Field_r8_Slot_inst_set,
+  Field_xt_wbr15_imm_Slot_inst_set,
+  Field_xt_wbr18_imm_Slot_inst_set,
+  Field_dfp_fld_op1_Slot_inst_set,
+  Field_dfp_fld_op2_Slot_inst_set,
+  Field_dfp_fld_r_0_Slot_inst_set,
+  Field_dfp_fld_r_2_1_Slot_inst_set,
+  Field_dfp_fld_r_3_Slot_inst_set,
+  Field_dfp_fld_r_3_1_Slot_inst_set,
+  Field_dfp_fld_s_0_Slot_inst_set,
+  Field_dfp_fld_s_3_1_Slot_inst_set,
+  Field_dfp_fld_op2_0_Slot_inst_set,
+  Field_dfp_fld_op2_1_0_Slot_inst_set,
+  Field_dfp_fld_op2_2_Slot_inst_set,
+  Field_dfp_fld_op2_3_Slot_inst_set,
+  Field_dfp_fld_op2_3_2_Slot_inst_set,
+  Field_dfp_fld_op2_3_1_Slot_inst_set,
+  Field_bitindex_Slot_inst_set,
+  Field_s3to1_Slot_inst_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_inst16a_get_field_fns[] = {
+  Field_t_Slot_inst16a_get,
+  0,
+  0,
+  0,
+  0,
+  Field_s_Slot_inst16a_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_op0_Slot_inst16a_get,
+  0,
+  0,
+  Field_r_Slot_inst16a_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_sr_Slot_inst16a_get,
+  Field_st_Slot_inst16a_get,
+  0,
+  Field_imm4_Slot_inst16a_get,
+  0,
+  Field_i_Slot_inst16a_get,
+  Field_imm6lo_Slot_inst16a_get,
+  Field_imm6hi_Slot_inst16a_get,
+  Field_imm7lo_Slot_inst16a_get,
+  Field_imm7hi_Slot_inst16a_get,
+  Field_z_Slot_inst16a_get,
+  Field_imm6_Slot_inst16a_get,
+  Field_imm7_Slot_inst16a_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_t2_Slot_inst16a_get,
+  Field_s2_Slot_inst16a_get,
+  Field_r2_Slot_inst16a_get,
+  Field_t4_Slot_inst16a_get,
+  Field_s4_Slot_inst16a_get,
+  Field_r4_Slot_inst16a_get,
+  Field_t8_Slot_inst16a_get,
+  Field_s8_Slot_inst16a_get,
+  Field_r8_Slot_inst16a_get,
+  0,
+  0,
+  0,
+  0,
+  Field_dfp_fld_r_0_Slot_inst16a_get,
+  Field_dfp_fld_r_2_1_Slot_inst16a_get,
+  Field_dfp_fld_r_3_Slot_inst16a_get,
+  Field_dfp_fld_r_3_1_Slot_inst16a_get,
+  Field_dfp_fld_s_0_Slot_inst16a_get,
+  Field_dfp_fld_s_3_1_Slot_inst16a_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_bitindex_Slot_inst16a_get,
+  Field_s3to1_Slot_inst16a_get,
+  Implicit_Field_ar0_get,
+  Implicit_Field_ar4_get,
+  Implicit_Field_ar8_get,
+  Implicit_Field_ar12_get,
+  Implicit_Field_mr0_get,
+  Implicit_Field_mr1_get,
+  Implicit_Field_mr2_get,
+  Implicit_Field_mr3_get,
+  Implicit_Field_bt16_get,
+  Implicit_Field_bs16_get,
+  Implicit_Field_br16_get,
+  Implicit_Field_brall_get
+};
+
+static xtensa_set_field_fn
+Slot_inst16a_set_field_fns[] = {
+  Field_t_Slot_inst16a_set,
+  0,
+  0,
+  0,
+  0,
+  Field_s_Slot_inst16a_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_op0_Slot_inst16a_set,
+  0,
+  0,
+  Field_r_Slot_inst16a_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_sr_Slot_inst16a_set,
+  Field_st_Slot_inst16a_set,
+  0,
+  Field_imm4_Slot_inst16a_set,
+  0,
+  Field_i_Slot_inst16a_set,
+  Field_imm6lo_Slot_inst16a_set,
+  Field_imm6hi_Slot_inst16a_set,
+  Field_imm7lo_Slot_inst16a_set,
+  Field_imm7hi_Slot_inst16a_set,
+  Field_z_Slot_inst16a_set,
+  Field_imm6_Slot_inst16a_set,
+  Field_imm7_Slot_inst16a_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_t2_Slot_inst16a_set,
+  Field_s2_Slot_inst16a_set,
+  Field_r2_Slot_inst16a_set,
+  Field_t4_Slot_inst16a_set,
+  Field_s4_Slot_inst16a_set,
+  Field_r4_Slot_inst16a_set,
+  Field_t8_Slot_inst16a_set,
+  Field_s8_Slot_inst16a_set,
+  Field_r8_Slot_inst16a_set,
+  0,
+  0,
+  0,
+  0,
+  Field_dfp_fld_r_0_Slot_inst16a_set,
+  Field_dfp_fld_r_2_1_Slot_inst16a_set,
+  Field_dfp_fld_r_3_Slot_inst16a_set,
+  Field_dfp_fld_r_3_1_Slot_inst16a_set,
+  Field_dfp_fld_s_0_Slot_inst16a_set,
+  Field_dfp_fld_s_3_1_Slot_inst16a_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_bitindex_Slot_inst16a_set,
+  Field_s3to1_Slot_inst16a_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_inst16b_get_field_fns[] = {
+  Field_t_Slot_inst16b_get,
+  0,
+  0,
+  0,
+  0,
+  Field_s_Slot_inst16b_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_op0_Slot_inst16b_get,
+  0,
+  0,
+  Field_r_Slot_inst16b_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_sr_Slot_inst16b_get,
+  Field_st_Slot_inst16b_get,
+  0,
+  Field_imm4_Slot_inst16b_get,
+  0,
+  Field_i_Slot_inst16b_get,
+  Field_imm6lo_Slot_inst16b_get,
+  Field_imm6hi_Slot_inst16b_get,
+  Field_imm7lo_Slot_inst16b_get,
+  Field_imm7hi_Slot_inst16b_get,
+  Field_z_Slot_inst16b_get,
+  Field_imm6_Slot_inst16b_get,
+  Field_imm7_Slot_inst16b_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_t2_Slot_inst16b_get,
+  Field_s2_Slot_inst16b_get,
+  Field_r2_Slot_inst16b_get,
+  Field_t4_Slot_inst16b_get,
+  Field_s4_Slot_inst16b_get,
+  Field_r4_Slot_inst16b_get,
+  Field_t8_Slot_inst16b_get,
+  Field_s8_Slot_inst16b_get,
+  Field_r8_Slot_inst16b_get,
+  0,
+  0,
+  0,
+  0,
+  Field_dfp_fld_r_0_Slot_inst16b_get,
+  Field_dfp_fld_r_2_1_Slot_inst16b_get,
+  Field_dfp_fld_r_3_Slot_inst16b_get,
+  Field_dfp_fld_r_3_1_Slot_inst16b_get,
+  Field_dfp_fld_s_0_Slot_inst16b_get,
+  Field_dfp_fld_s_3_1_Slot_inst16b_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_bitindex_Slot_inst16b_get,
+  Field_s3to1_Slot_inst16b_get,
+  Implicit_Field_ar0_get,
+  Implicit_Field_ar4_get,
+  Implicit_Field_ar8_get,
+  Implicit_Field_ar12_get,
+  Implicit_Field_mr0_get,
+  Implicit_Field_mr1_get,
+  Implicit_Field_mr2_get,
+  Implicit_Field_mr3_get,
+  Implicit_Field_bt16_get,
+  Implicit_Field_bs16_get,
+  Implicit_Field_br16_get,
+  Implicit_Field_brall_get
+};
+
+static xtensa_set_field_fn
+Slot_inst16b_set_field_fns[] = {
+  Field_t_Slot_inst16b_set,
+  0,
+  0,
+  0,
+  0,
+  Field_s_Slot_inst16b_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_op0_Slot_inst16b_set,
+  0,
+  0,
+  Field_r_Slot_inst16b_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_sr_Slot_inst16b_set,
+  Field_st_Slot_inst16b_set,
+  0,
+  Field_imm4_Slot_inst16b_set,
+  0,
+  Field_i_Slot_inst16b_set,
+  Field_imm6lo_Slot_inst16b_set,
+  Field_imm6hi_Slot_inst16b_set,
+  Field_imm7lo_Slot_inst16b_set,
+  Field_imm7hi_Slot_inst16b_set,
+  Field_z_Slot_inst16b_set,
+  Field_imm6_Slot_inst16b_set,
+  Field_imm7_Slot_inst16b_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_t2_Slot_inst16b_set,
+  Field_s2_Slot_inst16b_set,
+  Field_r2_Slot_inst16b_set,
+  Field_t4_Slot_inst16b_set,
+  Field_s4_Slot_inst16b_set,
+  Field_r4_Slot_inst16b_set,
+  Field_t8_Slot_inst16b_set,
+  Field_s8_Slot_inst16b_set,
+  Field_r8_Slot_inst16b_set,
+  0,
+  0,
+  0,
+  0,
+  Field_dfp_fld_r_0_Slot_inst16b_set,
+  Field_dfp_fld_r_2_1_Slot_inst16b_set,
+  Field_dfp_fld_r_3_Slot_inst16b_set,
+  Field_dfp_fld_r_3_1_Slot_inst16b_set,
+  Field_dfp_fld_s_0_Slot_inst16b_set,
+  Field_dfp_fld_s_3_1_Slot_inst16b_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_bitindex_Slot_inst16b_set,
+  Field_s3to1_Slot_inst16b_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set
+};
+
+static xtensa_slot_internal slots[] = {
+  { "Inst", "x24", 0,
+    Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
+    Slot_inst_get_field_fns, Slot_inst_set_field_fns,
+    Slot_inst_decode, "nop" },
+  { "Inst16a", "x16a", 0,
+    Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
+    Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
+    Slot_inst16a_decode, "" },
+  { "Inst16b", "x16b", 0,
+    Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
+    Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
+    Slot_inst16b_decode, "nop.n" }
+};
+
+\f
+/* Instruction formats.  */
+
+static void
+Format_x24_encode (xtensa_insnbuf insn)
+{
+  insn[0] = 0;
+}
+
+static void
+Format_x16a_encode (xtensa_insnbuf insn)
+{
+  insn[0] = 0x8;
+}
+
+static void
+Format_x16b_encode (xtensa_insnbuf insn)
+{
+  insn[0] = 0xc;
+}
+
+static int Format_x24_slots[] = { 0 };
+
+static int Format_x16a_slots[] = { 1 };
+
+static int Format_x16b_slots[] = { 2 };
+
+static xtensa_format_internal formats[] = {
+  { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
+  { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
+  { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
+};
+
+
+static int
+format_decoder (const xtensa_insnbuf insn)
+{
+  if ((insn[0] & 0x8) == 0)
+    return 0; /* x24 */
+  if ((insn[0] & 0xc) == 0x8)
+    return 1; /* x16a */
+  if ((insn[0] & 0xe) == 0xc)
+    return 2; /* x16b */
+  return -1;
+}
+
+static int length_table[256] = {
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1
+};
+
+static int
+length_decoder (const unsigned char *insn)
+{
+  int l = insn[0];
+  return length_table[l];
+}
+
+\f
+/* Top-level ISA structure.  */
+
+xtensa_isa_internal xtensa_esp32_modules = {
+  0 /* little-endian */,
+  3 /* insn_size */, 0,
+  3, formats, format_decoder, length_decoder,
+  3, slots,
+  83 /* num_fields */,
+  140, operands,
+  390, iclasses,
+  513, opcodes, 0,
+  8, regfiles,
+  NUM_STATES, states, 0,
+  NUM_SYSREGS, sysregs, 0,
+  { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
+  6, interfaces, 0,
+  0, funcUnits, 0
+};
diff --git a/bfd/xtensa-esp32s2-modules.c b/bfd/xtensa-esp32s2-modules.c
new file mode 100644
index 00000000000..a8f70fd3a5c
--- /dev/null
+++ b/bfd/xtensa-esp32s2-modules.c
@@ -0,0 +1,11671 @@
+/* Xtensa configuration-specific ISA information.
+
+   Customer ID=14525; Build=0x787b1; Copyright (c) 2003-2018 Tensilica Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+#include "ansidecl.h"
+#include <xtensa-isa.h>
+#include "xtensa-isa-internal.h"
+
+\f
+/* Sysregs.  */
+
+static xtensa_sysreg_internal sysregs[] = {
+  { "MMID", 89, 0 },
+  { "DDR", 104, 0 },
+  { "CONFIGID0", 176, 0 },
+  { "CONFIGID1", 208, 0 },
+  { "INTERRUPT", 226, 0 },
+  { "INTCLEAR", 227, 0 },
+  { "CCOUNT", 234, 0 },
+  { "PRID", 235, 0 },
+  { "ICOUNT", 236, 0 },
+  { "CCOMPARE0", 240, 0 },
+  { "CCOMPARE1", 241, 0 },
+  { "CCOMPARE2", 242, 0 },
+  { "VECBASE", 231, 0 },
+  { "EPC1", 177, 0 },
+  { "EPC2", 178, 0 },
+  { "EPC3", 179, 0 },
+  { "EPC4", 180, 0 },
+  { "EPC5", 181, 0 },
+  { "EPC6", 182, 0 },
+  { "EPC7", 183, 0 },
+  { "EXCSAVE1", 209, 0 },
+  { "EXCSAVE2", 210, 0 },
+  { "EXCSAVE3", 211, 0 },
+  { "EXCSAVE4", 212, 0 },
+  { "EXCSAVE5", 213, 0 },
+  { "EXCSAVE6", 214, 0 },
+  { "EXCSAVE7", 215, 0 },
+  { "EPS2", 194, 0 },
+  { "EPS3", 195, 0 },
+  { "EPS4", 196, 0 },
+  { "EPS5", 197, 0 },
+  { "EPS6", 198, 0 },
+  { "EPS7", 199, 0 },
+  { "EXCCAUSE", 232, 0 },
+  { "DEPC", 192, 0 },
+  { "EXCVADDR", 238, 0 },
+  { "WINDOWBASE", 72, 0 },
+  { "WINDOWSTART", 73, 0 },
+  { "SAR", 3, 0 },
+  { "PS", 230, 0 },
+  { "MISC0", 244, 0 },
+  { "MISC1", 245, 0 },
+  { "MISC2", 246, 0 },
+  { "MISC3", 247, 0 },
+  { "INTENABLE", 228, 0 },
+  { "DBREAKA0", 144, 0 },
+  { "DBREAKC0", 160, 0 },
+  { "DBREAKA1", 145, 0 },
+  { "DBREAKC1", 161, 0 },
+  { "IBREAKA0", 128, 0 },
+  { "IBREAKA1", 129, 0 },
+  { "IBREAKENABLE", 96, 0 },
+  { "ICOUNTLEVEL", 237, 0 },
+  { "DEBUGCAUSE", 233, 0 },
+  { "CPENABLE", 224, 0 },
+  { "THREADPTR", 231, 1 },
+  { "GPIO_OUT", 0, 1 }
+};
+
+#define NUM_SYSREGS 57
+#define MAX_SPECIAL_REG 247
+#define MAX_USER_REG 231
+
+\f
+/* Processor states.  */
+
+static xtensa_state_internal states[] = {
+  { "PC", 32, 0 },
+  { "ICOUNT", 32, 0 },
+  { "DDR", 32, 0 },
+  { "INTERRUPT", 32, 0 },
+  { "CCOUNT", 32, 0 },
+  { "XTSYNC", 1, 0 },
+  { "VECBASE", 22, 0 },
+  { "EPC1", 32, 0 },
+  { "EPC2", 32, 0 },
+  { "EPC3", 32, 0 },
+  { "EPC4", 32, 0 },
+  { "EPC5", 32, 0 },
+  { "EPC6", 32, 0 },
+  { "EPC7", 32, 0 },
+  { "EXCSAVE1", 32, 0 },
+  { "EXCSAVE2", 32, 0 },
+  { "EXCSAVE3", 32, 0 },
+  { "EXCSAVE4", 32, 0 },
+  { "EXCSAVE5", 32, 0 },
+  { "EXCSAVE6", 32, 0 },
+  { "EXCSAVE7", 32, 0 },
+  { "EPS2", 13, 0 },
+  { "EPS3", 13, 0 },
+  { "EPS4", 13, 0 },
+  { "EPS5", 13, 0 },
+  { "EPS6", 13, 0 },
+  { "EPS7", 13, 0 },
+  { "EXCCAUSE", 6, 0 },
+  { "PSINTLEVEL", 4, 0 },
+  { "PSUM", 1, 0 },
+  { "PSWOE", 1, 0 },
+  { "PSEXCM", 1, 0 },
+  { "DEPC", 32, 0 },
+  { "EXCVADDR", 32, 0 },
+  { "WindowBase", 4, 0 },
+  { "WindowStart", 16, 0 },
+  { "PSCALLINC", 2, 0 },
+  { "PSOWB", 4, 0 },
+  { "SAR", 6, 0 },
+  { "THREADPTR", 32, 0 },
+  { "MISC0", 32, 0 },
+  { "MISC1", 32, 0 },
+  { "MISC2", 32, 0 },
+  { "MISC3", 32, 0 },
+  { "InOCDMode", 1, 0 },
+  { "INTENABLE", 32, 0 },
+  { "DBREAKA0", 32, 0 },
+  { "DBREAKC0", 8, 0 },
+  { "DBREAKA1", 32, 0 },
+  { "DBREAKC1", 8, 0 },
+  { "IBREAKA0", 32, 0 },
+  { "IBREAKA1", 32, 0 },
+  { "IBREAKENABLE", 2, 0 },
+  { "ICOUNTLEVEL", 4, 0 },
+  { "DEBUGCAUSE", 6, 0 },
+  { "DBNUM", 4, 0 },
+  { "CCOMPARE0", 32, 0 },
+  { "CCOMPARE1", 32, 0 },
+  { "CCOMPARE2", 32, 0 },
+  { "CPENABLE", 8, 0 },
+  { "ERI_RAW_INTERLOCK", 1, 0 },
+  { "GPIO_OUT", 8, XTENSA_STATE_IS_EXPORTED }
+};
+
+#define NUM_STATES 62
+
+enum xtensa_state_id {
+  STATE_PC,
+  STATE_ICOUNT,
+  STATE_DDR,
+  STATE_INTERRUPT,
+  STATE_CCOUNT,
+  STATE_XTSYNC,
+  STATE_VECBASE,
+  STATE_EPC1,
+  STATE_EPC2,
+  STATE_EPC3,
+  STATE_EPC4,
+  STATE_EPC5,
+  STATE_EPC6,
+  STATE_EPC7,
+  STATE_EXCSAVE1,
+  STATE_EXCSAVE2,
+  STATE_EXCSAVE3,
+  STATE_EXCSAVE4,
+  STATE_EXCSAVE5,
+  STATE_EXCSAVE6,
+  STATE_EXCSAVE7,
+  STATE_EPS2,
+  STATE_EPS3,
+  STATE_EPS4,
+  STATE_EPS5,
+  STATE_EPS6,
+  STATE_EPS7,
+  STATE_EXCCAUSE,
+  STATE_PSINTLEVEL,
+  STATE_PSUM,
+  STATE_PSWOE,
+  STATE_PSEXCM,
+  STATE_DEPC,
+  STATE_EXCVADDR,
+  STATE_WindowBase,
+  STATE_WindowStart,
+  STATE_PSCALLINC,
+  STATE_PSOWB,
+  STATE_SAR,
+  STATE_THREADPTR,
+  STATE_MISC0,
+  STATE_MISC1,
+  STATE_MISC2,
+  STATE_MISC3,
+  STATE_InOCDMode,
+  STATE_INTENABLE,
+  STATE_DBREAKA0,
+  STATE_DBREAKC0,
+  STATE_DBREAKA1,
+  STATE_DBREAKC1,
+  STATE_IBREAKA0,
+  STATE_IBREAKA1,
+  STATE_IBREAKENABLE,
+  STATE_ICOUNTLEVEL,
+  STATE_DEBUGCAUSE,
+  STATE_DBNUM,
+  STATE_CCOMPARE0,
+  STATE_CCOMPARE1,
+  STATE_CCOMPARE2,
+  STATE_CPENABLE,
+  STATE_ERI_RAW_INTERLOCK,
+  STATE_GPIO_OUT
+};
+
+\f
+/* Field definitions.  */
+
+static unsigned
+Field_t_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_s_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_r_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
+  return tie_t;
+}
+
+static void
+Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
+}
+
+static unsigned
+Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+  return tie_t;
+}
+
+static void
+Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+  return tie_t;
+}
+
+static void
+Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_n_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+  return tie_t;
+}
+
+static void
+Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_m_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+  return tie_t;
+}
+
+static void
+Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+  tie_t = (val << 24) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_st_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+  tie_t = (val << 24) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+  return tie_t;
+}
+
+static void
+Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_fld_inst_23_12_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_23_12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 20) >> 20;
+  insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_fld_inst_3_0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_3_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_fld_inst_23_8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_23_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 16) >> 16;
+  insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
+}
+
+static unsigned
+Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+  return tie_t;
+}
+
+static void
+Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+  return tie_t;
+}
+
+static void
+Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+  return tie_t;
+}
+
+static void
+Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+  return tie_t;
+}
+
+static void
+Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+  return tie_t;
+}
+
+static void
+Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+  tie_t = (val << 27) >> 31;
+  insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
+  return tie_t;
+}
+
+static void
+Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 20) >> 20;
+  insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
+  return tie_t;
+}
+
+static void
+Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 24) >> 24;
+  insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
+  return tie_t;
+}
+
+static void
+Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 24) >> 24;
+  insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
+  tie_t = (val << 20) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
+  return tie_t;
+}
+
+static void
+Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 16) >> 16;
+  insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
+}
+
+static unsigned
+Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
+  return tie_t;
+}
+
+static void
+Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 14) >> 14;
+  insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+  return tie_t;
+}
+
+static void
+Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+  return tie_t;
+}
+
+static void
+Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+  tie_t = (val << 27) >> 31;
+  insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+  tie_t = (val << 27) >> 31;
+  insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+  tie_t = (val << 27) >> 31;
+  insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+  return tie_t;
+}
+
+static void
+Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+  tie_t = (val << 27) >> 31;
+  insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+  tie_t = (val << 24) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+  tie_t = (val << 24) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+  tie_t = (val << 24) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+  tie_t = (val << 24) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+  return tie_t;
+}
+
+static void
+Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+  tie_t = (val << 28) >> 30;
+  insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+  return tie_t;
+}
+
+static void
+Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+  return tie_t;
+}
+
+static void
+Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+  return tie_t;
+}
+
+static void
+Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+  return tie_t;
+}
+
+static void
+Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+  return tie_t;
+}
+
+static void
+Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+  return tie_t;
+}
+
+static void
+Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+  tie_t = (val << 26) >> 30;
+  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+  tie_t = (val << 26) >> 30;
+  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+  tie_t = (val << 25) >> 29;
+  insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+  tie_t = (val << 25) >> 29;
+  insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
+  return tie_t;
+}
+
+static void
+Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 17) >> 17;
+  insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
+  return tie_t;
+}
+
+static void
+Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 14) >> 14;
+  insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_fld_wr_mask_gpio_out_mask_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_wr_mask_gpio_out_mask_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_wr_mask_gpio_out_value_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_wr_mask_gpio_out_value_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_set_bit_gpio_out_mask_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24);
+  return tie_t;
+}
+
+static void
+Field_fld_set_bit_gpio_out_mask_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 24) >> 24;
+  insn[0] = (insn[0] & ~0xff0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_clr_bit_gpio_out_mask_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24);
+  return tie_t;
+}
+
+static void
+Field_fld_clr_bit_gpio_out_mask_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 24) >> 24;
+  insn[0] = (insn[0] & ~0xff0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_get_gpio_in_i_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_get_gpio_in_i_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static void
+Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
+		    uint32 val ATTRIBUTE_UNUSED)
+{
+  /* Do nothing.  */
+}
+
+static unsigned
+Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static unsigned
+Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 4;
+}
+
+static unsigned
+Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 8;
+}
+
+static unsigned
+Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 12;
+}
+
+enum xtensa_field_id {
+  FIELD_t,
+  FIELD_bbi4,
+  FIELD_bbi,
+  FIELD_imm12,
+  FIELD_imm8,
+  FIELD_s,
+  FIELD_imm12b,
+  FIELD_imm16,
+  FIELD_m,
+  FIELD_n,
+  FIELD_offset,
+  FIELD_op0,
+  FIELD_op1,
+  FIELD_op2,
+  FIELD_r,
+  FIELD_sa4,
+  FIELD_sae4,
+  FIELD_sae,
+  FIELD_sal,
+  FIELD_sargt,
+  FIELD_sas4,
+  FIELD_sas,
+  FIELD_sr,
+  FIELD_st,
+  FIELD_thi3,
+  FIELD_imm4,
+  FIELD_mn,
+  FIELD_i,
+  FIELD_imm6lo,
+  FIELD_imm6hi,
+  FIELD_imm7lo,
+  FIELD_imm7hi,
+  FIELD_z,
+  FIELD_imm6,
+  FIELD_imm7,
+  FIELD_xt_wbr15_imm,
+  FIELD_xt_wbr18_imm,
+  FIELD_fld_WR_MASK_GPIO_OUT_mask,
+  FIELD_fld_WR_MASK_GPIO_OUT_value,
+  FIELD_fld_SET_BIT_GPIO_OUT_mask,
+  FIELD_fld_Inst_3_0,
+  FIELD_fld_Inst_23_12,
+  FIELD_fld_CLR_BIT_GPIO_OUT_mask,
+  FIELD_fld_Inst_23_8,
+  FIELD_fld_GET_GPIO_IN_I,
+  FIELD__ar0,
+  FIELD__ar4,
+  FIELD__ar8,
+  FIELD__ar12
+};
+
+\f
+/* Functional units.  */
+
+#define funcUnits 0
+
+\f
+/* Register files.  */
+
+enum xtensa_regfile_id {
+  REGFILE_AR
+};
+
+static xtensa_regfile_internal regfiles[] = {
+  { "AR", "a", REGFILE_AR, 32, 64 }
+};
+
+\f
+/* Interfaces.  */
+
+static xtensa_interface_internal interfaces[] = {
+  { "ERI_RD_Out", 14, 0, 0, 'o' },
+  { "ERI_RD_In", 32, 0, 1, 'i' },
+  { "ERI_RD_Rdy", 1, 0, 0, 'i' },
+  { "ERI_WR_Out", 46, 0, 2, 'o' },
+  { "ERI_WR_In", 1, 0, 3, 'i' },
+  { "GPIO_IN", 8, 0, 4, 'i' }
+};
+
+enum xtensa_interface_id {
+  INTERFACE_ERI_RD_Out,
+  INTERFACE_ERI_RD_In,
+  INTERFACE_ERI_RD_Rdy,
+  INTERFACE_ERI_WR_Out,
+  INTERFACE_ERI_WR_In,
+  INTERFACE_GPIO_IN
+};
+
+
+/* Constant tables.  */
+
+/* constant table ai4c */
+static const unsigned CONST_TBL_ai4c_0[] = {
+  0xffffffff,
+  0x1,
+  0x2,
+  0x3,
+  0x4,
+  0x5,
+  0x6,
+  0x7,
+  0x8,
+  0x9,
+  0xa,
+  0xb,
+  0xc,
+  0xd,
+  0xe,
+  0xf,
+  0
+};
+
+/* constant table b4c */
+static const unsigned CONST_TBL_b4c_0[] = {
+  0xffffffff,
+  0x1,
+  0x2,
+  0x3,
+  0x4,
+  0x5,
+  0x6,
+  0x7,
+  0x8,
+  0xa,
+  0xc,
+  0x10,
+  0x20,
+  0x40,
+  0x80,
+  0x100,
+  0
+};
+
+/* constant table b4cu */
+static const unsigned CONST_TBL_b4cu_0[] = {
+  0x8000,
+  0x10000,
+  0x2,
+  0x3,
+  0x4,
+  0x5,
+  0x6,
+  0x7,
+  0x8,
+  0xa,
+  0xc,
+  0x10,
+  0x20,
+  0x40,
+  0x80,
+  0x100,
+  0
+};
+
+\f
+/* Instruction operands.  */
+
+static int
+OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp)
+{
+  unsigned soffsetx4_out_0;
+  unsigned soffsetx4_in_0;
+  soffsetx4_in_0 = *valp & 0x3ffff;
+  soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
+  *valp = soffsetx4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp)
+{
+  unsigned soffsetx4_in_0;
+  unsigned soffsetx4_out_0;
+  soffsetx4_out_0 = *valp;
+  soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
+  *valp = soffsetx4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp)
+{
+  unsigned uimm12x8_out_0;
+  unsigned uimm12x8_in_0;
+  uimm12x8_in_0 = *valp & 0xfff;
+  uimm12x8_out_0 = uimm12x8_in_0 << 3;
+  *valp = uimm12x8_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp)
+{
+  unsigned uimm12x8_in_0;
+  unsigned uimm12x8_out_0;
+  uimm12x8_out_0 = *valp;
+  uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
+  *valp = uimm12x8_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm4_decode (uint32 *valp)
+{
+  unsigned simm4_out_0;
+  unsigned simm4_in_0;
+  simm4_in_0 = *valp & 0xf;
+  simm4_out_0 = ((int) simm4_in_0 << 28) >> 28;
+  *valp = simm4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm4_encode (uint32 *valp)
+{
+  unsigned simm4_in_0;
+  unsigned simm4_out_0;
+  simm4_out_0 = *valp;
+  simm4_in_0 = (simm4_out_0 & 0xf);
+  *valp = simm4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 64);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_0_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 64);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_1_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 64);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_2_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 64);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_3_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 64);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_4_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 64);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_immrx4_decode (uint32 *valp)
+{
+  unsigned immrx4_out_0;
+  unsigned immrx4_in_0;
+  immrx4_in_0 = *valp & 0xf;
+  immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
+  *valp = immrx4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_immrx4_encode (uint32 *valp)
+{
+  unsigned immrx4_in_0;
+  unsigned immrx4_out_0;
+  immrx4_out_0 = *valp;
+  immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
+  *valp = immrx4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp)
+{
+  unsigned lsi4x4_out_0;
+  unsigned lsi4x4_in_0;
+  lsi4x4_in_0 = *valp & 0xf;
+  lsi4x4_out_0 = lsi4x4_in_0 << 2;
+  *valp = lsi4x4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp)
+{
+  unsigned lsi4x4_in_0;
+  unsigned lsi4x4_out_0;
+  lsi4x4_out_0 = *valp;
+  lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
+  *valp = lsi4x4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm7_decode (uint32 *valp)
+{
+  unsigned simm7_out_0;
+  unsigned simm7_in_0;
+  simm7_in_0 = *valp & 0x7f;
+  simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0;
+  *valp = simm7_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm7_encode (uint32 *valp)
+{
+  unsigned simm7_in_0;
+  unsigned simm7_out_0;
+  simm7_out_0 = *valp;
+  simm7_in_0 = (simm7_out_0 & 0x7f);
+  *valp = simm7_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm6_decode (uint32 *valp)
+{
+  unsigned uimm6_out_0;
+  unsigned uimm6_in_0;
+  uimm6_in_0 = *valp & 0x3f;
+  uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
+  *valp = uimm6_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm6_encode (uint32 *valp)
+{
+  unsigned uimm6_in_0;
+  unsigned uimm6_out_0;
+  uimm6_out_0 = *valp;
+  uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
+  *valp = uimm6_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_ai4const_decode (uint32 *valp)
+{
+  unsigned ai4const_out_0;
+  unsigned ai4const_in_0;
+  ai4const_in_0 = *valp & 0xf;
+  ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
+  *valp = ai4const_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_ai4const_encode (uint32 *valp)
+{
+  unsigned ai4const_in_0;
+  unsigned ai4const_out_0;
+  ai4const_out_0 = *valp;
+  switch (ai4const_out_0)
+    {
+    case 0xffffffff: ai4const_in_0 = 0; break;
+    case 0x1: ai4const_in_0 = 0x1; break;
+    case 0x2: ai4const_in_0 = 0x2; break;
+    case 0x3: ai4const_in_0 = 0x3; break;
+    case 0x4: ai4const_in_0 = 0x4; break;
+    case 0x5: ai4const_in_0 = 0x5; break;
+    case 0x6: ai4const_in_0 = 0x6; break;
+    case 0x7: ai4const_in_0 = 0x7; break;
+    case 0x8: ai4const_in_0 = 0x8; break;
+    case 0x9: ai4const_in_0 = 0x9; break;
+    case 0xa: ai4const_in_0 = 0xa; break;
+    case 0xb: ai4const_in_0 = 0xb; break;
+    case 0xc: ai4const_in_0 = 0xc; break;
+    case 0xd: ai4const_in_0 = 0xd; break;
+    case 0xe: ai4const_in_0 = 0xe; break;
+    default: ai4const_in_0 = 0xf; break;
+    }
+  *valp = ai4const_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4const_decode (uint32 *valp)
+{
+  unsigned b4const_out_0;
+  unsigned b4const_in_0;
+  b4const_in_0 = *valp & 0xf;
+  b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
+  *valp = b4const_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4const_encode (uint32 *valp)
+{
+  unsigned b4const_in_0;
+  unsigned b4const_out_0;
+  b4const_out_0 = *valp;
+  switch (b4const_out_0)
+    {
+    case 0xffffffff: b4const_in_0 = 0; break;
+    case 0x1: b4const_in_0 = 0x1; break;
+    case 0x2: b4const_in_0 = 0x2; break;
+    case 0x3: b4const_in_0 = 0x3; break;
+    case 0x4: b4const_in_0 = 0x4; break;
+    case 0x5: b4const_in_0 = 0x5; break;
+    case 0x6: b4const_in_0 = 0x6; break;
+    case 0x7: b4const_in_0 = 0x7; break;
+    case 0x8: b4const_in_0 = 0x8; break;
+    case 0xa: b4const_in_0 = 0x9; break;
+    case 0xc: b4const_in_0 = 0xa; break;
+    case 0x10: b4const_in_0 = 0xb; break;
+    case 0x20: b4const_in_0 = 0xc; break;
+    case 0x40: b4const_in_0 = 0xd; break;
+    case 0x80: b4const_in_0 = 0xe; break;
+    default: b4const_in_0 = 0xf; break;
+    }
+  *valp = b4const_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4constu_decode (uint32 *valp)
+{
+  unsigned b4constu_out_0;
+  unsigned b4constu_in_0;
+  b4constu_in_0 = *valp & 0xf;
+  b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
+  *valp = b4constu_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4constu_encode (uint32 *valp)
+{
+  unsigned b4constu_in_0;
+  unsigned b4constu_out_0;
+  b4constu_out_0 = *valp;
+  switch (b4constu_out_0)
+    {
+    case 0x8000: b4constu_in_0 = 0; break;
+    case 0x10000: b4constu_in_0 = 0x1; break;
+    case 0x2: b4constu_in_0 = 0x2; break;
+    case 0x3: b4constu_in_0 = 0x3; break;
+    case 0x4: b4constu_in_0 = 0x4; break;
+    case 0x5: b4constu_in_0 = 0x5; break;
+    case 0x6: b4constu_in_0 = 0x6; break;
+    case 0x7: b4constu_in_0 = 0x7; break;
+    case 0x8: b4constu_in_0 = 0x8; break;
+    case 0xa: b4constu_in_0 = 0x9; break;
+    case 0xc: b4constu_in_0 = 0xa; break;
+    case 0x10: b4constu_in_0 = 0xb; break;
+    case 0x20: b4constu_in_0 = 0xc; break;
+    case 0x40: b4constu_in_0 = 0xd; break;
+    case 0x80: b4constu_in_0 = 0xe; break;
+    default: b4constu_in_0 = 0xf; break;
+    }
+  *valp = b4constu_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8_decode (uint32 *valp)
+{
+  unsigned uimm8_out_0;
+  unsigned uimm8_in_0;
+  uimm8_in_0 = *valp & 0xff;
+  uimm8_out_0 = uimm8_in_0;
+  *valp = uimm8_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8_encode (uint32 *valp)
+{
+  unsigned uimm8_in_0;
+  unsigned uimm8_out_0;
+  uimm8_out_0 = *valp;
+  uimm8_in_0 = (uimm8_out_0 & 0xff);
+  *valp = uimm8_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp)
+{
+  unsigned uimm8x2_out_0;
+  unsigned uimm8x2_in_0;
+  uimm8x2_in_0 = *valp & 0xff;
+  uimm8x2_out_0 = uimm8x2_in_0 << 1;
+  *valp = uimm8x2_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp)
+{
+  unsigned uimm8x2_in_0;
+  unsigned uimm8x2_out_0;
+  uimm8x2_out_0 = *valp;
+  uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
+  *valp = uimm8x2_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp)
+{
+  unsigned uimm8x4_out_0;
+  unsigned uimm8x4_in_0;
+  uimm8x4_in_0 = *valp & 0xff;
+  uimm8x4_out_0 = uimm8x4_in_0 << 2;
+  *valp = uimm8x4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp)
+{
+  unsigned uimm8x4_in_0;
+  unsigned uimm8x4_out_0;
+  uimm8x4_out_0 = *valp;
+  uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
+  *valp = uimm8x4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp)
+{
+  unsigned uimm4x16_out_0;
+  unsigned uimm4x16_in_0;
+  uimm4x16_in_0 = *valp & 0xf;
+  uimm4x16_out_0 = uimm4x16_in_0 << 4;
+  *valp = uimm4x16_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp)
+{
+  unsigned uimm4x16_in_0;
+  unsigned uimm4x16_out_0;
+  uimm4x16_out_0 = *valp;
+  uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
+  *valp = uimm4x16_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp)
+{
+  unsigned uimmrx4_out_0;
+  unsigned uimmrx4_in_0;
+  uimmrx4_in_0 = *valp & 0xf;
+  uimmrx4_out_0 = uimmrx4_in_0 << 2;
+  *valp = uimmrx4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp)
+{
+  unsigned uimmrx4_in_0;
+  unsigned uimmrx4_out_0;
+  uimmrx4_out_0 = *valp;
+  uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf);
+  *valp = uimmrx4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8_decode (uint32 *valp)
+{
+  unsigned simm8_out_0;
+  unsigned simm8_in_0;
+  simm8_in_0 = *valp & 0xff;
+  simm8_out_0 = ((int) simm8_in_0 << 24) >> 24;
+  *valp = simm8_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8_encode (uint32 *valp)
+{
+  unsigned simm8_in_0;
+  unsigned simm8_out_0;
+  simm8_out_0 = *valp;
+  simm8_in_0 = (simm8_out_0 & 0xff);
+  *valp = simm8_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8x256_decode (uint32 *valp)
+{
+  unsigned simm8x256_out_0;
+  unsigned simm8x256_in_0;
+  simm8x256_in_0 = *valp & 0xff;
+  simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8;
+  *valp = simm8x256_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8x256_encode (uint32 *valp)
+{
+  unsigned simm8x256_in_0;
+  unsigned simm8x256_out_0;
+  simm8x256_out_0 = *valp;
+  simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
+  *valp = simm8x256_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm12b_decode (uint32 *valp)
+{
+  unsigned simm12b_out_0;
+  unsigned simm12b_in_0;
+  simm12b_in_0 = *valp & 0xfff;
+  simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20;
+  *valp = simm12b_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm12b_encode (uint32 *valp)
+{
+  unsigned simm12b_in_0;
+  unsigned simm12b_out_0;
+  simm12b_out_0 = *valp;
+  simm12b_in_0 = (simm12b_out_0 & 0xfff);
+  *valp = simm12b_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_msalp32_decode (uint32 *valp)
+{
+  unsigned msalp32_out_0;
+  unsigned msalp32_in_0;
+  msalp32_in_0 = *valp & 0x1f;
+  msalp32_out_0 = 0x20 - msalp32_in_0;
+  *valp = msalp32_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_msalp32_encode (uint32 *valp)
+{
+  unsigned msalp32_in_0;
+  unsigned msalp32_out_0;
+  msalp32_out_0 = *valp;
+  msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
+  *valp = msalp32_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_op2p1_decode (uint32 *valp)
+{
+  unsigned op2p1_out_0;
+  unsigned op2p1_in_0;
+  op2p1_in_0 = *valp & 0xf;
+  op2p1_out_0 = op2p1_in_0 + 0x1;
+  *valp = op2p1_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_op2p1_encode (uint32 *valp)
+{
+  unsigned op2p1_in_0;
+  unsigned op2p1_out_0;
+  op2p1_out_0 = *valp;
+  op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
+  *valp = op2p1_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_label8_decode (uint32 *valp)
+{
+  unsigned label8_out_0;
+  unsigned label8_in_0;
+  label8_in_0 = *valp & 0xff;
+  label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
+  *valp = label8_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_label8_encode (uint32 *valp)
+{
+  unsigned label8_in_0;
+  unsigned label8_out_0;
+  label8_out_0 = *valp;
+  label8_in_0 = (label8_out_0 - 0x4) & 0xff;
+  *valp = label8_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_label12_decode (uint32 *valp)
+{
+  unsigned label12_out_0;
+  unsigned label12_in_0;
+  label12_in_0 = *valp & 0xfff;
+  label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
+  *valp = label12_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_label12_encode (uint32 *valp)
+{
+  unsigned label12_in_0;
+  unsigned label12_out_0;
+  label12_out_0 = *valp;
+  label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
+  *valp = label12_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffset_decode (uint32 *valp)
+{
+  unsigned soffset_out_0;
+  unsigned soffset_in_0;
+  soffset_in_0 = *valp & 0x3ffff;
+  soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
+  *valp = soffset_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffset_encode (uint32 *valp)
+{
+  unsigned soffset_in_0;
+  unsigned soffset_out_0;
+  soffset_out_0 = *valp;
+  soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
+  *valp = soffset_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp)
+{
+  unsigned uimm16x4_out_0;
+  unsigned uimm16x4_in_0;
+  uimm16x4_in_0 = *valp & 0xffff;
+  uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
+  *valp = uimm16x4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp)
+{
+  unsigned uimm16x4_in_0;
+  unsigned uimm16x4_out_0;
+  uimm16x4_out_0 = *valp;
+  uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
+  *valp = uimm16x4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_bbi_decode (uint32 *valp)
+{
+  unsigned bbi_out_0;
+  unsigned bbi_in_0;
+  bbi_in_0 = *valp & 0x1f;
+  bbi_out_0 = (0 << 5) | bbi_in_0;
+  *valp = bbi_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_bbi_encode (uint32 *valp)
+{
+  unsigned bbi_in_0;
+  unsigned bbi_out_0;
+  bbi_out_0 = *valp;
+  bbi_in_0 = (bbi_out_0 & 0x1f);
+  *valp = bbi_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_s_decode (uint32 *valp)
+{
+  unsigned s_out_0;
+  unsigned s_in_0;
+  s_in_0 = *valp & 0xf;
+  s_out_0 = (0 << 4) | s_in_0;
+  *valp = s_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_s_encode (uint32 *valp)
+{
+  unsigned s_in_0;
+  unsigned s_out_0;
+  s_out_0 = *valp;
+  s_in_0 = (s_out_0 & 0xf);
+  *valp = s_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_immt_decode (uint32 *valp)
+{
+  unsigned immt_out_0;
+  unsigned immt_in_0;
+  immt_in_0 = *valp & 0xf;
+  immt_out_0 = immt_in_0;
+  *valp = immt_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_immt_encode (uint32 *valp)
+{
+  unsigned immt_in_0;
+  unsigned immt_out_0;
+  immt_out_0 = *valp;
+  immt_in_0 = immt_out_0 & 0xf;
+  *valp = immt_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_tp7_decode (uint32 *valp)
+{
+  unsigned tp7_out_0;
+  unsigned tp7_in_0;
+  tp7_in_0 = *valp & 0xf;
+  tp7_out_0 = tp7_in_0 + 0x7;
+  *valp = tp7_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_tp7_encode (uint32 *valp)
+{
+  unsigned tp7_in_0;
+  unsigned tp7_out_0;
+  tp7_out_0 = *valp;
+  tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
+  *valp = tp7_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp)
+{
+  unsigned xt_wbr15_label_out_0;
+  unsigned xt_wbr15_label_in_0;
+  xt_wbr15_label_in_0 = *valp & 0x7fff;
+  xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
+  *valp = xt_wbr15_label_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp)
+{
+  unsigned xt_wbr15_label_in_0;
+  unsigned xt_wbr15_label_out_0;
+  xt_wbr15_label_out_0 = *valp;
+  xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
+  *valp = xt_wbr15_label_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp)
+{
+  unsigned xt_wbr18_label_out_0;
+  unsigned xt_wbr18_label_in_0;
+  xt_wbr18_label_in_0 = *valp & 0x3ffff;
+  xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14);
+  *valp = xt_wbr18_label_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp)
+{
+  unsigned xt_wbr18_label_in_0;
+  unsigned xt_wbr18_label_out_0;
+  xt_wbr18_label_out_0 = *valp;
+  xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff;
+  *valp = xt_wbr18_label_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_opnd_SET_BIT_GPIO_OUT_mask_decode (uint32 *valp)
+{
+  unsigned opnd_SET_BIT_GPIO_OUT_mask_out_0;
+  unsigned opnd_SET_BIT_GPIO_OUT_mask_in_0;
+  opnd_SET_BIT_GPIO_OUT_mask_in_0 = *valp & 0xff;
+  opnd_SET_BIT_GPIO_OUT_mask_out_0 = (0 << 8) | opnd_SET_BIT_GPIO_OUT_mask_in_0;
+  *valp = opnd_SET_BIT_GPIO_OUT_mask_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_opnd_SET_BIT_GPIO_OUT_mask_encode (uint32 *valp)
+{
+  unsigned opnd_SET_BIT_GPIO_OUT_mask_in_0;
+  unsigned opnd_SET_BIT_GPIO_OUT_mask_out_0;
+  opnd_SET_BIT_GPIO_OUT_mask_out_0 = *valp;
+  opnd_SET_BIT_GPIO_OUT_mask_in_0 = (opnd_SET_BIT_GPIO_OUT_mask_out_0 & 0xff);
+  *valp = opnd_SET_BIT_GPIO_OUT_mask_in_0;
+  return 0;
+}
+
+static int
+Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= (pc & ~0x3);
+  return 0;
+}
+
+static int
+Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += (pc & ~0x3);
+  return 0;
+}
+
+static int
+Operand_uimm6_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= pc;
+  return 0;
+}
+
+static int
+Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += pc;
+  return 0;
+}
+
+static int
+Operand_label8_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= pc;
+  return 0;
+}
+
+static int
+Operand_label8_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += pc;
+  return 0;
+}
+
+static int
+Operand_label12_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= pc;
+  return 0;
+}
+
+static int
+Operand_label12_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += pc;
+  return 0;
+}
+
+static int
+Operand_soffset_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= pc;
+  return 0;
+}
+
+static int
+Operand_soffset_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += pc;
+  return 0;
+}
+
+static int
+Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= ((pc + 3) & ~0x3);
+  return 0;
+}
+
+static int
+Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += ((pc + 3) & ~0x3);
+  return 0;
+}
+
+static int
+Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= pc;
+  return 0;
+}
+
+static int
+Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += pc;
+  return 0;
+}
+
+static int
+Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= pc;
+  return 0;
+}
+
+static int
+Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += pc;
+  return 0;
+}
+
+static xtensa_operand_internal operands[] = {
+  { "soffsetx4", FIELD_offset, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode,
+    Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
+  { "uimm12x8", FIELD_imm12, -1, 0,
+    0,
+    OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode,
+    0, 0 },
+  { "simm4", FIELD_mn, -1, 0,
+    0,
+    OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode,
+    0, 0 },
+  { "arr", FIELD_r, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "ars", FIELD_s, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "art", FIELD_t, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "ar0", FIELD__ar0, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+    OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode,
+    0, 0 },
+  { "ar4", FIELD__ar4, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+    OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode,
+    0, 0 },
+  { "ar8", FIELD__ar8, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+    OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode,
+    0, 0 },
+  { "ar12", FIELD__ar12, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+    OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode,
+    0, 0 },
+  { "ars_entry", FIELD_s, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode,
+    0, 0 },
+  { "immrx4", FIELD_r, -1, 0,
+    0,
+    OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode,
+    0, 0 },
+  { "lsi4x4", FIELD_r, -1, 0,
+    0,
+    OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
+    0, 0 },
+  { "simm7", FIELD_imm7, -1, 0,
+    0,
+    OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode,
+    0, 0 },
+  { "uimm6", FIELD_imm6, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode,
+    Operand_uimm6_ator, Operand_uimm6_rtoa },
+  { "ai4const", FIELD_t, -1, 0,
+    0,
+    OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode,
+    0, 0 },
+  { "b4const", FIELD_r, -1, 0,
+    0,
+    OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode,
+    0, 0 },
+  { "b4constu", FIELD_r, -1, 0,
+    0,
+    OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode,
+    0, 0 },
+  { "uimm8", FIELD_imm8, -1, 0,
+    0,
+    OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode,
+    0, 0 },
+  { "uimm8x2", FIELD_imm8, -1, 0,
+    0,
+    OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode,
+    0, 0 },
+  { "uimm8x4", FIELD_imm8, -1, 0,
+    0,
+    OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode,
+    0, 0 },
+  { "uimm4x16", FIELD_op2, -1, 0,
+    0,
+    OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode,
+    0, 0 },
+  { "uimmrx4", FIELD_r, -1, 0,
+    0,
+    OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode,
+    0, 0 },
+  { "simm8", FIELD_imm8, -1, 0,
+    0,
+    OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode,
+    0, 0 },
+  { "simm8x256", FIELD_imm8, -1, 0,
+    0,
+    OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode,
+    0, 0 },
+  { "simm12b", FIELD_imm12b, -1, 0,
+    0,
+    OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode,
+    0, 0 },
+  { "msalp32", FIELD_sal, -1, 0,
+    0,
+    OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode,
+    0, 0 },
+  { "op2p1", FIELD_op2, -1, 0,
+    0,
+    OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode,
+    0, 0 },
+  { "label8", FIELD_imm8, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode,
+    Operand_label8_ator, Operand_label8_rtoa },
+  { "label12", FIELD_imm12, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode,
+    Operand_label12_ator, Operand_label12_rtoa },
+  { "soffset", FIELD_offset, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
+    Operand_soffset_ator, Operand_soffset_rtoa },
+  { "uimm16x4", FIELD_imm16, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode,
+    Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
+  { "bbi", FIELD_bbi, -1, 0,
+    0,
+    OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+    0, 0 },
+  { "sae", FIELD_sae, -1, 0,
+    0,
+    OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+    0, 0 },
+  { "sas", FIELD_sas, -1, 0,
+    0,
+    OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+    0, 0 },
+  { "sargt", FIELD_sargt, -1, 0,
+    0,
+    OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+    0, 0 },
+  { "s", FIELD_s, -1, 0,
+    0,
+    OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
+    0, 0 },
+  { "immt", FIELD_t, -1, 0,
+    0,
+    OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
+    0, 0 },
+  { "imms", FIELD_s, -1, 0,
+    0,
+    OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
+    0, 0 },
+  { "tp7", FIELD_t, -1, 0,
+    0,
+    OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode,
+    0, 0 },
+  { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode,
+    Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
+  { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode,
+    Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
+  { "opnd_WR_MASK_GPIO_OUT_mask", FIELD_fld_WR_MASK_GPIO_OUT_mask, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_WR_MASK_GPIO_OUT_value", FIELD_fld_WR_MASK_GPIO_OUT_value, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_SET_BIT_GPIO_OUT_mask", FIELD_fld_SET_BIT_GPIO_OUT_mask, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_SET_BIT_GPIO_OUT_mask_encode, OperandSem_opnd_sem_opnd_SET_BIT_GPIO_OUT_mask_decode,
+    0, 0 },
+  { "opnd_CLR_BIT_GPIO_OUT_mask", FIELD_fld_CLR_BIT_GPIO_OUT_mask, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_SET_BIT_GPIO_OUT_mask_encode, OperandSem_opnd_sem_opnd_SET_BIT_GPIO_OUT_mask_decode,
+    0, 0 },
+  { "opnd_GET_GPIO_IN_I", FIELD_fld_GET_GPIO_IN_I, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
+  { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
+  { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
+  { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
+  { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
+  { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
+  { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
+  { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
+  { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
+  { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
+  { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
+  { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
+  { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
+  { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
+  { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
+  { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
+  { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
+  { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
+  { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
+  { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
+  { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_WR_MASK_GPIO_OUT_mask", FIELD_fld_WR_MASK_GPIO_OUT_mask, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_WR_MASK_GPIO_OUT_value", FIELD_fld_WR_MASK_GPIO_OUT_value, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_SET_BIT_GPIO_OUT_mask", FIELD_fld_SET_BIT_GPIO_OUT_mask, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_3_0", FIELD_fld_Inst_3_0, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_23_12", FIELD_fld_Inst_23_12, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_CLR_BIT_GPIO_OUT_mask", FIELD_fld_CLR_BIT_GPIO_OUT_mask, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_23_8", FIELD_fld_Inst_23_8, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_GET_GPIO_IN_I", FIELD_fld_GET_GPIO_IN_I, -1, 0, 0, 0, 0, 0, 0 }
+};
+
+enum xtensa_operand_id {
+  OPERAND_soffsetx4,
+  OPERAND_uimm12x8,
+  OPERAND_simm4,
+  OPERAND_arr,
+  OPERAND_ars,
+  OPERAND__ars_invisible,
+  OPERAND_art,
+  OPERAND_ar0,
+  OPERAND_ar4,
+  OPERAND_ar8,
+  OPERAND_ar12,
+  OPERAND_ars_entry,
+  OPERAND_immrx4,
+  OPERAND_lsi4x4,
+  OPERAND_simm7,
+  OPERAND_uimm6,
+  OPERAND_ai4const,
+  OPERAND_b4const,
+  OPERAND_b4constu,
+  OPERAND_uimm8,
+  OPERAND_uimm8x2,
+  OPERAND_uimm8x4,
+  OPERAND_uimm4x16,
+  OPERAND_uimmrx4,
+  OPERAND_simm8,
+  OPERAND_simm8x256,
+  OPERAND_simm12b,
+  OPERAND_msalp32,
+  OPERAND_op2p1,
+  OPERAND_label8,
+  OPERAND_label12,
+  OPERAND_soffset,
+  OPERAND_uimm16x4,
+  OPERAND_bbi,
+  OPERAND_sae,
+  OPERAND_sas,
+  OPERAND_sargt,
+  OPERAND_s,
+  OPERAND_immt,
+  OPERAND_imms,
+  OPERAND_tp7,
+  OPERAND_xt_wbr15_label,
+  OPERAND_xt_wbr18_label,
+  OPERAND_opnd_WR_MASK_GPIO_OUT_mask,
+  OPERAND_opnd_WR_MASK_GPIO_OUT_value,
+  OPERAND_opnd_SET_BIT_GPIO_OUT_mask,
+  OPERAND_opnd_CLR_BIT_GPIO_OUT_mask,
+  OPERAND_opnd_GET_GPIO_IN_I,
+  OPERAND_t,
+  OPERAND_bbi4,
+  OPERAND_imm12,
+  OPERAND_imm8,
+  OPERAND_imm12b,
+  OPERAND_imm16,
+  OPERAND_m,
+  OPERAND_n,
+  OPERAND_offset,
+  OPERAND_op0,
+  OPERAND_op1,
+  OPERAND_op2,
+  OPERAND_r,
+  OPERAND_sa4,
+  OPERAND_sae4,
+  OPERAND_sal,
+  OPERAND_sas4,
+  OPERAND_sr,
+  OPERAND_st,
+  OPERAND_thi3,
+  OPERAND_imm4,
+  OPERAND_mn,
+  OPERAND_i,
+  OPERAND_imm6lo,
+  OPERAND_imm6hi,
+  OPERAND_imm7lo,
+  OPERAND_imm7hi,
+  OPERAND_z,
+  OPERAND_imm6,
+  OPERAND_imm7,
+  OPERAND_xt_wbr15_imm,
+  OPERAND_xt_wbr18_imm,
+  OPERAND_fld_WR_MASK_GPIO_OUT_mask,
+  OPERAND_fld_WR_MASK_GPIO_OUT_value,
+  OPERAND_fld_SET_BIT_GPIO_OUT_mask,
+  OPERAND_fld_Inst_3_0,
+  OPERAND_fld_Inst_23_12,
+  OPERAND_fld_CLR_BIT_GPIO_OUT_mask,
+  OPERAND_fld_Inst_23_8,
+  OPERAND_fld_GET_GPIO_IN_I
+};
+
+\f
+/* Iclass table.  */
+
+static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
+  { { STATE_PSEXCM }, 'o' },
+  { { STATE_EPC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
+  { { STATE_DEPC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
+  { { OPERAND_soffsetx4 }, 'i' },
+  { { OPERAND_ar12 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
+  { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
+  { { OPERAND_soffsetx4 }, 'i' },
+  { { OPERAND_ar8 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
+  { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
+  { { OPERAND_soffsetx4 }, 'i' },
+  { { OPERAND_ar4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
+  { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_ar12 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
+  { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_ar8 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
+  { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_ar4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
+  { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
+  { { OPERAND_ars_entry }, 's' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm12x8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
+  { { STATE_PSCALLINC }, 'i' },
+  { { STATE_PSEXCM }, 'i' },
+  { { STATE_PSWOE }, 'i' },
+  { { STATE_WindowBase }, 'm' },
+  { { STATE_WindowStart }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
+  { { STATE_WindowBase }, 'i' },
+  { { STATE_WindowStart }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
+  { { OPERAND_simm4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
+  { { STATE_WindowBase }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
+  { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
+  { { STATE_WindowBase }, 'm' },
+  { { STATE_WindowStart }, 'm' },
+  { { STATE_PSCALLINC }, 'o' },
+  { { STATE_PSEXCM }, 'i' },
+  { { STATE_PSWOE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
+  { { STATE_EPC1 }, 'i' },
+  { { STATE_PSEXCM }, 'o' },
+  { { STATE_WindowBase }, 'm' },
+  { { STATE_WindowStart }, 'm' },
+  { { STATE_PSOWB }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_immrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_immrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
+  { { STATE_WindowBase }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
+  { { STATE_WindowBase }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
+  { { STATE_WindowBase }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
+  { { STATE_WindowStart }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
+  { { STATE_WindowStart }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
+  { { STATE_WindowStart }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_ai4const }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_lsi4x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
+  { { OPERAND_ars }, 'o' },
+  { { OPERAND_simm7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
+  { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_lsi4x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
+  { { STATE_THREADPTR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
+  { { STATE_THREADPTR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_simm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_simm8x256 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_b4const }, 'i' },
+  { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_bbi }, 'i' },
+  { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_b4constu }, 'i' },
+  { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_label12 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
+  { { OPERAND_soffsetx4 }, 'i' },
+  { { OPERAND_ar0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_ar0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_sae }, 'i' },
+  { { OPERAND_op2p1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
+  { { OPERAND_soffset }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_uimm16x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_simm12b }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
+  { { OPERAND_arr }, 'm' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
+  { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimmrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
+  { { STATE_SAR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
+  { { OPERAND_sas }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
+  { { STATE_SAR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
+  { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
+  { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
+  { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_msalp32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_sargt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
+  { { STATE_XTSYNC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
+  { { STATE_PSWOE }, 'i' },
+  { { STATE_PSCALLINC }, 'i' },
+  { { STATE_PSOWB }, 'i' },
+  { { STATE_PSUM }, 'i' },
+  { { STATE_PSEXCM }, 'i' },
+  { { STATE_PSINTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
+  { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
+  { { STATE_SAR }, 'o' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
+  { { STATE_SAR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
+  { { STATE_PSWOE }, 'i' },
+  { { STATE_PSCALLINC }, 'i' },
+  { { STATE_PSOWB }, 'i' },
+  { { STATE_PSUM }, 'i' },
+  { { STATE_PSEXCM }, 'i' },
+  { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
+  { { STATE_PSWOE }, 'o' },
+  { { STATE_PSCALLINC }, 'o' },
+  { { STATE_PSOWB }, 'o' },
+  { { STATE_PSUM }, 'o' },
+  { { STATE_PSEXCM }, 'o' },
+  { { STATE_PSINTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
+  { { STATE_PSWOE }, 'm' },
+  { { STATE_PSCALLINC }, 'm' },
+  { { STATE_PSOWB }, 'm' },
+  { { STATE_PSUM }, 'm' },
+  { { STATE_PSEXCM }, 'm' },
+  { { STATE_PSINTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
+  { { STATE_EPC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
+  { { STATE_EPC1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
+  { { STATE_EPC1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
+  { { STATE_EXCSAVE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
+  { { STATE_EXCSAVE1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
+  { { STATE_EXCSAVE1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
+  { { STATE_EPC2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
+  { { STATE_EPC2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
+  { { STATE_EPC2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
+  { { STATE_EXCSAVE2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
+  { { STATE_EXCSAVE2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
+  { { STATE_EXCSAVE2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
+  { { STATE_EPC3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
+  { { STATE_EPC3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
+  { { STATE_EPC3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
+  { { STATE_EXCSAVE3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
+  { { STATE_EXCSAVE3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
+  { { STATE_EXCSAVE3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
+  { { STATE_EPC4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
+  { { STATE_EPC4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
+  { { STATE_EPC4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
+  { { STATE_EXCSAVE4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
+  { { STATE_EXCSAVE4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
+  { { STATE_EXCSAVE4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
+  { { STATE_EPC5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
+  { { STATE_EPC5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
+  { { STATE_EPC5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
+  { { STATE_EXCSAVE5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
+  { { STATE_EXCSAVE5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
+  { { STATE_EXCSAVE5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
+  { { STATE_EPC6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
+  { { STATE_EPC6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
+  { { STATE_EPC6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
+  { { STATE_EXCSAVE6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
+  { { STATE_EXCSAVE6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
+  { { STATE_EXCSAVE6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
+  { { STATE_EPC7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
+  { { STATE_EPC7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
+  { { STATE_EPC7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
+  { { STATE_EXCSAVE7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
+  { { STATE_EXCSAVE7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
+  { { STATE_EXCSAVE7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
+  { { STATE_EPS2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
+  { { STATE_EPS2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
+  { { STATE_EPS2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
+  { { STATE_EPS3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
+  { { STATE_EPS3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
+  { { STATE_EPS3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
+  { { STATE_EPS4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
+  { { STATE_EPS4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
+  { { STATE_EPS4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
+  { { STATE_EPS5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
+  { { STATE_EPS5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
+  { { STATE_EPS5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
+  { { STATE_EPS6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
+  { { STATE_EPS6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
+  { { STATE_EPS6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
+  { { STATE_EPS7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
+  { { STATE_EPS7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
+  { { STATE_EPS7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
+  { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
+  { { STATE_EXCVADDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
+  { { STATE_EXCVADDR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
+  { { STATE_DEPC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
+  { { STATE_DEPC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
+  { { STATE_DEPC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
+  { { STATE_EXCCAUSE }, 'i' },
+  { { STATE_XTSYNC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
+  { { STATE_EXCCAUSE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
+  { { STATE_EXCCAUSE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
+  { { STATE_MISC0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
+  { { STATE_MISC0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
+  { { STATE_MISC0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
+  { { STATE_MISC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
+  { { STATE_MISC1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
+  { { STATE_MISC1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_stateArgs[] = {
+  { { STATE_MISC2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_stateArgs[] = {
+  { { STATE_MISC2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_stateArgs[] = {
+  { { STATE_MISC2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_stateArgs[] = {
+  { { STATE_MISC3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_stateArgs[] = {
+  { { STATE_MISC3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_stateArgs[] = {
+  { { STATE_MISC3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
+  { { STATE_VECBASE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
+  { { STATE_VECBASE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
+  { { STATE_VECBASE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_salt_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul16_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul32_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul32h_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
+  { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
+  { { STATE_PSWOE }, 'o' },
+  { { STATE_PSCALLINC }, 'o' },
+  { { STATE_PSOWB }, 'o' },
+  { { STATE_PSUM }, 'o' },
+  { { STATE_PSEXCM }, 'o' },
+  { { STATE_PSINTLEVEL }, 'o' },
+  { { STATE_EPC1 }, 'i' },
+  { { STATE_EPC2 }, 'i' },
+  { { STATE_EPC3 }, 'i' },
+  { { STATE_EPC4 }, 'i' },
+  { { STATE_EPC5 }, 'i' },
+  { { STATE_EPC6 }, 'i' },
+  { { STATE_EPC7 }, 'i' },
+  { { STATE_EPS2 }, 'i' },
+  { { STATE_EPS3 }, 'i' },
+  { { STATE_EPS4 }, 'i' },
+  { { STATE_EPS5 }, 'i' },
+  { { STATE_EPS6 }, 'i' },
+  { { STATE_EPS7 }, 'i' },
+  { { STATE_InOCDMode }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
+  { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
+  { { STATE_PSINTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
+  { { STATE_INTERRUPT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
+  { { STATE_INTENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
+  { { STATE_INTENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
+  { { STATE_INTENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
+  { { OPERAND_imms }, 'i' },
+  { { OPERAND_immt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
+  { { STATE_PSEXCM }, 'i' },
+  { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
+  { { OPERAND_imms }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
+  { { STATE_PSEXCM }, 'i' },
+  { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
+  { { STATE_DBREAKA0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
+  { { STATE_DBREAKA0 }, 'o' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
+  { { STATE_DBREAKA0 }, 'm' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
+  { { STATE_DBREAKC0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
+  { { STATE_DBREAKC0 }, 'o' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
+  { { STATE_DBREAKC0 }, 'm' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
+  { { STATE_DBREAKA1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
+  { { STATE_DBREAKA1 }, 'o' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
+  { { STATE_DBREAKA1 }, 'm' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
+  { { STATE_DBREAKC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
+  { { STATE_DBREAKC1 }, 'o' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
+  { { STATE_DBREAKC1 }, 'm' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
+  { { STATE_IBREAKA0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
+  { { STATE_IBREAKA0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
+  { { STATE_IBREAKA0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
+  { { STATE_IBREAKA1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
+  { { STATE_IBREAKA1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
+  { { STATE_IBREAKA1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
+  { { STATE_IBREAKENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
+  { { STATE_IBREAKENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
+  { { STATE_IBREAKENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
+  { { STATE_DEBUGCAUSE }, 'i' },
+  { { STATE_DBNUM }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
+  { { STATE_DEBUGCAUSE }, 'o' },
+  { { STATE_DBNUM }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
+  { { STATE_DEBUGCAUSE }, 'm' },
+  { { STATE_DBNUM }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
+  { { STATE_ICOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_ICOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_ICOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
+  { { STATE_ICOUNTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
+  { { STATE_ICOUNTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
+  { { STATE_ICOUNTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
+  { { STATE_DDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_DDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_DDR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = {
+  { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_InOCDMode }, 'i' },
+  { { STATE_DDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = {
+  { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = {
+  { { STATE_InOCDMode }, 'i' },
+  { { STATE_DDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
+  { { OPERAND_imms }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
+  { { STATE_InOCDMode }, 'm' },
+  { { STATE_EPC6 }, 'i' },
+  { { STATE_PSWOE }, 'o' },
+  { { STATE_PSCALLINC }, 'o' },
+  { { STATE_PSOWB }, 'o' },
+  { { STATE_PSUM }, 'o' },
+  { { STATE_PSEXCM }, 'o' },
+  { { STATE_PSINTLEVEL }, 'o' },
+  { { STATE_EPS6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
+  { { STATE_InOCDMode }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
+  { { STATE_CCOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_CCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_CCOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
+  { { STATE_CCOMPARE0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
+  { { STATE_CCOMPARE0 }, 'o' },
+  { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
+  { { STATE_CCOMPARE0 }, 'm' },
+  { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
+  { { STATE_CCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
+  { { STATE_CCOMPARE1 }, 'o' },
+  { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
+  { { STATE_CCOMPARE1 }, 'm' },
+  { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
+  { { STATE_CCOMPARE2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
+  { { STATE_CCOMPARE2 }, 'o' },
+  { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
+  { { STATE_CCOMPARE2 }, 'm' },
+  { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
+  { { STATE_CPENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
+  { { STATE_CPENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_tp7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_tp7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = {
+  { { STATE_ERI_RAW_INTERLOCK }, 'i' }
+};
+
+static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = {
+  INTERFACE_ERI_RD_In,
+  INTERFACE_ERI_RD_Out
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = {
+  { { STATE_ERI_RAW_INTERLOCK }, 'o' }
+};
+
+static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = {
+  INTERFACE_ERI_WR_In,
+  INTERFACE_ERI_WR_Out
+};
+
+static xtensa_arg_internal Iclass_WR_MASK_GPIO_OUT_args[] = {
+  { { OPERAND_opnd_WR_MASK_GPIO_OUT_value }, 'i' },
+  { { OPERAND_opnd_WR_MASK_GPIO_OUT_mask }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_WR_MASK_GPIO_OUT_stateArgs[] = {
+  { { STATE_GPIO_OUT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_SET_BIT_GPIO_OUT_args[] = {
+  { { OPERAND_opnd_SET_BIT_GPIO_OUT_mask }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_SET_BIT_GPIO_OUT_stateArgs[] = {
+  { { STATE_GPIO_OUT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_CLR_BIT_GPIO_OUT_args[] = {
+  { { OPERAND_opnd_CLR_BIT_GPIO_OUT_mask }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_CLR_BIT_GPIO_OUT_stateArgs[] = {
+  { { STATE_GPIO_OUT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_GET_GPIO_IN_args[] = {
+  { { OPERAND_opnd_GET_GPIO_IN_I }, 'o' }
+};
+
+static xtensa_interface Iclass_GET_GPIO_IN_intfArgs[] = {
+  INTERFACE_GPIO_IN
+};
+
+static xtensa_arg_internal Iclass_rur_gpio_out_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_gpio_out_stateArgs[] = {
+  { { STATE_GPIO_OUT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_gpio_out_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_gpio_out_stateArgs[] = {
+  { { STATE_GPIO_OUT }, 'o' }
+};
+
+static xtensa_iclass_internal iclasses[] = {
+  { 0, 0 /* xt_iclass_excw */,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_rfe */,
+    2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
+  { 0, 0 /* xt_iclass_rfde */,
+    1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
+  { 0, 0 /* xt_iclass_syscall */,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_call12_args,
+    1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_call8_args,
+    1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_call4_args,
+    1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_callx12_args,
+    1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_callx8_args,
+    1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_callx4_args,
+    1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_entry_args,
+    5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_movsp_args,
+    2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rotw_args,
+    1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_retw_args,
+    5, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
+  { 0, 0 /* xt_iclass_rfwou */,
+    5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_l32e_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_s32e_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_windowbase_args,
+    1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_windowbase_args,
+    1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_windowbase_args,
+    1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_windowstart_args,
+    1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_windowstart_args,
+    1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_windowstart_args,
+    1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_add_n_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_addi_n_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_bz6_args,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_ill_n */,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_loadi4_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_mov_n_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_movi_n_args,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_nopn */,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_retn_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_storei4_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_rur_threadptr_args,
+    1, Iclass_rur_threadptr_stateArgs, 0, 0 },
+  { 1, Iclass_wur_threadptr_args,
+    1, Iclass_wur_threadptr_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_addi_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_addmi_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_addsub_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_bit_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_bsi8_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_bsi8b_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_bsi8u_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_bst8_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_bsz12_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_call0_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_callx0_args,
+    0, 0, 0, 0 },
+  { 4, Iclass_xt_iclass_exti_args,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_ill */,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_jump_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_jumpx_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_l16ui_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_l16si_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_l32i_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_l32r_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_l8i_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_movi_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_movz_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_neg_args,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_nop */,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_return_args,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_simcall */,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_s16i_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_s32i_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_s32nb_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_s8i_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_sar_args,
+    1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_sari_args,
+    1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_shifts_args,
+    1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_shiftst_args,
+    1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_shiftt_args,
+    1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_slli_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_srai_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_srli_args,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_memw */,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_extw */,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_isync */,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_sync */,
+    1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_rsil_args,
+    6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_sar_args,
+    1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_sar_args,
+    2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_sar_args,
+    1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_memctl_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_memctl_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_memctl_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_litbase_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_litbase_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_litbase_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_configid0_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_configid0_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_configid1_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ps_args,
+    6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ps_args,
+    6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ps_args,
+    6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_epc1_args,
+    1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_epc1_args,
+    1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_epc1_args,
+    1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_excsave1_args,
+    1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_excsave1_args,
+    1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_excsave1_args,
+    1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_epc2_args,
+    1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_epc2_args,
+    1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_epc2_args,
+    1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_excsave2_args,
+    1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_excsave2_args,
+    1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_excsave2_args,
+    1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_epc3_args,
+    1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_epc3_args,
+    1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_epc3_args,
+    1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_excsave3_args,
+    1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_excsave3_args,
+    1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_excsave3_args,
+    1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_epc4_args,
+    1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_epc4_args,
+    1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_epc4_args,
+    1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_excsave4_args,
+    1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_excsave4_args,
+    1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_excsave4_args,
+    1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_epc5_args,
+    1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_epc5_args,
+    1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_epc5_args,
+    1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_excsave5_args,
+    1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_excsave5_args,
+    1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_excsave5_args,
+    1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_epc6_args,
+    1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_epc6_args,
+    1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_epc6_args,
+    1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_excsave6_args,
+    1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_excsave6_args,
+    1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_excsave6_args,
+    1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_epc7_args,
+    1, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_epc7_args,
+    1, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_epc7_args,
+    1, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_excsave7_args,
+    1, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_excsave7_args,
+    1, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_excsave7_args,
+    1, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_eps2_args,
+    1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_eps2_args,
+    1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_eps2_args,
+    1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_eps3_args,
+    1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_eps3_args,
+    1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_eps3_args,
+    1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_eps4_args,
+    1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_eps4_args,
+    1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_eps4_args,
+    1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_eps5_args,
+    1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_eps5_args,
+    1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_eps5_args,
+    1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_eps6_args,
+    1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_eps6_args,
+    1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_eps6_args,
+    1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_eps7_args,
+    1, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_eps7_args,
+    1, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_eps7_args,
+    1, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_excvaddr_args,
+    1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_excvaddr_args,
+    1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_excvaddr_args,
+    1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_depc_args,
+    1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_depc_args,
+    1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_depc_args,
+    1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_exccause_args,
+    2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_exccause_args,
+    1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_exccause_args,
+    1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_misc0_args,
+    1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_misc0_args,
+    1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_misc0_args,
+    1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_misc1_args,
+    1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_misc1_args,
+    1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_misc1_args,
+    1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_misc2_args,
+    1, Iclass_xt_iclass_rsr_misc2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_misc2_args,
+    1, Iclass_xt_iclass_wsr_misc2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_misc2_args,
+    1, Iclass_xt_iclass_xsr_misc2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_misc3_args,
+    1, Iclass_xt_iclass_rsr_misc3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_misc3_args,
+    1, Iclass_xt_iclass_wsr_misc3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_misc3_args,
+    1, Iclass_xt_iclass_xsr_misc3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_prid_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_vecbase_args,
+    1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_vecbase_args,
+    1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_vecbase_args,
+    1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_salt_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_mul16_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_mul32_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_mul32h_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rfi_args,
+    20, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wait_args,
+    1, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_interrupt_args,
+    1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_intset_args,
+    2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_intclear_args,
+    2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_intenable_args,
+    1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_intenable_args,
+    1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_intenable_args,
+    1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_break_args,
+    2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_break_n_args,
+    2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
+    1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
+    2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
+    2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
+    1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
+    2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
+    2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
+    1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
+    2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
+    2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
+    1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
+    2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
+    2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
+    1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
+    1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
+    1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
+    1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
+    1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
+    1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
+    1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
+    1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
+    1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_debugcause_args,
+    2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_debugcause_args,
+    2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_debugcause_args,
+    2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_icount_args,
+    1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_icount_args,
+    2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_icount_args,
+    2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_icountlevel_args,
+    1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_icountlevel_args,
+    1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_icountlevel_args,
+    1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ddr_args,
+    1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ddr_args,
+    2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ddr_args,
+    2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_lddr32_p_args,
+    3, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_sddr32_p_args,
+    2, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rfdo_args,
+    9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
+  { 0, 0 /* xt_iclass_rfdd */,
+    1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_mmid_args,
+    1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ccount_args,
+    1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ccount_args,
+    2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ccount_args,
+    2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ccompare0_args,
+    1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ccompare0_args,
+    2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ccompare0_args,
+    2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ccompare1_args,
+    1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ccompare1_args,
+    2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ccompare1_args,
+    2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ccompare2_args,
+    1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ccompare2_args,
+    2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ccompare2_args,
+    2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_idtlb_args,
+    1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_rdtlb_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_wdtlb_args,
+    1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_iitlb_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_ritlb_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_witlb_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_cpenable_args,
+    1, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_cpenable_args,
+    1, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_cpenable_args,
+    1, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_clamp_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_minmax_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_nsa_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_sx_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_l32ai_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_s32ri_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_div_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_eraccess_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_eraccess_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_eraccess_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_rer_args,
+    1, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs },
+  { 2, Iclass_xt_iclass_wer_args,
+    1, Iclass_xt_iclass_wer_stateArgs, 2, Iclass_xt_iclass_wer_intfArgs },
+  { 2, Iclass_WR_MASK_GPIO_OUT_args,
+    1, Iclass_WR_MASK_GPIO_OUT_stateArgs, 0, 0 },
+  { 1, Iclass_SET_BIT_GPIO_OUT_args,
+    1, Iclass_SET_BIT_GPIO_OUT_stateArgs, 0, 0 },
+  { 1, Iclass_CLR_BIT_GPIO_OUT_args,
+    1, Iclass_CLR_BIT_GPIO_OUT_stateArgs, 0, 0 },
+  { 1, Iclass_GET_GPIO_IN_args,
+    0, 0, 1, Iclass_GET_GPIO_IN_intfArgs },
+  { 1, Iclass_rur_gpio_out_args,
+    1, Iclass_rur_gpio_out_stateArgs, 0, 0 },
+  { 1, Iclass_wur_gpio_out_args,
+    1, Iclass_wur_gpio_out_stateArgs, 0, 0 }
+};
+
+enum xtensa_iclass_id {
+  ICLASS_xt_iclass_excw,
+  ICLASS_xt_iclass_rfe,
+  ICLASS_xt_iclass_rfde,
+  ICLASS_xt_iclass_syscall,
+  ICLASS_xt_iclass_call12,
+  ICLASS_xt_iclass_call8,
+  ICLASS_xt_iclass_call4,
+  ICLASS_xt_iclass_callx12,
+  ICLASS_xt_iclass_callx8,
+  ICLASS_xt_iclass_callx4,
+  ICLASS_xt_iclass_entry,
+  ICLASS_xt_iclass_movsp,
+  ICLASS_xt_iclass_rotw,
+  ICLASS_xt_iclass_retw,
+  ICLASS_xt_iclass_rfwou,
+  ICLASS_xt_iclass_l32e,
+  ICLASS_xt_iclass_s32e,
+  ICLASS_xt_iclass_rsr_windowbase,
+  ICLASS_xt_iclass_wsr_windowbase,
+  ICLASS_xt_iclass_xsr_windowbase,
+  ICLASS_xt_iclass_rsr_windowstart,
+  ICLASS_xt_iclass_wsr_windowstart,
+  ICLASS_xt_iclass_xsr_windowstart,
+  ICLASS_xt_iclass_add_n,
+  ICLASS_xt_iclass_addi_n,
+  ICLASS_xt_iclass_bz6,
+  ICLASS_xt_iclass_ill_n,
+  ICLASS_xt_iclass_loadi4,
+  ICLASS_xt_iclass_mov_n,
+  ICLASS_xt_iclass_movi_n,
+  ICLASS_xt_iclass_nopn,
+  ICLASS_xt_iclass_retn,
+  ICLASS_xt_iclass_storei4,
+  ICLASS_rur_threadptr,
+  ICLASS_wur_threadptr,
+  ICLASS_xt_iclass_addi,
+  ICLASS_xt_iclass_addmi,
+  ICLASS_xt_iclass_addsub,
+  ICLASS_xt_iclass_bit,
+  ICLASS_xt_iclass_bsi8,
+  ICLASS_xt_iclass_bsi8b,
+  ICLASS_xt_iclass_bsi8u,
+  ICLASS_xt_iclass_bst8,
+  ICLASS_xt_iclass_bsz12,
+  ICLASS_xt_iclass_call0,
+  ICLASS_xt_iclass_callx0,
+  ICLASS_xt_iclass_exti,
+  ICLASS_xt_iclass_ill,
+  ICLASS_xt_iclass_jump,
+  ICLASS_xt_iclass_jumpx,
+  ICLASS_xt_iclass_l16ui,
+  ICLASS_xt_iclass_l16si,
+  ICLASS_xt_iclass_l32i,
+  ICLASS_xt_iclass_l32r,
+  ICLASS_xt_iclass_l8i,
+  ICLASS_xt_iclass_movi,
+  ICLASS_xt_iclass_movz,
+  ICLASS_xt_iclass_neg,
+  ICLASS_xt_iclass_nop,
+  ICLASS_xt_iclass_return,
+  ICLASS_xt_iclass_simcall,
+  ICLASS_xt_iclass_s16i,
+  ICLASS_xt_iclass_s32i,
+  ICLASS_xt_iclass_s32nb,
+  ICLASS_xt_iclass_s8i,
+  ICLASS_xt_iclass_sar,
+  ICLASS_xt_iclass_sari,
+  ICLASS_xt_iclass_shifts,
+  ICLASS_xt_iclass_shiftst,
+  ICLASS_xt_iclass_shiftt,
+  ICLASS_xt_iclass_slli,
+  ICLASS_xt_iclass_srai,
+  ICLASS_xt_iclass_srli,
+  ICLASS_xt_iclass_memw,
+  ICLASS_xt_iclass_extw,
+  ICLASS_xt_iclass_isync,
+  ICLASS_xt_iclass_sync,
+  ICLASS_xt_iclass_rsil,
+  ICLASS_xt_iclass_rsr_sar,
+  ICLASS_xt_iclass_wsr_sar,
+  ICLASS_xt_iclass_xsr_sar,
+  ICLASS_xt_iclass_rsr_memctl,
+  ICLASS_xt_iclass_wsr_memctl,
+  ICLASS_xt_iclass_xsr_memctl,
+  ICLASS_xt_iclass_rsr_litbase,
+  ICLASS_xt_iclass_wsr_litbase,
+  ICLASS_xt_iclass_xsr_litbase,
+  ICLASS_xt_iclass_rsr_configid0,
+  ICLASS_xt_iclass_wsr_configid0,
+  ICLASS_xt_iclass_rsr_configid1,
+  ICLASS_xt_iclass_rsr_ps,
+  ICLASS_xt_iclass_wsr_ps,
+  ICLASS_xt_iclass_xsr_ps,
+  ICLASS_xt_iclass_rsr_epc1,
+  ICLASS_xt_iclass_wsr_epc1,
+  ICLASS_xt_iclass_xsr_epc1,
+  ICLASS_xt_iclass_rsr_excsave1,
+  ICLASS_xt_iclass_wsr_excsave1,
+  ICLASS_xt_iclass_xsr_excsave1,
+  ICLASS_xt_iclass_rsr_epc2,
+  ICLASS_xt_iclass_wsr_epc2,
+  ICLASS_xt_iclass_xsr_epc2,
+  ICLASS_xt_iclass_rsr_excsave2,
+  ICLASS_xt_iclass_wsr_excsave2,
+  ICLASS_xt_iclass_xsr_excsave2,
+  ICLASS_xt_iclass_rsr_epc3,
+  ICLASS_xt_iclass_wsr_epc3,
+  ICLASS_xt_iclass_xsr_epc3,
+  ICLASS_xt_iclass_rsr_excsave3,
+  ICLASS_xt_iclass_wsr_excsave3,
+  ICLASS_xt_iclass_xsr_excsave3,
+  ICLASS_xt_iclass_rsr_epc4,
+  ICLASS_xt_iclass_wsr_epc4,
+  ICLASS_xt_iclass_xsr_epc4,
+  ICLASS_xt_iclass_rsr_excsave4,
+  ICLASS_xt_iclass_wsr_excsave4,
+  ICLASS_xt_iclass_xsr_excsave4,
+  ICLASS_xt_iclass_rsr_epc5,
+  ICLASS_xt_iclass_wsr_epc5,
+  ICLASS_xt_iclass_xsr_epc5,
+  ICLASS_xt_iclass_rsr_excsave5,
+  ICLASS_xt_iclass_wsr_excsave5,
+  ICLASS_xt_iclass_xsr_excsave5,
+  ICLASS_xt_iclass_rsr_epc6,
+  ICLASS_xt_iclass_wsr_epc6,
+  ICLASS_xt_iclass_xsr_epc6,
+  ICLASS_xt_iclass_rsr_excsave6,
+  ICLASS_xt_iclass_wsr_excsave6,
+  ICLASS_xt_iclass_xsr_excsave6,
+  ICLASS_xt_iclass_rsr_epc7,
+  ICLASS_xt_iclass_wsr_epc7,
+  ICLASS_xt_iclass_xsr_epc7,
+  ICLASS_xt_iclass_rsr_excsave7,
+  ICLASS_xt_iclass_wsr_excsave7,
+  ICLASS_xt_iclass_xsr_excsave7,
+  ICLASS_xt_iclass_rsr_eps2,
+  ICLASS_xt_iclass_wsr_eps2,
+  ICLASS_xt_iclass_xsr_eps2,
+  ICLASS_xt_iclass_rsr_eps3,
+  ICLASS_xt_iclass_wsr_eps3,
+  ICLASS_xt_iclass_xsr_eps3,
+  ICLASS_xt_iclass_rsr_eps4,
+  ICLASS_xt_iclass_wsr_eps4,
+  ICLASS_xt_iclass_xsr_eps4,
+  ICLASS_xt_iclass_rsr_eps5,
+  ICLASS_xt_iclass_wsr_eps5,
+  ICLASS_xt_iclass_xsr_eps5,
+  ICLASS_xt_iclass_rsr_eps6,
+  ICLASS_xt_iclass_wsr_eps6,
+  ICLASS_xt_iclass_xsr_eps6,
+  ICLASS_xt_iclass_rsr_eps7,
+  ICLASS_xt_iclass_wsr_eps7,
+  ICLASS_xt_iclass_xsr_eps7,
+  ICLASS_xt_iclass_rsr_excvaddr,
+  ICLASS_xt_iclass_wsr_excvaddr,
+  ICLASS_xt_iclass_xsr_excvaddr,
+  ICLASS_xt_iclass_rsr_depc,
+  ICLASS_xt_iclass_wsr_depc,
+  ICLASS_xt_iclass_xsr_depc,
+  ICLASS_xt_iclass_rsr_exccause,
+  ICLASS_xt_iclass_wsr_exccause,
+  ICLASS_xt_iclass_xsr_exccause,
+  ICLASS_xt_iclass_rsr_misc0,
+  ICLASS_xt_iclass_wsr_misc0,
+  ICLASS_xt_iclass_xsr_misc0,
+  ICLASS_xt_iclass_rsr_misc1,
+  ICLASS_xt_iclass_wsr_misc1,
+  ICLASS_xt_iclass_xsr_misc1,
+  ICLASS_xt_iclass_rsr_misc2,
+  ICLASS_xt_iclass_wsr_misc2,
+  ICLASS_xt_iclass_xsr_misc2,
+  ICLASS_xt_iclass_rsr_misc3,
+  ICLASS_xt_iclass_wsr_misc3,
+  ICLASS_xt_iclass_xsr_misc3,
+  ICLASS_xt_iclass_rsr_prid,
+  ICLASS_xt_iclass_rsr_vecbase,
+  ICLASS_xt_iclass_wsr_vecbase,
+  ICLASS_xt_iclass_xsr_vecbase,
+  ICLASS_xt_iclass_salt,
+  ICLASS_xt_mul16,
+  ICLASS_xt_mul32,
+  ICLASS_xt_mul32h,
+  ICLASS_xt_iclass_rfi,
+  ICLASS_xt_iclass_wait,
+  ICLASS_xt_iclass_rsr_interrupt,
+  ICLASS_xt_iclass_wsr_intset,
+  ICLASS_xt_iclass_wsr_intclear,
+  ICLASS_xt_iclass_rsr_intenable,
+  ICLASS_xt_iclass_wsr_intenable,
+  ICLASS_xt_iclass_xsr_intenable,
+  ICLASS_xt_iclass_break,
+  ICLASS_xt_iclass_break_n,
+  ICLASS_xt_iclass_rsr_dbreaka0,
+  ICLASS_xt_iclass_wsr_dbreaka0,
+  ICLASS_xt_iclass_xsr_dbreaka0,
+  ICLASS_xt_iclass_rsr_dbreakc0,
+  ICLASS_xt_iclass_wsr_dbreakc0,
+  ICLASS_xt_iclass_xsr_dbreakc0,
+  ICLASS_xt_iclass_rsr_dbreaka1,
+  ICLASS_xt_iclass_wsr_dbreaka1,
+  ICLASS_xt_iclass_xsr_dbreaka1,
+  ICLASS_xt_iclass_rsr_dbreakc1,
+  ICLASS_xt_iclass_wsr_dbreakc1,
+  ICLASS_xt_iclass_xsr_dbreakc1,
+  ICLASS_xt_iclass_rsr_ibreaka0,
+  ICLASS_xt_iclass_wsr_ibreaka0,
+  ICLASS_xt_iclass_xsr_ibreaka0,
+  ICLASS_xt_iclass_rsr_ibreaka1,
+  ICLASS_xt_iclass_wsr_ibreaka1,
+  ICLASS_xt_iclass_xsr_ibreaka1,
+  ICLASS_xt_iclass_rsr_ibreakenable,
+  ICLASS_xt_iclass_wsr_ibreakenable,
+  ICLASS_xt_iclass_xsr_ibreakenable,
+  ICLASS_xt_iclass_rsr_debugcause,
+  ICLASS_xt_iclass_wsr_debugcause,
+  ICLASS_xt_iclass_xsr_debugcause,
+  ICLASS_xt_iclass_rsr_icount,
+  ICLASS_xt_iclass_wsr_icount,
+  ICLASS_xt_iclass_xsr_icount,
+  ICLASS_xt_iclass_rsr_icountlevel,
+  ICLASS_xt_iclass_wsr_icountlevel,
+  ICLASS_xt_iclass_xsr_icountlevel,
+  ICLASS_xt_iclass_rsr_ddr,
+  ICLASS_xt_iclass_wsr_ddr,
+  ICLASS_xt_iclass_xsr_ddr,
+  ICLASS_xt_iclass_lddr32_p,
+  ICLASS_xt_iclass_sddr32_p,
+  ICLASS_xt_iclass_rfdo,
+  ICLASS_xt_iclass_rfdd,
+  ICLASS_xt_iclass_wsr_mmid,
+  ICLASS_xt_iclass_rsr_ccount,
+  ICLASS_xt_iclass_wsr_ccount,
+  ICLASS_xt_iclass_xsr_ccount,
+  ICLASS_xt_iclass_rsr_ccompare0,
+  ICLASS_xt_iclass_wsr_ccompare0,
+  ICLASS_xt_iclass_xsr_ccompare0,
+  ICLASS_xt_iclass_rsr_ccompare1,
+  ICLASS_xt_iclass_wsr_ccompare1,
+  ICLASS_xt_iclass_xsr_ccompare1,
+  ICLASS_xt_iclass_rsr_ccompare2,
+  ICLASS_xt_iclass_wsr_ccompare2,
+  ICLASS_xt_iclass_xsr_ccompare2,
+  ICLASS_xt_iclass_idtlb,
+  ICLASS_xt_iclass_rdtlb,
+  ICLASS_xt_iclass_wdtlb,
+  ICLASS_xt_iclass_iitlb,
+  ICLASS_xt_iclass_ritlb,
+  ICLASS_xt_iclass_witlb,
+  ICLASS_xt_iclass_rsr_cpenable,
+  ICLASS_xt_iclass_wsr_cpenable,
+  ICLASS_xt_iclass_xsr_cpenable,
+  ICLASS_xt_iclass_clamp,
+  ICLASS_xt_iclass_minmax,
+  ICLASS_xt_iclass_nsa,
+  ICLASS_xt_iclass_sx,
+  ICLASS_xt_iclass_l32ai,
+  ICLASS_xt_iclass_s32ri,
+  ICLASS_xt_iclass_div,
+  ICLASS_xt_iclass_rsr_eraccess,
+  ICLASS_xt_iclass_wsr_eraccess,
+  ICLASS_xt_iclass_xsr_eraccess,
+  ICLASS_xt_iclass_rer,
+  ICLASS_xt_iclass_wer,
+  ICLASS_WR_MASK_GPIO_OUT,
+  ICLASS_SET_BIT_GPIO_OUT,
+  ICLASS_CLR_BIT_GPIO_OUT,
+  ICLASS_GET_GPIO_IN,
+  ICLASS_rur_gpio_out,
+  ICLASS_wur_gpio_out
+};
+
+\f
+/*  Opcode encodings.  */
+
+static void
+Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2080;
+}
+
+static void
+Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3000;
+}
+
+static void
+Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3200;
+}
+
+static void
+Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x5000;
+}
+
+static void
+Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x35;
+}
+
+static void
+Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x25;
+}
+
+static void
+Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x15;
+}
+
+static void
+Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf0;
+}
+
+static void
+Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe0;
+}
+
+static void
+Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd0;
+}
+
+static void
+Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x36;
+}
+
+static void
+Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1000;
+}
+
+static void
+Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x408000;
+}
+
+static void
+Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x90;
+}
+
+static void
+Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf01d;
+}
+
+static void
+Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3400;
+}
+
+static void
+Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3500;
+}
+
+static void
+Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x90000;
+}
+
+static void
+Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x490000;
+}
+
+static void
+Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x34800;
+}
+
+static void
+Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x134800;
+}
+
+static void
+Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x614800;
+}
+
+static void
+Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x34900;
+}
+
+static void
+Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x134900;
+}
+
+static void
+Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x614900;
+}
+
+static void
+Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa;
+}
+
+static void
+Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb;
+}
+
+static void
+Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8c;
+}
+
+static void
+Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcc;
+}
+
+static void
+Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf06d;
+}
+
+static void
+Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8;
+}
+
+static void
+Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd;
+}
+
+static void
+Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc;
+}
+
+static void
+Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf03d;
+}
+
+static void
+Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf00d;
+}
+
+static void
+Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x9;
+}
+
+static void
+Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe30e70;
+}
+
+static void
+Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf3e700;
+}
+
+static void
+Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc002;
+}
+
+static void
+Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd002;
+}
+
+static void
+Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x800000;
+}
+
+static void
+Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc00000;
+}
+
+static void
+Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x900000;
+}
+
+static void
+Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa00000;
+}
+
+static void
+Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb00000;
+}
+
+static void
+Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd00000;
+}
+
+static void
+Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe00000;
+}
+
+static void
+Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf00000;
+}
+
+static void
+Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x100000;
+}
+
+static void
+Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x200000;
+}
+
+static void
+Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x300000;
+}
+
+static void
+Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x26;
+}
+
+static void
+Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x66;
+}
+
+static void
+Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe6;
+}
+
+static void
+Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa6;
+}
+
+static void
+Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6007;
+}
+
+static void
+Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe007;
+}
+
+static void
+Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf6;
+}
+
+static void
+Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb6;
+}
+
+static void
+Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1007;
+}
+
+static void
+Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x9007;
+}
+
+static void
+Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa007;
+}
+
+static void
+Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2007;
+}
+
+static void
+Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb007;
+}
+
+static void
+Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3007;
+}
+
+static void
+Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8007;
+}
+
+static void
+Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x7;
+}
+
+static void
+Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x4007;
+}
+
+static void
+Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc007;
+}
+
+static void
+Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x5007;
+}
+
+static void
+Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd007;
+}
+
+static void
+Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x16;
+}
+
+static void
+Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x56;
+}
+
+static void
+Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd6;
+}
+
+static void
+Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x96;
+}
+
+static void
+Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x5;
+}
+
+static void
+Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc0;
+}
+
+static void
+Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x40000;
+}
+
+static void
+Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0;
+}
+
+static void
+Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6;
+}
+
+static void
+Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa0;
+}
+
+static void
+Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1002;
+}
+
+static void
+Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x9002;
+}
+
+static void
+Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2002;
+}
+
+static void
+Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1;
+}
+
+static void
+Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2;
+}
+
+static void
+Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa002;
+}
+
+static void
+Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x830000;
+}
+
+static void
+Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x930000;
+}
+
+static void
+Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa30000;
+}
+
+static void
+Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb30000;
+}
+
+static void
+Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x600000;
+}
+
+static void
+Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x600100;
+}
+
+static void
+Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x20f0;
+}
+
+static void
+Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x80;
+}
+
+static void
+Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x5100;
+}
+
+static void
+Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x5002;
+}
+
+static void
+Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6002;
+}
+
+static void
+Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x590000;
+}
+
+static void
+Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x4002;
+}
+
+static void
+Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x400000;
+}
+
+static void
+Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x401000;
+}
+
+static void
+Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x402000;
+}
+
+static void
+Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x403000;
+}
+
+static void
+Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x404000;
+}
+
+static void
+Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa10000;
+}
+
+static void
+Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x810000;
+}
+
+static void
+Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x910000;
+}
+
+static void
+Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb10000;
+}
+
+static void
+Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x10000;
+}
+
+static void
+Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x210000;
+}
+
+static void
+Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x410000;
+}
+
+static void
+Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x20c0;
+}
+
+static void
+Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x20d0;
+}
+
+static void
+Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2000;
+}
+
+static void
+Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2010;
+}
+
+static void
+Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2020;
+}
+
+static void
+Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2030;
+}
+
+static void
+Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6000;
+}
+
+static void
+Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x30300;
+}
+
+static void
+Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x130300;
+}
+
+static void
+Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x610300;
+}
+
+static void
+Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x36100;
+}
+
+static void
+Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x136100;
+}
+
+static void
+Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x616100;
+}
+
+static void
+Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x30500;
+}
+
+static void
+Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x130500;
+}
+
+static void
+Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x610500;
+}
+
+static void
+Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b000;
+}
+
+static void
+Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13b000;
+}
+
+static void
+Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d000;
+}
+
+static void
+Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3e600;
+}
+
+static void
+Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13e600;
+}
+
+static void
+Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61e600;
+}
+
+static void
+Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b100;
+}
+
+static void
+Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13b100;
+}
+
+static void
+Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61b100;
+}
+
+static void
+Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d100;
+}
+
+static void
+Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13d100;
+}
+
+static void
+Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61d100;
+}
+
+static void
+Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b200;
+}
+
+static void
+Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13b200;
+}
+
+static void
+Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61b200;
+}
+
+static void
+Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d200;
+}
+
+static void
+Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13d200;
+}
+
+static void
+Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61d200;
+}
+
+static void
+Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b300;
+}
+
+static void
+Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13b300;
+}
+
+static void
+Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61b300;
+}
+
+static void
+Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d300;
+}
+
+static void
+Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13d300;
+}
+
+static void
+Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61d300;
+}
+
+static void
+Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b400;
+}
+
+static void
+Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13b400;
+}
+
+static void
+Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61b400;
+}
+
+static void
+Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d400;
+}
+
+static void
+Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13d400;
+}
+
+static void
+Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61d400;
+}
+
+static void
+Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b500;
+}
+
+static void
+Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13b500;
+}
+
+static void
+Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61b500;
+}
+
+static void
+Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d500;
+}
+
+static void
+Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13d500;
+}
+
+static void
+Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61d500;
+}
+
+static void
+Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b600;
+}
+
+static void
+Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13b600;
+}
+
+static void
+Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61b600;
+}
+
+static void
+Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d600;
+}
+
+static void
+Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13d600;
+}
+
+static void
+Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61d600;
+}
+
+static void
+Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b700;
+}
+
+static void
+Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13b700;
+}
+
+static void
+Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61b700;
+}
+
+static void
+Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d700;
+}
+
+static void
+Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13d700;
+}
+
+static void
+Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61d700;
+}
+
+static void
+Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3c200;
+}
+
+static void
+Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13c200;
+}
+
+static void
+Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61c200;
+}
+
+static void
+Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3c300;
+}
+
+static void
+Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13c300;
+}
+
+static void
+Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61c300;
+}
+
+static void
+Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3c400;
+}
+
+static void
+Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13c400;
+}
+
+static void
+Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61c400;
+}
+
+static void
+Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3c500;
+}
+
+static void
+Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13c500;
+}
+
+static void
+Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61c500;
+}
+
+static void
+Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3c600;
+}
+
+static void
+Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13c600;
+}
+
+static void
+Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61c600;
+}
+
+static void
+Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3c700;
+}
+
+static void
+Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13c700;
+}
+
+static void
+Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61c700;
+}
+
+static void
+Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3ee00;
+}
+
+static void
+Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13ee00;
+}
+
+static void
+Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61ee00;
+}
+
+static void
+Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3c000;
+}
+
+static void
+Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13c000;
+}
+
+static void
+Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61c000;
+}
+
+static void
+Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3e800;
+}
+
+static void
+Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13e800;
+}
+
+static void
+Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61e800;
+}
+
+static void
+Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3f400;
+}
+
+static void
+Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13f400;
+}
+
+static void
+Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61f400;
+}
+
+static void
+Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3f500;
+}
+
+static void
+Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13f500;
+}
+
+static void
+Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61f500;
+}
+
+static void
+Opcode_rsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3f600;
+}
+
+static void
+Opcode_wsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13f600;
+}
+
+static void
+Opcode_xsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61f600;
+}
+
+static void
+Opcode_rsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3f700;
+}
+
+static void
+Opcode_wsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13f700;
+}
+
+static void
+Opcode_xsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61f700;
+}
+
+static void
+Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3eb00;
+}
+
+static void
+Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3e700;
+}
+
+static void
+Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13e700;
+}
+
+static void
+Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61e700;
+}
+
+static void
+Opcode_salt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x720000;
+}
+
+static void
+Opcode_saltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x620000;
+}
+
+static void
+Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc10000;
+}
+
+static void
+Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd10000;
+}
+
+static void
+Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x820000;
+}
+
+static void
+Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa20000;
+}
+
+static void
+Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb20000;
+}
+
+static void
+Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3010;
+}
+
+static void
+Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x7000;
+}
+
+static void
+Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3e200;
+}
+
+static void
+Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13e200;
+}
+
+static void
+Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13e300;
+}
+
+static void
+Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3e400;
+}
+
+static void
+Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13e400;
+}
+
+static void
+Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61e400;
+}
+
+static void
+Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x4000;
+}
+
+static void
+Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf02d;
+}
+
+static void
+Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x39000;
+}
+
+static void
+Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x139000;
+}
+
+static void
+Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x619000;
+}
+
+static void
+Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3a000;
+}
+
+static void
+Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13a000;
+}
+
+static void
+Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61a000;
+}
+
+static void
+Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x39100;
+}
+
+static void
+Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x139100;
+}
+
+static void
+Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x619100;
+}
+
+static void
+Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3a100;
+}
+
+static void
+Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13a100;
+}
+
+static void
+Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61a100;
+}
+
+static void
+Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x38000;
+}
+
+static void
+Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x138000;
+}
+
+static void
+Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x618000;
+}
+
+static void
+Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x38100;
+}
+
+static void
+Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x138100;
+}
+
+static void
+Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x618100;
+}
+
+static void
+Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x36000;
+}
+
+static void
+Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x136000;
+}
+
+static void
+Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x616000;
+}
+
+static void
+Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3e900;
+}
+
+static void
+Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13e900;
+}
+
+static void
+Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61e900;
+}
+
+static void
+Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3ec00;
+}
+
+static void
+Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13ec00;
+}
+
+static void
+Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61ec00;
+}
+
+static void
+Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3ed00;
+}
+
+static void
+Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13ed00;
+}
+
+static void
+Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61ed00;
+}
+
+static void
+Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x36800;
+}
+
+static void
+Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x136800;
+}
+
+static void
+Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x616800;
+}
+
+static void
+Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x70e0;
+}
+
+static void
+Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x70f0;
+}
+
+static void
+Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf1e000;
+}
+
+static void
+Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf1e010;
+}
+
+static void
+Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x135900;
+}
+
+static void
+Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3ea00;
+}
+
+static void
+Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13ea00;
+}
+
+static void
+Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61ea00;
+}
+
+static void
+Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3f000;
+}
+
+static void
+Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13f000;
+}
+
+static void
+Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61f000;
+}
+
+static void
+Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3f100;
+}
+
+static void
+Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13f100;
+}
+
+static void
+Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61f100;
+}
+
+static void
+Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3f200;
+}
+
+static void
+Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13f200;
+}
+
+static void
+Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61f200;
+}
+
+static void
+Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x50c000;
+}
+
+static void
+Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x50d000;
+}
+
+static void
+Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x50b000;
+}
+
+static void
+Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x50f000;
+}
+
+static void
+Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x50e000;
+}
+
+static void
+Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x504000;
+}
+
+static void
+Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x505000;
+}
+
+static void
+Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x503000;
+}
+
+static void
+Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x507000;
+}
+
+static void
+Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x506000;
+}
+
+static void
+Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3e000;
+}
+
+static void
+Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13e000;
+}
+
+static void
+Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61e000;
+}
+
+static void
+Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x330000;
+}
+
+static void
+Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x430000;
+}
+
+static void
+Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x530000;
+}
+
+static void
+Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x630000;
+}
+
+static void
+Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x730000;
+}
+
+static void
+Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x40e000;
+}
+
+static void
+Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x40f000;
+}
+
+static void
+Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x230000;
+}
+
+static void
+Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb002;
+}
+
+static void
+Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf002;
+}
+
+static void
+Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc20000;
+}
+
+static void
+Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd20000;
+}
+
+static void
+Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe20000;
+}
+
+static void
+Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf20000;
+}
+
+static void
+Opcode_rsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x35f00;
+}
+
+static void
+Opcode_wsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x135f00;
+}
+
+static void
+Opcode_xsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x615f00;
+}
+
+static void
+Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x406000;
+}
+
+static void
+Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x407000;
+}
+
+static void
+Opcode_wr_mask_gpio_out_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x62000;
+}
+
+static void
+Opcode_set_bit_gpio_out_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61000;
+}
+
+static void
+Opcode_clr_bit_gpio_out_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x60000;
+}
+
+static void
+Opcode_get_gpio_in_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x63000;
+}
+
+static void
+Opcode_rur_gpio_out_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe30000;
+}
+
+static void
+Opcode_wur_gpio_out_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf30000;
+}
+
+static const xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
+  Opcode_excw_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
+  Opcode_rfe_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
+  Opcode_rfde_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
+  Opcode_syscall_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
+  Opcode_call12_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
+  Opcode_call8_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
+  Opcode_call4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
+  Opcode_callx12_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
+  Opcode_callx8_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
+  Opcode_callx4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
+  Opcode_entry_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
+  Opcode_movsp_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
+  Opcode_rotw_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
+  Opcode_retw_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
+  0, 0, Opcode_retw_n_Slot_inst16b_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
+  Opcode_rfwo_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
+  Opcode_rfwu_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
+  Opcode_l32e_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
+  Opcode_s32e_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
+  Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
+  Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
+  Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
+  Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
+  Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
+  Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
+  0, Opcode_add_n_Slot_inst16a_encode, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
+  0, Opcode_addi_n_Slot_inst16a_encode, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
+  0, 0, Opcode_beqz_n_Slot_inst16b_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
+  0, 0, Opcode_bnez_n_Slot_inst16b_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
+  0, 0, Opcode_ill_n_Slot_inst16b_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
+  0, Opcode_l32i_n_Slot_inst16a_encode, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
+  0, 0, Opcode_mov_n_Slot_inst16b_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
+  0, 0, Opcode_movi_n_Slot_inst16b_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
+  0, 0, Opcode_nop_n_Slot_inst16b_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
+  0, 0, Opcode_ret_n_Slot_inst16b_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
+  0, Opcode_s32i_n_Slot_inst16a_encode, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
+  Opcode_rur_threadptr_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
+  Opcode_wur_threadptr_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
+  Opcode_addi_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
+  Opcode_addmi_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
+  Opcode_add_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
+  Opcode_sub_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
+  Opcode_addx2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
+  Opcode_addx4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
+  Opcode_addx8_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
+  Opcode_subx2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
+  Opcode_subx4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
+  Opcode_subx8_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
+  Opcode_and_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
+  Opcode_or_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
+  Opcode_xor_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
+  Opcode_beqi_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
+  Opcode_bnei_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
+  Opcode_bgei_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
+  Opcode_blti_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
+  Opcode_bbci_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
+  Opcode_bbsi_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
+  Opcode_bgeui_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
+  Opcode_bltui_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
+  Opcode_beq_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
+  Opcode_bne_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
+  Opcode_bge_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
+  Opcode_blt_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
+  Opcode_bgeu_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
+  Opcode_bltu_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
+  Opcode_bany_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
+  Opcode_bnone_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
+  Opcode_ball_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
+  Opcode_bnall_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
+  Opcode_bbc_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
+  Opcode_bbs_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
+  Opcode_beqz_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
+  Opcode_bnez_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
+  Opcode_bgez_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
+  Opcode_bltz_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
+  Opcode_call0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
+  Opcode_callx0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
+  Opcode_extui_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
+  Opcode_ill_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
+  Opcode_j_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
+  Opcode_jx_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
+  Opcode_l16ui_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
+  Opcode_l16si_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
+  Opcode_l32i_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
+  Opcode_l32r_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
+  Opcode_l8ui_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
+  Opcode_movi_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
+  Opcode_moveqz_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
+  Opcode_movnez_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
+  Opcode_movltz_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
+  Opcode_movgez_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
+  Opcode_neg_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
+  Opcode_abs_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
+  Opcode_nop_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
+  Opcode_ret_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
+  Opcode_simcall_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
+  Opcode_s16i_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
+  Opcode_s32i_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = {
+  Opcode_s32nb_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
+  Opcode_s8i_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
+  Opcode_ssr_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
+  Opcode_ssl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
+  Opcode_ssa8l_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
+  Opcode_ssa8b_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
+  Opcode_ssai_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
+  Opcode_sll_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
+  Opcode_src_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
+  Opcode_srl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
+  Opcode_sra_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
+  Opcode_slli_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
+  Opcode_srai_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
+  Opcode_srli_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
+  Opcode_memw_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
+  Opcode_extw_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
+  Opcode_isync_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
+  Opcode_rsync_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
+  Opcode_esync_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
+  Opcode_dsync_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
+  Opcode_rsil_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
+  Opcode_rsr_sar_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
+  Opcode_wsr_sar_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
+  Opcode_xsr_sar_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = {
+  Opcode_rsr_memctl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = {
+  Opcode_wsr_memctl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = {
+  Opcode_xsr_memctl_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
+  Opcode_rsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
+  Opcode_wsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
+  Opcode_xsr_litbase_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = {
+  Opcode_rsr_configid0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = {
+  Opcode_wsr_configid0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = {
+  Opcode_rsr_configid1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
+  Opcode_rsr_ps_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
+  Opcode_wsr_ps_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
+  Opcode_xsr_ps_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
+  Opcode_rsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
+  Opcode_wsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
+  Opcode_xsr_epc1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
+  Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
+  Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
+  Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
+  Opcode_rsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
+  Opcode_wsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
+  Opcode_xsr_epc2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
+  Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
+  Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
+  Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
+  Opcode_rsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
+  Opcode_wsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
+  Opcode_xsr_epc3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
+  Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
+  Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
+  Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
+  Opcode_rsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
+  Opcode_wsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
+  Opcode_xsr_epc4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
+  Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
+  Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
+  Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
+  Opcode_rsr_epc5_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
+  Opcode_wsr_epc5_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
+  Opcode_xsr_epc5_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
+  Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
+  Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
+  Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
+  Opcode_rsr_epc6_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
+  Opcode_wsr_epc6_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
+  Opcode_xsr_epc6_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
+  Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
+  Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
+  Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
+  Opcode_rsr_epc7_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
+  Opcode_wsr_epc7_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
+  Opcode_xsr_epc7_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
+  Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
+  Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
+  Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
+  Opcode_rsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
+  Opcode_wsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
+  Opcode_xsr_eps2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
+  Opcode_rsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
+  Opcode_wsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
+  Opcode_xsr_eps3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
+  Opcode_rsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
+  Opcode_wsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
+  Opcode_xsr_eps4_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
+  Opcode_rsr_eps5_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
+  Opcode_wsr_eps5_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
+  Opcode_xsr_eps5_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
+  Opcode_rsr_eps6_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
+  Opcode_wsr_eps6_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
+  Opcode_xsr_eps6_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
+  Opcode_rsr_eps7_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
+  Opcode_wsr_eps7_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
+  Opcode_xsr_eps7_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
+  Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
+  Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
+  Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
+  Opcode_rsr_depc_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
+  Opcode_wsr_depc_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
+  Opcode_xsr_depc_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
+  Opcode_rsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
+  Opcode_wsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
+  Opcode_xsr_exccause_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
+  Opcode_rsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
+  Opcode_wsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
+  Opcode_xsr_misc0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
+  Opcode_rsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
+  Opcode_wsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
+  Opcode_xsr_misc1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_misc2_encode_fns[] = {
+  Opcode_rsr_misc2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_misc2_encode_fns[] = {
+  Opcode_wsr_misc2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_misc2_encode_fns[] = {
+  Opcode_xsr_misc2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_misc3_encode_fns[] = {
+  Opcode_rsr_misc3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_misc3_encode_fns[] = {
+  Opcode_wsr_misc3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_misc3_encode_fns[] = {
+  Opcode_xsr_misc3_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
+  Opcode_rsr_prid_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
+  Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
+  Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
+  Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_salt_encode_fns[] = {
+  Opcode_salt_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_saltu_encode_fns[] = {
+  Opcode_saltu_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
+  Opcode_mul16u_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
+  Opcode_mul16s_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
+  Opcode_mull_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = {
+  Opcode_muluh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = {
+  Opcode_mulsh_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
+  Opcode_rfi_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
+  Opcode_waiti_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
+  Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
+  Opcode_wsr_intset_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
+  Opcode_wsr_intclear_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
+  Opcode_rsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
+  Opcode_wsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
+  Opcode_xsr_intenable_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
+  Opcode_break_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
+  0, 0, Opcode_break_n_Slot_inst16b_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
+  Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
+  Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
+  Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
+  Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
+  Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
+  Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
+  Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
+  Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
+  Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
+  Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
+  Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
+  Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
+  Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
+  Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
+  Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
+  Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
+  Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
+  Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
+  Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
+  Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
+  Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
+  Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
+  Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
+  Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
+  Opcode_rsr_icount_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
+  Opcode_wsr_icount_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
+  Opcode_xsr_icount_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
+  Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
+  Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
+  Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
+  Opcode_rsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
+  Opcode_wsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
+  Opcode_xsr_ddr_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = {
+  Opcode_lddr32_p_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = {
+  Opcode_sddr32_p_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
+  Opcode_rfdo_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
+  Opcode_rfdd_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
+  Opcode_wsr_mmid_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
+  Opcode_rsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
+  Opcode_wsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
+  Opcode_xsr_ccount_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
+  Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
+  Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
+  Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
+  Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
+  Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
+  Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
+  Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
+  Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
+  Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
+  Opcode_idtlb_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
+  Opcode_pdtlb_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
+  Opcode_rdtlb0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
+  Opcode_rdtlb1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
+  Opcode_wdtlb_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
+  Opcode_iitlb_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
+  Opcode_pitlb_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
+  Opcode_ritlb0_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
+  Opcode_ritlb1_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
+  Opcode_witlb_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
+  Opcode_rsr_cpenable_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
+  Opcode_wsr_cpenable_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
+  Opcode_xsr_cpenable_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
+  Opcode_clamps_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
+  Opcode_min_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
+  Opcode_max_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
+  Opcode_minu_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
+  Opcode_maxu_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
+  Opcode_nsa_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
+  Opcode_nsau_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
+  Opcode_sext_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
+  Opcode_l32ai_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
+  Opcode_s32ri_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
+  Opcode_quou_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
+  Opcode_quos_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
+  Opcode_remu_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
+  Opcode_rems_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_eraccess_encode_fns[] = {
+  Opcode_rsr_eraccess_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_eraccess_encode_fns[] = {
+  Opcode_wsr_eraccess_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_eraccess_encode_fns[] = {
+  Opcode_xsr_eraccess_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = {
+  Opcode_rer_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = {
+  Opcode_wer_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wr_mask_gpio_out_encode_fns[] = {
+  Opcode_wr_mask_gpio_out_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_set_bit_gpio_out_encode_fns[] = {
+  Opcode_set_bit_gpio_out_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_clr_bit_gpio_out_encode_fns[] = {
+  Opcode_clr_bit_gpio_out_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_get_gpio_in_encode_fns[] = {
+  Opcode_get_gpio_in_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_gpio_out_encode_fns[] = {
+  Opcode_rur_gpio_out_Slot_inst_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_gpio_out_encode_fns[] = {
+  Opcode_wur_gpio_out_Slot_inst_encode, 0, 0
+};
+
+\f
+/* Opcode table.  */
+
+static xtensa_opcode_internal opcodes[] = {
+  { "excw", ICLASS_xt_iclass_excw,
+    0,
+    Opcode_excw_encode_fns, 0, 0 },
+  { "rfe", ICLASS_xt_iclass_rfe,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_rfe_encode_fns, 0, 0 },
+  { "rfde", ICLASS_xt_iclass_rfde,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_rfde_encode_fns, 0, 0 },
+  { "syscall", ICLASS_xt_iclass_syscall,
+    0,
+    Opcode_syscall_encode_fns, 0, 0 },
+  { "call12", ICLASS_xt_iclass_call12,
+    XTENSA_OPCODE_IS_CALL,
+    Opcode_call12_encode_fns, 0, 0 },
+  { "call8", ICLASS_xt_iclass_call8,
+    XTENSA_OPCODE_IS_CALL,
+    Opcode_call8_encode_fns, 0, 0 },
+  { "call4", ICLASS_xt_iclass_call4,
+    XTENSA_OPCODE_IS_CALL,
+    Opcode_call4_encode_fns, 0, 0 },
+  { "callx12", ICLASS_xt_iclass_callx12,
+    XTENSA_OPCODE_IS_CALL,
+    Opcode_callx12_encode_fns, 0, 0 },
+  { "callx8", ICLASS_xt_iclass_callx8,
+    XTENSA_OPCODE_IS_CALL,
+    Opcode_callx8_encode_fns, 0, 0 },
+  { "callx4", ICLASS_xt_iclass_callx4,
+    XTENSA_OPCODE_IS_CALL,
+    Opcode_callx4_encode_fns, 0, 0 },
+  { "entry", ICLASS_xt_iclass_entry,
+    0,
+    Opcode_entry_encode_fns, 0, 0 },
+  { "movsp", ICLASS_xt_iclass_movsp,
+    0,
+    Opcode_movsp_encode_fns, 0, 0 },
+  { "rotw", ICLASS_xt_iclass_rotw,
+    0,
+    Opcode_rotw_encode_fns, 0, 0 },
+  { "retw", ICLASS_xt_iclass_retw,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_retw_encode_fns, 0, 0 },
+  { "retw.n", ICLASS_xt_iclass_retw,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_retw_n_encode_fns, 0, 0 },
+  { "rfwo", ICLASS_xt_iclass_rfwou,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_rfwo_encode_fns, 0, 0 },
+  { "rfwu", ICLASS_xt_iclass_rfwou,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_rfwu_encode_fns, 0, 0 },
+  { "l32e", ICLASS_xt_iclass_l32e,
+    0,
+    Opcode_l32e_encode_fns, 0, 0 },
+  { "s32e", ICLASS_xt_iclass_s32e,
+    0,
+    Opcode_s32e_encode_fns, 0, 0 },
+  { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase,
+    0,
+    Opcode_rsr_windowbase_encode_fns, 0, 0 },
+  { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase,
+    0,
+    Opcode_wsr_windowbase_encode_fns, 0, 0 },
+  { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase,
+    0,
+    Opcode_xsr_windowbase_encode_fns, 0, 0 },
+  { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart,
+    0,
+    Opcode_rsr_windowstart_encode_fns, 0, 0 },
+  { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart,
+    0,
+    Opcode_wsr_windowstart_encode_fns, 0, 0 },
+  { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart,
+    0,
+    Opcode_xsr_windowstart_encode_fns, 0, 0 },
+  { "add.n", ICLASS_xt_iclass_add_n,
+    0,
+    Opcode_add_n_encode_fns, 0, 0 },
+  { "addi.n", ICLASS_xt_iclass_addi_n,
+    0,
+    Opcode_addi_n_encode_fns, 0, 0 },
+  { "beqz.n", ICLASS_xt_iclass_bz6,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_beqz_n_encode_fns, 0, 0 },
+  { "bnez.n", ICLASS_xt_iclass_bz6,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bnez_n_encode_fns, 0, 0 },
+  { "ill.n", ICLASS_xt_iclass_ill_n,
+    0,
+    Opcode_ill_n_encode_fns, 0, 0 },
+  { "l32i.n", ICLASS_xt_iclass_loadi4,
+    0,
+    Opcode_l32i_n_encode_fns, 0, 0 },
+  { "mov.n", ICLASS_xt_iclass_mov_n,
+    0,
+    Opcode_mov_n_encode_fns, 0, 0 },
+  { "movi.n", ICLASS_xt_iclass_movi_n,
+    0,
+    Opcode_movi_n_encode_fns, 0, 0 },
+  { "nop.n", ICLASS_xt_iclass_nopn,
+    0,
+    Opcode_nop_n_encode_fns, 0, 0 },
+  { "ret.n", ICLASS_xt_iclass_retn,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_ret_n_encode_fns, 0, 0 },
+  { "s32i.n", ICLASS_xt_iclass_storei4,
+    0,
+    Opcode_s32i_n_encode_fns, 0, 0 },
+  { "rur.threadptr", ICLASS_rur_threadptr,
+    0,
+    Opcode_rur_threadptr_encode_fns, 0, 0 },
+  { "wur.threadptr", ICLASS_wur_threadptr,
+    0,
+    Opcode_wur_threadptr_encode_fns, 0, 0 },
+  { "addi", ICLASS_xt_iclass_addi,
+    0,
+    Opcode_addi_encode_fns, 0, 0 },
+  { "addmi", ICLASS_xt_iclass_addmi,
+    0,
+    Opcode_addmi_encode_fns, 0, 0 },
+  { "add", ICLASS_xt_iclass_addsub,
+    0,
+    Opcode_add_encode_fns, 0, 0 },
+  { "sub", ICLASS_xt_iclass_addsub,
+    0,
+    Opcode_sub_encode_fns, 0, 0 },
+  { "addx2", ICLASS_xt_iclass_addsub,
+    0,
+    Opcode_addx2_encode_fns, 0, 0 },
+  { "addx4", ICLASS_xt_iclass_addsub,
+    0,
+    Opcode_addx4_encode_fns, 0, 0 },
+  { "addx8", ICLASS_xt_iclass_addsub,
+    0,
+    Opcode_addx8_encode_fns, 0, 0 },
+  { "subx2", ICLASS_xt_iclass_addsub,
+    0,
+    Opcode_subx2_encode_fns, 0, 0 },
+  { "subx4", ICLASS_xt_iclass_addsub,
+    0,
+    Opcode_subx4_encode_fns, 0, 0 },
+  { "subx8", ICLASS_xt_iclass_addsub,
+    0,
+    Opcode_subx8_encode_fns, 0, 0 },
+  { "and", ICLASS_xt_iclass_bit,
+    0,
+    Opcode_and_encode_fns, 0, 0 },
+  { "or", ICLASS_xt_iclass_bit,
+    0,
+    Opcode_or_encode_fns, 0, 0 },
+  { "xor", ICLASS_xt_iclass_bit,
+    0,
+    Opcode_xor_encode_fns, 0, 0 },
+  { "beqi", ICLASS_xt_iclass_bsi8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_beqi_encode_fns, 0, 0 },
+  { "bnei", ICLASS_xt_iclass_bsi8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bnei_encode_fns, 0, 0 },
+  { "bgei", ICLASS_xt_iclass_bsi8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bgei_encode_fns, 0, 0 },
+  { "blti", ICLASS_xt_iclass_bsi8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_blti_encode_fns, 0, 0 },
+  { "bbci", ICLASS_xt_iclass_bsi8b,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bbci_encode_fns, 0, 0 },
+  { "bbsi", ICLASS_xt_iclass_bsi8b,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bbsi_encode_fns, 0, 0 },
+  { "bgeui", ICLASS_xt_iclass_bsi8u,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bgeui_encode_fns, 0, 0 },
+  { "bltui", ICLASS_xt_iclass_bsi8u,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bltui_encode_fns, 0, 0 },
+  { "beq", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_beq_encode_fns, 0, 0 },
+  { "bne", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bne_encode_fns, 0, 0 },
+  { "bge", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bge_encode_fns, 0, 0 },
+  { "blt", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_blt_encode_fns, 0, 0 },
+  { "bgeu", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bgeu_encode_fns, 0, 0 },
+  { "bltu", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bltu_encode_fns, 0, 0 },
+  { "bany", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bany_encode_fns, 0, 0 },
+  { "bnone", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bnone_encode_fns, 0, 0 },
+  { "ball", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_ball_encode_fns, 0, 0 },
+  { "bnall", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bnall_encode_fns, 0, 0 },
+  { "bbc", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bbc_encode_fns, 0, 0 },
+  { "bbs", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bbs_encode_fns, 0, 0 },
+  { "beqz", ICLASS_xt_iclass_bsz12,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_beqz_encode_fns, 0, 0 },
+  { "bnez", ICLASS_xt_iclass_bsz12,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bnez_encode_fns, 0, 0 },
+  { "bgez", ICLASS_xt_iclass_bsz12,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bgez_encode_fns, 0, 0 },
+  { "bltz", ICLASS_xt_iclass_bsz12,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bltz_encode_fns, 0, 0 },
+  { "call0", ICLASS_xt_iclass_call0,
+    XTENSA_OPCODE_IS_CALL,
+    Opcode_call0_encode_fns, 0, 0 },
+  { "callx0", ICLASS_xt_iclass_callx0,
+    XTENSA_OPCODE_IS_CALL,
+    Opcode_callx0_encode_fns, 0, 0 },
+  { "extui", ICLASS_xt_iclass_exti,
+    0,
+    Opcode_extui_encode_fns, 0, 0 },
+  { "ill", ICLASS_xt_iclass_ill,
+    0,
+    Opcode_ill_encode_fns, 0, 0 },
+  { "j", ICLASS_xt_iclass_jump,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_j_encode_fns, 0, 0 },
+  { "jx", ICLASS_xt_iclass_jumpx,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_jx_encode_fns, 0, 0 },
+  { "l16ui", ICLASS_xt_iclass_l16ui,
+    0,
+    Opcode_l16ui_encode_fns, 0, 0 },
+  { "l16si", ICLASS_xt_iclass_l16si,
+    0,
+    Opcode_l16si_encode_fns, 0, 0 },
+  { "l32i", ICLASS_xt_iclass_l32i,
+    0,
+    Opcode_l32i_encode_fns, 0, 0 },
+  { "l32r", ICLASS_xt_iclass_l32r,
+    0,
+    Opcode_l32r_encode_fns, 0, 0 },
+  { "l8ui", ICLASS_xt_iclass_l8i,
+    0,
+    Opcode_l8ui_encode_fns, 0, 0 },
+  { "movi", ICLASS_xt_iclass_movi,
+    0,
+    Opcode_movi_encode_fns, 0, 0 },
+  { "moveqz", ICLASS_xt_iclass_movz,
+    0,
+    Opcode_moveqz_encode_fns, 0, 0 },
+  { "movnez", ICLASS_xt_iclass_movz,
+    0,
+    Opcode_movnez_encode_fns, 0, 0 },
+  { "movltz", ICLASS_xt_iclass_movz,
+    0,
+    Opcode_movltz_encode_fns, 0, 0 },
+  { "movgez", ICLASS_xt_iclass_movz,
+    0,
+    Opcode_movgez_encode_fns, 0, 0 },
+  { "neg", ICLASS_xt_iclass_neg,
+    0,
+    Opcode_neg_encode_fns, 0, 0 },
+  { "abs", ICLASS_xt_iclass_neg,
+    0,
+    Opcode_abs_encode_fns, 0, 0 },
+  { "nop", ICLASS_xt_iclass_nop,
+    0,
+    Opcode_nop_encode_fns, 0, 0 },
+  { "ret", ICLASS_xt_iclass_return,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_ret_encode_fns, 0, 0 },
+  { "simcall", ICLASS_xt_iclass_simcall,
+    0,
+    Opcode_simcall_encode_fns, 0, 0 },
+  { "s16i", ICLASS_xt_iclass_s16i,
+    0,
+    Opcode_s16i_encode_fns, 0, 0 },
+  { "s32i", ICLASS_xt_iclass_s32i,
+    0,
+    Opcode_s32i_encode_fns, 0, 0 },
+  { "s32nb", ICLASS_xt_iclass_s32nb,
+    0,
+    Opcode_s32nb_encode_fns, 0, 0 },
+  { "s8i", ICLASS_xt_iclass_s8i,
+    0,
+    Opcode_s8i_encode_fns, 0, 0 },
+  { "ssr", ICLASS_xt_iclass_sar,
+    0,
+    Opcode_ssr_encode_fns, 0, 0 },
+  { "ssl", ICLASS_xt_iclass_sar,
+    0,
+    Opcode_ssl_encode_fns, 0, 0 },
+  { "ssa8l", ICLASS_xt_iclass_sar,
+    0,
+    Opcode_ssa8l_encode_fns, 0, 0 },
+  { "ssa8b", ICLASS_xt_iclass_sar,
+    0,
+    Opcode_ssa8b_encode_fns, 0, 0 },
+  { "ssai", ICLASS_xt_iclass_sari,
+    0,
+    Opcode_ssai_encode_fns, 0, 0 },
+  { "sll", ICLASS_xt_iclass_shifts,
+    0,
+    Opcode_sll_encode_fns, 0, 0 },
+  { "src", ICLASS_xt_iclass_shiftst,
+    0,
+    Opcode_src_encode_fns, 0, 0 },
+  { "srl", ICLASS_xt_iclass_shiftt,
+    0,
+    Opcode_srl_encode_fns, 0, 0 },
+  { "sra", ICLASS_xt_iclass_shiftt,
+    0,
+    Opcode_sra_encode_fns, 0, 0 },
+  { "slli", ICLASS_xt_iclass_slli,
+    0,
+    Opcode_slli_encode_fns, 0, 0 },
+  { "srai", ICLASS_xt_iclass_srai,
+    0,
+    Opcode_srai_encode_fns, 0, 0 },
+  { "srli", ICLASS_xt_iclass_srli,
+    0,
+    Opcode_srli_encode_fns, 0, 0 },
+  { "memw", ICLASS_xt_iclass_memw,
+    0,
+    Opcode_memw_encode_fns, 0, 0 },
+  { "extw", ICLASS_xt_iclass_extw,
+    0,
+    Opcode_extw_encode_fns, 0, 0 },
+  { "isync", ICLASS_xt_iclass_isync,
+    0,
+    Opcode_isync_encode_fns, 0, 0 },
+  { "rsync", ICLASS_xt_iclass_sync,
+    0,
+    Opcode_rsync_encode_fns, 0, 0 },
+  { "esync", ICLASS_xt_iclass_sync,
+    0,
+    Opcode_esync_encode_fns, 0, 0 },
+  { "dsync", ICLASS_xt_iclass_sync,
+    0,
+    Opcode_dsync_encode_fns, 0, 0 },
+  { "rsil", ICLASS_xt_iclass_rsil,
+    0,
+    Opcode_rsil_encode_fns, 0, 0 },
+  { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
+    0,
+    Opcode_rsr_sar_encode_fns, 0, 0 },
+  { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
+    0,
+    Opcode_wsr_sar_encode_fns, 0, 0 },
+  { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
+    0,
+    Opcode_xsr_sar_encode_fns, 0, 0 },
+  { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl,
+    0,
+    Opcode_rsr_memctl_encode_fns, 0, 0 },
+  { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl,
+    0,
+    Opcode_wsr_memctl_encode_fns, 0, 0 },
+  { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl,
+    0,
+    Opcode_xsr_memctl_encode_fns, 0, 0 },
+  { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase,
+    0,
+    Opcode_rsr_litbase_encode_fns, 0, 0 },
+  { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase,
+    0,
+    Opcode_wsr_litbase_encode_fns, 0, 0 },
+  { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
+    0,
+    Opcode_xsr_litbase_encode_fns, 0, 0 },
+  { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0,
+    0,
+    Opcode_rsr_configid0_encode_fns, 0, 0 },
+  { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0,
+    0,
+    Opcode_wsr_configid0_encode_fns, 0, 0 },
+  { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1,
+    0,
+    Opcode_rsr_configid1_encode_fns, 0, 0 },
+  { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
+    0,
+    Opcode_rsr_ps_encode_fns, 0, 0 },
+  { "wsr.ps", ICLASS_xt_iclass_wsr_ps,
+    0,
+    Opcode_wsr_ps_encode_fns, 0, 0 },
+  { "xsr.ps", ICLASS_xt_iclass_xsr_ps,
+    0,
+    Opcode_xsr_ps_encode_fns, 0, 0 },
+  { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
+    0,
+    Opcode_rsr_epc1_encode_fns, 0, 0 },
+  { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
+    0,
+    Opcode_wsr_epc1_encode_fns, 0, 0 },
+  { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
+    0,
+    Opcode_xsr_epc1_encode_fns, 0, 0 },
+  { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
+    0,
+    Opcode_rsr_excsave1_encode_fns, 0, 0 },
+  { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
+    0,
+    Opcode_wsr_excsave1_encode_fns, 0, 0 },
+  { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
+    0,
+    Opcode_xsr_excsave1_encode_fns, 0, 0 },
+  { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
+    0,
+    Opcode_rsr_epc2_encode_fns, 0, 0 },
+  { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
+    0,
+    Opcode_wsr_epc2_encode_fns, 0, 0 },
+  { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
+    0,
+    Opcode_xsr_epc2_encode_fns, 0, 0 },
+  { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
+    0,
+    Opcode_rsr_excsave2_encode_fns, 0, 0 },
+  { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
+    0,
+    Opcode_wsr_excsave2_encode_fns, 0, 0 },
+  { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
+    0,
+    Opcode_xsr_excsave2_encode_fns, 0, 0 },
+  { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3,
+    0,
+    Opcode_rsr_epc3_encode_fns, 0, 0 },
+  { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3,
+    0,
+    Opcode_wsr_epc3_encode_fns, 0, 0 },
+  { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3,
+    0,
+    Opcode_xsr_epc3_encode_fns, 0, 0 },
+  { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3,
+    0,
+    Opcode_rsr_excsave3_encode_fns, 0, 0 },
+  { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3,
+    0,
+    Opcode_wsr_excsave3_encode_fns, 0, 0 },
+  { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3,
+    0,
+    Opcode_xsr_excsave3_encode_fns, 0, 0 },
+  { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4,
+    0,
+    Opcode_rsr_epc4_encode_fns, 0, 0 },
+  { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4,
+    0,
+    Opcode_wsr_epc4_encode_fns, 0, 0 },
+  { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4,
+    0,
+    Opcode_xsr_epc4_encode_fns, 0, 0 },
+  { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4,
+    0,
+    Opcode_rsr_excsave4_encode_fns, 0, 0 },
+  { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4,
+    0,
+    Opcode_wsr_excsave4_encode_fns, 0, 0 },
+  { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4,
+    0,
+    Opcode_xsr_excsave4_encode_fns, 0, 0 },
+  { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5,
+    0,
+    Opcode_rsr_epc5_encode_fns, 0, 0 },
+  { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5,
+    0,
+    Opcode_wsr_epc5_encode_fns, 0, 0 },
+  { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5,
+    0,
+    Opcode_xsr_epc5_encode_fns, 0, 0 },
+  { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5,
+    0,
+    Opcode_rsr_excsave5_encode_fns, 0, 0 },
+  { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5,
+    0,
+    Opcode_wsr_excsave5_encode_fns, 0, 0 },
+  { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5,
+    0,
+    Opcode_xsr_excsave5_encode_fns, 0, 0 },
+  { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6,
+    0,
+    Opcode_rsr_epc6_encode_fns, 0, 0 },
+  { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6,
+    0,
+    Opcode_wsr_epc6_encode_fns, 0, 0 },
+  { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6,
+    0,
+    Opcode_xsr_epc6_encode_fns, 0, 0 },
+  { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6,
+    0,
+    Opcode_rsr_excsave6_encode_fns, 0, 0 },
+  { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6,
+    0,
+    Opcode_wsr_excsave6_encode_fns, 0, 0 },
+  { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6,
+    0,
+    Opcode_xsr_excsave6_encode_fns, 0, 0 },
+  { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7,
+    0,
+    Opcode_rsr_epc7_encode_fns, 0, 0 },
+  { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7,
+    0,
+    Opcode_wsr_epc7_encode_fns, 0, 0 },
+  { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7,
+    0,
+    Opcode_xsr_epc7_encode_fns, 0, 0 },
+  { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7,
+    0,
+    Opcode_rsr_excsave7_encode_fns, 0, 0 },
+  { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7,
+    0,
+    Opcode_wsr_excsave7_encode_fns, 0, 0 },
+  { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7,
+    0,
+    Opcode_xsr_excsave7_encode_fns, 0, 0 },
+  { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
+    0,
+    Opcode_rsr_eps2_encode_fns, 0, 0 },
+  { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
+    0,
+    Opcode_wsr_eps2_encode_fns, 0, 0 },
+  { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
+    0,
+    Opcode_xsr_eps2_encode_fns, 0, 0 },
+  { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3,
+    0,
+    Opcode_rsr_eps3_encode_fns, 0, 0 },
+  { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3,
+    0,
+    Opcode_wsr_eps3_encode_fns, 0, 0 },
+  { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3,
+    0,
+    Opcode_xsr_eps3_encode_fns, 0, 0 },
+  { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4,
+    0,
+    Opcode_rsr_eps4_encode_fns, 0, 0 },
+  { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4,
+    0,
+    Opcode_wsr_eps4_encode_fns, 0, 0 },
+  { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4,
+    0,
+    Opcode_xsr_eps4_encode_fns, 0, 0 },
+  { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5,
+    0,
+    Opcode_rsr_eps5_encode_fns, 0, 0 },
+  { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5,
+    0,
+    Opcode_wsr_eps5_encode_fns, 0, 0 },
+  { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5,
+    0,
+    Opcode_xsr_eps5_encode_fns, 0, 0 },
+  { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6,
+    0,
+    Opcode_rsr_eps6_encode_fns, 0, 0 },
+  { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6,
+    0,
+    Opcode_wsr_eps6_encode_fns, 0, 0 },
+  { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6,
+    0,
+    Opcode_xsr_eps6_encode_fns, 0, 0 },
+  { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7,
+    0,
+    Opcode_rsr_eps7_encode_fns, 0, 0 },
+  { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7,
+    0,
+    Opcode_wsr_eps7_encode_fns, 0, 0 },
+  { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7,
+    0,
+    Opcode_xsr_eps7_encode_fns, 0, 0 },
+  { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
+    0,
+    Opcode_rsr_excvaddr_encode_fns, 0, 0 },
+  { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
+    0,
+    Opcode_wsr_excvaddr_encode_fns, 0, 0 },
+  { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
+    0,
+    Opcode_xsr_excvaddr_encode_fns, 0, 0 },
+  { "rsr.depc", ICLASS_xt_iclass_rsr_depc,
+    0,
+    Opcode_rsr_depc_encode_fns, 0, 0 },
+  { "wsr.depc", ICLASS_xt_iclass_wsr_depc,
+    0,
+    Opcode_wsr_depc_encode_fns, 0, 0 },
+  { "xsr.depc", ICLASS_xt_iclass_xsr_depc,
+    0,
+    Opcode_xsr_depc_encode_fns, 0, 0 },
+  { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
+    0,
+    Opcode_rsr_exccause_encode_fns, 0, 0 },
+  { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
+    0,
+    Opcode_wsr_exccause_encode_fns, 0, 0 },
+  { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
+    0,
+    Opcode_xsr_exccause_encode_fns, 0, 0 },
+  { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0,
+    0,
+    Opcode_rsr_misc0_encode_fns, 0, 0 },
+  { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0,
+    0,
+    Opcode_wsr_misc0_encode_fns, 0, 0 },
+  { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0,
+    0,
+    Opcode_xsr_misc0_encode_fns, 0, 0 },
+  { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
+    0,
+    Opcode_rsr_misc1_encode_fns, 0, 0 },
+  { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
+    0,
+    Opcode_wsr_misc1_encode_fns, 0, 0 },
+  { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
+    0,
+    Opcode_xsr_misc1_encode_fns, 0, 0 },
+  { "rsr.misc2", ICLASS_xt_iclass_rsr_misc2,
+    0,
+    Opcode_rsr_misc2_encode_fns, 0, 0 },
+  { "wsr.misc2", ICLASS_xt_iclass_wsr_misc2,
+    0,
+    Opcode_wsr_misc2_encode_fns, 0, 0 },
+  { "xsr.misc2", ICLASS_xt_iclass_xsr_misc2,
+    0,
+    Opcode_xsr_misc2_encode_fns, 0, 0 },
+  { "rsr.misc3", ICLASS_xt_iclass_rsr_misc3,
+    0,
+    Opcode_rsr_misc3_encode_fns, 0, 0 },
+  { "wsr.misc3", ICLASS_xt_iclass_wsr_misc3,
+    0,
+    Opcode_wsr_misc3_encode_fns, 0, 0 },
+  { "xsr.misc3", ICLASS_xt_iclass_xsr_misc3,
+    0,
+    Opcode_xsr_misc3_encode_fns, 0, 0 },
+  { "rsr.prid", ICLASS_xt_iclass_rsr_prid,
+    0,
+    Opcode_rsr_prid_encode_fns, 0, 0 },
+  { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
+    0,
+    Opcode_rsr_vecbase_encode_fns, 0, 0 },
+  { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
+    0,
+    Opcode_wsr_vecbase_encode_fns, 0, 0 },
+  { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
+    0,
+    Opcode_xsr_vecbase_encode_fns, 0, 0 },
+  { "salt", ICLASS_xt_iclass_salt,
+    0,
+    Opcode_salt_encode_fns, 0, 0 },
+  { "saltu", ICLASS_xt_iclass_salt,
+    0,
+    Opcode_saltu_encode_fns, 0, 0 },
+  { "mul16u", ICLASS_xt_mul16,
+    0,
+    Opcode_mul16u_encode_fns, 0, 0 },
+  { "mul16s", ICLASS_xt_mul16,
+    0,
+    Opcode_mul16s_encode_fns, 0, 0 },
+  { "mull", ICLASS_xt_mul32,
+    0,
+    Opcode_mull_encode_fns, 0, 0 },
+  { "muluh", ICLASS_xt_mul32h,
+    0,
+    Opcode_muluh_encode_fns, 0, 0 },
+  { "mulsh", ICLASS_xt_mul32h,
+    0,
+    Opcode_mulsh_encode_fns, 0, 0 },
+  { "rfi", ICLASS_xt_iclass_rfi,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_rfi_encode_fns, 0, 0 },
+  { "waiti", ICLASS_xt_iclass_wait,
+    0,
+    Opcode_waiti_encode_fns, 0, 0 },
+  { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
+    0,
+    Opcode_rsr_interrupt_encode_fns, 0, 0 },
+  { "wsr.intset", ICLASS_xt_iclass_wsr_intset,
+    0,
+    Opcode_wsr_intset_encode_fns, 0, 0 },
+  { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
+    0,
+    Opcode_wsr_intclear_encode_fns, 0, 0 },
+  { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
+    0,
+    Opcode_rsr_intenable_encode_fns, 0, 0 },
+  { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
+    0,
+    Opcode_wsr_intenable_encode_fns, 0, 0 },
+  { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
+    0,
+    Opcode_xsr_intenable_encode_fns, 0, 0 },
+  { "break", ICLASS_xt_iclass_break,
+    0,
+    Opcode_break_encode_fns, 0, 0 },
+  { "break.n", ICLASS_xt_iclass_break_n,
+    0,
+    Opcode_break_n_encode_fns, 0, 0 },
+  { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0,
+    0,
+    Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
+  { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0,
+    0,
+    Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
+  { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0,
+    0,
+    Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
+  { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0,
+    0,
+    Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
+  { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0,
+    0,
+    Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
+  { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0,
+    0,
+    Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
+  { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1,
+    0,
+    Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
+  { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1,
+    0,
+    Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
+  { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1,
+    0,
+    Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
+  { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1,
+    0,
+    Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
+  { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1,
+    0,
+    Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
+  { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1,
+    0,
+    Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
+  { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0,
+    0,
+    Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
+  { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0,
+    0,
+    Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
+  { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0,
+    0,
+    Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
+  { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1,
+    0,
+    Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
+  { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1,
+    0,
+    Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
+  { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1,
+    0,
+    Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
+  { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable,
+    0,
+    Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
+  { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable,
+    0,
+    Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
+  { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable,
+    0,
+    Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
+  { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
+    0,
+    Opcode_rsr_debugcause_encode_fns, 0, 0 },
+  { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
+    0,
+    Opcode_wsr_debugcause_encode_fns, 0, 0 },
+  { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
+    0,
+    Opcode_xsr_debugcause_encode_fns, 0, 0 },
+  { "rsr.icount", ICLASS_xt_iclass_rsr_icount,
+    0,
+    Opcode_rsr_icount_encode_fns, 0, 0 },
+  { "wsr.icount", ICLASS_xt_iclass_wsr_icount,
+    0,
+    Opcode_wsr_icount_encode_fns, 0, 0 },
+  { "xsr.icount", ICLASS_xt_iclass_xsr_icount,
+    0,
+    Opcode_xsr_icount_encode_fns, 0, 0 },
+  { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
+    0,
+    Opcode_rsr_icountlevel_encode_fns, 0, 0 },
+  { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
+    0,
+    Opcode_wsr_icountlevel_encode_fns, 0, 0 },
+  { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
+    0,
+    Opcode_xsr_icountlevel_encode_fns, 0, 0 },
+  { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
+    0,
+    Opcode_rsr_ddr_encode_fns, 0, 0 },
+  { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
+    0,
+    Opcode_wsr_ddr_encode_fns, 0, 0 },
+  { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
+    0,
+    Opcode_xsr_ddr_encode_fns, 0, 0 },
+  { "lddr32.p", ICLASS_xt_iclass_lddr32_p,
+    0,
+    Opcode_lddr32_p_encode_fns, 0, 0 },
+  { "sddr32.p", ICLASS_xt_iclass_sddr32_p,
+    0,
+    Opcode_sddr32_p_encode_fns, 0, 0 },
+  { "rfdo", ICLASS_xt_iclass_rfdo,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_rfdo_encode_fns, 0, 0 },
+  { "rfdd", ICLASS_xt_iclass_rfdd,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_rfdd_encode_fns, 0, 0 },
+  { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid,
+    0,
+    Opcode_wsr_mmid_encode_fns, 0, 0 },
+  { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
+    0,
+    Opcode_rsr_ccount_encode_fns, 0, 0 },
+  { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
+    0,
+    Opcode_wsr_ccount_encode_fns, 0, 0 },
+  { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
+    0,
+    Opcode_xsr_ccount_encode_fns, 0, 0 },
+  { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
+    0,
+    Opcode_rsr_ccompare0_encode_fns, 0, 0 },
+  { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
+    0,
+    Opcode_wsr_ccompare0_encode_fns, 0, 0 },
+  { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
+    0,
+    Opcode_xsr_ccompare0_encode_fns, 0, 0 },
+  { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1,
+    0,
+    Opcode_rsr_ccompare1_encode_fns, 0, 0 },
+  { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1,
+    0,
+    Opcode_wsr_ccompare1_encode_fns, 0, 0 },
+  { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1,
+    0,
+    Opcode_xsr_ccompare1_encode_fns, 0, 0 },
+  { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2,
+    0,
+    Opcode_rsr_ccompare2_encode_fns, 0, 0 },
+  { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2,
+    0,
+    Opcode_wsr_ccompare2_encode_fns, 0, 0 },
+  { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2,
+    0,
+    Opcode_xsr_ccompare2_encode_fns, 0, 0 },
+  { "idtlb", ICLASS_xt_iclass_idtlb,
+    0,
+    Opcode_idtlb_encode_fns, 0, 0 },
+  { "pdtlb", ICLASS_xt_iclass_rdtlb,
+    0,
+    Opcode_pdtlb_encode_fns, 0, 0 },
+  { "rdtlb0", ICLASS_xt_iclass_rdtlb,
+    0,
+    Opcode_rdtlb0_encode_fns, 0, 0 },
+  { "rdtlb1", ICLASS_xt_iclass_rdtlb,
+    0,
+    Opcode_rdtlb1_encode_fns, 0, 0 },
+  { "wdtlb", ICLASS_xt_iclass_wdtlb,
+    0,
+    Opcode_wdtlb_encode_fns, 0, 0 },
+  { "iitlb", ICLASS_xt_iclass_iitlb,
+    0,
+    Opcode_iitlb_encode_fns, 0, 0 },
+  { "pitlb", ICLASS_xt_iclass_ritlb,
+    0,
+    Opcode_pitlb_encode_fns, 0, 0 },
+  { "ritlb0", ICLASS_xt_iclass_ritlb,
+    0,
+    Opcode_ritlb0_encode_fns, 0, 0 },
+  { "ritlb1", ICLASS_xt_iclass_ritlb,
+    0,
+    Opcode_ritlb1_encode_fns, 0, 0 },
+  { "witlb", ICLASS_xt_iclass_witlb,
+    0,
+    Opcode_witlb_encode_fns, 0, 0 },
+  { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable,
+    0,
+    Opcode_rsr_cpenable_encode_fns, 0, 0 },
+  { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable,
+    0,
+    Opcode_wsr_cpenable_encode_fns, 0, 0 },
+  { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable,
+    0,
+    Opcode_xsr_cpenable_encode_fns, 0, 0 },
+  { "clamps", ICLASS_xt_iclass_clamp,
+    0,
+    Opcode_clamps_encode_fns, 0, 0 },
+  { "min", ICLASS_xt_iclass_minmax,
+    0,
+    Opcode_min_encode_fns, 0, 0 },
+  { "max", ICLASS_xt_iclass_minmax,
+    0,
+    Opcode_max_encode_fns, 0, 0 },
+  { "minu", ICLASS_xt_iclass_minmax,
+    0,
+    Opcode_minu_encode_fns, 0, 0 },
+  { "maxu", ICLASS_xt_iclass_minmax,
+    0,
+    Opcode_maxu_encode_fns, 0, 0 },
+  { "nsa", ICLASS_xt_iclass_nsa,
+    0,
+    Opcode_nsa_encode_fns, 0, 0 },
+  { "nsau", ICLASS_xt_iclass_nsa,
+    0,
+    Opcode_nsau_encode_fns, 0, 0 },
+  { "sext", ICLASS_xt_iclass_sx,
+    0,
+    Opcode_sext_encode_fns, 0, 0 },
+  { "l32ai", ICLASS_xt_iclass_l32ai,
+    0,
+    Opcode_l32ai_encode_fns, 0, 0 },
+  { "s32ri", ICLASS_xt_iclass_s32ri,
+    0,
+    Opcode_s32ri_encode_fns, 0, 0 },
+  { "quou", ICLASS_xt_iclass_div,
+    0,
+    Opcode_quou_encode_fns, 0, 0 },
+  { "quos", ICLASS_xt_iclass_div,
+    0,
+    Opcode_quos_encode_fns, 0, 0 },
+  { "remu", ICLASS_xt_iclass_div,
+    0,
+    Opcode_remu_encode_fns, 0, 0 },
+  { "rems", ICLASS_xt_iclass_div,
+    0,
+    Opcode_rems_encode_fns, 0, 0 },
+  { "rsr.eraccess", ICLASS_xt_iclass_rsr_eraccess,
+    0,
+    Opcode_rsr_eraccess_encode_fns, 0, 0 },
+  { "wsr.eraccess", ICLASS_xt_iclass_wsr_eraccess,
+    0,
+    Opcode_wsr_eraccess_encode_fns, 0, 0 },
+  { "xsr.eraccess", ICLASS_xt_iclass_xsr_eraccess,
+    0,
+    Opcode_xsr_eraccess_encode_fns, 0, 0 },
+  { "rer", ICLASS_xt_iclass_rer,
+    0,
+    Opcode_rer_encode_fns, 0, 0 },
+  { "wer", ICLASS_xt_iclass_wer,
+    0,
+    Opcode_wer_encode_fns, 0, 0 },
+  { "wr_mask_gpio_out", ICLASS_WR_MASK_GPIO_OUT,
+    0,
+    Opcode_wr_mask_gpio_out_encode_fns, 0, 0 },
+  { "set_bit_gpio_out", ICLASS_SET_BIT_GPIO_OUT,
+    0,
+    Opcode_set_bit_gpio_out_encode_fns, 0, 0 },
+  { "clr_bit_gpio_out", ICLASS_CLR_BIT_GPIO_OUT,
+    0,
+    Opcode_clr_bit_gpio_out_encode_fns, 0, 0 },
+  { "get_gpio_in", ICLASS_GET_GPIO_IN,
+    0,
+    Opcode_get_gpio_in_encode_fns, 0, 0 },
+  { "rur.gpio_out", ICLASS_rur_gpio_out,
+    0,
+    Opcode_rur_gpio_out_encode_fns, 0, 0 },
+  { "wur.gpio_out", ICLASS_wur_gpio_out,
+    0,
+    Opcode_wur_gpio_out_encode_fns, 0, 0 }
+};
+
+enum xtensa_opcode_id {
+  OPCODE_EXCW,
+  OPCODE_RFE,
+  OPCODE_RFDE,
+  OPCODE_SYSCALL,
+  OPCODE_CALL12,
+  OPCODE_CALL8,
+  OPCODE_CALL4,
+  OPCODE_CALLX12,
+  OPCODE_CALLX8,
+  OPCODE_CALLX4,
+  OPCODE_ENTRY,
+  OPCODE_MOVSP,
+  OPCODE_ROTW,
+  OPCODE_RETW,
+  OPCODE_RETW_N,
+  OPCODE_RFWO,
+  OPCODE_RFWU,
+  OPCODE_L32E,
+  OPCODE_S32E,
+  OPCODE_RSR_WINDOWBASE,
+  OPCODE_WSR_WINDOWBASE,
+  OPCODE_XSR_WINDOWBASE,
+  OPCODE_RSR_WINDOWSTART,
+  OPCODE_WSR_WINDOWSTART,
+  OPCODE_XSR_WINDOWSTART,
+  OPCODE_ADD_N,
+  OPCODE_ADDI_N,
+  OPCODE_BEQZ_N,
+  OPCODE_BNEZ_N,
+  OPCODE_ILL_N,
+  OPCODE_L32I_N,
+  OPCODE_MOV_N,
+  OPCODE_MOVI_N,
+  OPCODE_NOP_N,
+  OPCODE_RET_N,
+  OPCODE_S32I_N,
+  OPCODE_RUR_THREADPTR,
+  OPCODE_WUR_THREADPTR,
+  OPCODE_ADDI,
+  OPCODE_ADDMI,
+  OPCODE_ADD,
+  OPCODE_SUB,
+  OPCODE_ADDX2,
+  OPCODE_ADDX4,
+  OPCODE_ADDX8,
+  OPCODE_SUBX2,
+  OPCODE_SUBX4,
+  OPCODE_SUBX8,
+  OPCODE_AND,
+  OPCODE_OR,
+  OPCODE_XOR,
+  OPCODE_BEQI,
+  OPCODE_BNEI,
+  OPCODE_BGEI,
+  OPCODE_BLTI,
+  OPCODE_BBCI,
+  OPCODE_BBSI,
+  OPCODE_BGEUI,
+  OPCODE_BLTUI,
+  OPCODE_BEQ,
+  OPCODE_BNE,
+  OPCODE_BGE,
+  OPCODE_BLT,
+  OPCODE_BGEU,
+  OPCODE_BLTU,
+  OPCODE_BANY,
+  OPCODE_BNONE,
+  OPCODE_BALL,
+  OPCODE_BNALL,
+  OPCODE_BBC,
+  OPCODE_BBS,
+  OPCODE_BEQZ,
+  OPCODE_BNEZ,
+  OPCODE_BGEZ,
+  OPCODE_BLTZ,
+  OPCODE_CALL0,
+  OPCODE_CALLX0,
+  OPCODE_EXTUI,
+  OPCODE_ILL,
+  OPCODE_J,
+  OPCODE_JX,
+  OPCODE_L16UI,
+  OPCODE_L16SI,
+  OPCODE_L32I,
+  OPCODE_L32R,
+  OPCODE_L8UI,
+  OPCODE_MOVI,
+  OPCODE_MOVEQZ,
+  OPCODE_MOVNEZ,
+  OPCODE_MOVLTZ,
+  OPCODE_MOVGEZ,
+  OPCODE_NEG,
+  OPCODE_ABS,
+  OPCODE_NOP,
+  OPCODE_RET,
+  OPCODE_SIMCALL,
+  OPCODE_S16I,
+  OPCODE_S32I,
+  OPCODE_S32NB,
+  OPCODE_S8I,
+  OPCODE_SSR,
+  OPCODE_SSL,
+  OPCODE_SSA8L,
+  OPCODE_SSA8B,
+  OPCODE_SSAI,
+  OPCODE_SLL,
+  OPCODE_SRC,
+  OPCODE_SRL,
+  OPCODE_SRA,
+  OPCODE_SLLI,
+  OPCODE_SRAI,
+  OPCODE_SRLI,
+  OPCODE_MEMW,
+  OPCODE_EXTW,
+  OPCODE_ISYNC,
+  OPCODE_RSYNC,
+  OPCODE_ESYNC,
+  OPCODE_DSYNC,
+  OPCODE_RSIL,
+  OPCODE_RSR_SAR,
+  OPCODE_WSR_SAR,
+  OPCODE_XSR_SAR,
+  OPCODE_RSR_MEMCTL,
+  OPCODE_WSR_MEMCTL,
+  OPCODE_XSR_MEMCTL,
+  OPCODE_RSR_LITBASE,
+  OPCODE_WSR_LITBASE,
+  OPCODE_XSR_LITBASE,
+  OPCODE_RSR_CONFIGID0,
+  OPCODE_WSR_CONFIGID0,
+  OPCODE_RSR_CONFIGID1,
+  OPCODE_RSR_PS,
+  OPCODE_WSR_PS,
+  OPCODE_XSR_PS,
+  OPCODE_RSR_EPC1,
+  OPCODE_WSR_EPC1,
+  OPCODE_XSR_EPC1,
+  OPCODE_RSR_EXCSAVE1,
+  OPCODE_WSR_EXCSAVE1,
+  OPCODE_XSR_EXCSAVE1,
+  OPCODE_RSR_EPC2,
+  OPCODE_WSR_EPC2,
+  OPCODE_XSR_EPC2,
+  OPCODE_RSR_EXCSAVE2,
+  OPCODE_WSR_EXCSAVE2,
+  OPCODE_XSR_EXCSAVE2,
+  OPCODE_RSR_EPC3,
+  OPCODE_WSR_EPC3,
+  OPCODE_XSR_EPC3,
+  OPCODE_RSR_EXCSAVE3,
+  OPCODE_WSR_EXCSAVE3,
+  OPCODE_XSR_EXCSAVE3,
+  OPCODE_RSR_EPC4,
+  OPCODE_WSR_EPC4,
+  OPCODE_XSR_EPC4,
+  OPCODE_RSR_EXCSAVE4,
+  OPCODE_WSR_EXCSAVE4,
+  OPCODE_XSR_EXCSAVE4,
+  OPCODE_RSR_EPC5,
+  OPCODE_WSR_EPC5,
+  OPCODE_XSR_EPC5,
+  OPCODE_RSR_EXCSAVE5,
+  OPCODE_WSR_EXCSAVE5,
+  OPCODE_XSR_EXCSAVE5,
+  OPCODE_RSR_EPC6,
+  OPCODE_WSR_EPC6,
+  OPCODE_XSR_EPC6,
+  OPCODE_RSR_EXCSAVE6,
+  OPCODE_WSR_EXCSAVE6,
+  OPCODE_XSR_EXCSAVE6,
+  OPCODE_RSR_EPC7,
+  OPCODE_WSR_EPC7,
+  OPCODE_XSR_EPC7,
+  OPCODE_RSR_EXCSAVE7,
+  OPCODE_WSR_EXCSAVE7,
+  OPCODE_XSR_EXCSAVE7,
+  OPCODE_RSR_EPS2,
+  OPCODE_WSR_EPS2,
+  OPCODE_XSR_EPS2,
+  OPCODE_RSR_EPS3,
+  OPCODE_WSR_EPS3,
+  OPCODE_XSR_EPS3,
+  OPCODE_RSR_EPS4,
+  OPCODE_WSR_EPS4,
+  OPCODE_XSR_EPS4,
+  OPCODE_RSR_EPS5,
+  OPCODE_WSR_EPS5,
+  OPCODE_XSR_EPS5,
+  OPCODE_RSR_EPS6,
+  OPCODE_WSR_EPS6,
+  OPCODE_XSR_EPS6,
+  OPCODE_RSR_EPS7,
+  OPCODE_WSR_EPS7,
+  OPCODE_XSR_EPS7,
+  OPCODE_RSR_EXCVADDR,
+  OPCODE_WSR_EXCVADDR,
+  OPCODE_XSR_EXCVADDR,
+  OPCODE_RSR_DEPC,
+  OPCODE_WSR_DEPC,
+  OPCODE_XSR_DEPC,
+  OPCODE_RSR_EXCCAUSE,
+  OPCODE_WSR_EXCCAUSE,
+  OPCODE_XSR_EXCCAUSE,
+  OPCODE_RSR_MISC0,
+  OPCODE_WSR_MISC0,
+  OPCODE_XSR_MISC0,
+  OPCODE_RSR_MISC1,
+  OPCODE_WSR_MISC1,
+  OPCODE_XSR_MISC1,
+  OPCODE_RSR_MISC2,
+  OPCODE_WSR_MISC2,
+  OPCODE_XSR_MISC2,
+  OPCODE_RSR_MISC3,
+  OPCODE_WSR_MISC3,
+  OPCODE_XSR_MISC3,
+  OPCODE_RSR_PRID,
+  OPCODE_RSR_VECBASE,
+  OPCODE_WSR_VECBASE,
+  OPCODE_XSR_VECBASE,
+  OPCODE_SALT,
+  OPCODE_SALTU,
+  OPCODE_MUL16U,
+  OPCODE_MUL16S,
+  OPCODE_MULL,
+  OPCODE_MULUH,
+  OPCODE_MULSH,
+  OPCODE_RFI,
+  OPCODE_WAITI,
+  OPCODE_RSR_INTERRUPT,
+  OPCODE_WSR_INTSET,
+  OPCODE_WSR_INTCLEAR,
+  OPCODE_RSR_INTENABLE,
+  OPCODE_WSR_INTENABLE,
+  OPCODE_XSR_INTENABLE,
+  OPCODE_BREAK,
+  OPCODE_BREAK_N,
+  OPCODE_RSR_DBREAKA0,
+  OPCODE_WSR_DBREAKA0,
+  OPCODE_XSR_DBREAKA0,
+  OPCODE_RSR_DBREAKC0,
+  OPCODE_WSR_DBREAKC0,
+  OPCODE_XSR_DBREAKC0,
+  OPCODE_RSR_DBREAKA1,
+  OPCODE_WSR_DBREAKA1,
+  OPCODE_XSR_DBREAKA1,
+  OPCODE_RSR_DBREAKC1,
+  OPCODE_WSR_DBREAKC1,
+  OPCODE_XSR_DBREAKC1,
+  OPCODE_RSR_IBREAKA0,
+  OPCODE_WSR_IBREAKA0,
+  OPCODE_XSR_IBREAKA0,
+  OPCODE_RSR_IBREAKA1,
+  OPCODE_WSR_IBREAKA1,
+  OPCODE_XSR_IBREAKA1,
+  OPCODE_RSR_IBREAKENABLE,
+  OPCODE_WSR_IBREAKENABLE,
+  OPCODE_XSR_IBREAKENABLE,
+  OPCODE_RSR_DEBUGCAUSE,
+  OPCODE_WSR_DEBUGCAUSE,
+  OPCODE_XSR_DEBUGCAUSE,
+  OPCODE_RSR_ICOUNT,
+  OPCODE_WSR_ICOUNT,
+  OPCODE_XSR_ICOUNT,
+  OPCODE_RSR_ICOUNTLEVEL,
+  OPCODE_WSR_ICOUNTLEVEL,
+  OPCODE_XSR_ICOUNTLEVEL,
+  OPCODE_RSR_DDR,
+  OPCODE_WSR_DDR,
+  OPCODE_XSR_DDR,
+  OPCODE_LDDR32_P,
+  OPCODE_SDDR32_P,
+  OPCODE_RFDO,
+  OPCODE_RFDD,
+  OPCODE_WSR_MMID,
+  OPCODE_RSR_CCOUNT,
+  OPCODE_WSR_CCOUNT,
+  OPCODE_XSR_CCOUNT,
+  OPCODE_RSR_CCOMPARE0,
+  OPCODE_WSR_CCOMPARE0,
+  OPCODE_XSR_CCOMPARE0,
+  OPCODE_RSR_CCOMPARE1,
+  OPCODE_WSR_CCOMPARE1,
+  OPCODE_XSR_CCOMPARE1,
+  OPCODE_RSR_CCOMPARE2,
+  OPCODE_WSR_CCOMPARE2,
+  OPCODE_XSR_CCOMPARE2,
+  OPCODE_IDTLB,
+  OPCODE_PDTLB,
+  OPCODE_RDTLB0,
+  OPCODE_RDTLB1,
+  OPCODE_WDTLB,
+  OPCODE_IITLB,
+  OPCODE_PITLB,
+  OPCODE_RITLB0,
+  OPCODE_RITLB1,
+  OPCODE_WITLB,
+  OPCODE_RSR_CPENABLE,
+  OPCODE_WSR_CPENABLE,
+  OPCODE_XSR_CPENABLE,
+  OPCODE_CLAMPS,
+  OPCODE_MIN,
+  OPCODE_MAX,
+  OPCODE_MINU,
+  OPCODE_MAXU,
+  OPCODE_NSA,
+  OPCODE_NSAU,
+  OPCODE_SEXT,
+  OPCODE_L32AI,
+  OPCODE_S32RI,
+  OPCODE_QUOU,
+  OPCODE_QUOS,
+  OPCODE_REMU,
+  OPCODE_REMS,
+  OPCODE_RSR_ERACCESS,
+  OPCODE_WSR_ERACCESS,
+  OPCODE_XSR_ERACCESS,
+  OPCODE_RER,
+  OPCODE_WER,
+  OPCODE_WR_MASK_GPIO_OUT,
+  OPCODE_SET_BIT_GPIO_OUT,
+  OPCODE_CLR_BIT_GPIO_OUT,
+  OPCODE_GET_GPIO_IN,
+  OPCODE_RUR_GPIO_OUT,
+  OPCODE_WUR_GPIO_OUT
+};
+
+\f
+/* Slot-specific opcode decode functions.  */
+
+static int
+Slot_inst_decode (const xtensa_insnbuf insn)
+{
+  if (Field_fld_inst_23_12_Slot_inst_get (insn) == 96 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 0)
+    return OPCODE_CLR_BIT_GPIO_OUT;
+  if (Field_fld_inst_23_12_Slot_inst_get (insn) == 97 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 0)
+    return OPCODE_SET_BIT_GPIO_OUT;
+  if (Field_fld_inst_23_12_Slot_inst_get (insn) == 98 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 0)
+    return OPCODE_WR_MASK_GPIO_OUT;
+  if (Field_fld_inst_23_8_Slot_inst_get (insn) == 1584 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 0)
+    return OPCODE_GET_GPIO_IN;
+  if (Field_op0_Slot_inst_get (insn) == 0)
+    {
+      if (Field_op1_Slot_inst_get (insn) == 0)
+	{
+	  if (Field_op2_Slot_inst_get (insn) == 0)
+	    {
+	      if (Field_r_Slot_inst_get (insn) == 0)
+		{
+		  if (Field_m_Slot_inst_get (insn) == 0 &&
+		      Field_s_Slot_inst_get (insn) == 0 &&
+		      Field_n_Slot_inst_get (insn) == 0)
+		    return OPCODE_ILL;
+		  if (Field_m_Slot_inst_get (insn) == 2)
+		    {
+		      if (Field_n_Slot_inst_get (insn) == 0)
+			return OPCODE_RET;
+		      if (Field_n_Slot_inst_get (insn) == 1)
+			return OPCODE_RETW;
+		      if (Field_n_Slot_inst_get (insn) == 2)
+			return OPCODE_JX;
+		    }
+		  if (Field_m_Slot_inst_get (insn) == 3)
+		    {
+		      if (Field_n_Slot_inst_get (insn) == 0)
+			return OPCODE_CALLX0;
+		      if (Field_n_Slot_inst_get (insn) == 1)
+			return OPCODE_CALLX4;
+		      if (Field_n_Slot_inst_get (insn) == 2)
+			return OPCODE_CALLX8;
+		      if (Field_n_Slot_inst_get (insn) == 3)
+			return OPCODE_CALLX12;
+		    }
+		}
+	      if (Field_r_Slot_inst_get (insn) == 1)
+		return OPCODE_MOVSP;
+	      if (Field_r_Slot_inst_get (insn) == 2)
+		{
+		  if (Field_s_Slot_inst_get (insn) == 0)
+		    {
+		      if (Field_t_Slot_inst_get (insn) == 0)
+			return OPCODE_ISYNC;
+		      if (Field_t_Slot_inst_get (insn) == 1)
+			return OPCODE_RSYNC;
+		      if (Field_t_Slot_inst_get (insn) == 2)
+			return OPCODE_ESYNC;
+		      if (Field_t_Slot_inst_get (insn) == 3)
+			return OPCODE_DSYNC;
+		      if (Field_t_Slot_inst_get (insn) == 8)
+			return OPCODE_EXCW;
+		      if (Field_t_Slot_inst_get (insn) == 12)
+			return OPCODE_MEMW;
+		      if (Field_t_Slot_inst_get (insn) == 13)
+			return OPCODE_EXTW;
+		      if (Field_t_Slot_inst_get (insn) == 15)
+			return OPCODE_NOP;
+		    }
+		}
+	      if (Field_r_Slot_inst_get (insn) == 3)
+		{
+		  if (Field_t_Slot_inst_get (insn) == 0)
+		    {
+		      if (Field_s_Slot_inst_get (insn) == 0)
+			return OPCODE_RFE;
+		      if (Field_s_Slot_inst_get (insn) == 2)
+			return OPCODE_RFDE;
+		      if (Field_s_Slot_inst_get (insn) == 4)
+			return OPCODE_RFWO;
+		      if (Field_s_Slot_inst_get (insn) == 5)
+			return OPCODE_RFWU;
+		    }
+		  if (Field_t_Slot_inst_get (insn) == 1)
+		    return OPCODE_RFI;
+		}
+	      if (Field_r_Slot_inst_get (insn) == 4)
+		return OPCODE_BREAK;
+	      if (Field_r_Slot_inst_get (insn) == 5)
+		{
+		  if (Field_s_Slot_inst_get (insn) == 0 &&
+		      Field_t_Slot_inst_get (insn) == 0)
+		    return OPCODE_SYSCALL;
+		  if (Field_s_Slot_inst_get (insn) == 1 &&
+		      Field_t_Slot_inst_get (insn) == 0)
+		    return OPCODE_SIMCALL;
+		}
+	      if (Field_r_Slot_inst_get (insn) == 6)
+		return OPCODE_RSIL;
+	      if (Field_r_Slot_inst_get (insn) == 7 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_WAITI;
+	      if (Field_r_Slot_inst_get (insn) == 7)
+		{
+		  if (Field_t_Slot_inst_get (insn) == 14)
+		    return OPCODE_LDDR32_P;
+		  if (Field_t_Slot_inst_get (insn) == 15)
+		    return OPCODE_SDDR32_P;
+		}
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 1)
+	    return OPCODE_AND;
+	  if (Field_op2_Slot_inst_get (insn) == 2)
+	    return OPCODE_OR;
+	  if (Field_op2_Slot_inst_get (insn) == 3)
+	    return OPCODE_XOR;
+	  if (Field_op2_Slot_inst_get (insn) == 4)
+	    {
+	      if (Field_r_Slot_inst_get (insn) == 0 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_SSR;
+	      if (Field_r_Slot_inst_get (insn) == 1 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_SSL;
+	      if (Field_r_Slot_inst_get (insn) == 2 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_SSA8L;
+	      if (Field_r_Slot_inst_get (insn) == 3 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_SSA8B;
+	      if (Field_r_Slot_inst_get (insn) == 4 &&
+		  Field_thi3_Slot_inst_get (insn) == 0)
+		return OPCODE_SSAI;
+	      if (Field_r_Slot_inst_get (insn) == 6)
+		return OPCODE_RER;
+	      if (Field_r_Slot_inst_get (insn) == 7)
+		return OPCODE_WER;
+	      if (Field_r_Slot_inst_get (insn) == 8 &&
+		  Field_s_Slot_inst_get (insn) == 0)
+		return OPCODE_ROTW;
+	      if (Field_r_Slot_inst_get (insn) == 14)
+		return OPCODE_NSA;
+	      if (Field_r_Slot_inst_get (insn) == 15)
+		return OPCODE_NSAU;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 5)
+	    {
+	      if (Field_r_Slot_inst_get (insn) == 3)
+		return OPCODE_RITLB0;
+	      if (Field_r_Slot_inst_get (insn) == 4 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_IITLB;
+	      if (Field_r_Slot_inst_get (insn) == 5)
+		return OPCODE_PITLB;
+	      if (Field_r_Slot_inst_get (insn) == 6)
+		return OPCODE_WITLB;
+	      if (Field_r_Slot_inst_get (insn) == 7)
+		return OPCODE_RITLB1;
+	      if (Field_r_Slot_inst_get (insn) == 11)
+		return OPCODE_RDTLB0;
+	      if (Field_r_Slot_inst_get (insn) == 12 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_IDTLB;
+	      if (Field_r_Slot_inst_get (insn) == 13)
+		return OPCODE_PDTLB;
+	      if (Field_r_Slot_inst_get (insn) == 14)
+		return OPCODE_WDTLB;
+	      if (Field_r_Slot_inst_get (insn) == 15)
+		return OPCODE_RDTLB1;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 6)
+	    {
+	      if (Field_s_Slot_inst_get (insn) == 0)
+		return OPCODE_NEG;
+	      if (Field_s_Slot_inst_get (insn) == 1)
+		return OPCODE_ABS;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 8)
+	    return OPCODE_ADD;
+	  if (Field_op2_Slot_inst_get (insn) == 9)
+	    return OPCODE_ADDX2;
+	  if (Field_op2_Slot_inst_get (insn) == 10)
+	    return OPCODE_ADDX4;
+	  if (Field_op2_Slot_inst_get (insn) == 11)
+	    return OPCODE_ADDX8;
+	  if (Field_op2_Slot_inst_get (insn) == 12)
+	    return OPCODE_SUB;
+	  if (Field_op2_Slot_inst_get (insn) == 13)
+	    return OPCODE_SUBX2;
+	  if (Field_op2_Slot_inst_get (insn) == 14)
+	    return OPCODE_SUBX4;
+	  if (Field_op2_Slot_inst_get (insn) == 15)
+	    return OPCODE_SUBX8;
+	}
+      if (Field_op1_Slot_inst_get (insn) == 1)
+	{
+	  if ((Field_op2_Slot_inst_get (insn) == 0 ||
+	       Field_op2_Slot_inst_get (insn) == 1))
+	    return OPCODE_SLLI;
+	  if ((Field_op2_Slot_inst_get (insn) == 2 ||
+	       Field_op2_Slot_inst_get (insn) == 3))
+	    return OPCODE_SRAI;
+	  if (Field_op2_Slot_inst_get (insn) == 4)
+	    return OPCODE_SRLI;
+	  if (Field_op2_Slot_inst_get (insn) == 6)
+	    {
+	      if (Field_sr_Slot_inst_get (insn) == 3)
+		return OPCODE_XSR_SAR;
+	      if (Field_sr_Slot_inst_get (insn) == 5)
+		return OPCODE_XSR_LITBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 72)
+		return OPCODE_XSR_WINDOWBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 73)
+		return OPCODE_XSR_WINDOWSTART;
+	      if (Field_sr_Slot_inst_get (insn) == 95)
+		return OPCODE_XSR_ERACCESS;
+	      if (Field_sr_Slot_inst_get (insn) == 96)
+		return OPCODE_XSR_IBREAKENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 97)
+		return OPCODE_XSR_MEMCTL;
+	      if (Field_sr_Slot_inst_get (insn) == 104)
+		return OPCODE_XSR_DDR;
+	      if (Field_sr_Slot_inst_get (insn) == 128)
+		return OPCODE_XSR_IBREAKA0;
+	      if (Field_sr_Slot_inst_get (insn) == 129)
+		return OPCODE_XSR_IBREAKA1;
+	      if (Field_sr_Slot_inst_get (insn) == 144)
+		return OPCODE_XSR_DBREAKA0;
+	      if (Field_sr_Slot_inst_get (insn) == 145)
+		return OPCODE_XSR_DBREAKA1;
+	      if (Field_sr_Slot_inst_get (insn) == 160)
+		return OPCODE_XSR_DBREAKC0;
+	      if (Field_sr_Slot_inst_get (insn) == 161)
+		return OPCODE_XSR_DBREAKC1;
+	      if (Field_sr_Slot_inst_get (insn) == 177)
+		return OPCODE_XSR_EPC1;
+	      if (Field_sr_Slot_inst_get (insn) == 178)
+		return OPCODE_XSR_EPC2;
+	      if (Field_sr_Slot_inst_get (insn) == 179)
+		return OPCODE_XSR_EPC3;
+	      if (Field_sr_Slot_inst_get (insn) == 180)
+		return OPCODE_XSR_EPC4;
+	      if (Field_sr_Slot_inst_get (insn) == 181)
+		return OPCODE_XSR_EPC5;
+	      if (Field_sr_Slot_inst_get (insn) == 182)
+		return OPCODE_XSR_EPC6;
+	      if (Field_sr_Slot_inst_get (insn) == 183)
+		return OPCODE_XSR_EPC7;
+	      if (Field_sr_Slot_inst_get (insn) == 192)
+		return OPCODE_XSR_DEPC;
+	      if (Field_sr_Slot_inst_get (insn) == 194)
+		return OPCODE_XSR_EPS2;
+	      if (Field_sr_Slot_inst_get (insn) == 195)
+		return OPCODE_XSR_EPS3;
+	      if (Field_sr_Slot_inst_get (insn) == 196)
+		return OPCODE_XSR_EPS4;
+	      if (Field_sr_Slot_inst_get (insn) == 197)
+		return OPCODE_XSR_EPS5;
+	      if (Field_sr_Slot_inst_get (insn) == 198)
+		return OPCODE_XSR_EPS6;
+	      if (Field_sr_Slot_inst_get (insn) == 199)
+		return OPCODE_XSR_EPS7;
+	      if (Field_sr_Slot_inst_get (insn) == 209)
+		return OPCODE_XSR_EXCSAVE1;
+	      if (Field_sr_Slot_inst_get (insn) == 210)
+		return OPCODE_XSR_EXCSAVE2;
+	      if (Field_sr_Slot_inst_get (insn) == 211)
+		return OPCODE_XSR_EXCSAVE3;
+	      if (Field_sr_Slot_inst_get (insn) == 212)
+		return OPCODE_XSR_EXCSAVE4;
+	      if (Field_sr_Slot_inst_get (insn) == 213)
+		return OPCODE_XSR_EXCSAVE5;
+	      if (Field_sr_Slot_inst_get (insn) == 214)
+		return OPCODE_XSR_EXCSAVE6;
+	      if (Field_sr_Slot_inst_get (insn) == 215)
+		return OPCODE_XSR_EXCSAVE7;
+	      if (Field_sr_Slot_inst_get (insn) == 224)
+		return OPCODE_XSR_CPENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 228)
+		return OPCODE_XSR_INTENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 230)
+		return OPCODE_XSR_PS;
+	      if (Field_sr_Slot_inst_get (insn) == 231)
+		return OPCODE_XSR_VECBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 232)
+		return OPCODE_XSR_EXCCAUSE;
+	      if (Field_sr_Slot_inst_get (insn) == 233)
+		return OPCODE_XSR_DEBUGCAUSE;
+	      if (Field_sr_Slot_inst_get (insn) == 234)
+		return OPCODE_XSR_CCOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 236)
+		return OPCODE_XSR_ICOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 237)
+		return OPCODE_XSR_ICOUNTLEVEL;
+	      if (Field_sr_Slot_inst_get (insn) == 238)
+		return OPCODE_XSR_EXCVADDR;
+	      if (Field_sr_Slot_inst_get (insn) == 240)
+		return OPCODE_XSR_CCOMPARE0;
+	      if (Field_sr_Slot_inst_get (insn) == 241)
+		return OPCODE_XSR_CCOMPARE1;
+	      if (Field_sr_Slot_inst_get (insn) == 242)
+		return OPCODE_XSR_CCOMPARE2;
+	      if (Field_sr_Slot_inst_get (insn) == 244)
+		return OPCODE_XSR_MISC0;
+	      if (Field_sr_Slot_inst_get (insn) == 245)
+		return OPCODE_XSR_MISC1;
+	      if (Field_sr_Slot_inst_get (insn) == 246)
+		return OPCODE_XSR_MISC2;
+	      if (Field_sr_Slot_inst_get (insn) == 247)
+		return OPCODE_XSR_MISC3;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 8)
+	    return OPCODE_SRC;
+	  if (Field_op2_Slot_inst_get (insn) == 9 &&
+	      Field_s_Slot_inst_get (insn) == 0)
+	    return OPCODE_SRL;
+	  if (Field_op2_Slot_inst_get (insn) == 10 &&
+	      Field_t_Slot_inst_get (insn) == 0)
+	    return OPCODE_SLL;
+	  if (Field_op2_Slot_inst_get (insn) == 11 &&
+	      Field_s_Slot_inst_get (insn) == 0)
+	    return OPCODE_SRA;
+	  if (Field_op2_Slot_inst_get (insn) == 12)
+	    return OPCODE_MUL16U;
+	  if (Field_op2_Slot_inst_get (insn) == 13)
+	    return OPCODE_MUL16S;
+	  if (Field_op2_Slot_inst_get (insn) == 15)
+	    {
+	      if (Field_r_Slot_inst_get (insn) == 14 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_RFDO;
+	      if (Field_r_Slot_inst_get (insn) == 14 &&
+		  Field_t_Slot_inst_get (insn) == 1)
+		return OPCODE_RFDD;
+	    }
+	}
+      if (Field_op1_Slot_inst_get (insn) == 2)
+	{
+	  if (Field_op2_Slot_inst_get (insn) == 6)
+	    return OPCODE_SALTU;
+	  if (Field_op2_Slot_inst_get (insn) == 7)
+	    return OPCODE_SALT;
+	  if (Field_op2_Slot_inst_get (insn) == 8)
+	    return OPCODE_MULL;
+	  if (Field_op2_Slot_inst_get (insn) == 10)
+	    return OPCODE_MULUH;
+	  if (Field_op2_Slot_inst_get (insn) == 11)
+	    return OPCODE_MULSH;
+	  if (Field_op2_Slot_inst_get (insn) == 12)
+	    return OPCODE_QUOU;
+	  if (Field_op2_Slot_inst_get (insn) == 13)
+	    return OPCODE_QUOS;
+	  if (Field_op2_Slot_inst_get (insn) == 14)
+	    return OPCODE_REMU;
+	  if (Field_op2_Slot_inst_get (insn) == 15)
+	    return OPCODE_REMS;
+	}
+      if (Field_op1_Slot_inst_get (insn) == 3)
+	{
+	  if (Field_op2_Slot_inst_get (insn) == 0)
+	    {
+	      if (Field_sr_Slot_inst_get (insn) == 3)
+		return OPCODE_RSR_SAR;
+	      if (Field_sr_Slot_inst_get (insn) == 5)
+		return OPCODE_RSR_LITBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 72)
+		return OPCODE_RSR_WINDOWBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 73)
+		return OPCODE_RSR_WINDOWSTART;
+	      if (Field_sr_Slot_inst_get (insn) == 95)
+		return OPCODE_RSR_ERACCESS;
+	      if (Field_sr_Slot_inst_get (insn) == 96)
+		return OPCODE_RSR_IBREAKENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 97)
+		return OPCODE_RSR_MEMCTL;
+	      if (Field_sr_Slot_inst_get (insn) == 104)
+		return OPCODE_RSR_DDR;
+	      if (Field_sr_Slot_inst_get (insn) == 128)
+		return OPCODE_RSR_IBREAKA0;
+	      if (Field_sr_Slot_inst_get (insn) == 129)
+		return OPCODE_RSR_IBREAKA1;
+	      if (Field_sr_Slot_inst_get (insn) == 144)
+		return OPCODE_RSR_DBREAKA0;
+	      if (Field_sr_Slot_inst_get (insn) == 145)
+		return OPCODE_RSR_DBREAKA1;
+	      if (Field_sr_Slot_inst_get (insn) == 160)
+		return OPCODE_RSR_DBREAKC0;
+	      if (Field_sr_Slot_inst_get (insn) == 161)
+		return OPCODE_RSR_DBREAKC1;
+	      if (Field_sr_Slot_inst_get (insn) == 176)
+		return OPCODE_RSR_CONFIGID0;
+	      if (Field_sr_Slot_inst_get (insn) == 177)
+		return OPCODE_RSR_EPC1;
+	      if (Field_sr_Slot_inst_get (insn) == 178)
+		return OPCODE_RSR_EPC2;
+	      if (Field_sr_Slot_inst_get (insn) == 179)
+		return OPCODE_RSR_EPC3;
+	      if (Field_sr_Slot_inst_get (insn) == 180)
+		return OPCODE_RSR_EPC4;
+	      if (Field_sr_Slot_inst_get (insn) == 181)
+		return OPCODE_RSR_EPC5;
+	      if (Field_sr_Slot_inst_get (insn) == 182)
+		return OPCODE_RSR_EPC6;
+	      if (Field_sr_Slot_inst_get (insn) == 183)
+		return OPCODE_RSR_EPC7;
+	      if (Field_sr_Slot_inst_get (insn) == 192)
+		return OPCODE_RSR_DEPC;
+	      if (Field_sr_Slot_inst_get (insn) == 194)
+		return OPCODE_RSR_EPS2;
+	      if (Field_sr_Slot_inst_get (insn) == 195)
+		return OPCODE_RSR_EPS3;
+	      if (Field_sr_Slot_inst_get (insn) == 196)
+		return OPCODE_RSR_EPS4;
+	      if (Field_sr_Slot_inst_get (insn) == 197)
+		return OPCODE_RSR_EPS5;
+	      if (Field_sr_Slot_inst_get (insn) == 198)
+		return OPCODE_RSR_EPS6;
+	      if (Field_sr_Slot_inst_get (insn) == 199)
+		return OPCODE_RSR_EPS7;
+	      if (Field_sr_Slot_inst_get (insn) == 208)
+		return OPCODE_RSR_CONFIGID1;
+	      if (Field_sr_Slot_inst_get (insn) == 209)
+		return OPCODE_RSR_EXCSAVE1;
+	      if (Field_sr_Slot_inst_get (insn) == 210)
+		return OPCODE_RSR_EXCSAVE2;
+	      if (Field_sr_Slot_inst_get (insn) == 211)
+		return OPCODE_RSR_EXCSAVE3;
+	      if (Field_sr_Slot_inst_get (insn) == 212)
+		return OPCODE_RSR_EXCSAVE4;
+	      if (Field_sr_Slot_inst_get (insn) == 213)
+		return OPCODE_RSR_EXCSAVE5;
+	      if (Field_sr_Slot_inst_get (insn) == 214)
+		return OPCODE_RSR_EXCSAVE6;
+	      if (Field_sr_Slot_inst_get (insn) == 215)
+		return OPCODE_RSR_EXCSAVE7;
+	      if (Field_sr_Slot_inst_get (insn) == 224)
+		return OPCODE_RSR_CPENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 226)
+		return OPCODE_RSR_INTERRUPT;
+	      if (Field_sr_Slot_inst_get (insn) == 228)
+		return OPCODE_RSR_INTENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 230)
+		return OPCODE_RSR_PS;
+	      if (Field_sr_Slot_inst_get (insn) == 231)
+		return OPCODE_RSR_VECBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 232)
+		return OPCODE_RSR_EXCCAUSE;
+	      if (Field_sr_Slot_inst_get (insn) == 233)
+		return OPCODE_RSR_DEBUGCAUSE;
+	      if (Field_sr_Slot_inst_get (insn) == 234)
+		return OPCODE_RSR_CCOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 235)
+		return OPCODE_RSR_PRID;
+	      if (Field_sr_Slot_inst_get (insn) == 236)
+		return OPCODE_RSR_ICOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 237)
+		return OPCODE_RSR_ICOUNTLEVEL;
+	      if (Field_sr_Slot_inst_get (insn) == 238)
+		return OPCODE_RSR_EXCVADDR;
+	      if (Field_sr_Slot_inst_get (insn) == 240)
+		return OPCODE_RSR_CCOMPARE0;
+	      if (Field_sr_Slot_inst_get (insn) == 241)
+		return OPCODE_RSR_CCOMPARE1;
+	      if (Field_sr_Slot_inst_get (insn) == 242)
+		return OPCODE_RSR_CCOMPARE2;
+	      if (Field_sr_Slot_inst_get (insn) == 244)
+		return OPCODE_RSR_MISC0;
+	      if (Field_sr_Slot_inst_get (insn) == 245)
+		return OPCODE_RSR_MISC1;
+	      if (Field_sr_Slot_inst_get (insn) == 246)
+		return OPCODE_RSR_MISC2;
+	      if (Field_sr_Slot_inst_get (insn) == 247)
+		return OPCODE_RSR_MISC3;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 1)
+	    {
+	      if (Field_sr_Slot_inst_get (insn) == 3)
+		return OPCODE_WSR_SAR;
+	      if (Field_sr_Slot_inst_get (insn) == 5)
+		return OPCODE_WSR_LITBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 72)
+		return OPCODE_WSR_WINDOWBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 73)
+		return OPCODE_WSR_WINDOWSTART;
+	      if (Field_sr_Slot_inst_get (insn) == 89)
+		return OPCODE_WSR_MMID;
+	      if (Field_sr_Slot_inst_get (insn) == 95)
+		return OPCODE_WSR_ERACCESS;
+	      if (Field_sr_Slot_inst_get (insn) == 96)
+		return OPCODE_WSR_IBREAKENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 97)
+		return OPCODE_WSR_MEMCTL;
+	      if (Field_sr_Slot_inst_get (insn) == 104)
+		return OPCODE_WSR_DDR;
+	      if (Field_sr_Slot_inst_get (insn) == 128)
+		return OPCODE_WSR_IBREAKA0;
+	      if (Field_sr_Slot_inst_get (insn) == 129)
+		return OPCODE_WSR_IBREAKA1;
+	      if (Field_sr_Slot_inst_get (insn) == 144)
+		return OPCODE_WSR_DBREAKA0;
+	      if (Field_sr_Slot_inst_get (insn) == 145)
+		return OPCODE_WSR_DBREAKA1;
+	      if (Field_sr_Slot_inst_get (insn) == 160)
+		return OPCODE_WSR_DBREAKC0;
+	      if (Field_sr_Slot_inst_get (insn) == 161)
+		return OPCODE_WSR_DBREAKC1;
+	      if (Field_sr_Slot_inst_get (insn) == 176)
+		return OPCODE_WSR_CONFIGID0;
+	      if (Field_sr_Slot_inst_get (insn) == 177)
+		return OPCODE_WSR_EPC1;
+	      if (Field_sr_Slot_inst_get (insn) == 178)
+		return OPCODE_WSR_EPC2;
+	      if (Field_sr_Slot_inst_get (insn) == 179)
+		return OPCODE_WSR_EPC3;
+	      if (Field_sr_Slot_inst_get (insn) == 180)
+		return OPCODE_WSR_EPC4;
+	      if (Field_sr_Slot_inst_get (insn) == 181)
+		return OPCODE_WSR_EPC5;
+	      if (Field_sr_Slot_inst_get (insn) == 182)
+		return OPCODE_WSR_EPC6;
+	      if (Field_sr_Slot_inst_get (insn) == 183)
+		return OPCODE_WSR_EPC7;
+	      if (Field_sr_Slot_inst_get (insn) == 192)
+		return OPCODE_WSR_DEPC;
+	      if (Field_sr_Slot_inst_get (insn) == 194)
+		return OPCODE_WSR_EPS2;
+	      if (Field_sr_Slot_inst_get (insn) == 195)
+		return OPCODE_WSR_EPS3;
+	      if (Field_sr_Slot_inst_get (insn) == 196)
+		return OPCODE_WSR_EPS4;
+	      if (Field_sr_Slot_inst_get (insn) == 197)
+		return OPCODE_WSR_EPS5;
+	      if (Field_sr_Slot_inst_get (insn) == 198)
+		return OPCODE_WSR_EPS6;
+	      if (Field_sr_Slot_inst_get (insn) == 199)
+		return OPCODE_WSR_EPS7;
+	      if (Field_sr_Slot_inst_get (insn) == 209)
+		return OPCODE_WSR_EXCSAVE1;
+	      if (Field_sr_Slot_inst_get (insn) == 210)
+		return OPCODE_WSR_EXCSAVE2;
+	      if (Field_sr_Slot_inst_get (insn) == 211)
+		return OPCODE_WSR_EXCSAVE3;
+	      if (Field_sr_Slot_inst_get (insn) == 212)
+		return OPCODE_WSR_EXCSAVE4;
+	      if (Field_sr_Slot_inst_get (insn) == 213)
+		return OPCODE_WSR_EXCSAVE5;
+	      if (Field_sr_Slot_inst_get (insn) == 214)
+		return OPCODE_WSR_EXCSAVE6;
+	      if (Field_sr_Slot_inst_get (insn) == 215)
+		return OPCODE_WSR_EXCSAVE7;
+	      if (Field_sr_Slot_inst_get (insn) == 224)
+		return OPCODE_WSR_CPENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 226)
+		return OPCODE_WSR_INTSET;
+	      if (Field_sr_Slot_inst_get (insn) == 227)
+		return OPCODE_WSR_INTCLEAR;
+	      if (Field_sr_Slot_inst_get (insn) == 228)
+		return OPCODE_WSR_INTENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 230)
+		return OPCODE_WSR_PS;
+	      if (Field_sr_Slot_inst_get (insn) == 231)
+		return OPCODE_WSR_VECBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 232)
+		return OPCODE_WSR_EXCCAUSE;
+	      if (Field_sr_Slot_inst_get (insn) == 233)
+		return OPCODE_WSR_DEBUGCAUSE;
+	      if (Field_sr_Slot_inst_get (insn) == 234)
+		return OPCODE_WSR_CCOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 236)
+		return OPCODE_WSR_ICOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 237)
+		return OPCODE_WSR_ICOUNTLEVEL;
+	      if (Field_sr_Slot_inst_get (insn) == 238)
+		return OPCODE_WSR_EXCVADDR;
+	      if (Field_sr_Slot_inst_get (insn) == 240)
+		return OPCODE_WSR_CCOMPARE0;
+	      if (Field_sr_Slot_inst_get (insn) == 241)
+		return OPCODE_WSR_CCOMPARE1;
+	      if (Field_sr_Slot_inst_get (insn) == 242)
+		return OPCODE_WSR_CCOMPARE2;
+	      if (Field_sr_Slot_inst_get (insn) == 244)
+		return OPCODE_WSR_MISC0;
+	      if (Field_sr_Slot_inst_get (insn) == 245)
+		return OPCODE_WSR_MISC1;
+	      if (Field_sr_Slot_inst_get (insn) == 246)
+		return OPCODE_WSR_MISC2;
+	      if (Field_sr_Slot_inst_get (insn) == 247)
+		return OPCODE_WSR_MISC3;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 2)
+	    return OPCODE_SEXT;
+	  if (Field_op2_Slot_inst_get (insn) == 3)
+	    return OPCODE_CLAMPS;
+	  if (Field_op2_Slot_inst_get (insn) == 4)
+	    return OPCODE_MIN;
+	  if (Field_op2_Slot_inst_get (insn) == 5)
+	    return OPCODE_MAX;
+	  if (Field_op2_Slot_inst_get (insn) == 6)
+	    return OPCODE_MINU;
+	  if (Field_op2_Slot_inst_get (insn) == 7)
+	    return OPCODE_MAXU;
+	  if (Field_op2_Slot_inst_get (insn) == 8)
+	    return OPCODE_MOVEQZ;
+	  if (Field_op2_Slot_inst_get (insn) == 9)
+	    return OPCODE_MOVNEZ;
+	  if (Field_op2_Slot_inst_get (insn) == 10)
+	    return OPCODE_MOVLTZ;
+	  if (Field_op2_Slot_inst_get (insn) == 11)
+	    return OPCODE_MOVGEZ;
+	  if (Field_op2_Slot_inst_get (insn) == 14)
+	    {
+	      if (Field_st_Slot_inst_get (insn) == 0)
+		return OPCODE_RUR_GPIO_OUT;
+	      if (Field_st_Slot_inst_get (insn) == 231)
+		return OPCODE_RUR_THREADPTR;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 15)
+	    {
+	      if (Field_sr_Slot_inst_get (insn) == 0)
+		return OPCODE_WUR_GPIO_OUT;
+	      if (Field_sr_Slot_inst_get (insn) == 231)
+		return OPCODE_WUR_THREADPTR;
+	    }
+	}
+      if ((Field_op1_Slot_inst_get (insn) == 4 ||
+	   Field_op1_Slot_inst_get (insn) == 5))
+	return OPCODE_EXTUI;
+      if (Field_op1_Slot_inst_get (insn) == 9)
+	{
+	  if (Field_op2_Slot_inst_get (insn) == 0)
+	    return OPCODE_L32E;
+	  if (Field_op2_Slot_inst_get (insn) == 4)
+	    return OPCODE_S32E;
+	  if (Field_op2_Slot_inst_get (insn) == 5)
+	    return OPCODE_S32NB;
+	}
+    }
+  if (Field_op0_Slot_inst_get (insn) == 1)
+    return OPCODE_L32R;
+  if (Field_op0_Slot_inst_get (insn) == 2)
+    {
+      if (Field_r_Slot_inst_get (insn) == 0)
+	return OPCODE_L8UI;
+      if (Field_r_Slot_inst_get (insn) == 1)
+	return OPCODE_L16UI;
+      if (Field_r_Slot_inst_get (insn) == 2)
+	return OPCODE_L32I;
+      if (Field_r_Slot_inst_get (insn) == 4)
+	return OPCODE_S8I;
+      if (Field_r_Slot_inst_get (insn) == 5)
+	return OPCODE_S16I;
+      if (Field_r_Slot_inst_get (insn) == 6)
+	return OPCODE_S32I;
+      if (Field_r_Slot_inst_get (insn) == 9)
+	return OPCODE_L16SI;
+      if (Field_r_Slot_inst_get (insn) == 10)
+	return OPCODE_MOVI;
+      if (Field_r_Slot_inst_get (insn) == 11)
+	return OPCODE_L32AI;
+      if (Field_r_Slot_inst_get (insn) == 12)
+	return OPCODE_ADDI;
+      if (Field_r_Slot_inst_get (insn) == 13)
+	return OPCODE_ADDMI;
+      if (Field_r_Slot_inst_get (insn) == 15)
+	return OPCODE_S32RI;
+    }
+  if (Field_op0_Slot_inst_get (insn) == 5)
+    {
+      if (Field_n_Slot_inst_get (insn) == 0)
+	return OPCODE_CALL0;
+      if (Field_n_Slot_inst_get (insn) == 1)
+	return OPCODE_CALL4;
+      if (Field_n_Slot_inst_get (insn) == 2)
+	return OPCODE_CALL8;
+      if (Field_n_Slot_inst_get (insn) == 3)
+	return OPCODE_CALL12;
+    }
+  if (Field_op0_Slot_inst_get (insn) == 6)
+    {
+      if (Field_n_Slot_inst_get (insn) == 0)
+	return OPCODE_J;
+      if (Field_n_Slot_inst_get (insn) == 1)
+	{
+	  if (Field_m_Slot_inst_get (insn) == 0)
+	    return OPCODE_BEQZ;
+	  if (Field_m_Slot_inst_get (insn) == 1)
+	    return OPCODE_BNEZ;
+	  if (Field_m_Slot_inst_get (insn) == 2)
+	    return OPCODE_BLTZ;
+	  if (Field_m_Slot_inst_get (insn) == 3)
+	    return OPCODE_BGEZ;
+	}
+      if (Field_n_Slot_inst_get (insn) == 2)
+	{
+	  if (Field_m_Slot_inst_get (insn) == 0)
+	    return OPCODE_BEQI;
+	  if (Field_m_Slot_inst_get (insn) == 1)
+	    return OPCODE_BNEI;
+	  if (Field_m_Slot_inst_get (insn) == 2)
+	    return OPCODE_BLTI;
+	  if (Field_m_Slot_inst_get (insn) == 3)
+	    return OPCODE_BGEI;
+	}
+      if (Field_n_Slot_inst_get (insn) == 3)
+	{
+	  if (Field_m_Slot_inst_get (insn) == 0)
+	    return OPCODE_ENTRY;
+	  if (Field_m_Slot_inst_get (insn) == 2)
+	    return OPCODE_BLTUI;
+	  if (Field_m_Slot_inst_get (insn) == 3)
+	    return OPCODE_BGEUI;
+	}
+    }
+  if (Field_op0_Slot_inst_get (insn) == 7)
+    {
+      if (Field_r_Slot_inst_get (insn) == 0)
+	return OPCODE_BNONE;
+      if (Field_r_Slot_inst_get (insn) == 1)
+	return OPCODE_BEQ;
+      if (Field_r_Slot_inst_get (insn) == 2)
+	return OPCODE_BLT;
+      if (Field_r_Slot_inst_get (insn) == 3)
+	return OPCODE_BLTU;
+      if (Field_r_Slot_inst_get (insn) == 4)
+	return OPCODE_BALL;
+      if (Field_r_Slot_inst_get (insn) == 5)
+	return OPCODE_BBC;
+      if ((Field_r_Slot_inst_get (insn) == 6 ||
+	   Field_r_Slot_inst_get (insn) == 7))
+	return OPCODE_BBCI;
+      if (Field_r_Slot_inst_get (insn) == 8)
+	return OPCODE_BANY;
+      if (Field_r_Slot_inst_get (insn) == 9)
+	return OPCODE_BNE;
+      if (Field_r_Slot_inst_get (insn) == 10)
+	return OPCODE_BGE;
+      if (Field_r_Slot_inst_get (insn) == 11)
+	return OPCODE_BGEU;
+      if (Field_r_Slot_inst_get (insn) == 12)
+	return OPCODE_BNALL;
+      if (Field_r_Slot_inst_get (insn) == 13)
+	return OPCODE_BBS;
+      if ((Field_r_Slot_inst_get (insn) == 14 ||
+	   Field_r_Slot_inst_get (insn) == 15))
+	return OPCODE_BBSI;
+    }
+  return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_inst16b_decode (const xtensa_insnbuf insn)
+{
+  if (Field_op0_Slot_inst16b_get (insn) == 12)
+    {
+      if (Field_i_Slot_inst16b_get (insn) == 0)
+	return OPCODE_MOVI_N;
+      if (Field_i_Slot_inst16b_get (insn) == 1)
+	{
+	  if (Field_z_Slot_inst16b_get (insn) == 0)
+	    return OPCODE_BEQZ_N;
+	  if (Field_z_Slot_inst16b_get (insn) == 1)
+	    return OPCODE_BNEZ_N;
+	}
+    }
+  if (Field_op0_Slot_inst16b_get (insn) == 13)
+    {
+      if (Field_r_Slot_inst16b_get (insn) == 0)
+	return OPCODE_MOV_N;
+      if (Field_r_Slot_inst16b_get (insn) == 15)
+	{
+	  if (Field_t_Slot_inst16b_get (insn) == 0)
+	    return OPCODE_RET_N;
+	  if (Field_t_Slot_inst16b_get (insn) == 1)
+	    return OPCODE_RETW_N;
+	  if (Field_t_Slot_inst16b_get (insn) == 2)
+	    return OPCODE_BREAK_N;
+	  if (Field_t_Slot_inst16b_get (insn) == 3 &&
+	      Field_s_Slot_inst16b_get (insn) == 0)
+	    return OPCODE_NOP_N;
+	  if (Field_t_Slot_inst16b_get (insn) == 6 &&
+	      Field_s_Slot_inst16b_get (insn) == 0)
+	    return OPCODE_ILL_N;
+	}
+    }
+  return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_inst16a_decode (const xtensa_insnbuf insn)
+{
+  if (Field_op0_Slot_inst16a_get (insn) == 8)
+    return OPCODE_L32I_N;
+  if (Field_op0_Slot_inst16a_get (insn) == 9)
+    return OPCODE_S32I_N;
+  if (Field_op0_Slot_inst16a_get (insn) == 10)
+    return OPCODE_ADD_N;
+  if (Field_op0_Slot_inst16a_get (insn) == 11)
+    return OPCODE_ADDI_N;
+  return XTENSA_UNDEFINED;
+}
+
+\f
+/* Instruction slots.  */
+
+static void
+Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
+			    xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = (insn[0] & 0xffffff);
+}
+
+static void
+Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
+			    const xtensa_insnbuf slotbuf)
+{
+  insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
+}
+
+static void
+Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
+				xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = (insn[0] & 0xffff);
+}
+
+static void
+Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
+				const xtensa_insnbuf slotbuf)
+{
+  insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
+}
+
+static void
+Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
+				xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = (insn[0] & 0xffff);
+}
+
+static void
+Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
+				const xtensa_insnbuf slotbuf)
+{
+  insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
+}
+
+static xtensa_get_field_fn
+Slot_inst_get_field_fns[] = {
+  Field_t_Slot_inst_get,
+  Field_bbi4_Slot_inst_get,
+  Field_bbi_Slot_inst_get,
+  Field_imm12_Slot_inst_get,
+  Field_imm8_Slot_inst_get,
+  Field_s_Slot_inst_get,
+  Field_imm12b_Slot_inst_get,
+  Field_imm16_Slot_inst_get,
+  Field_m_Slot_inst_get,
+  Field_n_Slot_inst_get,
+  Field_offset_Slot_inst_get,
+  Field_op0_Slot_inst_get,
+  Field_op1_Slot_inst_get,
+  Field_op2_Slot_inst_get,
+  Field_r_Slot_inst_get,
+  Field_sa4_Slot_inst_get,
+  Field_sae4_Slot_inst_get,
+  Field_sae_Slot_inst_get,
+  Field_sal_Slot_inst_get,
+  Field_sargt_Slot_inst_get,
+  Field_sas4_Slot_inst_get,
+  Field_sas_Slot_inst_get,
+  Field_sr_Slot_inst_get,
+  Field_st_Slot_inst_get,
+  Field_thi3_Slot_inst_get,
+  Field_imm4_Slot_inst_get,
+  Field_mn_Slot_inst_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_xt_wbr15_imm_Slot_inst_get,
+  Field_xt_wbr18_imm_Slot_inst_get,
+  Field_fld_wr_mask_gpio_out_mask_Slot_inst_get,
+  Field_fld_wr_mask_gpio_out_value_Slot_inst_get,
+  Field_fld_set_bit_gpio_out_mask_Slot_inst_get,
+  Field_fld_inst_3_0_Slot_inst_get,
+  Field_fld_inst_23_12_Slot_inst_get,
+  Field_fld_clr_bit_gpio_out_mask_Slot_inst_get,
+  Field_fld_inst_23_8_Slot_inst_get,
+  Field_fld_get_gpio_in_i_Slot_inst_get,
+  Implicit_Field_ar0_get,
+  Implicit_Field_ar4_get,
+  Implicit_Field_ar8_get,
+  Implicit_Field_ar12_get
+};
+
+static xtensa_set_field_fn
+Slot_inst_set_field_fns[] = {
+  Field_t_Slot_inst_set,
+  Field_bbi4_Slot_inst_set,
+  Field_bbi_Slot_inst_set,
+  Field_imm12_Slot_inst_set,
+  Field_imm8_Slot_inst_set,
+  Field_s_Slot_inst_set,
+  Field_imm12b_Slot_inst_set,
+  Field_imm16_Slot_inst_set,
+  Field_m_Slot_inst_set,
+  Field_n_Slot_inst_set,
+  Field_offset_Slot_inst_set,
+  Field_op0_Slot_inst_set,
+  Field_op1_Slot_inst_set,
+  Field_op2_Slot_inst_set,
+  Field_r_Slot_inst_set,
+  Field_sa4_Slot_inst_set,
+  Field_sae4_Slot_inst_set,
+  Field_sae_Slot_inst_set,
+  Field_sal_Slot_inst_set,
+  Field_sargt_Slot_inst_set,
+  Field_sas4_Slot_inst_set,
+  Field_sas_Slot_inst_set,
+  Field_sr_Slot_inst_set,
+  Field_st_Slot_inst_set,
+  Field_thi3_Slot_inst_set,
+  Field_imm4_Slot_inst_set,
+  Field_mn_Slot_inst_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_xt_wbr15_imm_Slot_inst_set,
+  Field_xt_wbr18_imm_Slot_inst_set,
+  Field_fld_wr_mask_gpio_out_mask_Slot_inst_set,
+  Field_fld_wr_mask_gpio_out_value_Slot_inst_set,
+  Field_fld_set_bit_gpio_out_mask_Slot_inst_set,
+  Field_fld_inst_3_0_Slot_inst_set,
+  Field_fld_inst_23_12_Slot_inst_set,
+  Field_fld_clr_bit_gpio_out_mask_Slot_inst_set,
+  Field_fld_inst_23_8_Slot_inst_set,
+  Field_fld_get_gpio_in_i_Slot_inst_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_inst16a_get_field_fns[] = {
+  Field_t_Slot_inst16a_get,
+  0,
+  0,
+  0,
+  0,
+  Field_s_Slot_inst16a_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_op0_Slot_inst16a_get,
+  0,
+  0,
+  Field_r_Slot_inst16a_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_sr_Slot_inst16a_get,
+  Field_st_Slot_inst16a_get,
+  0,
+  Field_imm4_Slot_inst16a_get,
+  0,
+  Field_i_Slot_inst16a_get,
+  Field_imm6lo_Slot_inst16a_get,
+  Field_imm6hi_Slot_inst16a_get,
+  Field_imm7lo_Slot_inst16a_get,
+  Field_imm7hi_Slot_inst16a_get,
+  Field_z_Slot_inst16a_get,
+  Field_imm6_Slot_inst16a_get,
+  Field_imm7_Slot_inst16a_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Implicit_Field_ar0_get,
+  Implicit_Field_ar4_get,
+  Implicit_Field_ar8_get,
+  Implicit_Field_ar12_get
+};
+
+static xtensa_set_field_fn
+Slot_inst16a_set_field_fns[] = {
+  Field_t_Slot_inst16a_set,
+  0,
+  0,
+  0,
+  0,
+  Field_s_Slot_inst16a_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_op0_Slot_inst16a_set,
+  0,
+  0,
+  Field_r_Slot_inst16a_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_sr_Slot_inst16a_set,
+  Field_st_Slot_inst16a_set,
+  0,
+  Field_imm4_Slot_inst16a_set,
+  0,
+  Field_i_Slot_inst16a_set,
+  Field_imm6lo_Slot_inst16a_set,
+  Field_imm6hi_Slot_inst16a_set,
+  Field_imm7lo_Slot_inst16a_set,
+  Field_imm7hi_Slot_inst16a_set,
+  Field_z_Slot_inst16a_set,
+  Field_imm6_Slot_inst16a_set,
+  Field_imm7_Slot_inst16a_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_inst16b_get_field_fns[] = {
+  Field_t_Slot_inst16b_get,
+  0,
+  0,
+  0,
+  0,
+  Field_s_Slot_inst16b_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_op0_Slot_inst16b_get,
+  0,
+  0,
+  Field_r_Slot_inst16b_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_sr_Slot_inst16b_get,
+  Field_st_Slot_inst16b_get,
+  0,
+  Field_imm4_Slot_inst16b_get,
+  0,
+  Field_i_Slot_inst16b_get,
+  Field_imm6lo_Slot_inst16b_get,
+  Field_imm6hi_Slot_inst16b_get,
+  Field_imm7lo_Slot_inst16b_get,
+  Field_imm7hi_Slot_inst16b_get,
+  Field_z_Slot_inst16b_get,
+  Field_imm6_Slot_inst16b_get,
+  Field_imm7_Slot_inst16b_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Implicit_Field_ar0_get,
+  Implicit_Field_ar4_get,
+  Implicit_Field_ar8_get,
+  Implicit_Field_ar12_get
+};
+
+static xtensa_set_field_fn
+Slot_inst16b_set_field_fns[] = {
+  Field_t_Slot_inst16b_set,
+  0,
+  0,
+  0,
+  0,
+  Field_s_Slot_inst16b_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_op0_Slot_inst16b_set,
+  0,
+  0,
+  Field_r_Slot_inst16b_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_sr_Slot_inst16b_set,
+  Field_st_Slot_inst16b_set,
+  0,
+  Field_imm4_Slot_inst16b_set,
+  0,
+  Field_i_Slot_inst16b_set,
+  Field_imm6lo_Slot_inst16b_set,
+  Field_imm6hi_Slot_inst16b_set,
+  Field_imm7lo_Slot_inst16b_set,
+  Field_imm7hi_Slot_inst16b_set,
+  Field_z_Slot_inst16b_set,
+  Field_imm6_Slot_inst16b_set,
+  Field_imm7_Slot_inst16b_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set
+};
+
+static xtensa_slot_internal slots[] = {
+  { "Inst", "x24", 0,
+    Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
+    Slot_inst_get_field_fns, Slot_inst_set_field_fns,
+    Slot_inst_decode, "nop" },
+  { "Inst16a", "x16a", 0,
+    Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
+    Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
+    Slot_inst16a_decode, "" },
+  { "Inst16b", "x16b", 0,
+    Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
+    Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
+    Slot_inst16b_decode, "nop.n" }
+};
+
+\f
+/* Instruction formats.  */
+
+static void
+Format_x24_encode (xtensa_insnbuf insn)
+{
+  insn[0] = 0;
+}
+
+static void
+Format_x16a_encode (xtensa_insnbuf insn)
+{
+  insn[0] = 0x8;
+}
+
+static void
+Format_x16b_encode (xtensa_insnbuf insn)
+{
+  insn[0] = 0xc;
+}
+
+static int Format_x24_slots[] = { 0 };
+
+static int Format_x16a_slots[] = { 1 };
+
+static int Format_x16b_slots[] = { 2 };
+
+static xtensa_format_internal formats[] = {
+  { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
+  { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
+  { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
+};
+
+
+static int
+format_decoder (const xtensa_insnbuf insn)
+{
+  if ((insn[0] & 0x8) == 0)
+    return 0; /* x24 */
+  if ((insn[0] & 0xc) == 0x8)
+    return 1; /* x16a */
+  if ((insn[0] & 0xe) == 0xc)
+    return 2; /* x16b */
+  return -1;
+}
+
+static int length_table[256] = {
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  -1
+};
+
+static int
+length_decoder (const unsigned char *insn)
+{
+  int l = insn[0];
+  return length_table[l];
+}
+
+\f
+/* Top-level ISA structure.  */
+
+xtensa_isa_internal xtensa_esp32s2_modules = {
+  0 /* little-endian */,
+  3 /* insn_size */, 0,
+  3, formats, format_decoder, length_decoder,
+  3, slots,
+  49 /* num_fields */,
+  88, operands,
+  269, iclasses,
+  324, opcodes, 0,
+  1, regfiles,
+  NUM_STATES, states, 0,
+  NUM_SYSREGS, sysregs, 0,
+  { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
+  6, interfaces, 0,
+  0, funcUnits, 0
+};
diff --git a/bfd/xtensa-esp32s3-modules.c b/bfd/xtensa-esp32s3-modules.c
new file mode 100644
index 00000000000..e491030deda
--- /dev/null
+++ b/bfd/xtensa-esp32s3-modules.c
@@ -0,0 +1,43674 @@
+/* Xtensa configuration-specific ISA information.
+
+   Customer ID=15128; Build=0x90f1f; Copyright (c) 2003-2021 Tensilica Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+#include "ansidecl.h"
+#include <xtensa-isa.h>
+#include "xtensa-isa-internal.h"
+
+\f
+/* Sysregs.  */
+
+static xtensa_sysreg_internal sysregs[] = {
+  { "LBEG", 0, 0 },
+  { "LEND", 1, 0 },
+  { "LCOUNT", 2, 0 },
+  { "BR", 4, 0 },
+  { "ACCLO", 16, 0 },
+  { "ACCHI", 17, 0 },
+  { "M0", 32, 0 },
+  { "M1", 33, 0 },
+  { "M2", 34, 0 },
+  { "M3", 35, 0 },
+  { "MMID", 89, 0 },
+  { "DDR", 104, 0 },
+  { "CONFIGID0", 176, 0 },
+  { "CONFIGID1", 208, 0 },
+  { "INTERRUPT", 226, 0 },
+  { "INTCLEAR", 227, 0 },
+  { "CCOUNT", 234, 0 },
+  { "PRID", 235, 0 },
+  { "ICOUNT", 236, 0 },
+  { "CCOMPARE0", 240, 0 },
+  { "CCOMPARE1", 241, 0 },
+  { "CCOMPARE2", 242, 0 },
+  { "VECBASE", 231, 0 },
+  { "EPC1", 177, 0 },
+  { "EPC2", 178, 0 },
+  { "EPC3", 179, 0 },
+  { "EPC4", 180, 0 },
+  { "EPC5", 181, 0 },
+  { "EPC6", 182, 0 },
+  { "EPC7", 183, 0 },
+  { "EXCSAVE1", 209, 0 },
+  { "EXCSAVE2", 210, 0 },
+  { "EXCSAVE3", 211, 0 },
+  { "EXCSAVE4", 212, 0 },
+  { "EXCSAVE5", 213, 0 },
+  { "EXCSAVE6", 214, 0 },
+  { "EXCSAVE7", 215, 0 },
+  { "EPS2", 194, 0 },
+  { "EPS3", 195, 0 },
+  { "EPS4", 196, 0 },
+  { "EPS5", 197, 0 },
+  { "EPS6", 198, 0 },
+  { "EPS7", 199, 0 },
+  { "EXCCAUSE", 232, 0 },
+  { "DEPC", 192, 0 },
+  { "EXCVADDR", 238, 0 },
+  { "WINDOWBASE", 72, 0 },
+  { "WINDOWSTART", 73, 0 },
+  { "MEMCTL", 97, 0 },
+  { "SAR", 3, 0 },
+  { "PS", 230, 0 },
+  { "MISC0", 244, 0 },
+  { "MISC1", 245, 0 },
+  { "MISC2", 246, 0 },
+  { "MISC3", 247, 0 },
+  { "INTENABLE", 228, 0 },
+  { "DBREAKA0", 144, 0 },
+  { "DBREAKC0", 160, 0 },
+  { "DBREAKA1", 145, 0 },
+  { "DBREAKC1", 161, 0 },
+  { "IBREAKA0", 128, 0 },
+  { "IBREAKA1", 129, 0 },
+  { "IBREAKENABLE", 96, 0 },
+  { "ICOUNTLEVEL", 237, 0 },
+  { "DEBUGCAUSE", 233, 0 },
+  { "CPENABLE", 224, 0 },
+  { "SCOMPARE1", 12, 0 },
+  { "ATOMCTL", 99, 0 },
+  { "THREADPTR", 231, 1 },
+  { "FCR", 232, 1 },
+  { "FSR", 233, 1 },
+  { "ACCX_0", 0, 1 },
+  { "ACCX_1", 1, 1 },
+  { "QACC_H_0", 2, 1 },
+  { "QACC_H_1", 3, 1 },
+  { "QACC_H_2", 4, 1 },
+  { "QACC_H_3", 5, 1 },
+  { "QACC_H_4", 6, 1 },
+  { "QACC_L_0", 7, 1 },
+  { "QACC_L_1", 8, 1 },
+  { "QACC_L_2", 9, 1 },
+  { "QACC_L_3", 10, 1 },
+  { "QACC_L_4", 11, 1 },
+  { "GPIO_OUT", 12, 1 },
+  { "SAR_BYTE", 13, 1 },
+  { "FFT_BIT_WIDTH", 14, 1 },
+  { "UA_STATE_0", 15, 1 },
+  { "UA_STATE_1", 16, 1 },
+  { "UA_STATE_2", 17, 1 },
+  { "UA_STATE_3", 18, 1 }
+};
+
+#define NUM_SYSREGS 90
+#define MAX_SPECIAL_REG 247
+#define MAX_USER_REG 233
+
+\f
+/* Processor states.  */
+
+static xtensa_state_internal states[] = {
+  { "LCOUNT", 32, 0 },
+  { "PC", 32, 0 },
+  { "ICOUNT", 32, 0 },
+  { "DDR", 32, 0 },
+  { "INTERRUPT", 32, 0 },
+  { "CCOUNT", 32, 0 },
+  { "XTSYNC", 1, 0 },
+  { "VECBASE", 22, 0 },
+  { "EPC1", 32, 0 },
+  { "EPC2", 32, 0 },
+  { "EPC3", 32, 0 },
+  { "EPC4", 32, 0 },
+  { "EPC5", 32, 0 },
+  { "EPC6", 32, 0 },
+  { "EPC7", 32, 0 },
+  { "EXCSAVE1", 32, 0 },
+  { "EXCSAVE2", 32, 0 },
+  { "EXCSAVE3", 32, 0 },
+  { "EXCSAVE4", 32, 0 },
+  { "EXCSAVE5", 32, 0 },
+  { "EXCSAVE6", 32, 0 },
+  { "EXCSAVE7", 32, 0 },
+  { "EPS2", 13, 0 },
+  { "EPS3", 13, 0 },
+  { "EPS4", 13, 0 },
+  { "EPS5", 13, 0 },
+  { "EPS6", 13, 0 },
+  { "EPS7", 13, 0 },
+  { "EXCCAUSE", 6, 0 },
+  { "PSINTLEVEL", 4, 0 },
+  { "PSUM", 1, 0 },
+  { "PSWOE", 1, 0 },
+  { "PSEXCM", 1, 0 },
+  { "DEPC", 32, 0 },
+  { "EXCVADDR", 32, 0 },
+  { "WindowBase", 4, 0 },
+  { "WindowStart", 16, 0 },
+  { "PSCALLINC", 2, 0 },
+  { "PSOWB", 4, 0 },
+  { "LBEG", 32, 0 },
+  { "LEND", 32, 0 },
+  { "MEMCTL", 1, 0 },
+  { "SAR", 6, 0 },
+  { "THREADPTR", 32, 0 },
+  { "MISC0", 32, 0 },
+  { "MISC1", 32, 0 },
+  { "MISC2", 32, 0 },
+  { "MISC3", 32, 0 },
+  { "ACC", 40, 0 },
+  { "InOCDMode", 1, 0 },
+  { "INTENABLE", 32, 0 },
+  { "DBREAKA0", 32, 0 },
+  { "DBREAKC0", 8, 0 },
+  { "DBREAKA1", 32, 0 },
+  { "DBREAKC1", 8, 0 },
+  { "IBREAKA0", 32, 0 },
+  { "IBREAKA1", 32, 0 },
+  { "IBREAKENABLE", 2, 0 },
+  { "ICOUNTLEVEL", 4, 0 },
+  { "DEBUGCAUSE", 6, 0 },
+  { "DBNUM", 4, 0 },
+  { "CCOMPARE0", 32, 0 },
+  { "CCOMPARE1", 32, 0 },
+  { "CCOMPARE2", 32, 0 },
+  { "CPENABLE", 8, 0 },
+  { "SCOMPARE1", 32, 0 },
+  { "ATOMCTL", 6, 0 },
+  { "ERI_RAW_INTERLOCK", 1, 0 },
+  { "RoundMode", 2, 0 },
+  { "InvalidEnable", 1, 0 },
+  { "DivZeroEnable", 1, 0 },
+  { "OverflowEnable", 1, 0 },
+  { "UnderflowEnable", 1, 0 },
+  { "InexactEnable", 1, 0 },
+  { "InvalidFlag", 1, XTENSA_STATE_IS_SHARED_OR },
+  { "DivZeroFlag", 1, XTENSA_STATE_IS_SHARED_OR },
+  { "OverflowFlag", 1, XTENSA_STATE_IS_SHARED_OR },
+  { "UnderflowFlag", 1, XTENSA_STATE_IS_SHARED_OR },
+  { "InexactFlag", 1, XTENSA_STATE_IS_SHARED_OR },
+  { "FPreserved20", 20, 0 },
+  { "FPreserved20a", 20, 0 },
+  { "FPreserved5", 5, 0 },
+  { "FPreserved7", 7, 0 },
+  { "ACCX", 40, 0 },
+  { "QACC_H", 160, 0 },
+  { "QACC_L", 160, 0 },
+  { "GPIO_OUT", 8, XTENSA_STATE_IS_EXPORTED },
+  { "SAR_BYTE", 4, 0 },
+  { "FFT_BIT_WIDTH", 4, 0 },
+  { "UA_STATE", 128, 0 }
+};
+
+#define NUM_STATES 90
+
+enum xtensa_state_id {
+  STATE_LCOUNT,
+  STATE_PC,
+  STATE_ICOUNT,
+  STATE_DDR,
+  STATE_INTERRUPT,
+  STATE_CCOUNT,
+  STATE_XTSYNC,
+  STATE_VECBASE,
+  STATE_EPC1,
+  STATE_EPC2,
+  STATE_EPC3,
+  STATE_EPC4,
+  STATE_EPC5,
+  STATE_EPC6,
+  STATE_EPC7,
+  STATE_EXCSAVE1,
+  STATE_EXCSAVE2,
+  STATE_EXCSAVE3,
+  STATE_EXCSAVE4,
+  STATE_EXCSAVE5,
+  STATE_EXCSAVE6,
+  STATE_EXCSAVE7,
+  STATE_EPS2,
+  STATE_EPS3,
+  STATE_EPS4,
+  STATE_EPS5,
+  STATE_EPS6,
+  STATE_EPS7,
+  STATE_EXCCAUSE,
+  STATE_PSINTLEVEL,
+  STATE_PSUM,
+  STATE_PSWOE,
+  STATE_PSEXCM,
+  STATE_DEPC,
+  STATE_EXCVADDR,
+  STATE_WindowBase,
+  STATE_WindowStart,
+  STATE_PSCALLINC,
+  STATE_PSOWB,
+  STATE_LBEG,
+  STATE_LEND,
+  STATE_MEMCTL,
+  STATE_SAR,
+  STATE_THREADPTR,
+  STATE_MISC0,
+  STATE_MISC1,
+  STATE_MISC2,
+  STATE_MISC3,
+  STATE_ACC,
+  STATE_InOCDMode,
+  STATE_INTENABLE,
+  STATE_DBREAKA0,
+  STATE_DBREAKC0,
+  STATE_DBREAKA1,
+  STATE_DBREAKC1,
+  STATE_IBREAKA0,
+  STATE_IBREAKA1,
+  STATE_IBREAKENABLE,
+  STATE_ICOUNTLEVEL,
+  STATE_DEBUGCAUSE,
+  STATE_DBNUM,
+  STATE_CCOMPARE0,
+  STATE_CCOMPARE1,
+  STATE_CCOMPARE2,
+  STATE_CPENABLE,
+  STATE_SCOMPARE1,
+  STATE_ATOMCTL,
+  STATE_ERI_RAW_INTERLOCK,
+  STATE_RoundMode,
+  STATE_InvalidEnable,
+  STATE_DivZeroEnable,
+  STATE_OverflowEnable,
+  STATE_UnderflowEnable,
+  STATE_InexactEnable,
+  STATE_InvalidFlag,
+  STATE_DivZeroFlag,
+  STATE_OverflowFlag,
+  STATE_UnderflowFlag,
+  STATE_InexactFlag,
+  STATE_FPreserved20,
+  STATE_FPreserved20a,
+  STATE_FPreserved5,
+  STATE_FPreserved7,
+  STATE_ACCX,
+  STATE_QACC_H,
+  STATE_QACC_L,
+  STATE_GPIO_OUT,
+  STATE_SAR_BYTE,
+  STATE_FFT_BIT_WIDTH,
+  STATE_UA_STATE
+};
+
+\f
+/* Field definitions.  */
+
+static unsigned
+Field_r_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+  return tie_t;
+}
+
+static void
+Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
+  return tie_t;
+}
+
+static void
+Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
+}
+
+static unsigned
+Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+  return tie_t;
+}
+
+static void
+Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_t_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_s_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_n_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+  return tie_t;
+}
+
+static void
+Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_m_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+  return tie_t;
+}
+
+static void
+Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+  tie_t = (val << 24) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_st_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+  tie_t = (val << 24) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+  return tie_t;
+}
+
+static void
+Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+  return tie_t;
+}
+
+static void
+Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+  return tie_t;
+}
+
+static void
+Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_w_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
+  return tie_t;
+}
+
+static void
+Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
+}
+
+static unsigned
+Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+  return tie_t;
+}
+
+static void
+Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_fld_inst_23_22_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_23_22_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22);
+}
+
+static unsigned
+Field_fld_inst_19_16_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_19_16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_fld_inst_14_12_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_14_12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
+}
+
+static unsigned
+Field_fld_inst_3_0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_3_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_fld_inst_9_6_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_9_6_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6);
+}
+
+static unsigned
+Field_fld_inst_4_0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_4_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 27) >> 27;
+  insn[0] = (insn[0] & ~0x1f) | (tie_t << 0);
+}
+
+static unsigned
+Field_fld_inst_23_12_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_23_12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 20) >> 20;
+  insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_fld_inst_23_8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_23_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 16) >> 16;
+  insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_inst_23_23_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_23_23_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_fld_inst_14_8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_14_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 25) >> 25;
+  insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_inst_11_8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_11_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_inst_21_15_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 7) | ((insn[0] << 10) >> 25);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_21_15_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 25) >> 25;
+  insn[0] = (insn[0] & ~0x3f8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_fld_inst_9_8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_9_8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_inst_11_0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_11_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 20) >> 20;
+  insn[0] = (insn[0] & ~0xfff) | (tie_t << 0);
+}
+
+static unsigned
+Field_fld_inst_23_0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 24) | ((insn[0] << 8) >> 8);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_23_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 8) >> 8;
+  insn[0] = (insn[0] & ~0xffffff) | (tie_t << 0);
+}
+
+static unsigned
+Field_fld_inst_14_0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 15) | ((insn[0] << 17) >> 17);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_14_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 17) >> 17;
+  insn[0] = (insn[0] & ~0x7fff) | (tie_t << 0);
+}
+
+static unsigned
+Field_fld_inst_13_13_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_13_13_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x2000) | (tie_t << 13);
+}
+
+static unsigned
+Field_fld_inst_7_0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_7_0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 24) >> 24;
+  insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
+}
+
+static unsigned
+Field_fld_inst_7_6_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_7_6_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_fld_inst_23_15_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 9) | ((insn[0] << 8) >> 23);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_23_15_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 23) >> 23;
+  insn[0] = (insn[0] & ~0xff8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_fld_inst_23_21_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_23_21_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21);
+}
+
+static unsigned
+Field_fld_inst_7_5_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_7_5_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_fld_inst_14_11_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 17) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_14_11_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0x7800) | (tie_t << 11);
+}
+
+static unsigned
+Field_fld_inst_13_12_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_13_12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
+}
+
+static unsigned
+Field_fld_inst_5_5_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_5_5_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x20) | (tie_t << 5);
+}
+
+static unsigned
+Field_fld_inst_11_7_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_11_7_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 27) >> 27;
+  insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
+}
+
+static unsigned
+Field_fld_inst_14_7_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_14_7_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 24) >> 24;
+  insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7);
+}
+
+static unsigned
+Field_fld_inst_9_9_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_inst_9_9_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x200) | (tie_t << 9);
+}
+
+static unsigned
+Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+  return tie_t;
+}
+
+static void
+Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+  return tie_t;
+}
+
+static void
+Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+  return tie_t;
+}
+
+static void
+Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+  return tie_t;
+}
+
+static void
+Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_slot_format_32_0_28_4_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 25) | ((insn[0] << 3) >> 7);
+  return tie_t;
+}
+
+static void
+Field_fld_slot_format_32_0_28_4_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 7) >> 7;
+  insn[0] = (insn[0] & ~0x1ffffff0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_slot_format_32_0_3_0_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_slot_format_32_0_3_0_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_fld_slot_format_32_0_28_24_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 5) | ((insn[0] << 3) >> 27);
+  return tie_t;
+}
+
+static void
+Field_fld_slot_format_32_0_28_24_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 27) >> 27;
+  insn[0] = (insn[0] & ~0x1f000000) | (tie_t << 24);
+}
+
+static unsigned
+Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 6) | ((insn[0] << 3) >> 26);
+  return tie_t;
+}
+
+static void
+Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 26) >> 26;
+  insn[0] = (insn[0] & ~0x1f800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_fld_slot_format_32_0_7_5_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_slot_format_32_0_7_5_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_fld_slot_format_32_0_28_22_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 7) | ((insn[0] << 3) >> 25);
+  return tie_t;
+}
+
+static void
+Field_fld_slot_format_32_0_28_22_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 25) >> 25;
+  insn[0] = (insn[0] & ~0x1fc00000) | (tie_t << 22);
+}
+
+static unsigned
+Field_fld_slot_format_32_0_10_4_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 7) | ((insn[0] << 21) >> 25);
+  return tie_t;
+}
+
+static void
+Field_fld_slot_format_32_0_10_4_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 25) >> 25;
+  insn[0] = (insn[0] & ~0x7f0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_slot_format_32_0_19_17_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_slot_format_32_0_19_17_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
+}
+
+static unsigned
+Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_slot_format_32_0_28_20_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 9) | ((insn[0] << 3) >> 23);
+  return tie_t;
+}
+
+static void
+Field_fld_slot_format_32_0_28_20_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 23) >> 23;
+  insn[0] = (insn[0] & ~0x1ff00000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_slot_format_32_0_10_6_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 5) | ((insn[0] << 21) >> 27);
+  return tie_t;
+}
+
+static void
+Field_fld_slot_format_32_0_10_6_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 27) >> 27;
+  insn[0] = (insn[0] & ~0x7c0) | (tie_t << 6);
+}
+
+static unsigned
+Field_fld_slot_format_32_0_7_6_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+  return tie_t;
+}
+
+static void
+Field_fld_slot_format_32_0_7_6_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_fld_slot_format_32_0_28_25_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 3) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_slot_format_32_0_28_25_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0x1e000000) | (tie_t << 25);
+}
+
+static unsigned
+Field_fld_slot_format_32_0_10_8_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_slot_format_32_0_10_8_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_slot_format_32_0_10_9_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
+  return tie_t;
+}
+
+static void
+Field_fld_slot_format_32_0_10_9_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
+}
+
+static unsigned
+Field_fld_slot_format_32_0_13_11_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_slot_format_32_0_13_11_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_fld_slot_format_32_0_13_13_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_slot_format_32_0_13_13_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x2000) | (tie_t << 13);
+}
+
+static unsigned
+Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+  return tie_t;
+}
+
+static void
+Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+  tie_t = (val << 27) >> 31;
+  insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
+  return tie_t;
+}
+
+static void
+Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 20) >> 20;
+  insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
+  return tie_t;
+}
+
+static void
+Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 24) >> 24;
+  insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
+  return tie_t;
+}
+
+static void
+Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 24) >> 24;
+  insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
+  tie_t = (val << 20) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
+  return tie_t;
+}
+
+static void
+Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 16) >> 16;
+  insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
+}
+
+static unsigned
+Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
+  return tie_t;
+}
+
+static void
+Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 14) >> 14;
+  insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+  return tie_t;
+}
+
+static void
+Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+  return tie_t;
+}
+
+static void
+Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+  tie_t = (val << 27) >> 31;
+  insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
+}
+
+static unsigned
+Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+  tie_t = (val << 27) >> 31;
+  insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+  tie_t = (val << 27) >> 31;
+  insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+  return tie_t;
+}
+
+static void
+Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+  tie_t = (val << 27) >> 31;
+  insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+}
+
+static unsigned
+Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+  tie_t = (val << 24) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+  tie_t = (val << 24) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+  tie_t = (val << 24) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+  tie_t = (val << 24) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+  return tie_t;
+}
+
+static void
+Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+  tie_t = (val << 28) >> 30;
+  insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+  return tie_t;
+}
+
+static void
+Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+  return tie_t;
+}
+
+static void
+Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+  return tie_t;
+}
+
+static void
+Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+  return tie_t;
+}
+
+static void
+Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+  return tie_t;
+}
+
+static void
+Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+  return tie_t;
+}
+
+static void
+Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+  tie_t = (val << 26) >> 30;
+  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+  tie_t = (val << 26) >> 30;
+  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+  tie_t = (val << 25) >> 29;
+  insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+  tie_t = (val << 25) >> 29;
+  insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
+  return tie_t;
+}
+
+static void
+Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
+}
+
+static unsigned
+Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+  return tie_t;
+}
+
+static void
+Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_y_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
+  return tie_t;
+}
+
+static void
+Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
+}
+
+static unsigned
+Field_x_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
+  return tie_t;
+}
+
+static void
+Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
+}
+
+static unsigned
+Field_t2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+  return tie_t;
+}
+
+static void
+Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+  return tie_t;
+}
+
+static void
+Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
+  return tie_t;
+}
+
+static void
+Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
+}
+
+static unsigned
+Field_s2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+  return tie_t;
+}
+
+static void
+Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+  return tie_t;
+}
+
+static void
+Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
+  return tie_t;
+}
+
+static void
+Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_r2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
+  return tie_t;
+}
+
+static void
+Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
+}
+
+static unsigned
+Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
+  return tie_t;
+}
+
+static void
+Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
+}
+
+static unsigned
+Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
+  return tie_t;
+}
+
+static void
+Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
+}
+
+static unsigned
+Field_t4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+  return tie_t;
+}
+
+static void
+Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+  return tie_t;
+}
+
+static void
+Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+  return tie_t;
+}
+
+static void
+Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_s4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
+  return tie_t;
+}
+
+static void
+Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
+}
+
+static unsigned
+Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
+  return tie_t;
+}
+
+static void
+Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
+}
+
+static unsigned
+Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
+  return tie_t;
+}
+
+static void
+Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
+}
+
+static unsigned
+Field_r4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+  return tie_t;
+}
+
+static void
+Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+  return tie_t;
+}
+
+static void
+Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
+  return tie_t;
+}
+
+static void
+Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
+}
+
+static unsigned
+Field_t8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+  return tie_t;
+}
+
+static void
+Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+  return tie_t;
+}
+
+static void
+Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+  return tie_t;
+}
+
+static void
+Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+}
+
+static unsigned
+Field_s8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
+  return tie_t;
+}
+
+static void
+Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
+}
+
+static unsigned
+Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
+  return tie_t;
+}
+
+static void
+Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
+}
+
+static unsigned
+Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
+  return tie_t;
+}
+
+static void
+Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
+}
+
+static unsigned
+Field_r8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+}
+
+static unsigned
+Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
+  return tie_t;
+}
+
+static void
+Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 17) >> 17;
+  insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
+}
+
+static unsigned
+Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
+  return tie_t;
+}
+
+static void
+Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 14) >> 14;
+  insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_fld_st_qr_b_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_st_qr_b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_st_qr_a_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_st_qr_a_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_ld_qr_b_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_ld_qr_b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_ld_qr_a_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_ld_qr_a_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_qr_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_qr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_mv_qr_b_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_mv_qr_b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x20) | (tie_t << 5);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
+}
+
+static unsigned
+Field_fld_mv_qr_a_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_mv_qr_a_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_ee_wr_mask_gpio_out_mask_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_wr_mask_gpio_out_mask_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_ee_wr_mask_gpio_out_value_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_wr_mask_gpio_out_value_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_ee_set_bit_gpio_out_mask_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_set_bit_gpio_out_mask_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 24) >> 24;
+  insn[0] = (insn[0] & ~0xff0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_ee_clr_bit_gpio_out_clear_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_clr_bit_gpio_out_clear_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 24) >> 24;
+  insn[0] = (insn[0] & ~0xff0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_ee_get_gpio_in_au_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_get_gpio_in_au_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_imm2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_imm2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 25) >> 25;
+  insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_imm1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_imm1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 25) >> 25;
+  insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_qu1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_qu1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_imm16f_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_imm16f_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_as_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_as_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_as_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_as_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_fu0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_fu0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_fu0_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_fu0_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_fu1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_fu1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_fu1_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_fu1_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_fu2_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_fu2_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_fu3_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_fu3_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_ad_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_ad_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_ad_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_ad_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_imm8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31);
+  tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 25) >> 25;
+  insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8);
+  tie_t = (val << 24) >> 31;
+  insn[0] = (insn[0] & ~0x400000) | (tie_t << 22);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_imm8_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25);
+  tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_imm8_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+  tie_t = (val << 24) >> 25;
+  insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_imm16_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31);
+  tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 25) >> 25;
+  insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8);
+  tie_t = (val << 24) >> 31;
+  insn[0] = (insn[0] & ~0x400000) | (tie_t << 22);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_imm4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31);
+  tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 25) >> 25;
+  insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8);
+  tie_t = (val << 24) >> 31;
+  insn[0] = (insn[0] & ~0x400000) | (tie_t << 22);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_sel8_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_sel8_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_sel4_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_sel4_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_qs_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 15) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_qs_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x1c000) | (tie_t << 14);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_qu_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_qu_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_qu_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_qu_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_fv0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_fv0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_fv0_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_fv0_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_fv1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_fv1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_fv1_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_fv1_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_fv2_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_fv2_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_fv3_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_fv3_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_qv_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_qv_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_semantic_ld_st_qv_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_ld_st_qv_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_ee_movi_32_a_sel4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_movi_32_a_sel4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
+}
+
+static unsigned
+Field_fld_ee_movi_32_a_au_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_movi_32_a_au_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_ee_movi_32_a_qs_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_movi_32_a_qs_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_ee_movi_32_q_sel4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_movi_32_q_sel4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
+}
+
+static unsigned
+Field_fld_ee_movi_32_q_as_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_movi_32_q_as_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_ee_movi_32_q_qu_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_movi_32_q_qu_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_ee_vzip_16_qs1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_vzip_16_qs1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_ee_vzip_16_qs0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_vzip_16_qs0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
+}
+
+static unsigned
+Field_fld_ee_vzip_32_qs1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_vzip_32_qs1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_ee_vzip_32_qs0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_vzip_32_qs0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
+}
+
+static unsigned
+Field_fld_ee_vzip_8_qs1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_vzip_8_qs1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_ee_vzip_8_qs0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_vzip_8_qs0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
+}
+
+static unsigned
+Field_fld_ee_vunzip_16_qs1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_vunzip_16_qs1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_ee_vunzip_16_qs0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_vunzip_16_qs0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
+}
+
+static unsigned
+Field_fld_ee_vunzip_32_qs1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_vunzip_32_qs1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_ee_vunzip_32_qs0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_vunzip_32_qs0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
+}
+
+static unsigned
+Field_fld_ee_vunzip_8_qs1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_vunzip_8_qs1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_ee_vunzip_8_qs0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_vunzip_8_qs0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
+}
+
+static unsigned
+Field_fld_ee_zero_q_qa_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_zero_q_qa_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_ee_mov_s16_qacc_qs_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_mov_s16_qacc_qs_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_ee_mov_s8_qacc_qs_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_mov_s8_qacc_qs_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_ee_mov_u16_qacc_qs_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_mov_u16_qacc_qs_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_ee_mov_u8_qacc_qs_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_mov_u8_qacc_qs_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_qa_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_qa_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_qa_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_qa_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_as_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_as_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_as_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_as_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_qu_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_qu_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x2000) | (tie_t << 13);
+  tie_t = (val << 30) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 31;
+  insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_qu_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_qu_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x700000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_qv_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_qv_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_sel4_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_sel4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_sel4_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_sel4_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_qy_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
+  tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_qy_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x1800) | (tie_t << 11);
+  tie_t = (val << 29) >> 31;
+  insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_qy_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_qy_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_qx_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_qx_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_qx_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 15) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_qx_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x1c000) | (tie_t << 14);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_qz_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_qz_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_qz_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_qz_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_qs1_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_qs1_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_qs0_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_qs0_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_imm16_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 7) >> 30);
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_imm16_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+  tie_t = (val << 26) >> 30;
+  insn[0] = (insn[0] & ~0x1800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_ad_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_ad_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_sel8_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_sel8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_sel8_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_sel8_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_sel16_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_sel16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+  tie_t = (val << 30) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 28) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_sel16_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
+  tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_sel16_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+  tie_t = (val << 28) >> 29;
+  insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
+}
+
+static unsigned
+Field_fld_semantic_srcmb_qacc_sel2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_srcmb_qacc_sel2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
+}
+
+static unsigned
+Field_fld_semantic_srcmb_qacc_as_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_srcmb_qacc_as_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_semantic_srcmb_qacc_qu_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_srcmb_qacc_qu_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_ee_srs_accx_sel2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_srs_accx_sel2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
+}
+
+static unsigned
+Field_fld_ee_srs_accx_as_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_srs_accx_as_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_ee_srs_accx_au_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_srs_accx_au_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_ax_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_ax_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_qs_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_qs_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_semantic_cal_double_q_ay_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_cal_double_q_ay_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_semantic_vlogic_qy_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_vlogic_qy_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x20) | (tie_t << 5);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
+}
+
+static unsigned
+Field_fld_semantic_vlogic_qx_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_vlogic_qx_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_fld_semantic_vlogic_qa_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_vlogic_qa_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_semantic_shfq_sar16_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_shfq_sar16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_semantic_shfq_qs0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_shfq_qs0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
+}
+
+static unsigned
+Field_fld_semantic_shfq_qs0_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 15) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_shfq_qs0_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x1c000) | (tie_t << 14);
+}
+
+static unsigned
+Field_fld_semantic_shfq_qs1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_shfq_qs1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_semantic_shfq_qs1_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_shfq_qs1_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_semantic_shfq_ad_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_shfq_ad_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_semantic_shfq_ad_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_shfq_ad_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_semantic_shfq_as_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_shfq_as_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_semantic_shfq_as_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_shfq_as_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_fld_semantic_shfq_imm16_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29);
+  tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+  tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_shfq_imm16_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
+  tie_t = (val << 27) >> 29;
+  insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+  tie_t = (val << 24) >> 29;
+  insn[0] = (insn[0] & ~0x700000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_semantic_shfq_qu_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_shfq_qu_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
+}
+
+static unsigned
+Field_fld_semantic_shfq_qa_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_shfq_qa_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_semantic_shfq_qs_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_shfq_qs_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_semantic_fft_rxbf_sar4_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_fft_rxbf_sar4_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x1800) | (tie_t << 11);
+}
+
+static unsigned
+Field_fld_semantic_fft_rxbf_as_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_fft_rxbf_as_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_fld_semantic_fft_rxbf_sel2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_fft_rxbf_sel2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_semantic_fft_rxbf_qy_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_fft_rxbf_qy_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x20) | (tie_t << 5);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
+}
+
+static unsigned
+Field_fld_semantic_fft_rxbf_qy_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_fft_rxbf_qy_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_semantic_fft_rxbf_qx_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_fft_rxbf_qx_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
+}
+
+static unsigned
+Field_fld_semantic_fft_rxbf_qx_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 15) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_fft_rxbf_qx_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x1c000) | (tie_t << 14);
+}
+
+static unsigned
+Field_fld_semantic_fft_rxbf_qa1_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_fft_rxbf_qa1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
+}
+
+static unsigned
+Field_fld_semantic_fft_rxbf_qa0_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_fft_rxbf_qa0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_semantic_fft_rxbf_qa0_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_semantic_fft_rxbf_qa0_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
+}
+
+static unsigned
+Field_fld_ee_fft_cmul_s16_ld_xp_sel8_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_cmul_s16_ld_xp_sel8_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x700000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_ee_fft_cmul_s16_ld_xp_qy_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_cmul_s16_ld_xp_qy_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_ee_fft_cmul_s16_ld_xp_qx_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 15) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_cmul_s16_ld_xp_qx_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x1c000) | (tie_t << 14);
+}
+
+static unsigned
+Field_fld_ee_fft_cmul_s16_ld_xp_qz_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_cmul_s16_ld_xp_qz_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
+}
+
+static unsigned
+Field_fld_ee_fft_cmul_s16_ld_xp_ad_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_cmul_s16_ld_xp_ad_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_ee_fft_cmul_s16_ld_xp_as_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_cmul_s16_ld_xp_as_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_fld_ee_fft_cmul_s16_ld_xp_qu_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_cmul_s16_ld_xp_qu_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_fld_ee_fft_cmul_s16_st_xp_sar4_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_cmul_s16_st_xp_sar4_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22);
+}
+
+static unsigned
+Field_fld_ee_fft_cmul_s16_st_xp_upd4_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_cmul_s16_st_xp_upd4_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 30) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_ee_fft_cmul_s16_st_xp_sel8_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_cmul_s16_st_xp_sel8_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_fld_ee_fft_cmul_s16_st_xp_ad_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_cmul_s16_st_xp_ad_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_ee_fft_cmul_s16_st_xp_as_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_cmul_s16_st_xp_as_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_fld_ee_fft_cmul_s16_st_xp_qv_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_cmul_s16_st_xp_qv_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
+}
+
+static unsigned
+Field_fld_ee_fft_cmul_s16_st_xp_qy_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_cmul_s16_st_xp_qy_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_ee_fft_cmul_s16_st_xp_qx_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 15) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_cmul_s16_st_xp_qx_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x1c000) | (tie_t << 14);
+}
+
+static unsigned
+Field_fld_ee_bitrev_ax_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_bitrev_ax_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_ee_bitrev_qa_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_bitrev_qa_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_ld_incp_sel2_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_ld_incp_sel2_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x400000) | (tie_t << 22);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_ld_incp_qm_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_ld_incp_qm_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_ld_incp_qy_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_ld_incp_qy_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_ld_incp_qx_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 15) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_ld_incp_qx_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x1c000) | (tie_t << 14);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_ld_incp_qz1_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_ld_incp_qz1_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_ld_incp_qz_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_ld_incp_qz_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_ld_incp_as_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_ld_incp_as_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_ld_incp_qu_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_ld_incp_qu_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_ld_incp_uaup_sel2_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_ld_incp_uaup_sel2_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x400000) | (tie_t << 22);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_ld_incp_uaup_qm_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_ld_incp_uaup_qm_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_ld_incp_uaup_qy_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_ld_incp_uaup_qy_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_ld_incp_uaup_qx_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 15) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_ld_incp_uaup_qx_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x1c000) | (tie_t << 14);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_ld_incp_uaup_qz1_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_ld_incp_uaup_qz1_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_ld_incp_uaup_qz_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_ld_incp_uaup_qz_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_ld_incp_uaup_as_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_ld_incp_uaup_as_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_ld_incp_uaup_qu_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_ld_incp_uaup_qu_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_ld_r32_decp_sel2_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_ld_r32_decp_sel2_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x400000) | (tie_t << 22);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_ld_r32_decp_qm_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_ld_r32_decp_qm_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_ld_r32_decp_qy_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_ld_r32_decp_qy_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_ld_r32_decp_qx_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 15) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_ld_r32_decp_qx_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x1c000) | (tie_t << 14);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_ld_r32_decp_qz1_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_ld_r32_decp_qz1_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_ld_r32_decp_qz_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_ld_r32_decp_qz_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_ld_r32_decp_as_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_ld_r32_decp_as_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_ld_r32_decp_qu_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_ld_r32_decp_qu_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_st_incp_sel2_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_st_incp_sel2_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x800000) | (tie_t << 23);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_st_incp_qm_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_st_incp_qm_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x3800) | (tie_t << 11);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_st_incp_qy_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 15) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_st_incp_qy_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x1c000) | (tie_t << 14);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_st_incp_qx_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_st_incp_qx_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_st_incp_as_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_st_incp_as_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_st_incp_as0_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_st_incp_as0_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_st_incp_qz1_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_st_incp_qz1_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x700000) | (tie_t << 20);
+}
+
+static unsigned
+Field_fld_ee_fft_ams_s16_st_incp_qv_Slot_slot_format_32_0_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_ams_s16_st_incp_qv_Slot_slot_format_32_0_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 29) >> 29;
+  insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
+}
+
+static unsigned
+Field_fld_ee_fft_vst_r32_decp_sar2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_vst_r32_decp_sar2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
+}
+
+static unsigned
+Field_fld_ee_fft_vst_r32_decp_as_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_vst_r32_decp_as_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
+}
+
+static unsigned
+Field_fld_ee_fft_vst_r32_decp_qv_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30);
+  tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
+  return tie_t;
+}
+
+static void
+Field_fld_ee_fft_vst_r32_decp_qv_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 31) >> 31;
+  insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
+  tie_t = (val << 29) >> 30;
+  insn[0] = (insn[0] & ~0x300000) | (tie_t << 20);
+}
+
+static void
+Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
+		    uint32 val ATTRIBUTE_UNUSED)
+{
+  /* Do nothing.  */
+}
+
+static unsigned
+Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static unsigned
+Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 4;
+}
+
+static unsigned
+Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 8;
+}
+
+static unsigned
+Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 12;
+}
+
+static unsigned
+Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static unsigned
+Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 1;
+}
+
+static unsigned
+Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 2;
+}
+
+static unsigned
+Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 3;
+}
+
+static unsigned
+Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static unsigned
+Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static unsigned
+Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static unsigned
+Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+enum xtensa_field_id {
+  FIELD_t,
+  FIELD_bbi4,
+  FIELD_bbi,
+  FIELD_imm12,
+  FIELD_imm8,
+  FIELD_s,
+  FIELD_imm12b,
+  FIELD_imm16,
+  FIELD_m,
+  FIELD_n,
+  FIELD_offset,
+  FIELD_op0,
+  FIELD_op1,
+  FIELD_op2,
+  FIELD_r,
+  FIELD_sa4,
+  FIELD_sae4,
+  FIELD_sae,
+  FIELD_sal,
+  FIELD_sargt,
+  FIELD_sas4,
+  FIELD_sas,
+  FIELD_sr,
+  FIELD_st,
+  FIELD_thi3,
+  FIELD_imm4,
+  FIELD_mn,
+  FIELD_i,
+  FIELD_imm6lo,
+  FIELD_imm6hi,
+  FIELD_imm7lo,
+  FIELD_imm7hi,
+  FIELD_z,
+  FIELD_imm6,
+  FIELD_imm7,
+  FIELD_r3,
+  FIELD_rbit2,
+  FIELD_rhi,
+  FIELD_t3,
+  FIELD_tbit2,
+  FIELD_tlo,
+  FIELD_w,
+  FIELD_y,
+  FIELD_x,
+  FIELD_t2,
+  FIELD_s2,
+  FIELD_r2,
+  FIELD_t4,
+  FIELD_s4,
+  FIELD_r4,
+  FIELD_t8,
+  FIELD_s8,
+  FIELD_r8,
+  FIELD_xt_wbr15_imm,
+  FIELD_xt_wbr18_imm,
+  FIELD_fld_slot_format_32_0_3_0,
+  FIELD_fld_slot_format_32_0_28_4,
+  FIELD_fld_st_QR_b,
+  FIELD_fld_st_QR_a,
+  FIELD_fld_ld_QR_b,
+  FIELD_fld_ld_QR_a,
+  FIELD_fld_QR,
+  FIELD_fld_Inst_4_0,
+  FIELD_fld_Inst_9_6,
+  FIELD_fld_mv_QR_b,
+  FIELD_fld_mv_QR_a,
+  FIELD_fld_EE_WR_MASK_GPIO_OUT_mask,
+  FIELD_fld_EE_WR_MASK_GPIO_OUT_value,
+  FIELD_fld_EE_SET_BIT_GPIO_OUT_mask,
+  FIELD_fld_EE_CLR_BIT_GPIO_OUT_clear,
+  FIELD_fld_Inst_23_8,
+  FIELD_fld_EE_GET_GPIO_IN_au,
+  FIELD_fld_Inst_23_22,
+  FIELD_fld_semantic_LD_ST_imm2,
+  FIELD_fld_Inst_14_8,
+  FIELD_fld_semantic_LD_ST_imm1,
+  FIELD_fld_Inst_11_8,
+  FIELD_fld_semantic_LD_ST_qu1,
+  FIELD_fld_semantic_LD_ST_imm16f,
+  FIELD_fld_semantic_LD_ST_as,
+  FIELD_fld_semantic_LD_ST_fu0,
+  FIELD_fld_semantic_LD_ST_fu1,
+  FIELD_fld_semantic_LD_ST_fu2,
+  FIELD_fld_semantic_LD_ST_fu3,
+  FIELD_fld_slot_format_32_0_28_24,
+  FIELD_fld_semantic_LD_ST_ad,
+  FIELD_fld_semantic_LD_ST_imm8,
+  FIELD_fld_slot_format_32_0_7_5,
+  FIELD_fld_Inst_3_0,
+  FIELD_fld_Inst_19_16,
+  FIELD_fld_Inst_23_23,
+  FIELD_fld_Inst_14_12,
+  FIELD_fld_Inst_21_15,
+  FIELD_fld_semantic_LD_ST_imm16,
+  FIELD_fld_Inst_23_12,
+  FIELD_fld_semantic_LD_ST_imm4,
+  FIELD_fld_semantic_LD_ST_sel8,
+  FIELD_fld_semantic_LD_ST_sel4,
+  FIELD_fld_semantic_LD_ST_qs,
+  FIELD_fld_semantic_LD_ST_qu,
+  FIELD_fld_slot_format_32_0_28_22,
+  FIELD_fld_semantic_LD_ST_fv0,
+  FIELD_fld_semantic_LD_ST_fv1,
+  FIELD_fld_semantic_LD_ST_fv2,
+  FIELD_fld_semantic_LD_ST_fv3,
+  FIELD_fld_semantic_LD_ST_qv,
+  FIELD_fld_EE_MOVI_32_A_sel4,
+  FIELD_fld_EE_MOVI_32_A_au,
+  FIELD_fld_EE_MOVI_32_A_qs,
+  FIELD_fld_EE_MOVI_32_Q_sel4,
+  FIELD_fld_EE_MOVI_32_Q_as,
+  FIELD_fld_EE_MOVI_32_Q_qu,
+  FIELD_fld_EE_VZIP_16_qs1,
+  FIELD_fld_EE_VZIP_16_qs0,
+  FIELD_fld_EE_VZIP_32_qs1,
+  FIELD_fld_EE_VZIP_32_qs0,
+  FIELD_fld_EE_VZIP_8_qs1,
+  FIELD_fld_EE_VZIP_8_qs0,
+  FIELD_fld_Inst_11_0,
+  FIELD_fld_EE_VUNZIP_16_qs1,
+  FIELD_fld_EE_VUNZIP_16_qs0,
+  FIELD_fld_EE_VUNZIP_32_qs1,
+  FIELD_fld_EE_VUNZIP_32_qs0,
+  FIELD_fld_EE_VUNZIP_8_qs1,
+  FIELD_fld_EE_VUNZIP_8_qs0,
+  FIELD_fld_Inst_23_0,
+  FIELD_fld_EE_ZERO_Q_qa,
+  FIELD_fld_Inst_14_0,
+  FIELD_fld_EE_MOV_S16_QACC_qs,
+  FIELD_fld_EE_MOV_S8_QACC_qs,
+  FIELD_fld_EE_MOV_U16_QACC_qs,
+  FIELD_fld_EE_MOV_U8_QACC_qs,
+  FIELD_fld_slot_format_32_0_10_4,
+  FIELD_fld_Inst_7_0,
+  FIELD_fld_semantic_CAL_DOUBLE_Q_qa,
+  FIELD_fld_semantic_CAL_DOUBLE_Q_as,
+  FIELD_fld_semantic_CAL_DOUBLE_Q_qu,
+  FIELD_fld_slot_format_32_0_10_6,
+  FIELD_fld_semantic_CAL_DOUBLE_Q_qv,
+  FIELD_fld_slot_format_32_0_28_20,
+  FIELD_fld_Inst_7_6,
+  FIELD_fld_semantic_CAL_DOUBLE_Q_sel4,
+  FIELD_fld_semantic_CAL_DOUBLE_Q_qy,
+  FIELD_fld_semantic_CAL_DOUBLE_Q_qx,
+  FIELD_fld_semantic_CAL_DOUBLE_Q_qz,
+  FIELD_fld_semantic_CAL_DOUBLE_Q_qs1,
+  FIELD_fld_semantic_CAL_DOUBLE_Q_qs0,
+  FIELD_fld_slot_format_32_0_28_25,
+  FIELD_fld_semantic_CAL_DOUBLE_Q_imm16,
+  FIELD_fld_slot_format_32_0_10_8,
+  FIELD_fld_slot_format_32_0_19_17,
+  FIELD_fld_slot_format_32_0_28_23,
+  FIELD_fld_semantic_CAL_DOUBLE_Q_ad,
+  FIELD_fld_slot_format_32_0_7_4,
+  FIELD_fld_Inst_23_21,
+  FIELD_fld_semantic_CAL_DOUBLE_Q_sel8,
+  FIELD_fld_slot_format_32_0_10_9,
+  FIELD_fld_Inst_7_5,
+  FIELD_fld_semantic_CAL_DOUBLE_Q_sel16,
+  FIELD_fld_Inst_14_11,
+  FIELD_fld_semantic_SRCMB_QACC_sel2,
+  FIELD_fld_semantic_SRCMB_QACC_as,
+  FIELD_fld_semantic_SRCMB_QACC_qu,
+  FIELD_fld_Inst_13_12,
+  FIELD_fld_Inst_23_15,
+  FIELD_fld_EE_SRS_ACCX_sel2,
+  FIELD_fld_EE_SRS_ACCX_as,
+  FIELD_fld_EE_SRS_ACCX_au,
+  FIELD_fld_semantic_CAL_DOUBLE_Q_ax,
+  FIELD_fld_semantic_CAL_DOUBLE_Q_qs,
+  FIELD_fld_Inst_13_13,
+  FIELD_fld_semantic_CAL_DOUBLE_Q_ay,
+  FIELD_fld_Inst_9_8,
+  FIELD_fld_semantic_VLOGIC_qy,
+  FIELD_fld_semantic_VLOGIC_qx,
+  FIELD_fld_semantic_VLOGIC_qa,
+  FIELD_fld_Inst_5_5,
+  FIELD_fld_semantic_SHFQ_sar16,
+  FIELD_fld_semantic_SHFQ_qs0,
+  FIELD_fld_semantic_SHFQ_qs1,
+  FIELD_fld_semantic_SHFQ_ad,
+  FIELD_fld_semantic_SHFQ_as,
+  FIELD_fld_semantic_SHFQ_imm16,
+  FIELD_fld_semantic_SHFQ_qu,
+  FIELD_fld_slot_format_32_0_7_6,
+  FIELD_fld_slot_format_32_0_13_11,
+  FIELD_fld_Inst_11_7,
+  FIELD_fld_semantic_SHFQ_qa,
+  FIELD_fld_Inst_14_7,
+  FIELD_fld_semantic_SHFQ_qs,
+  FIELD_fld_semantic_FFT_RxBF_sar4,
+  FIELD_fld_semantic_FFT_RxBF_as,
+  FIELD_fld_slot_format_32_0_13_13,
+  FIELD_fld_Inst_9_9,
+  FIELD_fld_semantic_FFT_RxBF_sel2,
+  FIELD_fld_semantic_FFT_RxBF_qy,
+  FIELD_fld_semantic_FFT_RxBF_qx,
+  FIELD_fld_semantic_FFT_RxBF_qa1,
+  FIELD_fld_semantic_FFT_RxBF_qa0,
+  FIELD_fld_EE_FFT_CMUL_S16_LD_XP_sel8,
+  FIELD_fld_EE_FFT_CMUL_S16_LD_XP_qy,
+  FIELD_fld_EE_FFT_CMUL_S16_LD_XP_qx,
+  FIELD_fld_EE_FFT_CMUL_S16_LD_XP_qz,
+  FIELD_fld_EE_FFT_CMUL_S16_LD_XP_ad,
+  FIELD_fld_EE_FFT_CMUL_S16_LD_XP_as,
+  FIELD_fld_EE_FFT_CMUL_S16_LD_XP_qu,
+  FIELD_fld_EE_FFT_CMUL_S16_ST_XP_sar4,
+  FIELD_fld_EE_FFT_CMUL_S16_ST_XP_upd4,
+  FIELD_fld_EE_FFT_CMUL_S16_ST_XP_sel8,
+  FIELD_fld_EE_FFT_CMUL_S16_ST_XP_ad,
+  FIELD_fld_EE_FFT_CMUL_S16_ST_XP_as,
+  FIELD_fld_EE_FFT_CMUL_S16_ST_XP_qv,
+  FIELD_fld_EE_FFT_CMUL_S16_ST_XP_qy,
+  FIELD_fld_EE_FFT_CMUL_S16_ST_XP_qx,
+  FIELD_fld_EE_BITREV_ax,
+  FIELD_fld_EE_BITREV_qa,
+  FIELD_fld_EE_FFT_AMS_S16_LD_INCP_sel2,
+  FIELD_fld_EE_FFT_AMS_S16_LD_INCP_qm,
+  FIELD_fld_EE_FFT_AMS_S16_LD_INCP_qy,
+  FIELD_fld_EE_FFT_AMS_S16_LD_INCP_qx,
+  FIELD_fld_EE_FFT_AMS_S16_LD_INCP_qz1,
+  FIELD_fld_EE_FFT_AMS_S16_LD_INCP_qz,
+  FIELD_fld_EE_FFT_AMS_S16_LD_INCP_as,
+  FIELD_fld_EE_FFT_AMS_S16_LD_INCP_qu,
+  FIELD_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_sel2,
+  FIELD_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_qm,
+  FIELD_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_qy,
+  FIELD_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_qx,
+  FIELD_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_qz1,
+  FIELD_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_qz,
+  FIELD_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_as,
+  FIELD_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_qu,
+  FIELD_fld_EE_FFT_AMS_S16_LD_R32_DECP_sel2,
+  FIELD_fld_EE_FFT_AMS_S16_LD_R32_DECP_qm,
+  FIELD_fld_EE_FFT_AMS_S16_LD_R32_DECP_qy,
+  FIELD_fld_EE_FFT_AMS_S16_LD_R32_DECP_qx,
+  FIELD_fld_EE_FFT_AMS_S16_LD_R32_DECP_qz1,
+  FIELD_fld_EE_FFT_AMS_S16_LD_R32_DECP_qz,
+  FIELD_fld_EE_FFT_AMS_S16_LD_R32_DECP_as,
+  FIELD_fld_EE_FFT_AMS_S16_LD_R32_DECP_qu,
+  FIELD_fld_EE_FFT_AMS_S16_ST_INCP_sel2,
+  FIELD_fld_EE_FFT_AMS_S16_ST_INCP_qm,
+  FIELD_fld_EE_FFT_AMS_S16_ST_INCP_qy,
+  FIELD_fld_EE_FFT_AMS_S16_ST_INCP_qx,
+  FIELD_fld_EE_FFT_AMS_S16_ST_INCP_as,
+  FIELD_fld_EE_FFT_AMS_S16_ST_INCP_as0,
+  FIELD_fld_EE_FFT_AMS_S16_ST_INCP_qz1,
+  FIELD_fld_EE_FFT_AMS_S16_ST_INCP_qv,
+  FIELD_fld_EE_FFT_VST_R32_DECP_sar2,
+  FIELD_fld_EE_FFT_VST_R32_DECP_as,
+  FIELD_fld_EE_FFT_VST_R32_DECP_qv,
+  FIELD__ar0,
+  FIELD__ar4,
+  FIELD__ar8,
+  FIELD__ar12,
+  FIELD__mr0,
+  FIELD__mr1,
+  FIELD__mr2,
+  FIELD__mr3,
+  FIELD__bt16,
+  FIELD__bs16,
+  FIELD__br16,
+  FIELD__brall
+};
+
+\f
+/* Functional units.  */
+
+static xtensa_funcUnit_internal funcUnits[] = {
+  { "func_addsub_s8x2_0", 1 },
+  { "func_addsub_s8x2_1", 1 },
+  { "func_addsub_s8x2_2", 1 },
+  { "func_addsub_s8x2_3", 1 },
+  { "func_addsub_s8x2_4", 1 },
+  { "func_addsub_s8x2_5", 1 },
+  { "func_addsub_s8x2_6", 1 },
+  { "func_addsub_s8x2_7", 1 },
+  { "func_addsub_s16x2_0", 1 },
+  { "func_addsub_s16x2_1", 1 },
+  { "func_addsub_s16x2_2", 1 },
+  { "func_addsub_s16x2_3", 1 },
+  { "func_addsub_s16x2_4", 1 },
+  { "func_addsub_s16x2_5", 1 },
+  { "func_addsub_s16x2_6", 1 },
+  { "func_addsub_s16x2_7", 1 },
+  { "func_addsub_s16x2_slot1_0", 1 },
+  { "func_addsub_s16x2_slot1_1", 1 },
+  { "func_addsub_s16x2_slot1_2", 1 },
+  { "func_addsub_s16x2_slot1_3", 1 },
+  { "func_addsub_s20x2_slot_end_0", 1 },
+  { "func_addsub_s20x2_slot_end_1", 1 },
+  { "func_addsub_s20x2_slot_end_2", 1 },
+  { "func_addsub_s20x2_slot_end_3", 1 },
+  { "func_addsub_s32x2_slot0_0", 1 },
+  { "func_addsub_s32x2_slot0_1", 1 },
+  { "func_addsub_s32x2_slot0_2", 1 },
+  { "func_addsub_s32x2_slot0_3", 1 },
+  { "func_addsub_s32x2_slot0_4", 1 },
+  { "func_addsub_s32x2_slot0_5", 1 },
+  { "func_addsub_s32x2_slot0_6", 1 },
+  { "func_addsub_s32x2_slot0_7", 1 },
+  { "func_addsub_s32x2_slot1_0", 1 },
+  { "func_addsub_s32x2_slot1_1", 1 },
+  { "func_addsub_s32x2_slot1_2", 1 },
+  { "func_addsub_s32x2_slot1_3", 1 },
+  { "func_addsub_s32x2_slot1_extra", 1 },
+  { "func_addsub_s40x2_0", 1 },
+  { "func_addsub_s40x2_1", 1 },
+  { "func_addsub_s40x2_2", 1 },
+  { "func_addsub_s40x2_3", 1 },
+  { "func_addsub_s40x2_4", 1 },
+  { "func_addsub_s40x2_5", 1 },
+  { "func_addsub_s40x2_6", 1 },
+  { "func_addsub_s40x2_7", 1 },
+  { "func_addsub_s32x2_spe", 1 },
+  { "func_mul_s8xs8_0", 1 },
+  { "func_mul_s8xs8_1", 1 },
+  { "func_mul_s8xs8_2", 1 },
+  { "func_mul_s8xs8_3", 1 },
+  { "func_mul_s8xs8_4", 1 },
+  { "func_mul_s8xs8_5", 1 },
+  { "func_mul_s8xs8_6", 1 },
+  { "func_mul_s8xs8_7", 1 },
+  { "func_mul_s16xs16_0", 1 },
+  { "func_mul_s16xs16_1", 1 },
+  { "func_mul_s16xs16_2", 1 },
+  { "func_mul_s16xs16_3", 1 },
+  { "func_mul_s16xs16_4", 1 },
+  { "func_mul_s16xs16_5", 1 },
+  { "func_mul_s16xs16_6", 1 },
+  { "func_mul_s16xs16_7", 1 },
+  { "func_shift_s16rs8_0", 1 },
+  { "func_shift_s16rs8_1", 1 },
+  { "func_shift_s16rs8_2", 1 },
+  { "func_shift_s16rs8_3", 1 },
+  { "func_shift_s16rs8_4", 1 },
+  { "func_shift_s16rs8_5", 1 },
+  { "func_shift_s16rs8_6", 1 },
+  { "func_shift_s16rs8_7", 1 },
+  { "func_shift_s16rs8_8", 1 },
+  { "func_shift_s16rs8_9", 1 },
+  { "func_shift_s16rs8_10", 1 },
+  { "func_shift_s16rs8_11", 1 },
+  { "func_shift_s16rs8_12", 1 },
+  { "func_shift_s16rs8_13", 1 },
+  { "func_shift_s16rs8_14", 1 },
+  { "func_shift_s16rs8_15", 1 },
+  { "func_shift_s40rs_slot_end_0", 1 },
+  { "func_shift_s40rs_slot_end_1", 1 },
+  { "func_shift_s40rs_slot_end_2", 1 },
+  { "func_shift_s40rs_slot_end_3", 1 },
+  { "func_shift_s40rs_slot_end_4", 1 },
+  { "func_shift_s40rs_slot_end_5", 1 },
+  { "func_shift_s40rs_slot_end_6", 1 },
+  { "func_shift_s40rs_slot_end_7", 1 },
+  { "func_shift_s32rs16_0", 1 },
+  { "func_shift_s32rs16_1", 1 },
+  { "func_shift_s32rs16_2", 1 },
+  { "func_shift_s32rs16_3", 1 },
+  { "func_shift_s32rs16_4", 1 },
+  { "func_shift_s32rs16_5", 1 },
+  { "func_shift_s32rs16_6", 1 },
+  { "func_shift_s32rs16_7", 1 }
+};
+
+enum xtensa_funcUnit_id {
+  FUNCUNIT_func_addsub_s8x2_0,
+  FUNCUNIT_func_addsub_s8x2_1,
+  FUNCUNIT_func_addsub_s8x2_2,
+  FUNCUNIT_func_addsub_s8x2_3,
+  FUNCUNIT_func_addsub_s8x2_4,
+  FUNCUNIT_func_addsub_s8x2_5,
+  FUNCUNIT_func_addsub_s8x2_6,
+  FUNCUNIT_func_addsub_s8x2_7,
+  FUNCUNIT_func_addsub_s16x2_0,
+  FUNCUNIT_func_addsub_s16x2_1,
+  FUNCUNIT_func_addsub_s16x2_2,
+  FUNCUNIT_func_addsub_s16x2_3,
+  FUNCUNIT_func_addsub_s16x2_4,
+  FUNCUNIT_func_addsub_s16x2_5,
+  FUNCUNIT_func_addsub_s16x2_6,
+  FUNCUNIT_func_addsub_s16x2_7,
+  FUNCUNIT_func_addsub_s16x2_slot1_0,
+  FUNCUNIT_func_addsub_s16x2_slot1_1,
+  FUNCUNIT_func_addsub_s16x2_slot1_2,
+  FUNCUNIT_func_addsub_s16x2_slot1_3,
+  FUNCUNIT_func_addsub_s20x2_slot_end_0,
+  FUNCUNIT_func_addsub_s20x2_slot_end_1,
+  FUNCUNIT_func_addsub_s20x2_slot_end_2,
+  FUNCUNIT_func_addsub_s20x2_slot_end_3,
+  FUNCUNIT_func_addsub_s32x2_slot0_0,
+  FUNCUNIT_func_addsub_s32x2_slot0_1,
+  FUNCUNIT_func_addsub_s32x2_slot0_2,
+  FUNCUNIT_func_addsub_s32x2_slot0_3,
+  FUNCUNIT_func_addsub_s32x2_slot0_4,
+  FUNCUNIT_func_addsub_s32x2_slot0_5,
+  FUNCUNIT_func_addsub_s32x2_slot0_6,
+  FUNCUNIT_func_addsub_s32x2_slot0_7,
+  FUNCUNIT_func_addsub_s32x2_slot1_0,
+  FUNCUNIT_func_addsub_s32x2_slot1_1,
+  FUNCUNIT_func_addsub_s32x2_slot1_2,
+  FUNCUNIT_func_addsub_s32x2_slot1_3,
+  FUNCUNIT_func_addsub_s32x2_slot1_extra,
+  FUNCUNIT_func_addsub_s40x2_0,
+  FUNCUNIT_func_addsub_s40x2_1,
+  FUNCUNIT_func_addsub_s40x2_2,
+  FUNCUNIT_func_addsub_s40x2_3,
+  FUNCUNIT_func_addsub_s40x2_4,
+  FUNCUNIT_func_addsub_s40x2_5,
+  FUNCUNIT_func_addsub_s40x2_6,
+  FUNCUNIT_func_addsub_s40x2_7,
+  FUNCUNIT_func_addsub_s32x2_spe,
+  FUNCUNIT_func_mul_s8xs8_0,
+  FUNCUNIT_func_mul_s8xs8_1,
+  FUNCUNIT_func_mul_s8xs8_2,
+  FUNCUNIT_func_mul_s8xs8_3,
+  FUNCUNIT_func_mul_s8xs8_4,
+  FUNCUNIT_func_mul_s8xs8_5,
+  FUNCUNIT_func_mul_s8xs8_6,
+  FUNCUNIT_func_mul_s8xs8_7,
+  FUNCUNIT_func_mul_s16xs16_0,
+  FUNCUNIT_func_mul_s16xs16_1,
+  FUNCUNIT_func_mul_s16xs16_2,
+  FUNCUNIT_func_mul_s16xs16_3,
+  FUNCUNIT_func_mul_s16xs16_4,
+  FUNCUNIT_func_mul_s16xs16_5,
+  FUNCUNIT_func_mul_s16xs16_6,
+  FUNCUNIT_func_mul_s16xs16_7,
+  FUNCUNIT_func_shift_s16rs8_0,
+  FUNCUNIT_func_shift_s16rs8_1,
+  FUNCUNIT_func_shift_s16rs8_2,
+  FUNCUNIT_func_shift_s16rs8_3,
+  FUNCUNIT_func_shift_s16rs8_4,
+  FUNCUNIT_func_shift_s16rs8_5,
+  FUNCUNIT_func_shift_s16rs8_6,
+  FUNCUNIT_func_shift_s16rs8_7,
+  FUNCUNIT_func_shift_s16rs8_8,
+  FUNCUNIT_func_shift_s16rs8_9,
+  FUNCUNIT_func_shift_s16rs8_10,
+  FUNCUNIT_func_shift_s16rs8_11,
+  FUNCUNIT_func_shift_s16rs8_12,
+  FUNCUNIT_func_shift_s16rs8_13,
+  FUNCUNIT_func_shift_s16rs8_14,
+  FUNCUNIT_func_shift_s16rs8_15,
+  FUNCUNIT_func_shift_s40rs_slot_end_0,
+  FUNCUNIT_func_shift_s40rs_slot_end_1,
+  FUNCUNIT_func_shift_s40rs_slot_end_2,
+  FUNCUNIT_func_shift_s40rs_slot_end_3,
+  FUNCUNIT_func_shift_s40rs_slot_end_4,
+  FUNCUNIT_func_shift_s40rs_slot_end_5,
+  FUNCUNIT_func_shift_s40rs_slot_end_6,
+  FUNCUNIT_func_shift_s40rs_slot_end_7,
+  FUNCUNIT_func_shift_s32rs16_0,
+  FUNCUNIT_func_shift_s32rs16_1,
+  FUNCUNIT_func_shift_s32rs16_2,
+  FUNCUNIT_func_shift_s32rs16_3,
+  FUNCUNIT_func_shift_s32rs16_4,
+  FUNCUNIT_func_shift_s32rs16_5,
+  FUNCUNIT_func_shift_s32rs16_6,
+  FUNCUNIT_func_shift_s32rs16_7
+};
+
+\f
+/* Register files.  */
+
+enum xtensa_regfile_id {
+  REGFILE_AR,
+  REGFILE_MR,
+  REGFILE_BR,
+  REGFILE_FR,
+  REGFILE_QR,
+  REGFILE_BR2,
+  REGFILE_BR4,
+  REGFILE_BR8,
+  REGFILE_BR16
+};
+
+static xtensa_regfile_internal regfiles[] = {
+  { "AR", "a", REGFILE_AR, 32, 64 },
+  { "MR", "m", REGFILE_MR, 32, 4 },
+  { "BR", "b", REGFILE_BR, 1, 16 },
+  { "FR", "f", REGFILE_FR, 32, 16 },
+  { "QR", "q", REGFILE_QR, 128, 8 },
+  { "BR2", "b", REGFILE_BR, 2, 8 },
+  { "BR4", "b", REGFILE_BR, 4, 4 },
+  { "BR8", "b", REGFILE_BR, 8, 2 },
+  { "BR16", "b", REGFILE_BR, 16, 1 }
+};
+
+\f
+/* Interfaces.  */
+
+static xtensa_interface_internal interfaces[] = {
+  { "ERI_RD_Out", 14, 0, 0, 'o' },
+  { "ERI_RD_In", 32, 0, 1, 'i' },
+  { "ERI_RD_Rdy", 1, 0, 0, 'i' },
+  { "ERI_WR_Out", 46, 0, 2, 'o' },
+  { "ERI_WR_In", 1, 0, 3, 'i' },
+  { "GPIO_IN", 8, 0, 4, 'i' }
+};
+
+enum xtensa_interface_id {
+  INTERFACE_ERI_RD_Out,
+  INTERFACE_ERI_RD_In,
+  INTERFACE_ERI_RD_Rdy,
+  INTERFACE_ERI_WR_Out,
+  INTERFACE_ERI_WR_In,
+  INTERFACE_GPIO_IN
+};
+
+
+/* Constant tables.  */
+
+/* constant table ai4c */
+static const unsigned CONST_TBL_ai4c_0[] = {
+  0xffffffff,
+  0x1,
+  0x2,
+  0x3,
+  0x4,
+  0x5,
+  0x6,
+  0x7,
+  0x8,
+  0x9,
+  0xa,
+  0xb,
+  0xc,
+  0xd,
+  0xe,
+  0xf,
+  0
+};
+
+/* constant table b4c */
+static const unsigned CONST_TBL_b4c_0[] = {
+  0xffffffff,
+  0x1,
+  0x2,
+  0x3,
+  0x4,
+  0x5,
+  0x6,
+  0x7,
+  0x8,
+  0xa,
+  0xc,
+  0x10,
+  0x20,
+  0x40,
+  0x80,
+  0x100,
+  0
+};
+
+/* constant table b4cu */
+static const unsigned CONST_TBL_b4cu_0[] = {
+  0x8000,
+  0x10000,
+  0x2,
+  0x3,
+  0x4,
+  0x5,
+  0x6,
+  0x7,
+  0x8,
+  0xa,
+  0xc,
+  0x10,
+  0x20,
+  0x40,
+  0x80,
+  0x100,
+  0
+};
+
+/* constant table RECIP_Data8 */
+static const unsigned CONST_TBL_RECIP_Data8_0[] = {
+  0xff & 0xff,
+  0xfd & 0xff,
+  0xfb & 0xff,
+  0xf9 & 0xff,
+  0xf7 & 0xff,
+  0xf5 & 0xff,
+  0xf4 & 0xff,
+  0xf2 & 0xff,
+  0xf0 & 0xff,
+  0xee & 0xff,
+  0xed & 0xff,
+  0xeb & 0xff,
+  0xe9 & 0xff,
+  0xe8 & 0xff,
+  0xe6 & 0xff,
+  0xe4 & 0xff,
+  0xe3 & 0xff,
+  0xe1 & 0xff,
+  0xe0 & 0xff,
+  0xde & 0xff,
+  0xdd & 0xff,
+  0xdb & 0xff,
+  0xda & 0xff,
+  0xd8 & 0xff,
+  0xd7 & 0xff,
+  0xd5 & 0xff,
+  0xd4 & 0xff,
+  0xd3 & 0xff,
+  0xd1 & 0xff,
+  0xd0 & 0xff,
+  0xcf & 0xff,
+  0xcd & 0xff,
+  0xcc & 0xff,
+  0xcb & 0xff,
+  0xca & 0xff,
+  0xc8 & 0xff,
+  0xc7 & 0xff,
+  0xc6 & 0xff,
+  0xc5 & 0xff,
+  0xc4 & 0xff,
+  0xc2 & 0xff,
+  0xc1 & 0xff,
+  0xc0 & 0xff,
+  0xbf & 0xff,
+  0xbe & 0xff,
+  0xbd & 0xff,
+  0xbc & 0xff,
+  0xbb & 0xff,
+  0xba & 0xff,
+  0xb9 & 0xff,
+  0xb8 & 0xff,
+  0xb7 & 0xff,
+  0xb6 & 0xff,
+  0xb5 & 0xff,
+  0xb4 & 0xff,
+  0xb3 & 0xff,
+  0xb2 & 0xff,
+  0xb1 & 0xff,
+  0xb0 & 0xff,
+  0xaf & 0xff,
+  0xae & 0xff,
+  0xad & 0xff,
+  0xac & 0xff,
+  0xab & 0xff,
+  0xaa & 0xff,
+  0xa9 & 0xff,
+  0xa8 & 0xff,
+  0xa8 & 0xff,
+  0xa7 & 0xff,
+  0xa6 & 0xff,
+  0xa5 & 0xff,
+  0xa4 & 0xff,
+  0xa3 & 0xff,
+  0xa3 & 0xff,
+  0xa2 & 0xff,
+  0xa1 & 0xff,
+  0xa0 & 0xff,
+  0x9f & 0xff,
+  0x9f & 0xff,
+  0x9e & 0xff,
+  0x9d & 0xff,
+  0x9c & 0xff,
+  0x9c & 0xff,
+  0x9b & 0xff,
+  0x9a & 0xff,
+  0x99 & 0xff,
+  0x99 & 0xff,
+  0x98 & 0xff,
+  0x97 & 0xff,
+  0x97 & 0xff,
+  0x96 & 0xff,
+  0x95 & 0xff,
+  0x95 & 0xff,
+  0x94 & 0xff,
+  0x93 & 0xff,
+  0x93 & 0xff,
+  0x92 & 0xff,
+  0x91 & 0xff,
+  0x91 & 0xff,
+  0x90 & 0xff,
+  0x8f & 0xff,
+  0x8f & 0xff,
+  0x8e & 0xff,
+  0x8e & 0xff,
+  0x8d & 0xff,
+  0x8c & 0xff,
+  0x8c & 0xff,
+  0x8b & 0xff,
+  0x8b & 0xff,
+  0x8a & 0xff,
+  0x89 & 0xff,
+  0x89 & 0xff,
+  0x88 & 0xff,
+  0x88 & 0xff,
+  0x87 & 0xff,
+  0x87 & 0xff,
+  0x86 & 0xff,
+  0x85 & 0xff,
+  0x85 & 0xff,
+  0x84 & 0xff,
+  0x84 & 0xff,
+  0x83 & 0xff,
+  0x83 & 0xff,
+  0x82 & 0xff,
+  0x82 & 0xff,
+  0x81 & 0xff,
+  0x81 & 0xff,
+  0x81 & 0xff,
+  0
+};
+
+/* constant table RSQRT_Data8 */
+static const unsigned CONST_TBL_RSQRT_Data8_0[] = {
+  0xb4 & 0xff,
+  0xb3 & 0xff,
+  0xb2 & 0xff,
+  0xb0 & 0xff,
+  0xaf & 0xff,
+  0xae & 0xff,
+  0xac & 0xff,
+  0xab & 0xff,
+  0xaa & 0xff,
+  0xa9 & 0xff,
+  0xa8 & 0xff,
+  0xa7 & 0xff,
+  0xa6 & 0xff,
+  0xa5 & 0xff,
+  0xa3 & 0xff,
+  0xa2 & 0xff,
+  0xa1 & 0xff,
+  0xa0 & 0xff,
+  0x9f & 0xff,
+  0x9e & 0xff,
+  0x9e & 0xff,
+  0x9d & 0xff,
+  0x9c & 0xff,
+  0x9b & 0xff,
+  0x9a & 0xff,
+  0x99 & 0xff,
+  0x98 & 0xff,
+  0x97 & 0xff,
+  0x97 & 0xff,
+  0x96 & 0xff,
+  0x95 & 0xff,
+  0x94 & 0xff,
+  0x93 & 0xff,
+  0x93 & 0xff,
+  0x92 & 0xff,
+  0x91 & 0xff,
+  0x90 & 0xff,
+  0x90 & 0xff,
+  0x8f & 0xff,
+  0x8e & 0xff,
+  0x8e & 0xff,
+  0x8d & 0xff,
+  0x8c & 0xff,
+  0x8c & 0xff,
+  0x8b & 0xff,
+  0x8a & 0xff,
+  0x8a & 0xff,
+  0x89 & 0xff,
+  0x89 & 0xff,
+  0x88 & 0xff,
+  0x87 & 0xff,
+  0x87 & 0xff,
+  0x86 & 0xff,
+  0x86 & 0xff,
+  0x85 & 0xff,
+  0x84 & 0xff,
+  0x84 & 0xff,
+  0x83 & 0xff,
+  0x83 & 0xff,
+  0x82 & 0xff,
+  0x82 & 0xff,
+  0x81 & 0xff,
+  0x81 & 0xff,
+  0x80 & 0xff,
+  0xff & 0xff,
+  0xfd & 0xff,
+  0xfb & 0xff,
+  0xf9 & 0xff,
+  0xf7 & 0xff,
+  0xf6 & 0xff,
+  0xf4 & 0xff,
+  0xf2 & 0xff,
+  0xf1 & 0xff,
+  0xef & 0xff,
+  0xed & 0xff,
+  0xec & 0xff,
+  0xea & 0xff,
+  0xe9 & 0xff,
+  0xe7 & 0xff,
+  0xe6 & 0xff,
+  0xe4 & 0xff,
+  0xe3 & 0xff,
+  0xe1 & 0xff,
+  0xe0 & 0xff,
+  0xdf & 0xff,
+  0xdd & 0xff,
+  0xdc & 0xff,
+  0xdb & 0xff,
+  0xda & 0xff,
+  0xd8 & 0xff,
+  0xd7 & 0xff,
+  0xd6 & 0xff,
+  0xd5 & 0xff,
+  0xd4 & 0xff,
+  0xd3 & 0xff,
+  0xd2 & 0xff,
+  0xd0 & 0xff,
+  0xcf & 0xff,
+  0xce & 0xff,
+  0xcd & 0xff,
+  0xcc & 0xff,
+  0xcb & 0xff,
+  0xca & 0xff,
+  0xc9 & 0xff,
+  0xc8 & 0xff,
+  0xc7 & 0xff,
+  0xc6 & 0xff,
+  0xc6 & 0xff,
+  0xc5 & 0xff,
+  0xc4 & 0xff,
+  0xc3 & 0xff,
+  0xc2 & 0xff,
+  0xc1 & 0xff,
+  0xc0 & 0xff,
+  0xbf & 0xff,
+  0xbf & 0xff,
+  0xbe & 0xff,
+  0xbd & 0xff,
+  0xbc & 0xff,
+  0xbb & 0xff,
+  0xbb & 0xff,
+  0xba & 0xff,
+  0xb9 & 0xff,
+  0xb8 & 0xff,
+  0xb8 & 0xff,
+  0xb7 & 0xff,
+  0xb6 & 0xff,
+  0xb5 & 0xff,
+  0
+};
+
+/* constant table RECIP_Data10_2 */
+static const unsigned CONST_TBL_RECIP_Data10_2_0[] = {
+  0x3fc & 0x3ff,
+  0x3f4 & 0x3ff,
+  0x3ec & 0x3ff,
+  0x3e5 & 0x3ff,
+  0x3dd & 0x3ff,
+  0x3d6 & 0x3ff,
+  0x3cf & 0x3ff,
+  0x3c7 & 0x3ff,
+  0x3c0 & 0x3ff,
+  0x3b9 & 0x3ff,
+  0x3b2 & 0x3ff,
+  0x3ac & 0x3ff,
+  0x3a5 & 0x3ff,
+  0x39e & 0x3ff,
+  0x398 & 0x3ff,
+  0x391 & 0x3ff,
+  0x38b & 0x3ff,
+  0x385 & 0x3ff,
+  0x37f & 0x3ff,
+  0x378 & 0x3ff,
+  0x373 & 0x3ff,
+  0x36c & 0x3ff,
+  0x367 & 0x3ff,
+  0x361 & 0x3ff,
+  0x35c & 0x3ff,
+  0x356 & 0x3ff,
+  0x350 & 0x3ff,
+  0x34b & 0x3ff,
+  0x345 & 0x3ff,
+  0x340 & 0x3ff,
+  0x33b & 0x3ff,
+  0x335 & 0x3ff,
+  0x330 & 0x3ff,
+  0x32c & 0x3ff,
+  0x327 & 0x3ff,
+  0x322 & 0x3ff,
+  0x31c & 0x3ff,
+  0x318 & 0x3ff,
+  0x314 & 0x3ff,
+  0x30e & 0x3ff,
+  0x30a & 0x3ff,
+  0x306 & 0x3ff,
+  0x300 & 0x3ff,
+  0x2fc & 0x3ff,
+  0x2f8 & 0x3ff,
+  0x2f4 & 0x3ff,
+  0x2f0 & 0x3ff,
+  0x2ea & 0x3ff,
+  0x2e6 & 0x3ff,
+  0x2e2 & 0x3ff,
+  0x2de & 0x3ff,
+  0x2da & 0x3ff,
+  0x2d6 & 0x3ff,
+  0x2d2 & 0x3ff,
+  0x2ce & 0x3ff,
+  0x2ca & 0x3ff,
+  0x2c6 & 0x3ff,
+  0x2c2 & 0x3ff,
+  0x2be & 0x3ff,
+  0x2ba & 0x3ff,
+  0x2b8 & 0x3ff,
+  0x2b4 & 0x3ff,
+  0x2b0 & 0x3ff,
+  0x2ac & 0x3ff,
+  0x2a8 & 0x3ff,
+  0x2a6 & 0x3ff,
+  0x2a2 & 0x3ff,
+  0x29e & 0x3ff,
+  0x29c & 0x3ff,
+  0x298 & 0x3ff,
+  0x294 & 0x3ff,
+  0x290 & 0x3ff,
+  0x28e & 0x3ff,
+  0x28a & 0x3ff,
+  0x288 & 0x3ff,
+  0x284 & 0x3ff,
+  0x280 & 0x3ff,
+  0x27e & 0x3ff,
+  0x27a & 0x3ff,
+  0x278 & 0x3ff,
+  0x274 & 0x3ff,
+  0x272 & 0x3ff,
+  0x26e & 0x3ff,
+  0x26c & 0x3ff,
+  0x268 & 0x3ff,
+  0x266 & 0x3ff,
+  0x264 & 0x3ff,
+  0x260 & 0x3ff,
+  0x25e & 0x3ff,
+  0x25a & 0x3ff,
+  0x258 & 0x3ff,
+  0x254 & 0x3ff,
+  0x252 & 0x3ff,
+  0x250 & 0x3ff,
+  0x24c & 0x3ff,
+  0x24a & 0x3ff,
+  0x248 & 0x3ff,
+  0x246 & 0x3ff,
+  0x242 & 0x3ff,
+  0x240 & 0x3ff,
+  0x23e & 0x3ff,
+  0x23c & 0x3ff,
+  0x238 & 0x3ff,
+  0x236 & 0x3ff,
+  0x234 & 0x3ff,
+  0x232 & 0x3ff,
+  0x230 & 0x3ff,
+  0x22c & 0x3ff,
+  0x22a & 0x3ff,
+  0x228 & 0x3ff,
+  0x226 & 0x3ff,
+  0x224 & 0x3ff,
+  0x220 & 0x3ff,
+  0x21e & 0x3ff,
+  0x21c & 0x3ff,
+  0x21a & 0x3ff,
+  0x218 & 0x3ff,
+  0x216 & 0x3ff,
+  0x214 & 0x3ff,
+  0x212 & 0x3ff,
+  0x210 & 0x3ff,
+  0x20e & 0x3ff,
+  0x20c & 0x3ff,
+  0x208 & 0x3ff,
+  0x208 & 0x3ff,
+  0x204 & 0x3ff,
+  0x204 & 0x3ff,
+  0x201 & 0x3ff,
+  0
+};
+
+/* constant table RSQRT_10b_256 */
+static const unsigned CONST_TBL_RSQRT_10b_256_0[] = {
+  0x1a5 & 0x3ff,
+  0x1a0 & 0x3ff,
+  0x19a & 0x3ff,
+  0x195 & 0x3ff,
+  0x18f & 0x3ff,
+  0x18a & 0x3ff,
+  0x185 & 0x3ff,
+  0x180 & 0x3ff,
+  0x17a & 0x3ff,
+  0x175 & 0x3ff,
+  0x170 & 0x3ff,
+  0x16b & 0x3ff,
+  0x166 & 0x3ff,
+  0x161 & 0x3ff,
+  0x15d & 0x3ff,
+  0x158 & 0x3ff,
+  0x153 & 0x3ff,
+  0x14e & 0x3ff,
+  0x14a & 0x3ff,
+  0x145 & 0x3ff,
+  0x140 & 0x3ff,
+  0x13c & 0x3ff,
+  0x138 & 0x3ff,
+  0x133 & 0x3ff,
+  0x12f & 0x3ff,
+  0x12a & 0x3ff,
+  0x126 & 0x3ff,
+  0x122 & 0x3ff,
+  0x11e & 0x3ff,
+  0x11a & 0x3ff,
+  0x115 & 0x3ff,
+  0x111 & 0x3ff,
+  0x10d & 0x3ff,
+  0x109 & 0x3ff,
+  0x105 & 0x3ff,
+  0x101 & 0x3ff,
+  0xfd & 0x3ff,
+  0xfa & 0x3ff,
+  0xf6 & 0x3ff,
+  0xf2 & 0x3ff,
+  0xee & 0x3ff,
+  0xea & 0x3ff,
+  0xe7 & 0x3ff,
+  0xe3 & 0x3ff,
+  0xdf & 0x3ff,
+  0xdc & 0x3ff,
+  0xd8 & 0x3ff,
+  0xd5 & 0x3ff,
+  0xd1 & 0x3ff,
+  0xce & 0x3ff,
+  0xca & 0x3ff,
+  0xc7 & 0x3ff,
+  0xc3 & 0x3ff,
+  0xc0 & 0x3ff,
+  0xbd & 0x3ff,
+  0xb9 & 0x3ff,
+  0xb6 & 0x3ff,
+  0xb3 & 0x3ff,
+  0xb0 & 0x3ff,
+  0xad & 0x3ff,
+  0xa9 & 0x3ff,
+  0xa6 & 0x3ff,
+  0xa3 & 0x3ff,
+  0xa0 & 0x3ff,
+  0x9d & 0x3ff,
+  0x9a & 0x3ff,
+  0x97 & 0x3ff,
+  0x94 & 0x3ff,
+  0x91 & 0x3ff,
+  0x8e & 0x3ff,
+  0x8b & 0x3ff,
+  0x88 & 0x3ff,
+  0x85 & 0x3ff,
+  0x82 & 0x3ff,
+  0x7f & 0x3ff,
+  0x7d & 0x3ff,
+  0x7a & 0x3ff,
+  0x77 & 0x3ff,
+  0x74 & 0x3ff,
+  0x71 & 0x3ff,
+  0x6f & 0x3ff,
+  0x6c & 0x3ff,
+  0x69 & 0x3ff,
+  0x67 & 0x3ff,
+  0x64 & 0x3ff,
+  0x61 & 0x3ff,
+  0x5f & 0x3ff,
+  0x5c & 0x3ff,
+  0x5a & 0x3ff,
+  0x57 & 0x3ff,
+  0x54 & 0x3ff,
+  0x52 & 0x3ff,
+  0x4f & 0x3ff,
+  0x4d & 0x3ff,
+  0x4a & 0x3ff,
+  0x48 & 0x3ff,
+  0x45 & 0x3ff,
+  0x43 & 0x3ff,
+  0x41 & 0x3ff,
+  0x3e & 0x3ff,
+  0x3c & 0x3ff,
+  0x3a & 0x3ff,
+  0x37 & 0x3ff,
+  0x35 & 0x3ff,
+  0x33 & 0x3ff,
+  0x30 & 0x3ff,
+  0x2e & 0x3ff,
+  0x2c & 0x3ff,
+  0x29 & 0x3ff,
+  0x27 & 0x3ff,
+  0x25 & 0x3ff,
+  0x23 & 0x3ff,
+  0x20 & 0x3ff,
+  0x1e & 0x3ff,
+  0x1c & 0x3ff,
+  0x1a & 0x3ff,
+  0x18 & 0x3ff,
+  0x16 & 0x3ff,
+  0x14 & 0x3ff,
+  0x11 & 0x3ff,
+  0xf & 0x3ff,
+  0xd & 0x3ff,
+  0xb & 0x3ff,
+  0x9 & 0x3ff,
+  0x7 & 0x3ff,
+  0x5 & 0x3ff,
+  0x3 & 0x3ff,
+  0x1 & 0x3ff,
+  0x3fc & 0x3ff,
+  0x3f4 & 0x3ff,
+  0x3ec & 0x3ff,
+  0x3e5 & 0x3ff,
+  0x3dd & 0x3ff,
+  0x3d5 & 0x3ff,
+  0x3ce & 0x3ff,
+  0x3c7 & 0x3ff,
+  0x3bf & 0x3ff,
+  0x3b8 & 0x3ff,
+  0x3b1 & 0x3ff,
+  0x3aa & 0x3ff,
+  0x3a3 & 0x3ff,
+  0x39c & 0x3ff,
+  0x395 & 0x3ff,
+  0x38e & 0x3ff,
+  0x388 & 0x3ff,
+  0x381 & 0x3ff,
+  0x37a & 0x3ff,
+  0x374 & 0x3ff,
+  0x36d & 0x3ff,
+  0x367 & 0x3ff,
+  0x361 & 0x3ff,
+  0x35a & 0x3ff,
+  0x354 & 0x3ff,
+  0x34e & 0x3ff,
+  0x348 & 0x3ff,
+  0x342 & 0x3ff,
+  0x33c & 0x3ff,
+  0x336 & 0x3ff,
+  0x330 & 0x3ff,
+  0x32b & 0x3ff,
+  0x325 & 0x3ff,
+  0x31f & 0x3ff,
+  0x31a & 0x3ff,
+  0x314 & 0x3ff,
+  0x30f & 0x3ff,
+  0x309 & 0x3ff,
+  0x304 & 0x3ff,
+  0x2fe & 0x3ff,
+  0x2f9 & 0x3ff,
+  0x2f4 & 0x3ff,
+  0x2ee & 0x3ff,
+  0x2e9 & 0x3ff,
+  0x2e4 & 0x3ff,
+  0x2df & 0x3ff,
+  0x2da & 0x3ff,
+  0x2d5 & 0x3ff,
+  0x2d0 & 0x3ff,
+  0x2cb & 0x3ff,
+  0x2c6 & 0x3ff,
+  0x2c1 & 0x3ff,
+  0x2bd & 0x3ff,
+  0x2b8 & 0x3ff,
+  0x2b3 & 0x3ff,
+  0x2ae & 0x3ff,
+  0x2aa & 0x3ff,
+  0x2a5 & 0x3ff,
+  0x2a1 & 0x3ff,
+  0x29c & 0x3ff,
+  0x298 & 0x3ff,
+  0x293 & 0x3ff,
+  0x28f & 0x3ff,
+  0x28a & 0x3ff,
+  0x286 & 0x3ff,
+  0x282 & 0x3ff,
+  0x27d & 0x3ff,
+  0x279 & 0x3ff,
+  0x275 & 0x3ff,
+  0x271 & 0x3ff,
+  0x26d & 0x3ff,
+  0x268 & 0x3ff,
+  0x264 & 0x3ff,
+  0x260 & 0x3ff,
+  0x25c & 0x3ff,
+  0x258 & 0x3ff,
+  0x254 & 0x3ff,
+  0x250 & 0x3ff,
+  0x24c & 0x3ff,
+  0x249 & 0x3ff,
+  0x245 & 0x3ff,
+  0x241 & 0x3ff,
+  0x23d & 0x3ff,
+  0x239 & 0x3ff,
+  0x235 & 0x3ff,
+  0x232 & 0x3ff,
+  0x22e & 0x3ff,
+  0x22a & 0x3ff,
+  0x227 & 0x3ff,
+  0x223 & 0x3ff,
+  0x220 & 0x3ff,
+  0x21c & 0x3ff,
+  0x218 & 0x3ff,
+  0x215 & 0x3ff,
+  0x211 & 0x3ff,
+  0x20e & 0x3ff,
+  0x20a & 0x3ff,
+  0x207 & 0x3ff,
+  0x204 & 0x3ff,
+  0x200 & 0x3ff,
+  0x1fd & 0x3ff,
+  0x1f9 & 0x3ff,
+  0x1f6 & 0x3ff,
+  0x1f3 & 0x3ff,
+  0x1f0 & 0x3ff,
+  0x1ec & 0x3ff,
+  0x1e9 & 0x3ff,
+  0x1e6 & 0x3ff,
+  0x1e3 & 0x3ff,
+  0x1df & 0x3ff,
+  0x1dc & 0x3ff,
+  0x1d9 & 0x3ff,
+  0x1d6 & 0x3ff,
+  0x1d3 & 0x3ff,
+  0x1d0 & 0x3ff,
+  0x1cd & 0x3ff,
+  0x1ca & 0x3ff,
+  0x1c7 & 0x3ff,
+  0x1c4 & 0x3ff,
+  0x1c1 & 0x3ff,
+  0x1be & 0x3ff,
+  0x1bb & 0x3ff,
+  0x1b8 & 0x3ff,
+  0x1b5 & 0x3ff,
+  0x1b2 & 0x3ff,
+  0x1af & 0x3ff,
+  0x1ac & 0x3ff,
+  0x1aa & 0x3ff,
+  0
+};
+
+/* constant table RECIP_10b_256 */
+static const unsigned CONST_TBL_RECIP_10b_256_0[] = {
+  0x3fc & 0x3ff,
+  0x3f4 & 0x3ff,
+  0x3ec & 0x3ff,
+  0x3e4 & 0x3ff,
+  0x3dd & 0x3ff,
+  0x3d5 & 0x3ff,
+  0x3cd & 0x3ff,
+  0x3c6 & 0x3ff,
+  0x3be & 0x3ff,
+  0x3b7 & 0x3ff,
+  0x3af & 0x3ff,
+  0x3a8 & 0x3ff,
+  0x3a1 & 0x3ff,
+  0x399 & 0x3ff,
+  0x392 & 0x3ff,
+  0x38b & 0x3ff,
+  0x384 & 0x3ff,
+  0x37d & 0x3ff,
+  0x376 & 0x3ff,
+  0x36f & 0x3ff,
+  0x368 & 0x3ff,
+  0x361 & 0x3ff,
+  0x35b & 0x3ff,
+  0x354 & 0x3ff,
+  0x34d & 0x3ff,
+  0x346 & 0x3ff,
+  0x340 & 0x3ff,
+  0x339 & 0x3ff,
+  0x333 & 0x3ff,
+  0x32c & 0x3ff,
+  0x326 & 0x3ff,
+  0x320 & 0x3ff,
+  0x319 & 0x3ff,
+  0x313 & 0x3ff,
+  0x30d & 0x3ff,
+  0x307 & 0x3ff,
+  0x300 & 0x3ff,
+  0x2fa & 0x3ff,
+  0x2f4 & 0x3ff,
+  0x2ee & 0x3ff,
+  0x2e8 & 0x3ff,
+  0x2e2 & 0x3ff,
+  0x2dc & 0x3ff,
+  0x2d7 & 0x3ff,
+  0x2d1 & 0x3ff,
+  0x2cb & 0x3ff,
+  0x2c5 & 0x3ff,
+  0x2bf & 0x3ff,
+  0x2ba & 0x3ff,
+  0x2b4 & 0x3ff,
+  0x2af & 0x3ff,
+  0x2a9 & 0x3ff,
+  0x2a3 & 0x3ff,
+  0x29e & 0x3ff,
+  0x299 & 0x3ff,
+  0x293 & 0x3ff,
+  0x28e & 0x3ff,
+  0x288 & 0x3ff,
+  0x283 & 0x3ff,
+  0x27e & 0x3ff,
+  0x279 & 0x3ff,
+  0x273 & 0x3ff,
+  0x26e & 0x3ff,
+  0x269 & 0x3ff,
+  0x264 & 0x3ff,
+  0x25f & 0x3ff,
+  0x25a & 0x3ff,
+  0x255 & 0x3ff,
+  0x250 & 0x3ff,
+  0x24b & 0x3ff,
+  0x246 & 0x3ff,
+  0x241 & 0x3ff,
+  0x23c & 0x3ff,
+  0x237 & 0x3ff,
+  0x232 & 0x3ff,
+  0x22e & 0x3ff,
+  0x229 & 0x3ff,
+  0x224 & 0x3ff,
+  0x21f & 0x3ff,
+  0x21b & 0x3ff,
+  0x216 & 0x3ff,
+  0x211 & 0x3ff,
+  0x20d & 0x3ff,
+  0x208 & 0x3ff,
+  0x204 & 0x3ff,
+  0x1ff & 0x3ff,
+  0x1fb & 0x3ff,
+  0x1f6 & 0x3ff,
+  0x1f2 & 0x3ff,
+  0x1ed & 0x3ff,
+  0x1e9 & 0x3ff,
+  0x1e5 & 0x3ff,
+  0x1e0 & 0x3ff,
+  0x1dc & 0x3ff,
+  0x1d8 & 0x3ff,
+  0x1d4 & 0x3ff,
+  0x1cf & 0x3ff,
+  0x1cb & 0x3ff,
+  0x1c7 & 0x3ff,
+  0x1c3 & 0x3ff,
+  0x1bf & 0x3ff,
+  0x1bb & 0x3ff,
+  0x1b6 & 0x3ff,
+  0x1b2 & 0x3ff,
+  0x1ae & 0x3ff,
+  0x1aa & 0x3ff,
+  0x1a6 & 0x3ff,
+  0x1a2 & 0x3ff,
+  0x19e & 0x3ff,
+  0x19a & 0x3ff,
+  0x197 & 0x3ff,
+  0x193 & 0x3ff,
+  0x18f & 0x3ff,
+  0x18b & 0x3ff,
+  0x187 & 0x3ff,
+  0x183 & 0x3ff,
+  0x17f & 0x3ff,
+  0x17c & 0x3ff,
+  0x178 & 0x3ff,
+  0x174 & 0x3ff,
+  0x171 & 0x3ff,
+  0x16d & 0x3ff,
+  0x169 & 0x3ff,
+  0x166 & 0x3ff,
+  0x162 & 0x3ff,
+  0x15e & 0x3ff,
+  0x15b & 0x3ff,
+  0x157 & 0x3ff,
+  0x154 & 0x3ff,
+  0x150 & 0x3ff,
+  0x14d & 0x3ff,
+  0x149 & 0x3ff,
+  0x146 & 0x3ff,
+  0x142 & 0x3ff,
+  0x13f & 0x3ff,
+  0x13b & 0x3ff,
+  0x138 & 0x3ff,
+  0x134 & 0x3ff,
+  0x131 & 0x3ff,
+  0x12e & 0x3ff,
+  0x12a & 0x3ff,
+  0x127 & 0x3ff,
+  0x124 & 0x3ff,
+  0x120 & 0x3ff,
+  0x11d & 0x3ff,
+  0x11a & 0x3ff,
+  0x117 & 0x3ff,
+  0x113 & 0x3ff,
+  0x110 & 0x3ff,
+  0x10d & 0x3ff,
+  0x10a & 0x3ff,
+  0x107 & 0x3ff,
+  0x103 & 0x3ff,
+  0x100 & 0x3ff,
+  0xfd & 0x3ff,
+  0xfa & 0x3ff,
+  0xf7 & 0x3ff,
+  0xf4 & 0x3ff,
+  0xf1 & 0x3ff,
+  0xee & 0x3ff,
+  0xeb & 0x3ff,
+  0xe8 & 0x3ff,
+  0xe5 & 0x3ff,
+  0xe2 & 0x3ff,
+  0xdf & 0x3ff,
+  0xdc & 0x3ff,
+  0xd9 & 0x3ff,
+  0xd6 & 0x3ff,
+  0xd3 & 0x3ff,
+  0xd0 & 0x3ff,
+  0xcd & 0x3ff,
+  0xca & 0x3ff,
+  0xc8 & 0x3ff,
+  0xc5 & 0x3ff,
+  0xc2 & 0x3ff,
+  0xbf & 0x3ff,
+  0xbc & 0x3ff,
+  0xb9 & 0x3ff,
+  0xb7 & 0x3ff,
+  0xb4 & 0x3ff,
+  0xb1 & 0x3ff,
+  0xae & 0x3ff,
+  0xac & 0x3ff,
+  0xa9 & 0x3ff,
+  0xa6 & 0x3ff,
+  0xa4 & 0x3ff,
+  0xa1 & 0x3ff,
+  0x9e & 0x3ff,
+  0x9c & 0x3ff,
+  0x99 & 0x3ff,
+  0x96 & 0x3ff,
+  0x94 & 0x3ff,
+  0x91 & 0x3ff,
+  0x8e & 0x3ff,
+  0x8c & 0x3ff,
+  0x89 & 0x3ff,
+  0x87 & 0x3ff,
+  0x84 & 0x3ff,
+  0x82 & 0x3ff,
+  0x7f & 0x3ff,
+  0x7c & 0x3ff,
+  0x7a & 0x3ff,
+  0x77 & 0x3ff,
+  0x75 & 0x3ff,
+  0x73 & 0x3ff,
+  0x70 & 0x3ff,
+  0x6e & 0x3ff,
+  0x6b & 0x3ff,
+  0x69 & 0x3ff,
+  0x66 & 0x3ff,
+  0x64 & 0x3ff,
+  0x61 & 0x3ff,
+  0x5f & 0x3ff,
+  0x5d & 0x3ff,
+  0x5a & 0x3ff,
+  0x58 & 0x3ff,
+  0x56 & 0x3ff,
+  0x53 & 0x3ff,
+  0x51 & 0x3ff,
+  0x4f & 0x3ff,
+  0x4c & 0x3ff,
+  0x4a & 0x3ff,
+  0x48 & 0x3ff,
+  0x45 & 0x3ff,
+  0x43 & 0x3ff,
+  0x41 & 0x3ff,
+  0x3f & 0x3ff,
+  0x3c & 0x3ff,
+  0x3a & 0x3ff,
+  0x38 & 0x3ff,
+  0x36 & 0x3ff,
+  0x33 & 0x3ff,
+  0x31 & 0x3ff,
+  0x2f & 0x3ff,
+  0x2d & 0x3ff,
+  0x2b & 0x3ff,
+  0x29 & 0x3ff,
+  0x26 & 0x3ff,
+  0x24 & 0x3ff,
+  0x22 & 0x3ff,
+  0x20 & 0x3ff,
+  0x1e & 0x3ff,
+  0x1c & 0x3ff,
+  0x1a & 0x3ff,
+  0x18 & 0x3ff,
+  0x15 & 0x3ff,
+  0x13 & 0x3ff,
+  0x11 & 0x3ff,
+  0xf & 0x3ff,
+  0xd & 0x3ff,
+  0xb & 0x3ff,
+  0x9 & 0x3ff,
+  0x7 & 0x3ff,
+  0x5 & 0x3ff,
+  0x3 & 0x3ff,
+  0x1 & 0x3ff,
+  0
+};
+
+/* constant table addend */
+static const unsigned CONST_TBL_addend_0[] = {
+  0,
+  0x8,
+  0x10,
+  0x20,
+  0x28,
+  0x30,
+  0x80,
+  0x200,
+  0
+};
+
+/* constant table r4bf_tb */
+static const unsigned CONST_TBL_r4bf_tb_0[] = {
+  0,
+  0x10,
+  0
+};
+
+\f
+/* Instruction operands.  */
+
+static int
+OperandSem_opnd_sem_MR_0_decode (uint32 *valp)
+{
+  *valp += 2;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_0_encode (uint32 *valp)
+{
+  int error;
+  error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
+  *valp = *valp & 1;
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp)
+{
+  unsigned soffsetx4_out_0;
+  unsigned soffsetx4_in_0;
+  soffsetx4_in_0 = *valp & 0x3ffff;
+  soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
+  *valp = soffsetx4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp)
+{
+  unsigned soffsetx4_in_0;
+  unsigned soffsetx4_out_0;
+  soffsetx4_out_0 = *valp;
+  soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
+  *valp = soffsetx4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp)
+{
+  unsigned uimm12x8_out_0;
+  unsigned uimm12x8_in_0;
+  uimm12x8_in_0 = *valp & 0xfff;
+  uimm12x8_out_0 = uimm12x8_in_0 << 3;
+  *valp = uimm12x8_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp)
+{
+  unsigned uimm12x8_in_0;
+  unsigned uimm12x8_out_0;
+  uimm12x8_out_0 = *valp;
+  uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
+  *valp = uimm12x8_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm4_decode (uint32 *valp)
+{
+  unsigned simm4_out_0;
+  unsigned simm4_in_0;
+  simm4_in_0 = *valp & 0xf;
+  simm4_out_0 = ((int) simm4_in_0 << 28) >> 28;
+  *valp = simm4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm4_encode (uint32 *valp)
+{
+  unsigned simm4_in_0;
+  unsigned simm4_out_0;
+  simm4_out_0 = *valp;
+  simm4_in_0 = (simm4_out_0 & 0xf);
+  *valp = simm4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 64);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_0_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 64);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_1_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 64);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_2_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 64);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_3_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 64);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_AR_4_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 64);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_immrx4_decode (uint32 *valp)
+{
+  unsigned immrx4_out_0;
+  unsigned immrx4_in_0;
+  immrx4_in_0 = *valp & 0xf;
+  immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
+  *valp = immrx4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_immrx4_encode (uint32 *valp)
+{
+  unsigned immrx4_in_0;
+  unsigned immrx4_out_0;
+  immrx4_out_0 = *valp;
+  immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
+  *valp = immrx4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp)
+{
+  unsigned lsi4x4_out_0;
+  unsigned lsi4x4_in_0;
+  lsi4x4_in_0 = *valp & 0xf;
+  lsi4x4_out_0 = lsi4x4_in_0 << 2;
+  *valp = lsi4x4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp)
+{
+  unsigned lsi4x4_in_0;
+  unsigned lsi4x4_out_0;
+  lsi4x4_out_0 = *valp;
+  lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
+  *valp = lsi4x4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm7_decode (uint32 *valp)
+{
+  unsigned simm7_out_0;
+  unsigned simm7_in_0;
+  simm7_in_0 = *valp & 0x7f;
+  simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0;
+  *valp = simm7_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm7_encode (uint32 *valp)
+{
+  unsigned simm7_in_0;
+  unsigned simm7_out_0;
+  simm7_out_0 = *valp;
+  simm7_in_0 = (simm7_out_0 & 0x7f);
+  *valp = simm7_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm6_decode (uint32 *valp)
+{
+  unsigned uimm6_out_0;
+  unsigned uimm6_in_0;
+  uimm6_in_0 = *valp & 0x3f;
+  uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
+  *valp = uimm6_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm6_encode (uint32 *valp)
+{
+  unsigned uimm6_in_0;
+  unsigned uimm6_out_0;
+  uimm6_out_0 = *valp;
+  uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
+  *valp = uimm6_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_ai4const_decode (uint32 *valp)
+{
+  unsigned ai4const_out_0;
+  unsigned ai4const_in_0;
+  ai4const_in_0 = *valp & 0xf;
+  ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
+  *valp = ai4const_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_ai4const_encode (uint32 *valp)
+{
+  unsigned ai4const_in_0;
+  unsigned ai4const_out_0;
+  ai4const_out_0 = *valp;
+  switch (ai4const_out_0)
+    {
+    case 0xffffffff: ai4const_in_0 = 0; break;
+    case 0x1: ai4const_in_0 = 0x1; break;
+    case 0x2: ai4const_in_0 = 0x2; break;
+    case 0x3: ai4const_in_0 = 0x3; break;
+    case 0x4: ai4const_in_0 = 0x4; break;
+    case 0x5: ai4const_in_0 = 0x5; break;
+    case 0x6: ai4const_in_0 = 0x6; break;
+    case 0x7: ai4const_in_0 = 0x7; break;
+    case 0x8: ai4const_in_0 = 0x8; break;
+    case 0x9: ai4const_in_0 = 0x9; break;
+    case 0xa: ai4const_in_0 = 0xa; break;
+    case 0xb: ai4const_in_0 = 0xb; break;
+    case 0xc: ai4const_in_0 = 0xc; break;
+    case 0xd: ai4const_in_0 = 0xd; break;
+    case 0xe: ai4const_in_0 = 0xe; break;
+    default: ai4const_in_0 = 0xf; break;
+    }
+  *valp = ai4const_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4const_decode (uint32 *valp)
+{
+  unsigned b4const_out_0;
+  unsigned b4const_in_0;
+  b4const_in_0 = *valp & 0xf;
+  b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
+  *valp = b4const_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4const_encode (uint32 *valp)
+{
+  unsigned b4const_in_0;
+  unsigned b4const_out_0;
+  b4const_out_0 = *valp;
+  switch (b4const_out_0)
+    {
+    case 0xffffffff: b4const_in_0 = 0; break;
+    case 0x1: b4const_in_0 = 0x1; break;
+    case 0x2: b4const_in_0 = 0x2; break;
+    case 0x3: b4const_in_0 = 0x3; break;
+    case 0x4: b4const_in_0 = 0x4; break;
+    case 0x5: b4const_in_0 = 0x5; break;
+    case 0x6: b4const_in_0 = 0x6; break;
+    case 0x7: b4const_in_0 = 0x7; break;
+    case 0x8: b4const_in_0 = 0x8; break;
+    case 0xa: b4const_in_0 = 0x9; break;
+    case 0xc: b4const_in_0 = 0xa; break;
+    case 0x10: b4const_in_0 = 0xb; break;
+    case 0x20: b4const_in_0 = 0xc; break;
+    case 0x40: b4const_in_0 = 0xd; break;
+    case 0x80: b4const_in_0 = 0xe; break;
+    default: b4const_in_0 = 0xf; break;
+    }
+  *valp = b4const_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4constu_decode (uint32 *valp)
+{
+  unsigned b4constu_out_0;
+  unsigned b4constu_in_0;
+  b4constu_in_0 = *valp & 0xf;
+  b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
+  *valp = b4constu_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4constu_encode (uint32 *valp)
+{
+  unsigned b4constu_in_0;
+  unsigned b4constu_out_0;
+  b4constu_out_0 = *valp;
+  switch (b4constu_out_0)
+    {
+    case 0x8000: b4constu_in_0 = 0; break;
+    case 0x10000: b4constu_in_0 = 0x1; break;
+    case 0x2: b4constu_in_0 = 0x2; break;
+    case 0x3: b4constu_in_0 = 0x3; break;
+    case 0x4: b4constu_in_0 = 0x4; break;
+    case 0x5: b4constu_in_0 = 0x5; break;
+    case 0x6: b4constu_in_0 = 0x6; break;
+    case 0x7: b4constu_in_0 = 0x7; break;
+    case 0x8: b4constu_in_0 = 0x8; break;
+    case 0xa: b4constu_in_0 = 0x9; break;
+    case 0xc: b4constu_in_0 = 0xa; break;
+    case 0x10: b4constu_in_0 = 0xb; break;
+    case 0x20: b4constu_in_0 = 0xc; break;
+    case 0x40: b4constu_in_0 = 0xd; break;
+    case 0x80: b4constu_in_0 = 0xe; break;
+    default: b4constu_in_0 = 0xf; break;
+    }
+  *valp = b4constu_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8_decode (uint32 *valp)
+{
+  unsigned uimm8_out_0;
+  unsigned uimm8_in_0;
+  uimm8_in_0 = *valp & 0xff;
+  uimm8_out_0 = uimm8_in_0;
+  *valp = uimm8_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8_encode (uint32 *valp)
+{
+  unsigned uimm8_in_0;
+  unsigned uimm8_out_0;
+  uimm8_out_0 = *valp;
+  uimm8_in_0 = (uimm8_out_0 & 0xff);
+  *valp = uimm8_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp)
+{
+  unsigned uimm8x2_out_0;
+  unsigned uimm8x2_in_0;
+  uimm8x2_in_0 = *valp & 0xff;
+  uimm8x2_out_0 = uimm8x2_in_0 << 1;
+  *valp = uimm8x2_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp)
+{
+  unsigned uimm8x2_in_0;
+  unsigned uimm8x2_out_0;
+  uimm8x2_out_0 = *valp;
+  uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
+  *valp = uimm8x2_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp)
+{
+  unsigned uimm8x4_out_0;
+  unsigned uimm8x4_in_0;
+  uimm8x4_in_0 = *valp & 0xff;
+  uimm8x4_out_0 = uimm8x4_in_0 << 2;
+  *valp = uimm8x4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp)
+{
+  unsigned uimm8x4_in_0;
+  unsigned uimm8x4_out_0;
+  uimm8x4_out_0 = *valp;
+  uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
+  *valp = uimm8x4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp)
+{
+  unsigned uimm4x16_out_0;
+  unsigned uimm4x16_in_0;
+  uimm4x16_in_0 = *valp & 0xf;
+  uimm4x16_out_0 = uimm4x16_in_0 << 4;
+  *valp = uimm4x16_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp)
+{
+  unsigned uimm4x16_in_0;
+  unsigned uimm4x16_out_0;
+  uimm4x16_out_0 = *valp;
+  uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
+  *valp = uimm4x16_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp)
+{
+  unsigned uimmrx4_out_0;
+  unsigned uimmrx4_in_0;
+  uimmrx4_in_0 = *valp & 0xf;
+  uimmrx4_out_0 = uimmrx4_in_0 << 2;
+  *valp = uimmrx4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp)
+{
+  unsigned uimmrx4_in_0;
+  unsigned uimmrx4_out_0;
+  uimmrx4_out_0 = *valp;
+  uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf);
+  *valp = uimmrx4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8_decode (uint32 *valp)
+{
+  unsigned simm8_out_0;
+  unsigned simm8_in_0;
+  simm8_in_0 = *valp & 0xff;
+  simm8_out_0 = ((int) simm8_in_0 << 24) >> 24;
+  *valp = simm8_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8_encode (uint32 *valp)
+{
+  unsigned simm8_in_0;
+  unsigned simm8_out_0;
+  simm8_out_0 = *valp;
+  simm8_in_0 = (simm8_out_0 & 0xff);
+  *valp = simm8_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8x256_decode (uint32 *valp)
+{
+  unsigned simm8x256_out_0;
+  unsigned simm8x256_in_0;
+  simm8x256_in_0 = *valp & 0xff;
+  simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8;
+  *valp = simm8x256_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8x256_encode (uint32 *valp)
+{
+  unsigned simm8x256_in_0;
+  unsigned simm8x256_out_0;
+  simm8x256_out_0 = *valp;
+  simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
+  *valp = simm8x256_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm12b_decode (uint32 *valp)
+{
+  unsigned simm12b_out_0;
+  unsigned simm12b_in_0;
+  simm12b_in_0 = *valp & 0xfff;
+  simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20;
+  *valp = simm12b_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm12b_encode (uint32 *valp)
+{
+  unsigned simm12b_in_0;
+  unsigned simm12b_out_0;
+  simm12b_out_0 = *valp;
+  simm12b_in_0 = (simm12b_out_0 & 0xfff);
+  *valp = simm12b_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_msalp32_decode (uint32 *valp)
+{
+  unsigned msalp32_out_0;
+  unsigned msalp32_in_0;
+  msalp32_in_0 = *valp & 0x1f;
+  msalp32_out_0 = 0x20 - msalp32_in_0;
+  *valp = msalp32_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_msalp32_encode (uint32 *valp)
+{
+  unsigned msalp32_in_0;
+  unsigned msalp32_out_0;
+  msalp32_out_0 = *valp;
+  msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
+  *valp = msalp32_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_op2p1_decode (uint32 *valp)
+{
+  unsigned op2p1_out_0;
+  unsigned op2p1_in_0;
+  op2p1_in_0 = *valp & 0xf;
+  op2p1_out_0 = op2p1_in_0 + 0x1;
+  *valp = op2p1_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_op2p1_encode (uint32 *valp)
+{
+  unsigned op2p1_in_0;
+  unsigned op2p1_out_0;
+  op2p1_out_0 = *valp;
+  op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
+  *valp = op2p1_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_label8_decode (uint32 *valp)
+{
+  unsigned label8_out_0;
+  unsigned label8_in_0;
+  label8_in_0 = *valp & 0xff;
+  label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
+  *valp = label8_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_label8_encode (uint32 *valp)
+{
+  unsigned label8_in_0;
+  unsigned label8_out_0;
+  label8_out_0 = *valp;
+  label8_in_0 = (label8_out_0 - 0x4) & 0xff;
+  *valp = label8_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_ulabel8_decode (uint32 *valp)
+{
+  unsigned ulabel8_out_0;
+  unsigned ulabel8_in_0;
+  ulabel8_in_0 = *valp & 0xff;
+  ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0);
+  *valp = ulabel8_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_ulabel8_encode (uint32 *valp)
+{
+  unsigned ulabel8_in_0;
+  unsigned ulabel8_out_0;
+  ulabel8_out_0 = *valp;
+  ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff;
+  *valp = ulabel8_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_label12_decode (uint32 *valp)
+{
+  unsigned label12_out_0;
+  unsigned label12_in_0;
+  label12_in_0 = *valp & 0xfff;
+  label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
+  *valp = label12_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_label12_encode (uint32 *valp)
+{
+  unsigned label12_in_0;
+  unsigned label12_out_0;
+  label12_out_0 = *valp;
+  label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
+  *valp = label12_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffset_decode (uint32 *valp)
+{
+  unsigned soffset_out_0;
+  unsigned soffset_in_0;
+  soffset_in_0 = *valp & 0x3ffff;
+  soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
+  *valp = soffset_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffset_encode (uint32 *valp)
+{
+  unsigned soffset_in_0;
+  unsigned soffset_out_0;
+  soffset_out_0 = *valp;
+  soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
+  *valp = soffset_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp)
+{
+  unsigned uimm16x4_out_0;
+  unsigned uimm16x4_in_0;
+  uimm16x4_in_0 = *valp & 0xffff;
+  uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
+  *valp = uimm16x4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp)
+{
+  unsigned uimm16x4_in_0;
+  unsigned uimm16x4_out_0;
+  uimm16x4_out_0 = *valp;
+  uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
+  *valp = uimm16x4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_bbi_decode (uint32 *valp)
+{
+  unsigned bbi_out_0;
+  unsigned bbi_in_0;
+  bbi_in_0 = *valp & 0x1f;
+  bbi_out_0 = (0 << 5) | bbi_in_0;
+  *valp = bbi_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_bbi_encode (uint32 *valp)
+{
+  unsigned bbi_in_0;
+  unsigned bbi_out_0;
+  bbi_out_0 = *valp;
+  bbi_in_0 = (bbi_out_0 & 0x1f);
+  *valp = bbi_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_s_decode (uint32 *valp)
+{
+  unsigned s_out_0;
+  unsigned s_in_0;
+  s_in_0 = *valp & 0xf;
+  s_out_0 = (0 << 4) | s_in_0;
+  *valp = s_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_s_encode (uint32 *valp)
+{
+  unsigned s_in_0;
+  unsigned s_out_0;
+  s_out_0 = *valp;
+  s_in_0 = (s_out_0 & 0xf);
+  *valp = s_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 4);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_MR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_1_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 4);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_MR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_2_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 4);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_MR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_3_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 4);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_MR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_4_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 4);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_MR_5_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_MR_5_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 4);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_immt_decode (uint32 *valp)
+{
+  unsigned immt_out_0;
+  unsigned immt_in_0;
+  immt_in_0 = *valp & 0xf;
+  immt_out_0 = immt_in_0;
+  *valp = immt_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_immt_encode (uint32 *valp)
+{
+  unsigned immt_in_0;
+  unsigned immt_out_0;
+  immt_out_0 = *valp;
+  immt_in_0 = immt_out_0 & 0xf;
+  *valp = immt_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 16);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_BR2_decode (uint32 *valp)
+{
+  *valp = *valp << 1;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR2_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 16) || ((*valp & 1) != 0);
+  *valp = *valp >> 1;
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_BR4_decode (uint32 *valp)
+{
+  *valp = *valp << 2;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR4_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 16) || ((*valp & 3) != 0);
+  *valp = *valp >> 2;
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_BR8_decode (uint32 *valp)
+{
+  *valp = *valp << 3;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR8_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 16) || ((*valp & 7) != 0);
+  *valp = *valp >> 3;
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_BR16_decode (uint32 *valp)
+{
+  *valp = *valp << 4;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR16_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 16) || ((*valp & 15) != 0);
+  *valp = *valp >> 4;
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_tp7_decode (uint32 *valp)
+{
+  unsigned tp7_out_0;
+  unsigned tp7_in_0;
+  tp7_in_0 = *valp & 0xf;
+  tp7_out_0 = tp7_in_0 + 0x7;
+  *valp = tp7_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_tp7_encode (uint32 *valp)
+{
+  unsigned tp7_in_0;
+  unsigned tp7_out_0;
+  tp7_out_0 = *valp;
+  tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
+  *valp = tp7_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp)
+{
+  unsigned xt_wbr15_label_out_0;
+  unsigned xt_wbr15_label_in_0;
+  xt_wbr15_label_in_0 = *valp & 0x7fff;
+  xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
+  *valp = xt_wbr15_label_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp)
+{
+  unsigned xt_wbr15_label_in_0;
+  unsigned xt_wbr15_label_out_0;
+  xt_wbr15_label_out_0 = *valp;
+  xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
+  *valp = xt_wbr15_label_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp)
+{
+  unsigned xt_wbr18_label_out_0;
+  unsigned xt_wbr18_label_in_0;
+  xt_wbr18_label_in_0 = *valp & 0x3ffff;
+  xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14);
+  *valp = xt_wbr18_label_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp)
+{
+  unsigned xt_wbr18_label_in_0;
+  unsigned xt_wbr18_label_out_0;
+  xt_wbr18_label_out_0 = *valp;
+  xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff;
+  *valp = xt_wbr18_label_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_FR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_FR_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 16);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_imm_t_decode (uint32 *valp)
+{
+  unsigned imm_t_out_0;
+  unsigned imm_t_in_0;
+  imm_t_in_0 = *valp & 0xf;
+  imm_t_out_0 = (0 << 4) | imm_t_in_0;
+  *valp = imm_t_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_imm_t_encode (uint32 *valp)
+{
+  unsigned imm_t_in_0;
+  unsigned imm_t_out_0;
+  imm_t_out_0 = *valp;
+  imm_t_in_0 = (imm_t_out_0 & 0xf);
+  *valp = imm_t_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_imm8x4_decode (uint32 *valp)
+{
+  unsigned imm8x4_out_0;
+  unsigned imm8x4_in_0;
+  imm8x4_in_0 = *valp & 0xff;
+  imm8x4_out_0 = (0 << 10) | (imm8x4_in_0 << 2) | 0;
+  *valp = imm8x4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_imm8x4_encode (uint32 *valp)
+{
+  unsigned imm8x4_in_0;
+  unsigned imm8x4_out_0;
+  imm8x4_out_0 = *valp;
+  imm8x4_in_0 = ((imm8x4_out_0 >> 2) & 0xff);
+  *valp = imm8x4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_imm8x8_decode (uint32 *valp)
+{
+  unsigned imm8x8_out_0;
+  unsigned imm8x8_in_0;
+  imm8x8_in_0 = *valp & 0xff;
+  imm8x8_out_0 = (0 << 11) | (imm8x8_in_0 << 3) | 0;
+  *valp = imm8x8_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_imm8x8_encode (uint32 *valp)
+{
+  unsigned imm8x8_in_0;
+  unsigned imm8x8_out_0;
+  imm8x8_out_0 = *valp;
+  imm8x8_in_0 = ((imm8x8_out_0 >> 3) & 0xff);
+  *valp = imm8x8_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_QR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_QR_encode (uint32 *valp)
+{
+  int error;
+  error = (*valp >= 8);
+  return error;
+}
+
+static int
+OperandSem_opnd_sem_opnd_semantic_LD_ST_imm16f_decode (uint32 *valp)
+{
+  unsigned opnd_semantic_LD_ST_imm16f_out_0;
+  unsigned opnd_semantic_LD_ST_imm16f_in_0;
+  opnd_semantic_LD_ST_imm16f_in_0 = *valp & 0xf;
+  opnd_semantic_LD_ST_imm16f_out_0 = (((int) opnd_semantic_LD_ST_imm16f_in_0 << 28) >> 28) << 4;
+  *valp = opnd_semantic_LD_ST_imm16f_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_opnd_semantic_LD_ST_imm16f_encode (uint32 *valp)
+{
+  unsigned opnd_semantic_LD_ST_imm16f_in_0;
+  unsigned opnd_semantic_LD_ST_imm16f_out_0;
+  opnd_semantic_LD_ST_imm16f_out_0 = *valp;
+  opnd_semantic_LD_ST_imm16f_in_0 = ((opnd_semantic_LD_ST_imm16f_out_0 >> 4) & 0xf);
+  *valp = opnd_semantic_LD_ST_imm16f_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_opnd_EE_SET_BIT_GPIO_OUT_mask_decode (uint32 *valp)
+{
+  unsigned opnd_EE_SET_BIT_GPIO_OUT_mask_out_0;
+  unsigned opnd_EE_SET_BIT_GPIO_OUT_mask_in_0;
+  opnd_EE_SET_BIT_GPIO_OUT_mask_in_0 = *valp & 0xff;
+  opnd_EE_SET_BIT_GPIO_OUT_mask_out_0 = (0 << 8) | opnd_EE_SET_BIT_GPIO_OUT_mask_in_0;
+  *valp = opnd_EE_SET_BIT_GPIO_OUT_mask_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_opnd_EE_SET_BIT_GPIO_OUT_mask_encode (uint32 *valp)
+{
+  unsigned opnd_EE_SET_BIT_GPIO_OUT_mask_in_0;
+  unsigned opnd_EE_SET_BIT_GPIO_OUT_mask_out_0;
+  opnd_EE_SET_BIT_GPIO_OUT_mask_out_0 = *valp;
+  opnd_EE_SET_BIT_GPIO_OUT_mask_in_0 = (opnd_EE_SET_BIT_GPIO_OUT_mask_out_0 & 0xff);
+  *valp = opnd_EE_SET_BIT_GPIO_OUT_mask_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_opnd_semantic_LD_ST_imm2_decode (uint32 *valp)
+{
+  unsigned opnd_semantic_LD_ST_imm2_out_0;
+  unsigned opnd_semantic_LD_ST_imm2_in_0;
+  opnd_semantic_LD_ST_imm2_in_0 = *valp & 0x7f;
+  opnd_semantic_LD_ST_imm2_out_0 = ((0 << 7) | opnd_semantic_LD_ST_imm2_in_0) << 1;
+  *valp = opnd_semantic_LD_ST_imm2_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_opnd_semantic_LD_ST_imm2_encode (uint32 *valp)
+{
+  unsigned opnd_semantic_LD_ST_imm2_in_0;
+  unsigned opnd_semantic_LD_ST_imm2_out_0;
+  opnd_semantic_LD_ST_imm2_out_0 = *valp;
+  opnd_semantic_LD_ST_imm2_in_0 = ((opnd_semantic_LD_ST_imm2_out_0 >> 1) & 0x7f);
+  *valp = opnd_semantic_LD_ST_imm2_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_opnd_semantic_LD_ST_imm1_decode (uint32 *valp)
+{
+  unsigned opnd_semantic_LD_ST_imm1_out_0;
+  unsigned opnd_semantic_LD_ST_imm1_in_0;
+  opnd_semantic_LD_ST_imm1_in_0 = *valp & 0x7f;
+  opnd_semantic_LD_ST_imm1_out_0 = (0 << 7) | opnd_semantic_LD_ST_imm1_in_0;
+  *valp = opnd_semantic_LD_ST_imm1_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_opnd_semantic_LD_ST_imm1_encode (uint32 *valp)
+{
+  unsigned opnd_semantic_LD_ST_imm1_in_0;
+  unsigned opnd_semantic_LD_ST_imm1_out_0;
+  opnd_semantic_LD_ST_imm1_out_0 = *valp;
+  opnd_semantic_LD_ST_imm1_in_0 = (opnd_semantic_LD_ST_imm1_out_0 & 0x7f);
+  *valp = opnd_semantic_LD_ST_imm1_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_opnd_semantic_LD_ST_imm8_decode (uint32 *valp)
+{
+  unsigned opnd_semantic_LD_ST_imm8_out_0;
+  unsigned opnd_semantic_LD_ST_imm8_in_0;
+  opnd_semantic_LD_ST_imm8_in_0 = *valp & 0xff;
+  opnd_semantic_LD_ST_imm8_out_0 = (((int) opnd_semantic_LD_ST_imm8_in_0 << 24) >> 24) << 3;
+  *valp = opnd_semantic_LD_ST_imm8_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_opnd_semantic_LD_ST_imm8_encode (uint32 *valp)
+{
+  unsigned opnd_semantic_LD_ST_imm8_in_0;
+  unsigned opnd_semantic_LD_ST_imm8_out_0;
+  opnd_semantic_LD_ST_imm8_out_0 = *valp;
+  opnd_semantic_LD_ST_imm8_in_0 = ((opnd_semantic_LD_ST_imm8_out_0 >> 3) & 0xff);
+  *valp = opnd_semantic_LD_ST_imm8_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_opnd_semantic_LD_ST_imm16_decode (uint32 *valp)
+{
+  unsigned opnd_semantic_LD_ST_imm16_out_0;
+  unsigned opnd_semantic_LD_ST_imm16_in_0;
+  opnd_semantic_LD_ST_imm16_in_0 = *valp & 0xff;
+  opnd_semantic_LD_ST_imm16_out_0 = (((int) opnd_semantic_LD_ST_imm16_in_0 << 24) >> 24) << 4;
+  *valp = opnd_semantic_LD_ST_imm16_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_opnd_semantic_LD_ST_imm16_encode (uint32 *valp)
+{
+  unsigned opnd_semantic_LD_ST_imm16_in_0;
+  unsigned opnd_semantic_LD_ST_imm16_out_0;
+  opnd_semantic_LD_ST_imm16_out_0 = *valp;
+  opnd_semantic_LD_ST_imm16_in_0 = ((opnd_semantic_LD_ST_imm16_out_0 >> 4) & 0xff);
+  *valp = opnd_semantic_LD_ST_imm16_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_opnd_semantic_LD_ST_imm4_decode (uint32 *valp)
+{
+  unsigned opnd_semantic_LD_ST_imm4_out_0;
+  unsigned opnd_semantic_LD_ST_imm4_in_0;
+  opnd_semantic_LD_ST_imm4_in_0 = *valp & 0xff;
+  opnd_semantic_LD_ST_imm4_out_0 = (((int) opnd_semantic_LD_ST_imm4_in_0 << 24) >> 24) << 2;
+  *valp = opnd_semantic_LD_ST_imm4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_opnd_semantic_LD_ST_imm4_encode (uint32 *valp)
+{
+  unsigned opnd_semantic_LD_ST_imm4_in_0;
+  unsigned opnd_semantic_LD_ST_imm4_out_0;
+  opnd_semantic_LD_ST_imm4_out_0 = *valp;
+  opnd_semantic_LD_ST_imm4_in_0 = ((opnd_semantic_LD_ST_imm4_out_0 >> 2) & 0xff);
+  *valp = opnd_semantic_LD_ST_imm4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_opnd_semantic_LD_ST_sel8_decode (uint32 *valp)
+{
+  unsigned opnd_semantic_LD_ST_sel8_out_0;
+  unsigned opnd_semantic_LD_ST_sel8_in_0;
+  opnd_semantic_LD_ST_sel8_in_0 = *valp & 0x7;
+  opnd_semantic_LD_ST_sel8_out_0 = (0 << 3) | opnd_semantic_LD_ST_sel8_in_0;
+  *valp = opnd_semantic_LD_ST_sel8_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_opnd_semantic_LD_ST_sel8_encode (uint32 *valp)
+{
+  unsigned opnd_semantic_LD_ST_sel8_in_0;
+  unsigned opnd_semantic_LD_ST_sel8_out_0;
+  opnd_semantic_LD_ST_sel8_out_0 = *valp;
+  opnd_semantic_LD_ST_sel8_in_0 = (opnd_semantic_LD_ST_sel8_out_0 & 0x7);
+  *valp = opnd_semantic_LD_ST_sel8_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_opnd_semantic_LD_ST_sel4_decode (uint32 *valp)
+{
+  unsigned opnd_semantic_LD_ST_sel4_out_0;
+  unsigned opnd_semantic_LD_ST_sel4_in_0;
+  opnd_semantic_LD_ST_sel4_in_0 = *valp & 0x3;
+  opnd_semantic_LD_ST_sel4_out_0 = (0 << 2) | opnd_semantic_LD_ST_sel4_in_0;
+  *valp = opnd_semantic_LD_ST_sel4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_opnd_semantic_LD_ST_sel4_encode (uint32 *valp)
+{
+  unsigned opnd_semantic_LD_ST_sel4_in_0;
+  unsigned opnd_semantic_LD_ST_sel4_out_0;
+  opnd_semantic_LD_ST_sel4_out_0 = *valp;
+  opnd_semantic_LD_ST_sel4_in_0 = (opnd_semantic_LD_ST_sel4_out_0 & 0x3);
+  *valp = opnd_semantic_LD_ST_sel4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_opnd_semantic_CAL_DOUBLE_Q_imm16_decode (uint32 *valp)
+{
+  unsigned opnd_semantic_CAL_DOUBLE_Q_imm16_out_0;
+  unsigned opnd_semantic_CAL_DOUBLE_Q_imm16_in_0;
+  opnd_semantic_CAL_DOUBLE_Q_imm16_in_0 = *valp & 0x3f;
+  opnd_semantic_CAL_DOUBLE_Q_imm16_out_0 = (((int) opnd_semantic_CAL_DOUBLE_Q_imm16_in_0 << 26) >> 26) << 4;
+  *valp = opnd_semantic_CAL_DOUBLE_Q_imm16_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_opnd_semantic_CAL_DOUBLE_Q_imm16_encode (uint32 *valp)
+{
+  unsigned opnd_semantic_CAL_DOUBLE_Q_imm16_in_0;
+  unsigned opnd_semantic_CAL_DOUBLE_Q_imm16_out_0;
+  opnd_semantic_CAL_DOUBLE_Q_imm16_out_0 = *valp;
+  opnd_semantic_CAL_DOUBLE_Q_imm16_in_0 = ((opnd_semantic_CAL_DOUBLE_Q_imm16_out_0 >> 4) & 0x3f);
+  *valp = opnd_semantic_CAL_DOUBLE_Q_imm16_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_opnd_semantic_CAL_DOUBLE_Q_sel16_decode (uint32 *valp)
+{
+  unsigned opnd_semantic_CAL_DOUBLE_Q_sel16_out_0;
+  unsigned opnd_semantic_CAL_DOUBLE_Q_sel16_in_0;
+  opnd_semantic_CAL_DOUBLE_Q_sel16_in_0 = *valp & 0xf;
+  opnd_semantic_CAL_DOUBLE_Q_sel16_out_0 = (0 << 4) | opnd_semantic_CAL_DOUBLE_Q_sel16_in_0;
+  *valp = opnd_semantic_CAL_DOUBLE_Q_sel16_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_opnd_semantic_CAL_DOUBLE_Q_sel16_encode (uint32 *valp)
+{
+  unsigned opnd_semantic_CAL_DOUBLE_Q_sel16_in_0;
+  unsigned opnd_semantic_CAL_DOUBLE_Q_sel16_out_0;
+  opnd_semantic_CAL_DOUBLE_Q_sel16_out_0 = *valp;
+  opnd_semantic_CAL_DOUBLE_Q_sel16_in_0 = (opnd_semantic_CAL_DOUBLE_Q_sel16_out_0 & 0xf);
+  *valp = opnd_semantic_CAL_DOUBLE_Q_sel16_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_opnd_semantic_SRCMB_QACC_sel2_decode (uint32 *valp)
+{
+  unsigned opnd_semantic_SRCMB_QACC_sel2_out_0;
+  unsigned opnd_semantic_SRCMB_QACC_sel2_in_0;
+  opnd_semantic_SRCMB_QACC_sel2_in_0 = *valp & 0x1;
+  opnd_semantic_SRCMB_QACC_sel2_out_0 = (0 << 1) | opnd_semantic_SRCMB_QACC_sel2_in_0;
+  *valp = opnd_semantic_SRCMB_QACC_sel2_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_opnd_semantic_SRCMB_QACC_sel2_encode (uint32 *valp)
+{
+  unsigned opnd_semantic_SRCMB_QACC_sel2_in_0;
+  unsigned opnd_semantic_SRCMB_QACC_sel2_out_0;
+  opnd_semantic_SRCMB_QACC_sel2_out_0 = *valp;
+  opnd_semantic_SRCMB_QACC_sel2_in_0 = (((opnd_semantic_SRCMB_QACC_sel2_out_0 >> 0) & 1)) & 0x1;
+  *valp = opnd_semantic_SRCMB_QACC_sel2_in_0;
+  return 0;
+}
+
+static int
+Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= (pc & ~0x3);
+  return 0;
+}
+
+static int
+Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += (pc & ~0x3);
+  return 0;
+}
+
+static int
+Operand_uimm6_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= pc;
+  return 0;
+}
+
+static int
+Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += pc;
+  return 0;
+}
+
+static int
+Operand_label8_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= pc;
+  return 0;
+}
+
+static int
+Operand_label8_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += pc;
+  return 0;
+}
+
+static int
+Operand_ulabel8_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= pc;
+  return 0;
+}
+
+static int
+Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += pc;
+  return 0;
+}
+
+static int
+Operand_label12_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= pc;
+  return 0;
+}
+
+static int
+Operand_label12_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += pc;
+  return 0;
+}
+
+static int
+Operand_soffset_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= pc;
+  return 0;
+}
+
+static int
+Operand_soffset_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += pc;
+  return 0;
+}
+
+static int
+Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= ((pc + 3) & ~0x3);
+  return 0;
+}
+
+static int
+Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += ((pc + 3) & ~0x3);
+  return 0;
+}
+
+static int
+Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= pc;
+  return 0;
+}
+
+static int
+Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += pc;
+  return 0;
+}
+
+static int
+Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
+{
+  *valp -= pc;
+  return 0;
+}
+
+static int
+Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
+{
+  *valp += pc;
+  return 0;
+}
+
+static xtensa_operand_internal operands[] = {
+  { "soffsetx4", FIELD_offset, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode,
+    Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
+  { "uimm12x8", FIELD_imm12, -1, 0,
+    0,
+    OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode,
+    0, 0 },
+  { "simm4", FIELD_mn, -1, 0,
+    0,
+    OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode,
+    0, 0 },
+  { "arr", FIELD_r, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "ars", FIELD_s, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "art", FIELD_t, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "ar0", FIELD__ar0, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+    OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode,
+    0, 0 },
+  { "ar4", FIELD__ar4, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+    OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode,
+    0, 0 },
+  { "ar8", FIELD__ar8, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+    OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode,
+    0, 0 },
+  { "ar12", FIELD__ar12, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+    OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode,
+    0, 0 },
+  { "ars_entry", FIELD_s, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode,
+    0, 0 },
+  { "immrx4", FIELD_r, -1, 0,
+    0,
+    OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode,
+    0, 0 },
+  { "lsi4x4", FIELD_r, -1, 0,
+    0,
+    OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
+    0, 0 },
+  { "simm7", FIELD_imm7, -1, 0,
+    0,
+    OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode,
+    0, 0 },
+  { "uimm6", FIELD_imm6, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode,
+    Operand_uimm6_ator, Operand_uimm6_rtoa },
+  { "ai4const", FIELD_t, -1, 0,
+    0,
+    OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode,
+    0, 0 },
+  { "b4const", FIELD_r, -1, 0,
+    0,
+    OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode,
+    0, 0 },
+  { "b4constu", FIELD_r, -1, 0,
+    0,
+    OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode,
+    0, 0 },
+  { "uimm8", FIELD_imm8, -1, 0,
+    0,
+    OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode,
+    0, 0 },
+  { "uimm8x2", FIELD_imm8, -1, 0,
+    0,
+    OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode,
+    0, 0 },
+  { "uimm8x4", FIELD_imm8, -1, 0,
+    0,
+    OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode,
+    0, 0 },
+  { "uimm4x16", FIELD_op2, -1, 0,
+    0,
+    OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode,
+    0, 0 },
+  { "uimmrx4", FIELD_r, -1, 0,
+    0,
+    OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode,
+    0, 0 },
+  { "simm8", FIELD_imm8, -1, 0,
+    0,
+    OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode,
+    0, 0 },
+  { "simm8x256", FIELD_imm8, -1, 0,
+    0,
+    OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode,
+    0, 0 },
+  { "simm12b", FIELD_imm12b, -1, 0,
+    0,
+    OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode,
+    0, 0 },
+  { "msalp32", FIELD_sal, -1, 0,
+    0,
+    OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode,
+    0, 0 },
+  { "op2p1", FIELD_op2, -1, 0,
+    0,
+    OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode,
+    0, 0 },
+  { "label8", FIELD_imm8, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode,
+    Operand_label8_ator, Operand_label8_rtoa },
+  { "ulabel8", FIELD_imm8, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode,
+    Operand_ulabel8_ator, Operand_ulabel8_rtoa },
+  { "label12", FIELD_imm12, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode,
+    Operand_label12_ator, Operand_label12_rtoa },
+  { "soffset", FIELD_offset, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
+    Operand_soffset_ator, Operand_soffset_rtoa },
+  { "uimm16x4", FIELD_imm16, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode,
+    Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
+  { "bbi", FIELD_bbi, -1, 0,
+    0,
+    OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+    0, 0 },
+  { "sae", FIELD_sae, -1, 0,
+    0,
+    OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+    0, 0 },
+  { "sas", FIELD_sas, -1, 0,
+    0,
+    OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+    0, 0 },
+  { "sargt", FIELD_sargt, -1, 0,
+    0,
+    OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+    0, 0 },
+  { "s", FIELD_s, -1, 0,
+    0,
+    OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
+    0, 0 },
+  { "mx", FIELD_x, REGFILE_MR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
+    OperandSem_opnd_sem_MR_encode, OperandSem_opnd_sem_MR_decode,
+    0, 0 },
+  { "my", FIELD_y, REGFILE_MR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
+    OperandSem_opnd_sem_MR_0_encode, OperandSem_opnd_sem_MR_0_decode,
+    0, 0 },
+  { "mw", FIELD_w, REGFILE_MR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_MR_1_encode, OperandSem_opnd_sem_MR_1_decode,
+    0, 0 },
+  { "mr0", FIELD__mr0, REGFILE_MR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+    OperandSem_opnd_sem_MR_2_encode, OperandSem_opnd_sem_MR_2_decode,
+    0, 0 },
+  { "mr1", FIELD__mr1, REGFILE_MR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+    OperandSem_opnd_sem_MR_3_encode, OperandSem_opnd_sem_MR_3_decode,
+    0, 0 },
+  { "mr2", FIELD__mr2, REGFILE_MR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+    OperandSem_opnd_sem_MR_4_encode, OperandSem_opnd_sem_MR_4_decode,
+    0, 0 },
+  { "mr3", FIELD__mr3, REGFILE_MR, 1,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+    OperandSem_opnd_sem_MR_5_encode, OperandSem_opnd_sem_MR_5_decode,
+    0, 0 },
+  { "immt", FIELD_t, -1, 0,
+    0,
+    OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
+    0, 0 },
+  { "imms", FIELD_s, -1, 0,
+    0,
+    OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
+    0, 0 },
+  { "bt", FIELD_t, REGFILE_BR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
+    0, 0 },
+  { "bs", FIELD_s, REGFILE_BR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
+    0, 0 },
+  { "br", FIELD_r, REGFILE_BR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
+    0, 0 },
+  { "bt2", FIELD_t2, REGFILE_BR, 2,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
+    0, 0 },
+  { "bs2", FIELD_s2, REGFILE_BR, 2,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
+    0, 0 },
+  { "br2", FIELD_r2, REGFILE_BR, 2,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
+    0, 0 },
+  { "bt4", FIELD_t4, REGFILE_BR, 4,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
+    0, 0 },
+  { "bs4", FIELD_s4, REGFILE_BR, 4,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
+    0, 0 },
+  { "br4", FIELD_r4, REGFILE_BR, 4,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
+    0, 0 },
+  { "bt8", FIELD_t8, REGFILE_BR, 8,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
+    0, 0 },
+  { "bs8", FIELD_s8, REGFILE_BR, 8,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
+    0, 0 },
+  { "br8", FIELD_r8, REGFILE_BR, 8,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
+    0, 0 },
+  { "bt16", FIELD__bt16, REGFILE_BR, 16,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
+    0, 0 },
+  { "bs16", FIELD__bs16, REGFILE_BR, 16,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
+    0, 0 },
+  { "br16", FIELD__br16, REGFILE_BR, 16,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
+    0, 0 },
+  { "brall", FIELD__brall, REGFILE_BR, 16,
+    XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
+    OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
+    0, 0 },
+  { "tp7", FIELD_t, -1, 0,
+    0,
+    OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode,
+    0, 0 },
+  { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode,
+    Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
+  { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
+    XTENSA_OPERAND_IS_PCRELATIVE,
+    OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode,
+    Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
+  { "frr", FIELD_r, REGFILE_FR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode,
+    0, 0 },
+  { "frs", FIELD_s, REGFILE_FR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode,
+    0, 0 },
+  { "frt", FIELD_t, REGFILE_FR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode,
+    0, 0 },
+  { "imm_t", FIELD_t, -1, 0,
+    0,
+    OperandSem_opnd_sem_imm_t_encode, OperandSem_opnd_sem_imm_t_decode,
+    0, 0 },
+  { "imm_s", FIELD_s, -1, 0,
+    0,
+    OperandSem_opnd_sem_imm_t_encode, OperandSem_opnd_sem_imm_t_decode,
+    0, 0 },
+  { "imm8x4", FIELD_imm8, -1, 0,
+    0,
+    OperandSem_opnd_sem_imm8x4_encode, OperandSem_opnd_sem_imm8x4_decode,
+    0, 0 },
+  { "imm8x8", FIELD_imm8, -1, 0,
+    0,
+    OperandSem_opnd_sem_imm8x8_encode, OperandSem_opnd_sem_imm8x8_decode,
+    0, 0 },
+  { "opnd_st.QR_b", FIELD_fld_st_QR_b, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_st.QR_a", FIELD_fld_st_QR_a, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_ld.QR_b", FIELD_fld_ld_QR_b, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_ld.QR_a", FIELD_fld_ld_QR_a, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_imm_QR", FIELD_fld_QR, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_LD_ST_imm16f_encode, OperandSem_opnd_sem_opnd_semantic_LD_ST_imm16f_decode,
+    0, 0 },
+  { "opnd_mv.QR_b", FIELD_fld_mv_QR_b, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_mv.QR_a", FIELD_fld_mv_QR_a, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.WR_MASK_GPIO_OUT_mask", FIELD_fld_EE_WR_MASK_GPIO_OUT_mask, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_EE.WR_MASK_GPIO_OUT_value", FIELD_fld_EE_WR_MASK_GPIO_OUT_value, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_EE.SET_BIT_GPIO_OUT_mask", FIELD_fld_EE_SET_BIT_GPIO_OUT_mask, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_EE_SET_BIT_GPIO_OUT_mask_encode, OperandSem_opnd_sem_opnd_EE_SET_BIT_GPIO_OUT_mask_decode,
+    0, 0 },
+  { "opnd_EE.CLR_BIT_GPIO_OUT_clear", FIELD_fld_EE_CLR_BIT_GPIO_OUT_clear, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_EE_SET_BIT_GPIO_OUT_mask_encode, OperandSem_opnd_sem_opnd_EE_SET_BIT_GPIO_OUT_mask_decode,
+    0, 0 },
+  { "opnd_EE.GET_GPIO_IN_au", FIELD_fld_EE_GET_GPIO_IN_au, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_semantic.LD_ST_imm2", FIELD_fld_semantic_LD_ST_imm2, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_LD_ST_imm2_encode, OperandSem_opnd_sem_opnd_semantic_LD_ST_imm2_decode,
+    0, 0 },
+  { "opnd_semantic.LD_ST_imm1", FIELD_fld_semantic_LD_ST_imm1, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_LD_ST_imm1_encode, OperandSem_opnd_sem_opnd_semantic_LD_ST_imm1_decode,
+    0, 0 },
+  { "opnd_semantic.LD_ST_qu1", FIELD_fld_semantic_LD_ST_qu1, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_semantic.LD_ST_imm16f", FIELD_fld_semantic_LD_ST_imm16f, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_LD_ST_imm16f_encode, OperandSem_opnd_sem_opnd_semantic_LD_ST_imm16f_decode,
+    0, 0 },
+  { "opnd_semantic.LD_ST_as", FIELD_fld_semantic_LD_ST_as, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_semantic.LD_ST_fu0", FIELD_fld_semantic_LD_ST_fu0, REGFILE_FR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode,
+    0, 0 },
+  { "opnd_semantic.LD_ST_fu1", FIELD_fld_semantic_LD_ST_fu1, REGFILE_FR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode,
+    0, 0 },
+  { "opnd_semantic.LD_ST_fu2", FIELD_fld_semantic_LD_ST_fu2, REGFILE_FR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode,
+    0, 0 },
+  { "opnd_semantic.LD_ST_fu3", FIELD_fld_semantic_LD_ST_fu3, REGFILE_FR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode,
+    0, 0 },
+  { "opnd_semantic.LD_ST_ad", FIELD_fld_semantic_LD_ST_ad, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_semantic.LD_ST_imm8", FIELD_fld_semantic_LD_ST_imm8, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_LD_ST_imm8_encode, OperandSem_opnd_sem_opnd_semantic_LD_ST_imm8_decode,
+    0, 0 },
+  { "opnd_semantic.LD_ST_imm16", FIELD_fld_semantic_LD_ST_imm16, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_LD_ST_imm16_encode, OperandSem_opnd_sem_opnd_semantic_LD_ST_imm16_decode,
+    0, 0 },
+  { "opnd_semantic.LD_ST_imm4", FIELD_fld_semantic_LD_ST_imm4, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_LD_ST_imm4_encode, OperandSem_opnd_sem_opnd_semantic_LD_ST_imm4_decode,
+    0, 0 },
+  { "opnd_semantic.LD_ST_sel8", FIELD_fld_semantic_LD_ST_sel8, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_LD_ST_sel8_encode, OperandSem_opnd_sem_opnd_semantic_LD_ST_sel8_decode,
+    0, 0 },
+  { "opnd_semantic.LD_ST_sel4", FIELD_fld_semantic_LD_ST_sel4, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_LD_ST_sel4_encode, OperandSem_opnd_sem_opnd_semantic_LD_ST_sel4_decode,
+    0, 0 },
+  { "opnd_semantic.LD_ST_qs", FIELD_fld_semantic_LD_ST_qs, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_semantic.LD_ST_qu", FIELD_fld_semantic_LD_ST_qu, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_semantic.LD_ST_fv0", FIELD_fld_semantic_LD_ST_fv0, REGFILE_FR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode,
+    0, 0 },
+  { "opnd_semantic.LD_ST_fv1", FIELD_fld_semantic_LD_ST_fv1, REGFILE_FR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode,
+    0, 0 },
+  { "opnd_semantic.LD_ST_fv2", FIELD_fld_semantic_LD_ST_fv2, REGFILE_FR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode,
+    0, 0 },
+  { "opnd_semantic.LD_ST_fv3", FIELD_fld_semantic_LD_ST_fv3, REGFILE_FR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode,
+    0, 0 },
+  { "opnd_semantic.LD_ST_qv", FIELD_fld_semantic_LD_ST_qv, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.MOVI.32.A_sel4", FIELD_fld_EE_MOVI_32_A_sel4, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_LD_ST_sel4_encode, OperandSem_opnd_sem_opnd_semantic_LD_ST_sel4_decode,
+    0, 0 },
+  { "opnd_EE.MOVI.32.A_au", FIELD_fld_EE_MOVI_32_A_au, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_EE.MOVI.32.A_qs", FIELD_fld_EE_MOVI_32_A_qs, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.MOVI.32.Q_sel4", FIELD_fld_EE_MOVI_32_Q_sel4, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_LD_ST_sel4_encode, OperandSem_opnd_sem_opnd_semantic_LD_ST_sel4_decode,
+    0, 0 },
+  { "opnd_EE.MOVI.32.Q_as", FIELD_fld_EE_MOVI_32_Q_as, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_EE.MOVI.32.Q_qu", FIELD_fld_EE_MOVI_32_Q_qu, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.VZIP.16_qs1", FIELD_fld_EE_VZIP_16_qs1, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.VZIP.16_qs0", FIELD_fld_EE_VZIP_16_qs0, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.VZIP.32_qs1", FIELD_fld_EE_VZIP_32_qs1, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.VZIP.32_qs0", FIELD_fld_EE_VZIP_32_qs0, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.VZIP.8_qs1", FIELD_fld_EE_VZIP_8_qs1, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.VZIP.8_qs0", FIELD_fld_EE_VZIP_8_qs0, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.VUNZIP.16_qs1", FIELD_fld_EE_VUNZIP_16_qs1, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.VUNZIP.16_qs0", FIELD_fld_EE_VUNZIP_16_qs0, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.VUNZIP.32_qs1", FIELD_fld_EE_VUNZIP_32_qs1, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.VUNZIP.32_qs0", FIELD_fld_EE_VUNZIP_32_qs0, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.VUNZIP.8_qs1", FIELD_fld_EE_VUNZIP_8_qs1, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.VUNZIP.8_qs0", FIELD_fld_EE_VUNZIP_8_qs0, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.ZERO.Q_qa", FIELD_fld_EE_ZERO_Q_qa, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.MOV.S16.QACC_qs", FIELD_fld_EE_MOV_S16_QACC_qs, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.MOV.S8.QACC_qs", FIELD_fld_EE_MOV_S8_QACC_qs, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.MOV.U16.QACC_qs", FIELD_fld_EE_MOV_U16_QACC_qs, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.MOV.U8.QACC_qs", FIELD_fld_EE_MOV_U8_QACC_qs, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_semantic.CAL_DOUBLE_Q_qa", FIELD_fld_semantic_CAL_DOUBLE_Q_qa, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_semantic.CAL_DOUBLE_Q_as", FIELD_fld_semantic_CAL_DOUBLE_Q_as, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_semantic.CAL_DOUBLE_Q_qu", FIELD_fld_semantic_CAL_DOUBLE_Q_qu, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_semantic.CAL_DOUBLE_Q_qv", FIELD_fld_semantic_CAL_DOUBLE_Q_qv, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_semantic.CAL_DOUBLE_Q_sel4", FIELD_fld_semantic_CAL_DOUBLE_Q_sel4, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_LD_ST_sel4_encode, OperandSem_opnd_sem_opnd_semantic_LD_ST_sel4_decode,
+    0, 0 },
+  { "opnd_semantic.CAL_DOUBLE_Q_qy", FIELD_fld_semantic_CAL_DOUBLE_Q_qy, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_semantic.CAL_DOUBLE_Q_qx", FIELD_fld_semantic_CAL_DOUBLE_Q_qx, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_semantic.CAL_DOUBLE_Q_qz", FIELD_fld_semantic_CAL_DOUBLE_Q_qz, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_semantic.CAL_DOUBLE_Q_qs1", FIELD_fld_semantic_CAL_DOUBLE_Q_qs1, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_semantic.CAL_DOUBLE_Q_qs0", FIELD_fld_semantic_CAL_DOUBLE_Q_qs0, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_semantic.CAL_DOUBLE_Q_imm16", FIELD_fld_semantic_CAL_DOUBLE_Q_imm16, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_CAL_DOUBLE_Q_imm16_encode, OperandSem_opnd_sem_opnd_semantic_CAL_DOUBLE_Q_imm16_decode,
+    0, 0 },
+  { "opnd_semantic.CAL_DOUBLE_Q_ad", FIELD_fld_semantic_CAL_DOUBLE_Q_ad, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_semantic.CAL_DOUBLE_Q_sel8", FIELD_fld_semantic_CAL_DOUBLE_Q_sel8, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_LD_ST_sel8_encode, OperandSem_opnd_sem_opnd_semantic_LD_ST_sel8_decode,
+    0, 0 },
+  { "opnd_semantic.CAL_DOUBLE_Q_sel16", FIELD_fld_semantic_CAL_DOUBLE_Q_sel16, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_CAL_DOUBLE_Q_sel16_encode, OperandSem_opnd_sem_opnd_semantic_CAL_DOUBLE_Q_sel16_decode,
+    0, 0 },
+  { "opnd_semantic.SRCMB_QACC_sel2", FIELD_fld_semantic_SRCMB_QACC_sel2, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_SRCMB_QACC_sel2_encode, OperandSem_opnd_sem_opnd_semantic_SRCMB_QACC_sel2_decode,
+    0, 0 },
+  { "opnd_semantic.SRCMB_QACC_as", FIELD_fld_semantic_SRCMB_QACC_as, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_semantic.SRCMB_QACC_qu", FIELD_fld_semantic_SRCMB_QACC_qu, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.SRS.ACCX_sel2", FIELD_fld_EE_SRS_ACCX_sel2, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_SRCMB_QACC_sel2_encode, OperandSem_opnd_sem_opnd_semantic_SRCMB_QACC_sel2_decode,
+    0, 0 },
+  { "opnd_EE.SRS.ACCX_as", FIELD_fld_EE_SRS_ACCX_as, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_EE.SRS.ACCX_au", FIELD_fld_EE_SRS_ACCX_au, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_semantic.CAL_DOUBLE_Q_ax", FIELD_fld_semantic_CAL_DOUBLE_Q_ax, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_semantic.CAL_DOUBLE_Q_qs", FIELD_fld_semantic_CAL_DOUBLE_Q_qs, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_semantic.CAL_DOUBLE_Q_ay", FIELD_fld_semantic_CAL_DOUBLE_Q_ay, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_semantic.VLOGIC_qy", FIELD_fld_semantic_VLOGIC_qy, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_semantic.VLOGIC_qx", FIELD_fld_semantic_VLOGIC_qx, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_semantic.VLOGIC_qa", FIELD_fld_semantic_VLOGIC_qa, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_semantic.SHFQ_sar16", FIELD_fld_semantic_SHFQ_sar16, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_CAL_DOUBLE_Q_sel16_encode, OperandSem_opnd_sem_opnd_semantic_CAL_DOUBLE_Q_sel16_decode,
+    0, 0 },
+  { "opnd_semantic.SHFQ_qs0", FIELD_fld_semantic_SHFQ_qs0, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_semantic.SHFQ_qs1", FIELD_fld_semantic_SHFQ_qs1, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_semantic.SHFQ_ad", FIELD_fld_semantic_SHFQ_ad, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_semantic.SHFQ_as", FIELD_fld_semantic_SHFQ_as, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_semantic.SHFQ_imm16", FIELD_fld_semantic_SHFQ_imm16, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_LD_ST_imm16_encode, OperandSem_opnd_sem_opnd_semantic_LD_ST_imm16_decode,
+    0, 0 },
+  { "opnd_semantic.SHFQ_qu", FIELD_fld_semantic_SHFQ_qu, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_semantic.SHFQ_qa", FIELD_fld_semantic_SHFQ_qa, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_semantic.SHFQ_qs", FIELD_fld_semantic_SHFQ_qs, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_semantic.FFT_RxBF_sar4", FIELD_fld_semantic_FFT_RxBF_sar4, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_LD_ST_sel4_encode, OperandSem_opnd_sem_opnd_semantic_LD_ST_sel4_decode,
+    0, 0 },
+  { "opnd_semantic.FFT_RxBF_as", FIELD_fld_semantic_FFT_RxBF_as, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_semantic.FFT_RxBF_sel2", FIELD_fld_semantic_FFT_RxBF_sel2, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_SRCMB_QACC_sel2_encode, OperandSem_opnd_sem_opnd_semantic_SRCMB_QACC_sel2_decode,
+    0, 0 },
+  { "opnd_semantic.FFT_RxBF_qy", FIELD_fld_semantic_FFT_RxBF_qy, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_semantic.FFT_RxBF_qx", FIELD_fld_semantic_FFT_RxBF_qx, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_semantic.FFT_RxBF_qa1", FIELD_fld_semantic_FFT_RxBF_qa1, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_semantic.FFT_RxBF_qa0", FIELD_fld_semantic_FFT_RxBF_qa0, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.CMUL.S16.LD.XP_sel8", FIELD_fld_EE_FFT_CMUL_S16_LD_XP_sel8, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_LD_ST_sel8_encode, OperandSem_opnd_sem_opnd_semantic_LD_ST_sel8_decode,
+    0, 0 },
+  { "opnd_EE.FFT.CMUL.S16.LD.XP_qy", FIELD_fld_EE_FFT_CMUL_S16_LD_XP_qy, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.CMUL.S16.LD.XP_qx", FIELD_fld_EE_FFT_CMUL_S16_LD_XP_qx, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.CMUL.S16.LD.XP_qz", FIELD_fld_EE_FFT_CMUL_S16_LD_XP_qz, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.CMUL.S16.LD.XP_ad", FIELD_fld_EE_FFT_CMUL_S16_LD_XP_ad, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.CMUL.S16.LD.XP_as", FIELD_fld_EE_FFT_CMUL_S16_LD_XP_as, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.CMUL.S16.LD.XP_qu", FIELD_fld_EE_FFT_CMUL_S16_LD_XP_qu, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.CMUL.S16.ST.XP_sar4", FIELD_fld_EE_FFT_CMUL_S16_ST_XP_sar4, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_LD_ST_sel4_encode, OperandSem_opnd_sem_opnd_semantic_LD_ST_sel4_decode,
+    0, 0 },
+  { "opnd_EE.FFT.CMUL.S16.ST.XP_upd4", FIELD_fld_EE_FFT_CMUL_S16_ST_XP_upd4, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_LD_ST_sel4_encode, OperandSem_opnd_sem_opnd_semantic_LD_ST_sel4_decode,
+    0, 0 },
+  { "opnd_EE.FFT.CMUL.S16.ST.XP_sel8", FIELD_fld_EE_FFT_CMUL_S16_ST_XP_sel8, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_LD_ST_sel8_encode, OperandSem_opnd_sem_opnd_semantic_LD_ST_sel8_decode,
+    0, 0 },
+  { "opnd_EE.FFT.CMUL.S16.ST.XP_ad", FIELD_fld_EE_FFT_CMUL_S16_ST_XP_ad, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.CMUL.S16.ST.XP_as", FIELD_fld_EE_FFT_CMUL_S16_ST_XP_as, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.CMUL.S16.ST.XP_qv", FIELD_fld_EE_FFT_CMUL_S16_ST_XP_qv, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.CMUL.S16.ST.XP_qy", FIELD_fld_EE_FFT_CMUL_S16_ST_XP_qy, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.CMUL.S16.ST.XP_qx", FIELD_fld_EE_FFT_CMUL_S16_ST_XP_qx, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.BITREV_ax", FIELD_fld_EE_BITREV_ax, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_EE.BITREV_qa", FIELD_fld_EE_BITREV_qa, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.LD.INCP_sel2", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_sel2, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_SRCMB_QACC_sel2_encode, OperandSem_opnd_sem_opnd_semantic_SRCMB_QACC_sel2_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.LD.INCP_qm", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_qm, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.LD.INCP_qy", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_qy, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.LD.INCP_qx", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_qx, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.LD.INCP_qz1", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_qz1, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.LD.INCP_qz", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_qz, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.LD.INCP_as", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_as, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.LD.INCP_qu", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_qu, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.LD.INCP.UAUP_sel2", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_sel2, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_SRCMB_QACC_sel2_encode, OperandSem_opnd_sem_opnd_semantic_SRCMB_QACC_sel2_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.LD.INCP.UAUP_qm", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_qm, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.LD.INCP.UAUP_qy", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_qy, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.LD.INCP.UAUP_qx", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_qx, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.LD.INCP.UAUP_qz1", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_qz1, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.LD.INCP.UAUP_qz", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_qz, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.LD.INCP.UAUP_as", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_as, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.LD.INCP.UAUP_qu", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_qu, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.LD.R32.DECP_sel2", FIELD_fld_EE_FFT_AMS_S16_LD_R32_DECP_sel2, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_SRCMB_QACC_sel2_encode, OperandSem_opnd_sem_opnd_semantic_SRCMB_QACC_sel2_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.LD.R32.DECP_qm", FIELD_fld_EE_FFT_AMS_S16_LD_R32_DECP_qm, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.LD.R32.DECP_qy", FIELD_fld_EE_FFT_AMS_S16_LD_R32_DECP_qy, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.LD.R32.DECP_qx", FIELD_fld_EE_FFT_AMS_S16_LD_R32_DECP_qx, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.LD.R32.DECP_qz1", FIELD_fld_EE_FFT_AMS_S16_LD_R32_DECP_qz1, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.LD.R32.DECP_qz", FIELD_fld_EE_FFT_AMS_S16_LD_R32_DECP_qz, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.LD.R32.DECP_as", FIELD_fld_EE_FFT_AMS_S16_LD_R32_DECP_as, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.LD.R32.DECP_qu", FIELD_fld_EE_FFT_AMS_S16_LD_R32_DECP_qu, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.ST.INCP_sel2", FIELD_fld_EE_FFT_AMS_S16_ST_INCP_sel2, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_SRCMB_QACC_sel2_encode, OperandSem_opnd_sem_opnd_semantic_SRCMB_QACC_sel2_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.ST.INCP_qm", FIELD_fld_EE_FFT_AMS_S16_ST_INCP_qm, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.ST.INCP_qy", FIELD_fld_EE_FFT_AMS_S16_ST_INCP_qy, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.ST.INCP_qx", FIELD_fld_EE_FFT_AMS_S16_ST_INCP_qx, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.ST.INCP_as", FIELD_fld_EE_FFT_AMS_S16_ST_INCP_as, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.ST.INCP_as0", FIELD_fld_EE_FFT_AMS_S16_ST_INCP_as0, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.ST.INCP_qz1", FIELD_fld_EE_FFT_AMS_S16_ST_INCP_qz1, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.AMS.S16.ST.INCP_qv", FIELD_fld_EE_FFT_AMS_S16_ST_INCP_qv, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.VST.R32.DECP_sar2", FIELD_fld_EE_FFT_VST_R32_DECP_sar2, -1, 0,
+    0,
+    OperandSem_opnd_sem_opnd_semantic_SRCMB_QACC_sel2_encode, OperandSem_opnd_sem_opnd_semantic_SRCMB_QACC_sel2_decode,
+    0, 0 },
+  { "opnd_EE.FFT.VST.R32.DECP_as", FIELD_fld_EE_FFT_VST_R32_DECP_as, REGFILE_AR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
+    0, 0 },
+  { "opnd_EE.FFT.VST.R32.DECP_qv", FIELD_fld_EE_FFT_VST_R32_DECP_qv, REGFILE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_QR_encode, OperandSem_opnd_sem_QR_decode,
+    0, 0 },
+  { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
+  { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
+  { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
+  { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
+  { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
+  { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
+  { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
+  { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
+  { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
+  { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
+  { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
+  { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
+  { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
+  { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
+  { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
+  { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
+  { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
+  { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
+  { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
+  { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
+  { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 },
+  { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 },
+  { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 },
+  { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 },
+  { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 },
+  { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 },
+  { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 },
+  { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 },
+  { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 },
+  { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 },
+  { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 },
+  { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 },
+  { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 },
+  { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 },
+  { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 },
+  { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 },
+  { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 },
+  { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 },
+  { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
+  { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_slot_format_32_0_3_0", FIELD_fld_slot_format_32_0_3_0, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_slot_format_32_0_28_4", FIELD_fld_slot_format_32_0_28_4, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_st.QR_b", FIELD_fld_st_QR_b, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_st.QR_a", FIELD_fld_st_QR_a, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_ld.QR_b", FIELD_fld_ld_QR_b, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_ld.QR_a", FIELD_fld_ld_QR_a, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_QR", FIELD_fld_QR, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_4_0", FIELD_fld_Inst_4_0, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_9_6", FIELD_fld_Inst_9_6, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_mv.QR_b", FIELD_fld_mv_QR_b, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_mv.QR_a", FIELD_fld_mv_QR_a, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.WR_MASK_GPIO_OUT_mask", FIELD_fld_EE_WR_MASK_GPIO_OUT_mask, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.WR_MASK_GPIO_OUT_value", FIELD_fld_EE_WR_MASK_GPIO_OUT_value, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.SET_BIT_GPIO_OUT_mask", FIELD_fld_EE_SET_BIT_GPIO_OUT_mask, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.CLR_BIT_GPIO_OUT_clear", FIELD_fld_EE_CLR_BIT_GPIO_OUT_clear, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_23_8", FIELD_fld_Inst_23_8, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.GET_GPIO_IN_au", FIELD_fld_EE_GET_GPIO_IN_au, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_23_22", FIELD_fld_Inst_23_22, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.LD_ST_imm2", FIELD_fld_semantic_LD_ST_imm2, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_14_8", FIELD_fld_Inst_14_8, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.LD_ST_imm1", FIELD_fld_semantic_LD_ST_imm1, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_11_8", FIELD_fld_Inst_11_8, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.LD_ST_qu1", FIELD_fld_semantic_LD_ST_qu1, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.LD_ST_imm16f", FIELD_fld_semantic_LD_ST_imm16f, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.LD_ST_as", FIELD_fld_semantic_LD_ST_as, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.LD_ST_fu0", FIELD_fld_semantic_LD_ST_fu0, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.LD_ST_fu1", FIELD_fld_semantic_LD_ST_fu1, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.LD_ST_fu2", FIELD_fld_semantic_LD_ST_fu2, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.LD_ST_fu3", FIELD_fld_semantic_LD_ST_fu3, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_slot_format_32_0_28_24", FIELD_fld_slot_format_32_0_28_24, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.LD_ST_ad", FIELD_fld_semantic_LD_ST_ad, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.LD_ST_imm8", FIELD_fld_semantic_LD_ST_imm8, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_slot_format_32_0_7_5", FIELD_fld_slot_format_32_0_7_5, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_3_0", FIELD_fld_Inst_3_0, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_19_16", FIELD_fld_Inst_19_16, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_23_23", FIELD_fld_Inst_23_23, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_14_12", FIELD_fld_Inst_14_12, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_21_15", FIELD_fld_Inst_21_15, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.LD_ST_imm16", FIELD_fld_semantic_LD_ST_imm16, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_23_12", FIELD_fld_Inst_23_12, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.LD_ST_imm4", FIELD_fld_semantic_LD_ST_imm4, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.LD_ST_sel8", FIELD_fld_semantic_LD_ST_sel8, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.LD_ST_sel4", FIELD_fld_semantic_LD_ST_sel4, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.LD_ST_qs", FIELD_fld_semantic_LD_ST_qs, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.LD_ST_qu", FIELD_fld_semantic_LD_ST_qu, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_slot_format_32_0_28_22", FIELD_fld_slot_format_32_0_28_22, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.LD_ST_fv0", FIELD_fld_semantic_LD_ST_fv0, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.LD_ST_fv1", FIELD_fld_semantic_LD_ST_fv1, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.LD_ST_fv2", FIELD_fld_semantic_LD_ST_fv2, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.LD_ST_fv3", FIELD_fld_semantic_LD_ST_fv3, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.LD_ST_qv", FIELD_fld_semantic_LD_ST_qv, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.MOVI.32.A_sel4", FIELD_fld_EE_MOVI_32_A_sel4, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.MOVI.32.A_au", FIELD_fld_EE_MOVI_32_A_au, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.MOVI.32.A_qs", FIELD_fld_EE_MOVI_32_A_qs, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.MOVI.32.Q_sel4", FIELD_fld_EE_MOVI_32_Q_sel4, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.MOVI.32.Q_as", FIELD_fld_EE_MOVI_32_Q_as, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.MOVI.32.Q_qu", FIELD_fld_EE_MOVI_32_Q_qu, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.VZIP.16_qs1", FIELD_fld_EE_VZIP_16_qs1, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.VZIP.16_qs0", FIELD_fld_EE_VZIP_16_qs0, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.VZIP.32_qs1", FIELD_fld_EE_VZIP_32_qs1, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.VZIP.32_qs0", FIELD_fld_EE_VZIP_32_qs0, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.VZIP.8_qs1", FIELD_fld_EE_VZIP_8_qs1, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.VZIP.8_qs0", FIELD_fld_EE_VZIP_8_qs0, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_11_0", FIELD_fld_Inst_11_0, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.VUNZIP.16_qs1", FIELD_fld_EE_VUNZIP_16_qs1, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.VUNZIP.16_qs0", FIELD_fld_EE_VUNZIP_16_qs0, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.VUNZIP.32_qs1", FIELD_fld_EE_VUNZIP_32_qs1, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.VUNZIP.32_qs0", FIELD_fld_EE_VUNZIP_32_qs0, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.VUNZIP.8_qs1", FIELD_fld_EE_VUNZIP_8_qs1, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.VUNZIP.8_qs0", FIELD_fld_EE_VUNZIP_8_qs0, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_23_0", FIELD_fld_Inst_23_0, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.ZERO.Q_qa", FIELD_fld_EE_ZERO_Q_qa, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_14_0", FIELD_fld_Inst_14_0, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.MOV.S16.QACC_qs", FIELD_fld_EE_MOV_S16_QACC_qs, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.MOV.S8.QACC_qs", FIELD_fld_EE_MOV_S8_QACC_qs, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.MOV.U16.QACC_qs", FIELD_fld_EE_MOV_U16_QACC_qs, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.MOV.U8.QACC_qs", FIELD_fld_EE_MOV_U8_QACC_qs, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_slot_format_32_0_10_4", FIELD_fld_slot_format_32_0_10_4, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_7_0", FIELD_fld_Inst_7_0, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.CAL_DOUBLE_Q_qa", FIELD_fld_semantic_CAL_DOUBLE_Q_qa, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.CAL_DOUBLE_Q_as", FIELD_fld_semantic_CAL_DOUBLE_Q_as, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.CAL_DOUBLE_Q_qu", FIELD_fld_semantic_CAL_DOUBLE_Q_qu, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_slot_format_32_0_10_6", FIELD_fld_slot_format_32_0_10_6, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.CAL_DOUBLE_Q_qv", FIELD_fld_semantic_CAL_DOUBLE_Q_qv, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_slot_format_32_0_28_20", FIELD_fld_slot_format_32_0_28_20, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_7_6", FIELD_fld_Inst_7_6, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.CAL_DOUBLE_Q_sel4", FIELD_fld_semantic_CAL_DOUBLE_Q_sel4, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.CAL_DOUBLE_Q_qy", FIELD_fld_semantic_CAL_DOUBLE_Q_qy, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.CAL_DOUBLE_Q_qx", FIELD_fld_semantic_CAL_DOUBLE_Q_qx, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.CAL_DOUBLE_Q_qz", FIELD_fld_semantic_CAL_DOUBLE_Q_qz, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.CAL_DOUBLE_Q_qs1", FIELD_fld_semantic_CAL_DOUBLE_Q_qs1, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.CAL_DOUBLE_Q_qs0", FIELD_fld_semantic_CAL_DOUBLE_Q_qs0, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_slot_format_32_0_28_25", FIELD_fld_slot_format_32_0_28_25, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.CAL_DOUBLE_Q_imm16", FIELD_fld_semantic_CAL_DOUBLE_Q_imm16, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_slot_format_32_0_10_8", FIELD_fld_slot_format_32_0_10_8, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_slot_format_32_0_19_17", FIELD_fld_slot_format_32_0_19_17, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_slot_format_32_0_28_23", FIELD_fld_slot_format_32_0_28_23, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.CAL_DOUBLE_Q_ad", FIELD_fld_semantic_CAL_DOUBLE_Q_ad, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_slot_format_32_0_7_4", FIELD_fld_slot_format_32_0_7_4, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_23_21", FIELD_fld_Inst_23_21, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.CAL_DOUBLE_Q_sel8", FIELD_fld_semantic_CAL_DOUBLE_Q_sel8, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_slot_format_32_0_10_9", FIELD_fld_slot_format_32_0_10_9, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_7_5", FIELD_fld_Inst_7_5, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.CAL_DOUBLE_Q_sel16", FIELD_fld_semantic_CAL_DOUBLE_Q_sel16, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_14_11", FIELD_fld_Inst_14_11, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.SRCMB_QACC_sel2", FIELD_fld_semantic_SRCMB_QACC_sel2, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.SRCMB_QACC_as", FIELD_fld_semantic_SRCMB_QACC_as, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.SRCMB_QACC_qu", FIELD_fld_semantic_SRCMB_QACC_qu, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_13_12", FIELD_fld_Inst_13_12, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_23_15", FIELD_fld_Inst_23_15, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.SRS.ACCX_sel2", FIELD_fld_EE_SRS_ACCX_sel2, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.SRS.ACCX_as", FIELD_fld_EE_SRS_ACCX_as, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.SRS.ACCX_au", FIELD_fld_EE_SRS_ACCX_au, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.CAL_DOUBLE_Q_ax", FIELD_fld_semantic_CAL_DOUBLE_Q_ax, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.CAL_DOUBLE_Q_qs", FIELD_fld_semantic_CAL_DOUBLE_Q_qs, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_13_13", FIELD_fld_Inst_13_13, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.CAL_DOUBLE_Q_ay", FIELD_fld_semantic_CAL_DOUBLE_Q_ay, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_9_8", FIELD_fld_Inst_9_8, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.VLOGIC_qy", FIELD_fld_semantic_VLOGIC_qy, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.VLOGIC_qx", FIELD_fld_semantic_VLOGIC_qx, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.VLOGIC_qa", FIELD_fld_semantic_VLOGIC_qa, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_5_5", FIELD_fld_Inst_5_5, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.SHFQ_sar16", FIELD_fld_semantic_SHFQ_sar16, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.SHFQ_qs0", FIELD_fld_semantic_SHFQ_qs0, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.SHFQ_qs1", FIELD_fld_semantic_SHFQ_qs1, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.SHFQ_ad", FIELD_fld_semantic_SHFQ_ad, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.SHFQ_as", FIELD_fld_semantic_SHFQ_as, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.SHFQ_imm16", FIELD_fld_semantic_SHFQ_imm16, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.SHFQ_qu", FIELD_fld_semantic_SHFQ_qu, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_slot_format_32_0_7_6", FIELD_fld_slot_format_32_0_7_6, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_slot_format_32_0_13_11", FIELD_fld_slot_format_32_0_13_11, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_11_7", FIELD_fld_Inst_11_7, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.SHFQ_qa", FIELD_fld_semantic_SHFQ_qa, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_14_7", FIELD_fld_Inst_14_7, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.SHFQ_qs", FIELD_fld_semantic_SHFQ_qs, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.FFT_RxBF_sar4", FIELD_fld_semantic_FFT_RxBF_sar4, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.FFT_RxBF_as", FIELD_fld_semantic_FFT_RxBF_as, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_slot_format_32_0_13_13", FIELD_fld_slot_format_32_0_13_13, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_Inst_9_9", FIELD_fld_Inst_9_9, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.FFT_RxBF_sel2", FIELD_fld_semantic_FFT_RxBF_sel2, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.FFT_RxBF_qy", FIELD_fld_semantic_FFT_RxBF_qy, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.FFT_RxBF_qx", FIELD_fld_semantic_FFT_RxBF_qx, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.FFT_RxBF_qa1", FIELD_fld_semantic_FFT_RxBF_qa1, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_semantic.FFT_RxBF_qa0", FIELD_fld_semantic_FFT_RxBF_qa0, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.CMUL.S16.LD.XP_sel8", FIELD_fld_EE_FFT_CMUL_S16_LD_XP_sel8, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.CMUL.S16.LD.XP_qy", FIELD_fld_EE_FFT_CMUL_S16_LD_XP_qy, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.CMUL.S16.LD.XP_qx", FIELD_fld_EE_FFT_CMUL_S16_LD_XP_qx, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.CMUL.S16.LD.XP_qz", FIELD_fld_EE_FFT_CMUL_S16_LD_XP_qz, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.CMUL.S16.LD.XP_ad", FIELD_fld_EE_FFT_CMUL_S16_LD_XP_ad, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.CMUL.S16.LD.XP_as", FIELD_fld_EE_FFT_CMUL_S16_LD_XP_as, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.CMUL.S16.LD.XP_qu", FIELD_fld_EE_FFT_CMUL_S16_LD_XP_qu, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.CMUL.S16.ST.XP_sar4", FIELD_fld_EE_FFT_CMUL_S16_ST_XP_sar4, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.CMUL.S16.ST.XP_upd4", FIELD_fld_EE_FFT_CMUL_S16_ST_XP_upd4, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.CMUL.S16.ST.XP_sel8", FIELD_fld_EE_FFT_CMUL_S16_ST_XP_sel8, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.CMUL.S16.ST.XP_ad", FIELD_fld_EE_FFT_CMUL_S16_ST_XP_ad, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.CMUL.S16.ST.XP_as", FIELD_fld_EE_FFT_CMUL_S16_ST_XP_as, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.CMUL.S16.ST.XP_qv", FIELD_fld_EE_FFT_CMUL_S16_ST_XP_qv, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.CMUL.S16.ST.XP_qy", FIELD_fld_EE_FFT_CMUL_S16_ST_XP_qy, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.CMUL.S16.ST.XP_qx", FIELD_fld_EE_FFT_CMUL_S16_ST_XP_qx, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.BITREV_ax", FIELD_fld_EE_BITREV_ax, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.BITREV_qa", FIELD_fld_EE_BITREV_qa, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.LD.INCP_sel2", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_sel2, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.LD.INCP_qm", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_qm, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.LD.INCP_qy", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_qy, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.LD.INCP_qx", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_qx, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.LD.INCP_qz1", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_qz1, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.LD.INCP_qz", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_qz, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.LD.INCP_as", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_as, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.LD.INCP_qu", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_qu, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.LD.INCP.UAUP_sel2", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_sel2, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.LD.INCP.UAUP_qm", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_qm, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.LD.INCP.UAUP_qy", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_qy, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.LD.INCP.UAUP_qx", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_qx, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.LD.INCP.UAUP_qz1", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_qz1, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.LD.INCP.UAUP_qz", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_qz, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.LD.INCP.UAUP_as", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_as, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.LD.INCP.UAUP_qu", FIELD_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_qu, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.LD.R32.DECP_sel2", FIELD_fld_EE_FFT_AMS_S16_LD_R32_DECP_sel2, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.LD.R32.DECP_qm", FIELD_fld_EE_FFT_AMS_S16_LD_R32_DECP_qm, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.LD.R32.DECP_qy", FIELD_fld_EE_FFT_AMS_S16_LD_R32_DECP_qy, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.LD.R32.DECP_qx", FIELD_fld_EE_FFT_AMS_S16_LD_R32_DECP_qx, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.LD.R32.DECP_qz1", FIELD_fld_EE_FFT_AMS_S16_LD_R32_DECP_qz1, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.LD.R32.DECP_qz", FIELD_fld_EE_FFT_AMS_S16_LD_R32_DECP_qz, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.LD.R32.DECP_as", FIELD_fld_EE_FFT_AMS_S16_LD_R32_DECP_as, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.LD.R32.DECP_qu", FIELD_fld_EE_FFT_AMS_S16_LD_R32_DECP_qu, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.ST.INCP_sel2", FIELD_fld_EE_FFT_AMS_S16_ST_INCP_sel2, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.ST.INCP_qm", FIELD_fld_EE_FFT_AMS_S16_ST_INCP_qm, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.ST.INCP_qy", FIELD_fld_EE_FFT_AMS_S16_ST_INCP_qy, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.ST.INCP_qx", FIELD_fld_EE_FFT_AMS_S16_ST_INCP_qx, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.ST.INCP_as", FIELD_fld_EE_FFT_AMS_S16_ST_INCP_as, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.ST.INCP_as0", FIELD_fld_EE_FFT_AMS_S16_ST_INCP_as0, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.ST.INCP_qz1", FIELD_fld_EE_FFT_AMS_S16_ST_INCP_qz1, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.AMS.S16.ST.INCP_qv", FIELD_fld_EE_FFT_AMS_S16_ST_INCP_qv, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.VST.R32.DECP_sar2", FIELD_fld_EE_FFT_VST_R32_DECP_sar2, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.VST.R32.DECP_as", FIELD_fld_EE_FFT_VST_R32_DECP_as, -1, 0, 0, 0, 0, 0, 0 },
+  { "fld_EE.FFT.VST.R32.DECP_qv", FIELD_fld_EE_FFT_VST_R32_DECP_qv, -1, 0, 0, 0, 0, 0, 0 }
+};
+
+enum xtensa_operand_id {
+  OPERAND_soffsetx4,
+  OPERAND_uimm12x8,
+  OPERAND_simm4,
+  OPERAND_arr,
+  OPERAND_ars,
+  OPERAND__ars_invisible,
+  OPERAND_art,
+  OPERAND_ar0,
+  OPERAND_ar4,
+  OPERAND_ar8,
+  OPERAND_ar12,
+  OPERAND_ars_entry,
+  OPERAND_immrx4,
+  OPERAND_lsi4x4,
+  OPERAND_simm7,
+  OPERAND_uimm6,
+  OPERAND_ai4const,
+  OPERAND_b4const,
+  OPERAND_b4constu,
+  OPERAND_uimm8,
+  OPERAND_uimm8x2,
+  OPERAND_uimm8x4,
+  OPERAND_uimm4x16,
+  OPERAND_uimmrx4,
+  OPERAND_simm8,
+  OPERAND_simm8x256,
+  OPERAND_simm12b,
+  OPERAND_msalp32,
+  OPERAND_op2p1,
+  OPERAND_label8,
+  OPERAND_ulabel8,
+  OPERAND_label12,
+  OPERAND_soffset,
+  OPERAND_uimm16x4,
+  OPERAND_bbi,
+  OPERAND_sae,
+  OPERAND_sas,
+  OPERAND_sargt,
+  OPERAND_s,
+  OPERAND_mx,
+  OPERAND_my,
+  OPERAND_mw,
+  OPERAND_mr0,
+  OPERAND_mr1,
+  OPERAND_mr2,
+  OPERAND_mr3,
+  OPERAND_immt,
+  OPERAND_imms,
+  OPERAND_bt,
+  OPERAND_bs,
+  OPERAND_br,
+  OPERAND_bt2,
+  OPERAND_bs2,
+  OPERAND_br2,
+  OPERAND_bt4,
+  OPERAND_bs4,
+  OPERAND_br4,
+  OPERAND_bt8,
+  OPERAND_bs8,
+  OPERAND_br8,
+  OPERAND_bt16,
+  OPERAND_bs16,
+  OPERAND_br16,
+  OPERAND_brall,
+  OPERAND_tp7,
+  OPERAND_xt_wbr15_label,
+  OPERAND_xt_wbr18_label,
+  OPERAND_frr,
+  OPERAND_frs,
+  OPERAND_frt,
+  OPERAND_imm_t,
+  OPERAND_imm_s,
+  OPERAND_imm8x4,
+  OPERAND_imm8x8,
+  OPERAND_opnd_st_QR_b,
+  OPERAND_opnd_st_QR_a,
+  OPERAND_opnd_ld_QR_b,
+  OPERAND_opnd_ld_QR_a,
+  OPERAND_opnd_imm_QR,
+  OPERAND_opnd_mv_QR_b,
+  OPERAND_opnd_mv_QR_a,
+  OPERAND_opnd_EE_WR_MASK_GPIO_OUT_mask,
+  OPERAND_opnd_EE_WR_MASK_GPIO_OUT_value,
+  OPERAND_opnd_EE_SET_BIT_GPIO_OUT_mask,
+  OPERAND_opnd_EE_CLR_BIT_GPIO_OUT_clear,
+  OPERAND_opnd_EE_GET_GPIO_IN_au,
+  OPERAND_opnd_semantic_LD_ST_imm2,
+  OPERAND_opnd_semantic_LD_ST_imm1,
+  OPERAND_opnd_semantic_LD_ST_qu1,
+  OPERAND_opnd_semantic_LD_ST_imm16f,
+  OPERAND_opnd_semantic_LD_ST_as,
+  OPERAND_opnd_semantic_LD_ST_fu0,
+  OPERAND_opnd_semantic_LD_ST_fu1,
+  OPERAND_opnd_semantic_LD_ST_fu2,
+  OPERAND_opnd_semantic_LD_ST_fu3,
+  OPERAND_opnd_semantic_LD_ST_ad,
+  OPERAND_opnd_semantic_LD_ST_imm8,
+  OPERAND_opnd_semantic_LD_ST_imm16,
+  OPERAND_opnd_semantic_LD_ST_imm4,
+  OPERAND_opnd_semantic_LD_ST_sel8,
+  OPERAND_opnd_semantic_LD_ST_sel4,
+  OPERAND_opnd_semantic_LD_ST_qs,
+  OPERAND_opnd_semantic_LD_ST_qu,
+  OPERAND_opnd_semantic_LD_ST_fv0,
+  OPERAND_opnd_semantic_LD_ST_fv1,
+  OPERAND_opnd_semantic_LD_ST_fv2,
+  OPERAND_opnd_semantic_LD_ST_fv3,
+  OPERAND_opnd_semantic_LD_ST_qv,
+  OPERAND_opnd_EE_MOVI_32_A_sel4,
+  OPERAND_opnd_EE_MOVI_32_A_au,
+  OPERAND_opnd_EE_MOVI_32_A_qs,
+  OPERAND_opnd_EE_MOVI_32_Q_sel4,
+  OPERAND_opnd_EE_MOVI_32_Q_as,
+  OPERAND_opnd_EE_MOVI_32_Q_qu,
+  OPERAND_opnd_EE_VZIP_16_qs1,
+  OPERAND_opnd_EE_VZIP_16_qs0,
+  OPERAND_opnd_EE_VZIP_32_qs1,
+  OPERAND_opnd_EE_VZIP_32_qs0,
+  OPERAND_opnd_EE_VZIP_8_qs1,
+  OPERAND_opnd_EE_VZIP_8_qs0,
+  OPERAND_opnd_EE_VUNZIP_16_qs1,
+  OPERAND_opnd_EE_VUNZIP_16_qs0,
+  OPERAND_opnd_EE_VUNZIP_32_qs1,
+  OPERAND_opnd_EE_VUNZIP_32_qs0,
+  OPERAND_opnd_EE_VUNZIP_8_qs1,
+  OPERAND_opnd_EE_VUNZIP_8_qs0,
+  OPERAND_opnd_EE_ZERO_Q_qa,
+  OPERAND_opnd_EE_MOV_S16_QACC_qs,
+  OPERAND_opnd_EE_MOV_S8_QACC_qs,
+  OPERAND_opnd_EE_MOV_U16_QACC_qs,
+  OPERAND_opnd_EE_MOV_U8_QACC_qs,
+  OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa,
+  OPERAND_opnd_semantic_CAL_DOUBLE_Q_as,
+  OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu,
+  OPERAND_opnd_semantic_CAL_DOUBLE_Q_qv,
+  OPERAND_opnd_semantic_CAL_DOUBLE_Q_sel4,
+  OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy,
+  OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx,
+  OPERAND_opnd_semantic_CAL_DOUBLE_Q_qz,
+  OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs1,
+  OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs0,
+  OPERAND_opnd_semantic_CAL_DOUBLE_Q_imm16,
+  OPERAND_opnd_semantic_CAL_DOUBLE_Q_ad,
+  OPERAND_opnd_semantic_CAL_DOUBLE_Q_sel8,
+  OPERAND_opnd_semantic_CAL_DOUBLE_Q_sel16,
+  OPERAND_opnd_semantic_SRCMB_QACC_sel2,
+  OPERAND_opnd_semantic_SRCMB_QACC_as,
+  OPERAND_opnd_semantic_SRCMB_QACC_qu,
+  OPERAND_opnd_EE_SRS_ACCX_sel2,
+  OPERAND_opnd_EE_SRS_ACCX_as,
+  OPERAND_opnd_EE_SRS_ACCX_au,
+  OPERAND_opnd_semantic_CAL_DOUBLE_Q_ax,
+  OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs,
+  OPERAND_opnd_semantic_CAL_DOUBLE_Q_ay,
+  OPERAND_opnd_semantic_VLOGIC_qy,
+  OPERAND_opnd_semantic_VLOGIC_qx,
+  OPERAND_opnd_semantic_VLOGIC_qa,
+  OPERAND_opnd_semantic_SHFQ_sar16,
+  OPERAND_opnd_semantic_SHFQ_qs0,
+  OPERAND_opnd_semantic_SHFQ_qs1,
+  OPERAND_opnd_semantic_SHFQ_ad,
+  OPERAND_opnd_semantic_SHFQ_as,
+  OPERAND_opnd_semantic_SHFQ_imm16,
+  OPERAND_opnd_semantic_SHFQ_qu,
+  OPERAND_opnd_semantic_SHFQ_qa,
+  OPERAND_opnd_semantic_SHFQ_qs,
+  OPERAND_opnd_semantic_FFT_RxBF_sar4,
+  OPERAND_opnd_semantic_FFT_RxBF_as,
+  OPERAND_opnd_semantic_FFT_RxBF_sel2,
+  OPERAND_opnd_semantic_FFT_RxBF_qy,
+  OPERAND_opnd_semantic_FFT_RxBF_qx,
+  OPERAND_opnd_semantic_FFT_RxBF_qa1,
+  OPERAND_opnd_semantic_FFT_RxBF_qa0,
+  OPERAND_opnd_EE_FFT_CMUL_S16_LD_XP_sel8,
+  OPERAND_opnd_EE_FFT_CMUL_S16_LD_XP_qy,
+  OPERAND_opnd_EE_FFT_CMUL_S16_LD_XP_qx,
+  OPERAND_opnd_EE_FFT_CMUL_S16_LD_XP_qz,
+  OPERAND_opnd_EE_FFT_CMUL_S16_LD_XP_ad,
+  OPERAND_opnd_EE_FFT_CMUL_S16_LD_XP_as,
+  OPERAND_opnd_EE_FFT_CMUL_S16_LD_XP_qu,
+  OPERAND_opnd_EE_FFT_CMUL_S16_ST_XP_sar4,
+  OPERAND_opnd_EE_FFT_CMUL_S16_ST_XP_upd4,
+  OPERAND_opnd_EE_FFT_CMUL_S16_ST_XP_sel8,
+  OPERAND_opnd_EE_FFT_CMUL_S16_ST_XP_ad,
+  OPERAND_opnd_EE_FFT_CMUL_S16_ST_XP_as,
+  OPERAND_opnd_EE_FFT_CMUL_S16_ST_XP_qv,
+  OPERAND_opnd_EE_FFT_CMUL_S16_ST_XP_qy,
+  OPERAND_opnd_EE_FFT_CMUL_S16_ST_XP_qx,
+  OPERAND_opnd_EE_BITREV_ax,
+  OPERAND_opnd_EE_BITREV_qa,
+  OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_sel2,
+  OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_qm,
+  OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_qy,
+  OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_qx,
+  OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_qz1,
+  OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_qz,
+  OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_as,
+  OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_qu,
+  OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_UAUP_sel2,
+  OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_UAUP_qm,
+  OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_UAUP_qy,
+  OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_UAUP_qx,
+  OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_UAUP_qz1,
+  OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_UAUP_qz,
+  OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_UAUP_as,
+  OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_UAUP_qu,
+  OPERAND_opnd_EE_FFT_AMS_S16_LD_R32_DECP_sel2,
+  OPERAND_opnd_EE_FFT_AMS_S16_LD_R32_DECP_qm,
+  OPERAND_opnd_EE_FFT_AMS_S16_LD_R32_DECP_qy,
+  OPERAND_opnd_EE_FFT_AMS_S16_LD_R32_DECP_qx,
+  OPERAND_opnd_EE_FFT_AMS_S16_LD_R32_DECP_qz1,
+  OPERAND_opnd_EE_FFT_AMS_S16_LD_R32_DECP_qz,
+  OPERAND_opnd_EE_FFT_AMS_S16_LD_R32_DECP_as,
+  OPERAND_opnd_EE_FFT_AMS_S16_LD_R32_DECP_qu,
+  OPERAND_opnd_EE_FFT_AMS_S16_ST_INCP_sel2,
+  OPERAND_opnd_EE_FFT_AMS_S16_ST_INCP_qm,
+  OPERAND_opnd_EE_FFT_AMS_S16_ST_INCP_qy,
+  OPERAND_opnd_EE_FFT_AMS_S16_ST_INCP_qx,
+  OPERAND_opnd_EE_FFT_AMS_S16_ST_INCP_as,
+  OPERAND_opnd_EE_FFT_AMS_S16_ST_INCP_as0,
+  OPERAND_opnd_EE_FFT_AMS_S16_ST_INCP_qz1,
+  OPERAND_opnd_EE_FFT_AMS_S16_ST_INCP_qv,
+  OPERAND_opnd_EE_FFT_VST_R32_DECP_sar2,
+  OPERAND_opnd_EE_FFT_VST_R32_DECP_as,
+  OPERAND_opnd_EE_FFT_VST_R32_DECP_qv,
+  OPERAND_t,
+  OPERAND_bbi4,
+  OPERAND_imm12,
+  OPERAND_imm8,
+  OPERAND_imm12b,
+  OPERAND_imm16,
+  OPERAND_m,
+  OPERAND_n,
+  OPERAND_offset,
+  OPERAND_op0,
+  OPERAND_op1,
+  OPERAND_op2,
+  OPERAND_r,
+  OPERAND_sa4,
+  OPERAND_sae4,
+  OPERAND_sal,
+  OPERAND_sas4,
+  OPERAND_sr,
+  OPERAND_st,
+  OPERAND_thi3,
+  OPERAND_imm4,
+  OPERAND_mn,
+  OPERAND_i,
+  OPERAND_imm6lo,
+  OPERAND_imm6hi,
+  OPERAND_imm7lo,
+  OPERAND_imm7hi,
+  OPERAND_z,
+  OPERAND_imm6,
+  OPERAND_imm7,
+  OPERAND_r3,
+  OPERAND_rbit2,
+  OPERAND_rhi,
+  OPERAND_t3,
+  OPERAND_tbit2,
+  OPERAND_tlo,
+  OPERAND_w,
+  OPERAND_y,
+  OPERAND_x,
+  OPERAND_t2,
+  OPERAND_s2,
+  OPERAND_r2,
+  OPERAND_t4,
+  OPERAND_s4,
+  OPERAND_r4,
+  OPERAND_t8,
+  OPERAND_s8,
+  OPERAND_r8,
+  OPERAND_xt_wbr15_imm,
+  OPERAND_xt_wbr18_imm,
+  OPERAND_fld_slot_format_32_0_3_0,
+  OPERAND_fld_slot_format_32_0_28_4,
+  OPERAND_fld_st_QR_b,
+  OPERAND_fld_st_QR_a,
+  OPERAND_fld_ld_QR_b,
+  OPERAND_fld_ld_QR_a,
+  OPERAND_fld_QR,
+  OPERAND_fld_Inst_4_0,
+  OPERAND_fld_Inst_9_6,
+  OPERAND_fld_mv_QR_b,
+  OPERAND_fld_mv_QR_a,
+  OPERAND_fld_EE_WR_MASK_GPIO_OUT_mask,
+  OPERAND_fld_EE_WR_MASK_GPIO_OUT_value,
+  OPERAND_fld_EE_SET_BIT_GPIO_OUT_mask,
+  OPERAND_fld_EE_CLR_BIT_GPIO_OUT_clear,
+  OPERAND_fld_Inst_23_8,
+  OPERAND_fld_EE_GET_GPIO_IN_au,
+  OPERAND_fld_Inst_23_22,
+  OPERAND_fld_semantic_LD_ST_imm2,
+  OPERAND_fld_Inst_14_8,
+  OPERAND_fld_semantic_LD_ST_imm1,
+  OPERAND_fld_Inst_11_8,
+  OPERAND_fld_semantic_LD_ST_qu1,
+  OPERAND_fld_semantic_LD_ST_imm16f,
+  OPERAND_fld_semantic_LD_ST_as,
+  OPERAND_fld_semantic_LD_ST_fu0,
+  OPERAND_fld_semantic_LD_ST_fu1,
+  OPERAND_fld_semantic_LD_ST_fu2,
+  OPERAND_fld_semantic_LD_ST_fu3,
+  OPERAND_fld_slot_format_32_0_28_24,
+  OPERAND_fld_semantic_LD_ST_ad,
+  OPERAND_fld_semantic_LD_ST_imm8,
+  OPERAND_fld_slot_format_32_0_7_5,
+  OPERAND_fld_Inst_3_0,
+  OPERAND_fld_Inst_19_16,
+  OPERAND_fld_Inst_23_23,
+  OPERAND_fld_Inst_14_12,
+  OPERAND_fld_Inst_21_15,
+  OPERAND_fld_semantic_LD_ST_imm16,
+  OPERAND_fld_Inst_23_12,
+  OPERAND_fld_semantic_LD_ST_imm4,
+  OPERAND_fld_semantic_LD_ST_sel8,
+  OPERAND_fld_semantic_LD_ST_sel4,
+  OPERAND_fld_semantic_LD_ST_qs,
+  OPERAND_fld_semantic_LD_ST_qu,
+  OPERAND_fld_slot_format_32_0_28_22,
+  OPERAND_fld_semantic_LD_ST_fv0,
+  OPERAND_fld_semantic_LD_ST_fv1,
+  OPERAND_fld_semantic_LD_ST_fv2,
+  OPERAND_fld_semantic_LD_ST_fv3,
+  OPERAND_fld_semantic_LD_ST_qv,
+  OPERAND_fld_EE_MOVI_32_A_sel4,
+  OPERAND_fld_EE_MOVI_32_A_au,
+  OPERAND_fld_EE_MOVI_32_A_qs,
+  OPERAND_fld_EE_MOVI_32_Q_sel4,
+  OPERAND_fld_EE_MOVI_32_Q_as,
+  OPERAND_fld_EE_MOVI_32_Q_qu,
+  OPERAND_fld_EE_VZIP_16_qs1,
+  OPERAND_fld_EE_VZIP_16_qs0,
+  OPERAND_fld_EE_VZIP_32_qs1,
+  OPERAND_fld_EE_VZIP_32_qs0,
+  OPERAND_fld_EE_VZIP_8_qs1,
+  OPERAND_fld_EE_VZIP_8_qs0,
+  OPERAND_fld_Inst_11_0,
+  OPERAND_fld_EE_VUNZIP_16_qs1,
+  OPERAND_fld_EE_VUNZIP_16_qs0,
+  OPERAND_fld_EE_VUNZIP_32_qs1,
+  OPERAND_fld_EE_VUNZIP_32_qs0,
+  OPERAND_fld_EE_VUNZIP_8_qs1,
+  OPERAND_fld_EE_VUNZIP_8_qs0,
+  OPERAND_fld_Inst_23_0,
+  OPERAND_fld_EE_ZERO_Q_qa,
+  OPERAND_fld_Inst_14_0,
+  OPERAND_fld_EE_MOV_S16_QACC_qs,
+  OPERAND_fld_EE_MOV_S8_QACC_qs,
+  OPERAND_fld_EE_MOV_U16_QACC_qs,
+  OPERAND_fld_EE_MOV_U8_QACC_qs,
+  OPERAND_fld_slot_format_32_0_10_4,
+  OPERAND_fld_Inst_7_0,
+  OPERAND_fld_semantic_CAL_DOUBLE_Q_qa,
+  OPERAND_fld_semantic_CAL_DOUBLE_Q_as,
+  OPERAND_fld_semantic_CAL_DOUBLE_Q_qu,
+  OPERAND_fld_slot_format_32_0_10_6,
+  OPERAND_fld_semantic_CAL_DOUBLE_Q_qv,
+  OPERAND_fld_slot_format_32_0_28_20,
+  OPERAND_fld_Inst_7_6,
+  OPERAND_fld_semantic_CAL_DOUBLE_Q_sel4,
+  OPERAND_fld_semantic_CAL_DOUBLE_Q_qy,
+  OPERAND_fld_semantic_CAL_DOUBLE_Q_qx,
+  OPERAND_fld_semantic_CAL_DOUBLE_Q_qz,
+  OPERAND_fld_semantic_CAL_DOUBLE_Q_qs1,
+  OPERAND_fld_semantic_CAL_DOUBLE_Q_qs0,
+  OPERAND_fld_slot_format_32_0_28_25,
+  OPERAND_fld_semantic_CAL_DOUBLE_Q_imm16,
+  OPERAND_fld_slot_format_32_0_10_8,
+  OPERAND_fld_slot_format_32_0_19_17,
+  OPERAND_fld_slot_format_32_0_28_23,
+  OPERAND_fld_semantic_CAL_DOUBLE_Q_ad,
+  OPERAND_fld_slot_format_32_0_7_4,
+  OPERAND_fld_Inst_23_21,
+  OPERAND_fld_semantic_CAL_DOUBLE_Q_sel8,
+  OPERAND_fld_slot_format_32_0_10_9,
+  OPERAND_fld_Inst_7_5,
+  OPERAND_fld_semantic_CAL_DOUBLE_Q_sel16,
+  OPERAND_fld_Inst_14_11,
+  OPERAND_fld_semantic_SRCMB_QACC_sel2,
+  OPERAND_fld_semantic_SRCMB_QACC_as,
+  OPERAND_fld_semantic_SRCMB_QACC_qu,
+  OPERAND_fld_Inst_13_12,
+  OPERAND_fld_Inst_23_15,
+  OPERAND_fld_EE_SRS_ACCX_sel2,
+  OPERAND_fld_EE_SRS_ACCX_as,
+  OPERAND_fld_EE_SRS_ACCX_au,
+  OPERAND_fld_semantic_CAL_DOUBLE_Q_ax,
+  OPERAND_fld_semantic_CAL_DOUBLE_Q_qs,
+  OPERAND_fld_Inst_13_13,
+  OPERAND_fld_semantic_CAL_DOUBLE_Q_ay,
+  OPERAND_fld_Inst_9_8,
+  OPERAND_fld_semantic_VLOGIC_qy,
+  OPERAND_fld_semantic_VLOGIC_qx,
+  OPERAND_fld_semantic_VLOGIC_qa,
+  OPERAND_fld_Inst_5_5,
+  OPERAND_fld_semantic_SHFQ_sar16,
+  OPERAND_fld_semantic_SHFQ_qs0,
+  OPERAND_fld_semantic_SHFQ_qs1,
+  OPERAND_fld_semantic_SHFQ_ad,
+  OPERAND_fld_semantic_SHFQ_as,
+  OPERAND_fld_semantic_SHFQ_imm16,
+  OPERAND_fld_semantic_SHFQ_qu,
+  OPERAND_fld_slot_format_32_0_7_6,
+  OPERAND_fld_slot_format_32_0_13_11,
+  OPERAND_fld_Inst_11_7,
+  OPERAND_fld_semantic_SHFQ_qa,
+  OPERAND_fld_Inst_14_7,
+  OPERAND_fld_semantic_SHFQ_qs,
+  OPERAND_fld_semantic_FFT_RxBF_sar4,
+  OPERAND_fld_semantic_FFT_RxBF_as,
+  OPERAND_fld_slot_format_32_0_13_13,
+  OPERAND_fld_Inst_9_9,
+  OPERAND_fld_semantic_FFT_RxBF_sel2,
+  OPERAND_fld_semantic_FFT_RxBF_qy,
+  OPERAND_fld_semantic_FFT_RxBF_qx,
+  OPERAND_fld_semantic_FFT_RxBF_qa1,
+  OPERAND_fld_semantic_FFT_RxBF_qa0,
+  OPERAND_fld_EE_FFT_CMUL_S16_LD_XP_sel8,
+  OPERAND_fld_EE_FFT_CMUL_S16_LD_XP_qy,
+  OPERAND_fld_EE_FFT_CMUL_S16_LD_XP_qx,
+  OPERAND_fld_EE_FFT_CMUL_S16_LD_XP_qz,
+  OPERAND_fld_EE_FFT_CMUL_S16_LD_XP_ad,
+  OPERAND_fld_EE_FFT_CMUL_S16_LD_XP_as,
+  OPERAND_fld_EE_FFT_CMUL_S16_LD_XP_qu,
+  OPERAND_fld_EE_FFT_CMUL_S16_ST_XP_sar4,
+  OPERAND_fld_EE_FFT_CMUL_S16_ST_XP_upd4,
+  OPERAND_fld_EE_FFT_CMUL_S16_ST_XP_sel8,
+  OPERAND_fld_EE_FFT_CMUL_S16_ST_XP_ad,
+  OPERAND_fld_EE_FFT_CMUL_S16_ST_XP_as,
+  OPERAND_fld_EE_FFT_CMUL_S16_ST_XP_qv,
+  OPERAND_fld_EE_FFT_CMUL_S16_ST_XP_qy,
+  OPERAND_fld_EE_FFT_CMUL_S16_ST_XP_qx,
+  OPERAND_fld_EE_BITREV_ax,
+  OPERAND_fld_EE_BITREV_qa,
+  OPERAND_fld_EE_FFT_AMS_S16_LD_INCP_sel2,
+  OPERAND_fld_EE_FFT_AMS_S16_LD_INCP_qm,
+  OPERAND_fld_EE_FFT_AMS_S16_LD_INCP_qy,
+  OPERAND_fld_EE_FFT_AMS_S16_LD_INCP_qx,
+  OPERAND_fld_EE_FFT_AMS_S16_LD_INCP_qz1,
+  OPERAND_fld_EE_FFT_AMS_S16_LD_INCP_qz,
+  OPERAND_fld_EE_FFT_AMS_S16_LD_INCP_as,
+  OPERAND_fld_EE_FFT_AMS_S16_LD_INCP_qu,
+  OPERAND_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_sel2,
+  OPERAND_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_qm,
+  OPERAND_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_qy,
+  OPERAND_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_qx,
+  OPERAND_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_qz1,
+  OPERAND_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_qz,
+  OPERAND_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_as,
+  OPERAND_fld_EE_FFT_AMS_S16_LD_INCP_UAUP_qu,
+  OPERAND_fld_EE_FFT_AMS_S16_LD_R32_DECP_sel2,
+  OPERAND_fld_EE_FFT_AMS_S16_LD_R32_DECP_qm,
+  OPERAND_fld_EE_FFT_AMS_S16_LD_R32_DECP_qy,
+  OPERAND_fld_EE_FFT_AMS_S16_LD_R32_DECP_qx,
+  OPERAND_fld_EE_FFT_AMS_S16_LD_R32_DECP_qz1,
+  OPERAND_fld_EE_FFT_AMS_S16_LD_R32_DECP_qz,
+  OPERAND_fld_EE_FFT_AMS_S16_LD_R32_DECP_as,
+  OPERAND_fld_EE_FFT_AMS_S16_LD_R32_DECP_qu,
+  OPERAND_fld_EE_FFT_AMS_S16_ST_INCP_sel2,
+  OPERAND_fld_EE_FFT_AMS_S16_ST_INCP_qm,
+  OPERAND_fld_EE_FFT_AMS_S16_ST_INCP_qy,
+  OPERAND_fld_EE_FFT_AMS_S16_ST_INCP_qx,
+  OPERAND_fld_EE_FFT_AMS_S16_ST_INCP_as,
+  OPERAND_fld_EE_FFT_AMS_S16_ST_INCP_as0,
+  OPERAND_fld_EE_FFT_AMS_S16_ST_INCP_qz1,
+  OPERAND_fld_EE_FFT_AMS_S16_ST_INCP_qv,
+  OPERAND_fld_EE_FFT_VST_R32_DECP_sar2,
+  OPERAND_fld_EE_FFT_VST_R32_DECP_as,
+  OPERAND_fld_EE_FFT_VST_R32_DECP_qv
+};
+
+\f
+/* Iclass table.  */
+
+static xtensa_arg_internal Iclass_LSI_args[] = {
+  { { OPERAND_frt }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_imm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_LSI_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_LSIP_args[] = {
+  { { OPERAND_frt }, 'o' },
+  { { OPERAND_ars }, 'm' },
+  { { OPERAND_imm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_LSIP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_LSX_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_LSX_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_LSXP_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_ars }, 'm' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_LSXP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_SSI_args[] = {
+  { { OPERAND_frt }, 'i' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_imm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_SSI_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_SSIP_args[] = {
+  { { OPERAND_frt }, 'i' },
+  { { OPERAND_ars }, 'm' },
+  { { OPERAND_imm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_SSIP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_SSX_args[] = {
+  { { OPERAND_frr }, 'i' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_SSX_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_SSXP_args[] = {
+  { { OPERAND_frr }, 'i' },
+  { { OPERAND_ars }, 'm' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_SSXP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ABS_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ABS_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_NEG_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_NEG_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOV_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOV_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOVEQZ_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOVEQZ_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOVNEZ_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOVNEZ_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOVLTZ_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOVLTZ_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOVGEZ_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOVGEZ_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOVF_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_bt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOVF_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOVT_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_bt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MOVT_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_WFR_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_WFR_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_RFR_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_RFR_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ROUND_S_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_imm_t }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ROUND_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_CEIL_S_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_imm_t }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_CEIL_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_FLOOR_S_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_imm_t }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_FLOOR_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_TRUNC_S_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_imm_t }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_TRUNC_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_UTRUNC_S_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_imm_t }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_UTRUNC_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_FLOAT_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_imm_t }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_FLOAT_S_stateArgs[] = {
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_RoundMode }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_UFLOAT_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_imm_t }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_UFLOAT_S_stateArgs[] = {
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_RoundMode }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_UN_S_args[] = {
+  { { OPERAND_br }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_UN_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ULT_S_args[] = {
+  { { OPERAND_br }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ULT_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ULE_S_args[] = {
+  { { OPERAND_br }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ULE_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_UEQ_S_args[] = {
+  { { OPERAND_br }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_UEQ_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_OLT_S_args[] = {
+  { { OPERAND_br }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_OLT_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_OLE_S_args[] = {
+  { { OPERAND_br }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_OLE_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_OEQ_S_args[] = {
+  { { OPERAND_br }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_OEQ_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ADD_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ADD_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_OverflowFlag }, 'm' },
+  { { STATE_UnderflowFlag }, 'm' },
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_RoundMode }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_SUB_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_SUB_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_OverflowFlag }, 'm' },
+  { { STATE_UnderflowFlag }, 'm' },
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_RoundMode }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MUL_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MUL_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_OverflowFlag }, 'm' },
+  { { STATE_UnderflowFlag }, 'm' },
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_RoundMode }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MADD_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MADD_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_OverflowFlag }, 'm' },
+  { { STATE_UnderflowFlag }, 'm' },
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_RoundMode }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MSUB_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MSUB_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_OverflowFlag }, 'm' },
+  { { STATE_UnderflowFlag }, 'm' },
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_RoundMode }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_SQRT0_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_SQRT0_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_DIV0_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_DIV0_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_RECIP0_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_RECIP0_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_DivZeroFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_RSQRT0_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_RSQRT0_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_DivZeroFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MADDN_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MADDN_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_DIVN_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' },
+  { { OPERAND_frt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_DIVN_S_stateArgs[] = {
+  { { STATE_OverflowFlag }, 'm' },
+  { { STATE_UnderflowFlag }, 'm' },
+  { { STATE_InexactFlag }, 'm' },
+  { { STATE_RoundMode }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_CONST_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_imm_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_CONST_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_NEXP01_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_NEXP01_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ADDEXP_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ADDEXP_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ADDEXPM_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ADDEXPM_S_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MKDADJ_S_args[] = {
+  { { OPERAND_frr }, 'm' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MKDADJ_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_DivZeroFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MKSADJ_S_args[] = {
+  { { OPERAND_frr }, 'o' },
+  { { OPERAND_frs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_MKSADJ_S_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
+  { { STATE_PSEXCM }, 'o' },
+  { { STATE_EPC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
+  { { STATE_DEPC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
+  { { OPERAND_soffsetx4 }, 'i' },
+  { { OPERAND_ar12 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
+  { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
+  { { OPERAND_soffsetx4 }, 'i' },
+  { { OPERAND_ar8 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
+  { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
+  { { OPERAND_soffsetx4 }, 'i' },
+  { { OPERAND_ar4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
+  { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_ar12 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
+  { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_ar8 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
+  { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_ar4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
+  { { STATE_PSCALLINC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
+  { { OPERAND_ars_entry }, 's' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm12x8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
+  { { STATE_PSCALLINC }, 'i' },
+  { { STATE_PSEXCM }, 'i' },
+  { { STATE_PSWOE }, 'i' },
+  { { STATE_WindowBase }, 'm' },
+  { { STATE_WindowStart }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
+  { { STATE_WindowBase }, 'i' },
+  { { STATE_WindowStart }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
+  { { OPERAND_simm4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
+  { { STATE_WindowBase }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
+  { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
+  { { STATE_WindowBase }, 'm' },
+  { { STATE_WindowStart }, 'm' },
+  { { STATE_PSCALLINC }, 'o' },
+  { { STATE_PSEXCM }, 'i' },
+  { { STATE_PSWOE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
+  { { STATE_EPC1 }, 'i' },
+  { { STATE_PSEXCM }, 'o' },
+  { { STATE_WindowBase }, 'm' },
+  { { STATE_WindowStart }, 'm' },
+  { { STATE_PSOWB }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_immrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_immrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
+  { { STATE_WindowBase }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
+  { { STATE_WindowBase }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
+  { { STATE_WindowBase }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
+  { { STATE_WindowStart }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
+  { { STATE_WindowStart }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
+  { { STATE_WindowStart }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_ai4const }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_lsi4x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
+  { { OPERAND_ars }, 'o' },
+  { { OPERAND_simm7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
+  { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_lsi4x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
+  { { STATE_THREADPTR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
+  { { STATE_THREADPTR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_simm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_simm8x256 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_b4const }, 'i' },
+  { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_bbi }, 'i' },
+  { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_b4constu }, 'i' },
+  { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_label12 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
+  { { OPERAND_soffsetx4 }, 'i' },
+  { { OPERAND_ar0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_ar0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_sae }, 'i' },
+  { { OPERAND_op2p1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
+  { { OPERAND_soffset }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_uimm16x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_ulabel8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
+  { { STATE_LBEG }, 'o' },
+  { { STATE_LEND }, 'o' },
+  { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_ulabel8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
+  { { STATE_LBEG }, 'o' },
+  { { STATE_LEND }, 'o' },
+  { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_simm12b }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
+  { { OPERAND_arr }, 'm' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
+  { { OPERAND__ars_invisible }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8x2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimmrx4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
+  { { STATE_SAR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
+  { { OPERAND_sas }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
+  { { STATE_SAR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
+  { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
+  { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
+  { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_msalp32 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_sargt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
+  { { STATE_XTSYNC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
+  { { STATE_PSWOE }, 'i' },
+  { { STATE_PSCALLINC }, 'i' },
+  { { STATE_PSOWB }, 'i' },
+  { { STATE_PSUM }, 'i' },
+  { { STATE_PSEXCM }, 'i' },
+  { { STATE_PSINTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
+  { { STATE_LEND }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
+  { { STATE_LEND }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
+  { { STATE_LEND }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
+  { { STATE_LCOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_LCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_LCOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
+  { { STATE_LBEG }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
+  { { STATE_LBEG }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
+  { { STATE_LBEG }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
+  { { STATE_SAR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
+  { { STATE_SAR }, 'o' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
+  { { STATE_SAR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_stateArgs[] = {
+  { { STATE_MEMCTL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_stateArgs[] = {
+  { { STATE_MEMCTL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_stateArgs[] = {
+  { { STATE_MEMCTL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
+  { { STATE_PSWOE }, 'i' },
+  { { STATE_PSCALLINC }, 'i' },
+  { { STATE_PSOWB }, 'i' },
+  { { STATE_PSUM }, 'i' },
+  { { STATE_PSEXCM }, 'i' },
+  { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
+  { { STATE_PSWOE }, 'o' },
+  { { STATE_PSCALLINC }, 'o' },
+  { { STATE_PSOWB }, 'o' },
+  { { STATE_PSUM }, 'o' },
+  { { STATE_PSEXCM }, 'o' },
+  { { STATE_PSINTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
+  { { STATE_PSWOE }, 'm' },
+  { { STATE_PSCALLINC }, 'm' },
+  { { STATE_PSOWB }, 'm' },
+  { { STATE_PSUM }, 'm' },
+  { { STATE_PSEXCM }, 'm' },
+  { { STATE_PSINTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
+  { { STATE_EPC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
+  { { STATE_EPC1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
+  { { STATE_EPC1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
+  { { STATE_EXCSAVE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
+  { { STATE_EXCSAVE1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
+  { { STATE_EXCSAVE1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
+  { { STATE_EPC2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
+  { { STATE_EPC2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
+  { { STATE_EPC2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
+  { { STATE_EXCSAVE2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
+  { { STATE_EXCSAVE2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
+  { { STATE_EXCSAVE2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
+  { { STATE_EPC3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
+  { { STATE_EPC3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
+  { { STATE_EPC3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
+  { { STATE_EXCSAVE3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
+  { { STATE_EXCSAVE3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
+  { { STATE_EXCSAVE3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
+  { { STATE_EPC4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
+  { { STATE_EPC4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
+  { { STATE_EPC4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
+  { { STATE_EXCSAVE4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
+  { { STATE_EXCSAVE4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
+  { { STATE_EXCSAVE4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
+  { { STATE_EPC5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
+  { { STATE_EPC5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
+  { { STATE_EPC5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
+  { { STATE_EXCSAVE5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
+  { { STATE_EXCSAVE5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
+  { { STATE_EXCSAVE5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
+  { { STATE_EPC6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
+  { { STATE_EPC6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
+  { { STATE_EPC6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
+  { { STATE_EXCSAVE6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
+  { { STATE_EXCSAVE6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
+  { { STATE_EXCSAVE6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
+  { { STATE_EPC7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
+  { { STATE_EPC7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
+  { { STATE_EPC7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
+  { { STATE_EXCSAVE7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
+  { { STATE_EXCSAVE7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
+  { { STATE_EXCSAVE7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
+  { { STATE_EPS2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
+  { { STATE_EPS2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
+  { { STATE_EPS2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
+  { { STATE_EPS3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
+  { { STATE_EPS3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
+  { { STATE_EPS3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
+  { { STATE_EPS4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
+  { { STATE_EPS4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
+  { { STATE_EPS4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
+  { { STATE_EPS5 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
+  { { STATE_EPS5 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
+  { { STATE_EPS5 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
+  { { STATE_EPS6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
+  { { STATE_EPS6 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
+  { { STATE_EPS6 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
+  { { STATE_EPS7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
+  { { STATE_EPS7 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
+  { { STATE_EPS7 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
+  { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
+  { { STATE_EXCVADDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
+  { { STATE_EXCVADDR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
+  { { STATE_DEPC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
+  { { STATE_DEPC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
+  { { STATE_DEPC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
+  { { STATE_EXCCAUSE }, 'i' },
+  { { STATE_XTSYNC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
+  { { STATE_EXCCAUSE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
+  { { STATE_EXCCAUSE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
+  { { STATE_MISC0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
+  { { STATE_MISC0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
+  { { STATE_MISC0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
+  { { STATE_MISC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
+  { { STATE_MISC1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
+  { { STATE_MISC1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_stateArgs[] = {
+  { { STATE_MISC2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_stateArgs[] = {
+  { { STATE_MISC2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_stateArgs[] = {
+  { { STATE_MISC2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_stateArgs[] = {
+  { { STATE_MISC3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_stateArgs[] = {
+  { { STATE_MISC3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_stateArgs[] = {
+  { { STATE_MISC3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
+  { { STATE_VECBASE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
+  { { STATE_VECBASE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
+  { { STATE_VECBASE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_salt_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul16_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul32_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul32h_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
+  { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
+  { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
+  { { OPERAND_mx }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
+  { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
+  { { OPERAND_mx }, 'i' },
+  { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
+  { { STATE_ACC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
+  { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
+  { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
+  { { OPERAND_mx }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
+  { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
+  { { OPERAND_mx }, 'i' },
+  { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
+  { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
+  { { OPERAND_mw }, 'o' },
+  { { OPERAND_ars }, 'm' },
+  { { OPERAND_mx }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
+  { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
+  { { OPERAND_mw }, 'o' },
+  { { OPERAND_ars }, 'm' },
+  { { OPERAND_mx }, 'i' },
+  { { OPERAND_my }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
+  { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
+  { { OPERAND_mw }, 'o' },
+  { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_mr0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_mr0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
+  { { OPERAND_art }, 'm' },
+  { { OPERAND_mr0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_mr1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_mr1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
+  { { OPERAND_art }, 'm' },
+  { { OPERAND_mr1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_mr2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_mr2 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
+  { { OPERAND_art }, 'm' },
+  { { OPERAND_mr2 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_mr3 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_mr3 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
+  { { OPERAND_art }, 'm' },
+  { { OPERAND_mr3 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
+  { { STATE_ACC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
+  { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
+  { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
+  { { STATE_ACC }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
+  { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
+  { { STATE_ACC }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
+  { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
+  { { STATE_PSWOE }, 'o' },
+  { { STATE_PSCALLINC }, 'o' },
+  { { STATE_PSOWB }, 'o' },
+  { { STATE_PSUM }, 'o' },
+  { { STATE_PSEXCM }, 'o' },
+  { { STATE_PSINTLEVEL }, 'o' },
+  { { STATE_EPC1 }, 'i' },
+  { { STATE_EPC2 }, 'i' },
+  { { STATE_EPC3 }, 'i' },
+  { { STATE_EPC4 }, 'i' },
+  { { STATE_EPC5 }, 'i' },
+  { { STATE_EPC6 }, 'i' },
+  { { STATE_EPC7 }, 'i' },
+  { { STATE_EPS2 }, 'i' },
+  { { STATE_EPS3 }, 'i' },
+  { { STATE_EPS4 }, 'i' },
+  { { STATE_EPS5 }, 'i' },
+  { { STATE_EPS6 }, 'i' },
+  { { STATE_EPS7 }, 'i' },
+  { { STATE_InOCDMode }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
+  { { OPERAND_s }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
+  { { STATE_PSINTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
+  { { STATE_INTERRUPT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
+  { { STATE_INTENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
+  { { STATE_INTENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
+  { { STATE_INTENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
+  { { OPERAND_imms }, 'i' },
+  { { OPERAND_immt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
+  { { STATE_PSEXCM }, 'i' },
+  { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
+  { { OPERAND_imms }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
+  { { STATE_PSEXCM }, 'i' },
+  { { STATE_PSINTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
+  { { STATE_DBREAKA0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
+  { { STATE_DBREAKA0 }, 'o' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
+  { { STATE_DBREAKA0 }, 'm' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
+  { { STATE_DBREAKC0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
+  { { STATE_DBREAKC0 }, 'o' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
+  { { STATE_DBREAKC0 }, 'm' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
+  { { STATE_DBREAKA1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
+  { { STATE_DBREAKA1 }, 'o' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
+  { { STATE_DBREAKA1 }, 'm' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
+  { { STATE_DBREAKC1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
+  { { STATE_DBREAKC1 }, 'o' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
+  { { STATE_DBREAKC1 }, 'm' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
+  { { STATE_IBREAKA0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
+  { { STATE_IBREAKA0 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
+  { { STATE_IBREAKA0 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
+  { { STATE_IBREAKA1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
+  { { STATE_IBREAKA1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
+  { { STATE_IBREAKA1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
+  { { STATE_IBREAKENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
+  { { STATE_IBREAKENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
+  { { STATE_IBREAKENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
+  { { STATE_DEBUGCAUSE }, 'i' },
+  { { STATE_DBNUM }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
+  { { STATE_DEBUGCAUSE }, 'o' },
+  { { STATE_DBNUM }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
+  { { STATE_DEBUGCAUSE }, 'm' },
+  { { STATE_DBNUM }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
+  { { STATE_ICOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_ICOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_ICOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
+  { { STATE_ICOUNTLEVEL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
+  { { STATE_ICOUNTLEVEL }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
+  { { STATE_ICOUNTLEVEL }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
+  { { STATE_DDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_DDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_DDR }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = {
+  { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_InOCDMode }, 'i' },
+  { { STATE_DDR }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = {
+  { { OPERAND_ars }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = {
+  { { STATE_InOCDMode }, 'i' },
+  { { STATE_DDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
+  { { OPERAND_imms }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
+  { { STATE_InOCDMode }, 'm' },
+  { { STATE_EPC6 }, 'i' },
+  { { STATE_PSWOE }, 'o' },
+  { { STATE_PSCALLINC }, 'o' },
+  { { STATE_PSOWB }, 'o' },
+  { { STATE_PSUM }, 'o' },
+  { { STATE_PSEXCM }, 'o' },
+  { { STATE_PSINTLEVEL }, 'o' },
+  { { STATE_EPS6 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
+  { { STATE_InOCDMode }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = {
+  { { OPERAND_br }, 'o' },
+  { { OPERAND_bs }, 'i' },
+  { { OPERAND_bt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = {
+  { { OPERAND_bt }, 'o' },
+  { { OPERAND_bs4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = {
+  { { OPERAND_bt }, 'o' },
+  { { OPERAND_bs8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = {
+  { { OPERAND_bs }, 'i' },
+  { { OPERAND_label8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = {
+  { { OPERAND_arr }, 'm' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_bt }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_brall }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_brall }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = {
+  { { OPERAND_art }, 'm' },
+  { { OPERAND_brall }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
+  { { STATE_CCOUNT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_CCOUNT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' },
+  { { STATE_CCOUNT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
+  { { STATE_CCOMPARE0 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
+  { { STATE_CCOMPARE0 }, 'o' },
+  { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
+  { { STATE_CCOMPARE0 }, 'm' },
+  { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
+  { { STATE_CCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
+  { { STATE_CCOMPARE1 }, 'o' },
+  { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
+  { { STATE_CCOMPARE1 }, 'm' },
+  { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
+  { { STATE_CCOMPARE2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
+  { { STATE_CCOMPARE2 }, 'o' },
+  { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
+  { { STATE_CCOMPARE2 }, 'm' },
+  { { STATE_INTERRUPT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
+  { { STATE_CPENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
+  { { STATE_CPENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_tp7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_tp7 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
+  { { OPERAND_art }, 'm' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_uimm8x4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
+  { { STATE_SCOMPARE1 }, 'i' },
+  { { STATE_XTSYNC }, 'i' },
+  { { STATE_SCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
+  { { STATE_SCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
+  { { STATE_SCOMPARE1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
+  { { STATE_SCOMPARE1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = {
+  { { STATE_ATOMCTL }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = {
+  { { STATE_ATOMCTL }, 'o' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = {
+  { { STATE_ATOMCTL }, 'm' },
+  { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
+  { { OPERAND_arr }, 'o' },
+  { { OPERAND_ars }, 'i' },
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_args[] = {
+  { { OPERAND_art }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_args[] = {
+  { { OPERAND_art }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = {
+  { { OPERAND_art }, 'o' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = {
+  { { STATE_ERI_RAW_INTERLOCK }, 'i' }
+};
+
+static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = {
+  INTERFACE_ERI_RD_In,
+  INTERFACE_ERI_RD_Out
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = {
+  { { OPERAND_art }, 'i' },
+  { { OPERAND_ars }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = {
+  { { STATE_ERI_RAW_INTERLOCK }, 'o' }
+};
+
+static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = {
+  INTERFACE_ERI_WR_In,
+  INTERFACE_ERI_WR_Out
+};
+
+static xtensa_arg_internal Iclass_rur_fcr_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_fcr_stateArgs[] = {
+  { { STATE_RoundMode }, 'i' },
+  { { STATE_InvalidEnable }, 'i' },
+  { { STATE_DivZeroEnable }, 'i' },
+  { { STATE_OverflowEnable }, 'i' },
+  { { STATE_UnderflowEnable }, 'i' },
+  { { STATE_InexactEnable }, 'i' },
+  { { STATE_FPreserved20 }, 'i' },
+  { { STATE_FPreserved5 }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_fcr_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_fcr_stateArgs[] = {
+  { { STATE_RoundMode }, 'o' },
+  { { STATE_InvalidEnable }, 'o' },
+  { { STATE_DivZeroEnable }, 'o' },
+  { { STATE_OverflowEnable }, 'o' },
+  { { STATE_UnderflowEnable }, 'o' },
+  { { STATE_InexactEnable }, 'o' },
+  { { STATE_FPreserved20 }, 'o' },
+  { { STATE_FPreserved5 }, 'o' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_fsr_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_fsr_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'i' },
+  { { STATE_DivZeroFlag }, 'i' },
+  { { STATE_OverflowFlag }, 'i' },
+  { { STATE_UnderflowFlag }, 'i' },
+  { { STATE_InexactFlag }, 'i' },
+  { { STATE_FPreserved20a }, 'i' },
+  { { STATE_FPreserved7 }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_fsr_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_fsr_stateArgs[] = {
+  { { STATE_InvalidFlag }, 'o' },
+  { { STATE_DivZeroFlag }, 'o' },
+  { { STATE_OverflowFlag }, 'o' },
+  { { STATE_UnderflowFlag }, 'o' },
+  { { STATE_InexactFlag }, 'o' },
+  { { STATE_FPreserved20a }, 'o' },
+  { { STATE_FPreserved7 }, 'o' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_st_QR_args[] = {
+  { { OPERAND_opnd_st_QR_a }, 'i' },
+  { { OPERAND_opnd_st_QR_b }, 'i' },
+  { { OPERAND_opnd_imm_QR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_st_QR_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ld_QR_args[] = {
+  { { OPERAND_opnd_ld_QR_a }, 'o' },
+  { { OPERAND_opnd_ld_QR_b }, 'i' },
+  { { OPERAND_opnd_imm_QR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_ld_QR_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_mv_QR_args[] = {
+  { { OPERAND_opnd_mv_QR_a }, 'o' },
+  { { OPERAND_opnd_mv_QR_b }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_mv_QR_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_WR_MASK_GPIO_OUT_args[] = {
+  { { OPERAND_opnd_EE_WR_MASK_GPIO_OUT_value }, 'i' },
+  { { OPERAND_opnd_EE_WR_MASK_GPIO_OUT_mask }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_WR_MASK_GPIO_OUT_stateArgs[] = {
+  { { STATE_GPIO_OUT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_EE_SET_BIT_GPIO_OUT_args[] = {
+  { { OPERAND_opnd_EE_SET_BIT_GPIO_OUT_mask }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_SET_BIT_GPIO_OUT_stateArgs[] = {
+  { { STATE_GPIO_OUT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_EE_CLR_BIT_GPIO_OUT_args[] = {
+  { { OPERAND_opnd_EE_CLR_BIT_GPIO_OUT_clear }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_CLR_BIT_GPIO_OUT_stateArgs[] = {
+  { { STATE_GPIO_OUT }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_EE_GET_GPIO_IN_args[] = {
+  { { OPERAND_opnd_EE_GET_GPIO_IN_au }, 'o' }
+};
+
+static xtensa_interface Iclass_EE_GET_GPIO_IN_intfArgs[] = {
+  INTERFACE_GPIO_IN
+};
+
+static xtensa_arg_internal Iclass_EE_VLD_128_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qu }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLD_128_IP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLD_128_XP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qu }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_ad }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLD_128_XP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLD_H_64_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qu }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLD_H_64_IP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLD_H_64_XP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qu }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_ad }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLD_H_64_XP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLD_L_64_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qu }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLD_L_64_IP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLD_L_64_XP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qu }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_ad }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLD_L_64_XP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLDBC_16_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qu }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLDBC_16_IP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLDBC_16_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qu }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLDBC_16_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLDBC_16_XP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qu }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_ad }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLDBC_16_XP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLDBC_32_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qu }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLDBC_32_IP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLDBC_32_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qu }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLDBC_32_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLDBC_32_XP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qu }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_ad }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLDBC_32_XP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLDBC_8_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qu }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLDBC_8_IP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLDBC_8_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qu }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLDBC_8_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLDBC_8_XP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qu }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_ad }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLDBC_8_XP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLDHBC_16_INCP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qu }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_qu1 }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_EE_VLDHBC_16_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDF_128_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_fu3 }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_fu2 }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_fu1 }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_fu0 }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm16f }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDF_128_IP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDF_128_XP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_fu3 }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_fu2 }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_fu1 }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_fu0 }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_ad }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDF_128_XP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDF_64_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_fu1 }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_fu0 }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDF_64_IP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDF_64_XP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_fu1 }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_fu0 }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_ad }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDF_64_XP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LD_128_USAR_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qu }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LD_128_USAR_IP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'o' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LD_128_USAR_XP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qu }, 'o' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_ad }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LD_128_USAR_XP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'o' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDQA_S16_128_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDQA_S16_128_IP_stateArgs[] = {
+  { { STATE_QACC_L }, 'o' },
+  { { STATE_QACC_H }, 'o' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDQA_S16_128_XP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_ad }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDQA_S16_128_XP_stateArgs[] = {
+  { { STATE_QACC_L }, 'o' },
+  { { STATE_QACC_H }, 'o' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDQA_S8_128_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDQA_S8_128_IP_stateArgs[] = {
+  { { STATE_QACC_L }, 'o' },
+  { { STATE_QACC_H }, 'o' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDQA_S8_128_XP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_ad }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDQA_S8_128_XP_stateArgs[] = {
+  { { STATE_QACC_L }, 'o' },
+  { { STATE_QACC_H }, 'o' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDQA_U16_128_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDQA_U16_128_IP_stateArgs[] = {
+  { { STATE_QACC_L }, 'o' },
+  { { STATE_QACC_H }, 'o' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDQA_U16_128_XP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_ad }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDQA_U16_128_XP_stateArgs[] = {
+  { { STATE_QACC_L }, 'o' },
+  { { STATE_QACC_H }, 'o' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDQA_U8_128_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDQA_U8_128_IP_stateArgs[] = {
+  { { STATE_QACC_L }, 'o' },
+  { { STATE_QACC_H }, 'o' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDQA_U8_128_XP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_ad }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDQA_U8_128_XP_stateArgs[] = {
+  { { STATE_QACC_L }, 'o' },
+  { { STATE_QACC_H }, 'o' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LD_QACC_H_H_32_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LD_QACC_H_H_32_IP_stateArgs[] = {
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LD_QACC_H_L_128_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LD_QACC_H_L_128_IP_stateArgs[] = {
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LD_QACC_L_H_32_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LD_QACC_L_H_32_IP_stateArgs[] = {
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LD_QACC_L_L_128_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LD_QACC_L_L_128_IP_stateArgs[] = {
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LD_ACCX_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LD_ACCX_IP_stateArgs[] = {
+  { { STATE_ACCX }, 'o' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDXQ_32_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qu }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_qs }, 'i' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'i' },
+  { { OPERAND_opnd_semantic_LD_ST_sel4 }, 'i' },
+  { { OPERAND_opnd_semantic_LD_ST_sel8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LDXQ_32_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LD_UA_STATE_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_LD_UA_STATE_IP_stateArgs[] = {
+  { { STATE_UA_STATE }, 'o' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_ST_UA_STATE_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_ST_UA_STATE_IP_stateArgs[] = {
+  { { STATE_UA_STATE }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VST_128_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qv }, 'i' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VST_128_IP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VST_128_XP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qv }, 'i' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_ad }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VST_128_XP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VST_H_64_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qv }, 'i' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VST_H_64_IP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VST_H_64_XP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qv }, 'i' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_ad }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VST_H_64_XP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VST_L_64_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qv }, 'i' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VST_L_64_IP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VST_L_64_XP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qv }, 'i' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_ad }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VST_L_64_XP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_STF_128_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_fv3 }, 'i' },
+  { { OPERAND_opnd_semantic_LD_ST_fv2 }, 'i' },
+  { { OPERAND_opnd_semantic_LD_ST_fv1 }, 'i' },
+  { { OPERAND_opnd_semantic_LD_ST_fv0 }, 'i' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm16f }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_STF_128_IP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_STF_128_XP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_fv3 }, 'i' },
+  { { OPERAND_opnd_semantic_LD_ST_fv2 }, 'i' },
+  { { OPERAND_opnd_semantic_LD_ST_fv1 }, 'i' },
+  { { OPERAND_opnd_semantic_LD_ST_fv0 }, 'i' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_ad }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_STF_128_XP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_STF_64_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_fv1 }, 'i' },
+  { { OPERAND_opnd_semantic_LD_ST_fv0 }, 'i' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_STF_64_IP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_STF_64_XP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_fv1 }, 'i' },
+  { { OPERAND_opnd_semantic_LD_ST_fv0 }, 'i' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_ad }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_STF_64_XP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_ST_QACC_H_H_32_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_ST_QACC_H_H_32_IP_stateArgs[] = {
+  { { STATE_QACC_H }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_ST_QACC_H_L_128_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_ST_QACC_H_L_128_IP_stateArgs[] = {
+  { { STATE_QACC_H }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_ST_QACC_L_H_32_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_ST_QACC_L_H_32_IP_stateArgs[] = {
+  { { STATE_QACC_L }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_ST_QACC_L_L_128_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_ST_QACC_L_L_128_IP_stateArgs[] = {
+  { { STATE_QACC_L }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_ST_ACCX_IP_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'm' },
+  { { OPERAND_opnd_semantic_LD_ST_imm8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_ST_ACCX_IP_stateArgs[] = {
+  { { STATE_ACCX }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_STXQ_32_args[] = {
+  { { OPERAND_opnd_semantic_LD_ST_qv }, 'i' },
+  { { OPERAND_opnd_semantic_LD_ST_qs }, 'i' },
+  { { OPERAND_opnd_semantic_LD_ST_as }, 'i' },
+  { { OPERAND_opnd_semantic_LD_ST_sel4 }, 'i' },
+  { { OPERAND_opnd_semantic_LD_ST_sel8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_STXQ_32_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_MOVI_32_A_args[] = {
+  { { OPERAND_opnd_EE_MOVI_32_A_qs }, 'i' },
+  { { OPERAND_opnd_EE_MOVI_32_A_au }, 'o' },
+  { { OPERAND_opnd_EE_MOVI_32_A_sel4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_MOVI_32_A_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_MOVI_32_Q_args[] = {
+  { { OPERAND_opnd_EE_MOVI_32_Q_qu }, 'm' },
+  { { OPERAND_opnd_EE_MOVI_32_Q_as }, 'i' },
+  { { OPERAND_opnd_EE_MOVI_32_Q_sel4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_MOVI_32_Q_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VZIP_16_args[] = {
+  { { OPERAND_opnd_EE_VZIP_16_qs0 }, 'm' },
+  { { OPERAND_opnd_EE_VZIP_16_qs1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_EE_VZIP_16_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VZIP_32_args[] = {
+  { { OPERAND_opnd_EE_VZIP_32_qs0 }, 'm' },
+  { { OPERAND_opnd_EE_VZIP_32_qs1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_EE_VZIP_32_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VZIP_8_args[] = {
+  { { OPERAND_opnd_EE_VZIP_8_qs0 }, 'm' },
+  { { OPERAND_opnd_EE_VZIP_8_qs1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_EE_VZIP_8_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VUNZIP_16_args[] = {
+  { { OPERAND_opnd_EE_VUNZIP_16_qs0 }, 'm' },
+  { { OPERAND_opnd_EE_VUNZIP_16_qs1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_EE_VUNZIP_16_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VUNZIP_32_args[] = {
+  { { OPERAND_opnd_EE_VUNZIP_32_qs0 }, 'm' },
+  { { OPERAND_opnd_EE_VUNZIP_32_qs1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_EE_VUNZIP_32_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VUNZIP_8_args[] = {
+  { { OPERAND_opnd_EE_VUNZIP_8_qs0 }, 'm' },
+  { { OPERAND_opnd_EE_VUNZIP_8_qs1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_EE_VUNZIP_8_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_ZERO_ACCX_stateArgs[] = {
+  { { STATE_ACCX }, 'o' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_ZERO_QACC_stateArgs[] = {
+  { { STATE_QACC_L }, 'o' },
+  { { STATE_QACC_H }, 'o' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_ZERO_Q_args[] = {
+  { { OPERAND_opnd_EE_ZERO_Q_qa }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_EE_ZERO_Q_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_MOV_S16_QACC_args[] = {
+  { { OPERAND_opnd_EE_MOV_S16_QACC_qs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_MOV_S16_QACC_stateArgs[] = {
+  { { STATE_QACC_L }, 'o' },
+  { { STATE_QACC_H }, 'o' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_MOV_S8_QACC_args[] = {
+  { { OPERAND_opnd_EE_MOV_S8_QACC_qs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_MOV_S8_QACC_stateArgs[] = {
+  { { STATE_QACC_L }, 'o' },
+  { { STATE_QACC_H }, 'o' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_MOV_U16_QACC_args[] = {
+  { { OPERAND_opnd_EE_MOV_U16_QACC_qs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_MOV_U16_QACC_stateArgs[] = {
+  { { STATE_QACC_L }, 'o' },
+  { { STATE_QACC_H }, 'o' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_MOV_U8_QACC_args[] = {
+  { { OPERAND_opnd_EE_MOV_U8_QACC_qs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_MOV_U8_QACC_stateArgs[] = {
+  { { STATE_QACC_L }, 'o' },
+  { { STATE_QACC_H }, 'o' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VADDS_S16_LD_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VADDS_S16_LD_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VADDS_S16_ST_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qv }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VADDS_S16_ST_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VADDS_S16_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VADDS_S16_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VADDS_S32_LD_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VADDS_S32_LD_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VADDS_S32_ST_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qv }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VADDS_S32_ST_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VADDS_S32_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VADDS_S32_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VADDS_S8_LD_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VADDS_S8_LD_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VADDS_S8_ST_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qv }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VADDS_S8_ST_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VADDS_S8_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VADDS_S8_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSUBS_S16_LD_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSUBS_S16_LD_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSUBS_S16_ST_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qv }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSUBS_S16_ST_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSUBS_S16_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSUBS_S16_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSUBS_S32_LD_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSUBS_S32_LD_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSUBS_S32_ST_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qv }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSUBS_S32_ST_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSUBS_S32_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSUBS_S32_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSUBS_S8_LD_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSUBS_S8_LD_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSUBS_S8_ST_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qv }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSUBS_S8_ST_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSUBS_S8_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSUBS_S8_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMUL_S16_LD_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qz }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMUL_S16_LD_INCP_stateArgs[] = {
+  { { STATE_SAR }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMUL_S16_ST_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qv }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qz }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMUL_S16_ST_INCP_stateArgs[] = {
+  { { STATE_SAR }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMUL_S16_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qz }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMUL_S16_stateArgs[] = {
+  { { STATE_SAR }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMUL_S8_LD_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qz }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMUL_S8_LD_INCP_stateArgs[] = {
+  { { STATE_SAR }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMUL_S8_ST_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qv }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qz }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMUL_S8_ST_INCP_stateArgs[] = {
+  { { STATE_SAR }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMUL_S8_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qz }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMUL_S8_stateArgs[] = {
+  { { STATE_SAR }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMUL_U16_LD_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qz }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMUL_U16_LD_INCP_stateArgs[] = {
+  { { STATE_SAR }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMUL_U16_ST_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qv }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qz }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMUL_U16_ST_INCP_stateArgs[] = {
+  { { STATE_SAR }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMUL_U16_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qz }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMUL_U16_stateArgs[] = {
+  { { STATE_SAR }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMUL_U8_LD_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qz }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMUL_U8_LD_INCP_stateArgs[] = {
+  { { STATE_SAR }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMUL_U8_ST_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qv }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qz }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMUL_U8_ST_INCP_stateArgs[] = {
+  { { STATE_SAR }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMUL_U8_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qz }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMUL_U8_stateArgs[] = {
+  { { STATE_SAR }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_CMUL_S16_LD_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qz }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_sel4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_CMUL_S16_LD_INCP_stateArgs[] = {
+  { { STATE_SAR }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_CMUL_S16_ST_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qv }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qz }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_sel4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_CMUL_S16_ST_INCP_stateArgs[] = {
+  { { STATE_SAR }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_CMUL_S16_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qz }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_sel4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_CMUL_S16_stateArgs[] = {
+  { { STATE_SAR }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S16_ACCX_LD_IP_QUP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_imm16 }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S16_ACCX_LD_IP_QUP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_ACCX }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S16_ACCX_LD_IP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_imm16 }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S16_ACCX_LD_IP_stateArgs[] = {
+  { { STATE_ACCX }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S16_ACCX_LD_XP_QUP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_ad }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S16_ACCX_LD_XP_QUP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_ACCX }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S16_ACCX_LD_XP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_ad }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S16_ACCX_LD_XP_stateArgs[] = {
+  { { STATE_ACCX }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S16_ACCX_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S16_ACCX_stateArgs[] = {
+  { { STATE_ACCX }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S8_ACCX_LD_IP_QUP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_imm16 }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S8_ACCX_LD_IP_QUP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_ACCX }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S8_ACCX_LD_IP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_imm16 }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S8_ACCX_LD_IP_stateArgs[] = {
+  { { STATE_ACCX }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S8_ACCX_LD_XP_QUP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_ad }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S8_ACCX_LD_XP_QUP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_ACCX }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S8_ACCX_LD_XP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_ad }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S8_ACCX_LD_XP_stateArgs[] = {
+  { { STATE_ACCX }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S8_ACCX_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S8_ACCX_stateArgs[] = {
+  { { STATE_ACCX }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U16_ACCX_LD_IP_QUP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_imm16 }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U16_ACCX_LD_IP_QUP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_ACCX }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U16_ACCX_LD_IP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_imm16 }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U16_ACCX_LD_IP_stateArgs[] = {
+  { { STATE_ACCX }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U16_ACCX_LD_XP_QUP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_ad }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U16_ACCX_LD_XP_QUP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_ACCX }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U16_ACCX_LD_XP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_ad }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U16_ACCX_LD_XP_stateArgs[] = {
+  { { STATE_ACCX }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U16_ACCX_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U16_ACCX_stateArgs[] = {
+  { { STATE_ACCX }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U8_ACCX_LD_IP_QUP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_imm16 }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U8_ACCX_LD_IP_QUP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_ACCX }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U8_ACCX_LD_IP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_imm16 }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U8_ACCX_LD_IP_stateArgs[] = {
+  { { STATE_ACCX }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U8_ACCX_LD_XP_QUP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_ad }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U8_ACCX_LD_XP_QUP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_ACCX }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U8_ACCX_LD_XP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_ad }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U8_ACCX_LD_XP_stateArgs[] = {
+  { { STATE_ACCX }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U8_ACCX_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U8_ACCX_stateArgs[] = {
+  { { STATE_ACCX }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S16_QACC_LDBC_INCP_QUP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S16_QACC_LDBC_INCP_QUP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S16_QACC_LDBC_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S16_QACC_LDBC_INCP_stateArgs[] = {
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S16_QACC_LD_IP_QUP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_imm16 }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S16_QACC_LD_IP_QUP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S16_QACC_LD_IP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_imm16 }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S16_QACC_LD_IP_stateArgs[] = {
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S16_QACC_LD_XP_QUP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_ad }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S16_QACC_LD_XP_QUP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S16_QACC_LD_XP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_ad }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S16_QACC_LD_XP_stateArgs[] = {
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S16_QACC_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S16_QACC_stateArgs[] = {
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S8_QACC_LDBC_INCP_QUP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S8_QACC_LDBC_INCP_QUP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S8_QACC_LDBC_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S8_QACC_LDBC_INCP_stateArgs[] = {
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S8_QACC_LD_IP_QUP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_imm16 }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S8_QACC_LD_IP_QUP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S8_QACC_LD_IP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_imm16 }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S8_QACC_LD_IP_stateArgs[] = {
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S8_QACC_LD_XP_QUP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_ad }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S8_QACC_LD_XP_QUP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S8_QACC_LD_XP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_ad }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S8_QACC_LD_XP_stateArgs[] = {
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S8_QACC_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_S8_QACC_stateArgs[] = {
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U16_QACC_LDBC_INCP_QUP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U16_QACC_LDBC_INCP_QUP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U16_QACC_LDBC_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U16_QACC_LDBC_INCP_stateArgs[] = {
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U16_QACC_LD_IP_QUP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_imm16 }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U16_QACC_LD_IP_QUP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U16_QACC_LD_IP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_imm16 }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U16_QACC_LD_IP_stateArgs[] = {
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U16_QACC_LD_XP_QUP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_ad }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U16_QACC_LD_XP_QUP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U16_QACC_LD_XP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_ad }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U16_QACC_LD_XP_stateArgs[] = {
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U16_QACC_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U16_QACC_stateArgs[] = {
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U8_QACC_LDBC_INCP_QUP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U8_QACC_LDBC_INCP_QUP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U8_QACC_LDBC_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U8_QACC_LDBC_INCP_stateArgs[] = {
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U8_QACC_LD_IP_QUP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_imm16 }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U8_QACC_LD_IP_QUP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U8_QACC_LD_IP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_imm16 }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U8_QACC_LD_IP_stateArgs[] = {
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U8_QACC_LD_XP_QUP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_ad }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U8_QACC_LD_XP_QUP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U8_QACC_LD_XP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_ad }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U8_QACC_LD_XP_stateArgs[] = {
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U8_QACC_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMULAS_U8_QACC_stateArgs[] = {
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSMULAS_S16_QACC_LD_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_sel8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSMULAS_S16_QACC_LD_INCP_stateArgs[] = {
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSMULAS_S16_QACC_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_sel8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSMULAS_S16_QACC_stateArgs[] = {
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSMULAS_S8_QACC_LD_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_sel16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSMULAS_S8_QACC_LD_INCP_stateArgs[] = {
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSMULAS_S8_QACC_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_sel16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSMULAS_S8_QACC_stateArgs[] = {
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_SRCMB_S16_QACC_args[] = {
+  { { OPERAND_opnd_semantic_SRCMB_QACC_qu }, 'o' },
+  { { OPERAND_opnd_semantic_SRCMB_QACC_as }, 'i' },
+  { { OPERAND_opnd_semantic_SRCMB_QACC_sel2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_SRCMB_S16_QACC_stateArgs[] = {
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_SRCMB_S8_QACC_args[] = {
+  { { OPERAND_opnd_semantic_SRCMB_QACC_qu }, 'o' },
+  { { OPERAND_opnd_semantic_SRCMB_QACC_as }, 'i' },
+  { { OPERAND_opnd_semantic_SRCMB_QACC_sel2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_SRCMB_S8_QACC_stateArgs[] = {
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_SRS_ACCX_args[] = {
+  { { OPERAND_opnd_EE_SRS_ACCX_au }, 'o' },
+  { { OPERAND_opnd_EE_SRS_ACCX_as }, 'i' },
+  { { OPERAND_opnd_EE_SRS_ACCX_sel2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_SRS_ACCX_stateArgs[] = {
+  { { STATE_ACCX }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VRELU_S16_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_ax }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_ay }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VRELU_S16_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VRELU_S8_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qs }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_ax }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_ay }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VRELU_S8_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VPRELU_S16_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qz }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_ay }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VPRELU_S16_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VPRELU_S8_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qz }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_ay }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VPRELU_S8_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMAX_S16_LD_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMAX_S16_LD_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMAX_S16_ST_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qv }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMAX_S16_ST_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMAX_S16_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMAX_S16_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMAX_S32_LD_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMAX_S32_LD_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMAX_S32_ST_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qv }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMAX_S32_ST_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMAX_S32_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMAX_S32_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMAX_S8_LD_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMAX_S8_LD_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMAX_S8_ST_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qv }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMAX_S8_ST_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMAX_S8_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMAX_S8_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMIN_S16_LD_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMIN_S16_LD_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMIN_S16_ST_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qv }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMIN_S16_ST_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMIN_S16_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMIN_S16_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMIN_S32_LD_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMIN_S32_LD_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMIN_S32_ST_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qv }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMIN_S32_ST_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMIN_S32_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMIN_S32_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMIN_S8_LD_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qu }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMIN_S8_LD_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMIN_S8_ST_INCP_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qv }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_as }, 'm' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMIN_S8_ST_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMIN_S8_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VMIN_S8_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VCMP_EQ_S16_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VCMP_EQ_S16_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VCMP_EQ_S32_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VCMP_EQ_S32_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VCMP_EQ_S8_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VCMP_EQ_S8_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VCMP_GT_S16_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VCMP_GT_S16_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VCMP_GT_S32_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VCMP_GT_S32_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VCMP_GT_S8_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VCMP_GT_S8_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VCMP_LT_S16_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VCMP_LT_S16_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VCMP_LT_S32_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VCMP_LT_S32_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VCMP_LT_S8_args[] = {
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qa }, 'o' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qx }, 'i' },
+  { { OPERAND_opnd_semantic_CAL_DOUBLE_Q_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VCMP_LT_S8_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_ANDQ_args[] = {
+  { { OPERAND_opnd_semantic_VLOGIC_qa }, 'o' },
+  { { OPERAND_opnd_semantic_VLOGIC_qx }, 'i' },
+  { { OPERAND_opnd_semantic_VLOGIC_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_ANDQ_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_NOTQ_args[] = {
+  { { OPERAND_opnd_semantic_VLOGIC_qa }, 'o' },
+  { { OPERAND_opnd_semantic_VLOGIC_qx }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_NOTQ_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_ORQ_args[] = {
+  { { OPERAND_opnd_semantic_VLOGIC_qa }, 'o' },
+  { { OPERAND_opnd_semantic_VLOGIC_qx }, 'i' },
+  { { OPERAND_opnd_semantic_VLOGIC_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_ORQ_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_XORQ_args[] = {
+  { { OPERAND_opnd_semantic_VLOGIC_qa }, 'o' },
+  { { OPERAND_opnd_semantic_VLOGIC_qx }, 'i' },
+  { { OPERAND_opnd_semantic_VLOGIC_qy }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_XORQ_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_SLCI_2Q_args[] = {
+  { { OPERAND_opnd_semantic_SHFQ_qs1 }, 'm' },
+  { { OPERAND_opnd_semantic_SHFQ_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_SHFQ_sar16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_SLCI_2Q_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_SLCXXP_2Q_args[] = {
+  { { OPERAND_opnd_semantic_SHFQ_qs1 }, 'm' },
+  { { OPERAND_opnd_semantic_SHFQ_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_SHFQ_as }, 'm' },
+  { { OPERAND_opnd_semantic_SHFQ_ad }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_SLCXXP_2Q_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_SRCI_2Q_args[] = {
+  { { OPERAND_opnd_semantic_SHFQ_qs1 }, 'm' },
+  { { OPERAND_opnd_semantic_SHFQ_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_SHFQ_sar16 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_SRCI_2Q_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_SRCQ_128_ST_INCP_args[] = {
+  { { OPERAND_opnd_semantic_SHFQ_qs0 }, 'i' },
+  { { OPERAND_opnd_semantic_SHFQ_qs1 }, 'i' },
+  { { OPERAND_opnd_semantic_SHFQ_as }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_EE_SRCQ_128_ST_INCP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_SRC_Q_LD_IP_args[] = {
+  { { OPERAND_opnd_semantic_SHFQ_qu }, 'o' },
+  { { OPERAND_opnd_semantic_SHFQ_as }, 'm' },
+  { { OPERAND_opnd_semantic_SHFQ_imm16 }, 'i' },
+  { { OPERAND_opnd_semantic_SHFQ_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_SHFQ_qs1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_SRC_Q_LD_IP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_SRC_Q_LD_XP_args[] = {
+  { { OPERAND_opnd_semantic_SHFQ_qu }, 'o' },
+  { { OPERAND_opnd_semantic_SHFQ_as }, 'm' },
+  { { OPERAND_opnd_semantic_SHFQ_ad }, 'i' },
+  { { OPERAND_opnd_semantic_SHFQ_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_SHFQ_qs1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_SRC_Q_LD_XP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_SRC_Q_QUP_args[] = {
+  { { OPERAND_opnd_semantic_SHFQ_qa }, 'o' },
+  { { OPERAND_opnd_semantic_SHFQ_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_SHFQ_qs1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_SRC_Q_QUP_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_SRC_Q_args[] = {
+  { { OPERAND_opnd_semantic_SHFQ_qa }, 'o' },
+  { { OPERAND_opnd_semantic_SHFQ_qs0 }, 'i' },
+  { { OPERAND_opnd_semantic_SHFQ_qs1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_SRC_Q_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_SRCXXP_2Q_args[] = {
+  { { OPERAND_opnd_semantic_SHFQ_qs1 }, 'm' },
+  { { OPERAND_opnd_semantic_SHFQ_qs0 }, 'm' },
+  { { OPERAND_opnd_semantic_SHFQ_as }, 'm' },
+  { { OPERAND_opnd_semantic_SHFQ_ad }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_SRCXXP_2Q_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSL_32_args[] = {
+  { { OPERAND_opnd_semantic_SHFQ_qa }, 'o' },
+  { { OPERAND_opnd_semantic_SHFQ_qs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSL_32_stateArgs[] = {
+  { { STATE_SAR }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSR_32_args[] = {
+  { { OPERAND_opnd_semantic_SHFQ_qa }, 'o' },
+  { { OPERAND_opnd_semantic_SHFQ_qs }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_VSR_32_stateArgs[] = {
+  { { STATE_SAR }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_FFT_R2BF_S16_ST_INCP_args[] = {
+  { { OPERAND_opnd_semantic_FFT_RxBF_qa0 }, 'o' },
+  { { OPERAND_opnd_semantic_FFT_RxBF_qx }, 'i' },
+  { { OPERAND_opnd_semantic_FFT_RxBF_qy }, 'i' },
+  { { OPERAND_opnd_semantic_FFT_RxBF_as }, 'm' },
+  { { OPERAND_opnd_semantic_FFT_RxBF_sar4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_FFT_R2BF_S16_ST_INCP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_FFT_R2BF_S16_args[] = {
+  { { OPERAND_opnd_semantic_FFT_RxBF_qa0 }, 'o' },
+  { { OPERAND_opnd_semantic_FFT_RxBF_qa1 }, 'o' },
+  { { OPERAND_opnd_semantic_FFT_RxBF_qx }, 'i' },
+  { { OPERAND_opnd_semantic_FFT_RxBF_qy }, 'i' },
+  { { OPERAND_opnd_semantic_FFT_RxBF_sel2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_FFT_R2BF_S16_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_FFT_CMUL_S16_LD_XP_args[] = {
+  { { OPERAND_opnd_EE_FFT_CMUL_S16_LD_XP_qu }, 'o' },
+  { { OPERAND_opnd_EE_FFT_CMUL_S16_LD_XP_as }, 'm' },
+  { { OPERAND_opnd_EE_FFT_CMUL_S16_LD_XP_ad }, 'i' },
+  { { OPERAND_opnd_EE_FFT_CMUL_S16_LD_XP_qz }, 'm' },
+  { { OPERAND_opnd_EE_FFT_CMUL_S16_LD_XP_qx }, 'i' },
+  { { OPERAND_opnd_EE_FFT_CMUL_S16_LD_XP_qy }, 'i' },
+  { { OPERAND_opnd_EE_FFT_CMUL_S16_LD_XP_sel8 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_FFT_CMUL_S16_LD_XP_stateArgs[] = {
+  { { STATE_SAR }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_FFT_CMUL_S16_ST_XP_args[] = {
+  { { OPERAND_opnd_EE_FFT_CMUL_S16_ST_XP_qx }, 'i' },
+  { { OPERAND_opnd_EE_FFT_CMUL_S16_ST_XP_qy }, 'i' },
+  { { OPERAND_opnd_EE_FFT_CMUL_S16_ST_XP_qv }, 'i' },
+  { { OPERAND_opnd_EE_FFT_CMUL_S16_ST_XP_as }, 'm' },
+  { { OPERAND_opnd_EE_FFT_CMUL_S16_ST_XP_ad }, 'i' },
+  { { OPERAND_opnd_EE_FFT_CMUL_S16_ST_XP_sel8 }, 'i' },
+  { { OPERAND_opnd_EE_FFT_CMUL_S16_ST_XP_upd4 }, 'i' },
+  { { OPERAND_opnd_EE_FFT_CMUL_S16_ST_XP_sar4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_FFT_CMUL_S16_ST_XP_stateArgs[] = {
+  { { STATE_SAR }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_BITREV_args[] = {
+  { { OPERAND_opnd_EE_BITREV_qa }, 'o' },
+  { { OPERAND_opnd_EE_BITREV_ax }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_EE_BITREV_stateArgs[] = {
+  { { STATE_FFT_BIT_WIDTH }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_FFT_AMS_S16_LD_INCP_args[] = {
+  { { OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_qu }, 'o' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_as }, 'm' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_qz }, 'm' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_qz1 }, 'm' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_qx }, 'i' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_qy }, 'i' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_qm }, 'i' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_sel2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_FFT_AMS_S16_LD_INCP_stateArgs[] = {
+  { { STATE_SAR }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_FFT_AMS_S16_LD_INCP_UAUP_args[] = {
+  { { OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_UAUP_qu }, 'o' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_UAUP_as }, 'm' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_UAUP_qz }, 'm' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_UAUP_qz1 }, 'm' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_UAUP_qx }, 'i' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_UAUP_qy }, 'i' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_UAUP_qm }, 'i' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_LD_INCP_UAUP_sel2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_FFT_AMS_S16_LD_INCP_UAUP_stateArgs[] = {
+  { { STATE_SAR }, 'i' },
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_UA_STATE }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_FFT_AMS_S16_LD_R32_DECP_args[] = {
+  { { OPERAND_opnd_EE_FFT_AMS_S16_LD_R32_DECP_qu }, 'o' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_LD_R32_DECP_as }, 'm' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_LD_R32_DECP_qz }, 'm' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_LD_R32_DECP_qz1 }, 'm' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_LD_R32_DECP_qx }, 'i' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_LD_R32_DECP_qy }, 'i' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_LD_R32_DECP_qm }, 'i' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_LD_R32_DECP_sel2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_FFT_AMS_S16_LD_R32_DECP_stateArgs[] = {
+  { { STATE_SAR }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_FFT_AMS_S16_ST_INCP_args[] = {
+  { { OPERAND_opnd_EE_FFT_AMS_S16_ST_INCP_qv }, 'i' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_ST_INCP_qz1 }, 'm' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_ST_INCP_as0 }, 'm' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_ST_INCP_as }, 'm' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_ST_INCP_qx }, 'i' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_ST_INCP_qy }, 'i' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_ST_INCP_qm }, 'i' },
+  { { OPERAND_opnd_EE_FFT_AMS_S16_ST_INCP_sel2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_FFT_AMS_S16_ST_INCP_stateArgs[] = {
+  { { STATE_SAR }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_FFT_VST_R32_DECP_args[] = {
+  { { OPERAND_opnd_EE_FFT_VST_R32_DECP_qv }, 'i' },
+  { { OPERAND_opnd_EE_FFT_VST_R32_DECP_as }, 'm' },
+  { { OPERAND_opnd_EE_FFT_VST_R32_DECP_sar2 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_EE_FFT_VST_R32_DECP_stateArgs[] = {
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_accx_0_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_accx_0_stateArgs[] = {
+  { { STATE_ACCX }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_accx_0_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_accx_0_stateArgs[] = {
+  { { STATE_ACCX }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_accx_1_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_accx_1_stateArgs[] = {
+  { { STATE_ACCX }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_accx_1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_accx_1_stateArgs[] = {
+  { { STATE_ACCX }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_qacc_h_0_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_qacc_h_0_stateArgs[] = {
+  { { STATE_QACC_H }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_qacc_h_0_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_qacc_h_0_stateArgs[] = {
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_qacc_h_1_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_qacc_h_1_stateArgs[] = {
+  { { STATE_QACC_H }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_qacc_h_1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_qacc_h_1_stateArgs[] = {
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_qacc_h_2_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_qacc_h_2_stateArgs[] = {
+  { { STATE_QACC_H }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_qacc_h_2_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_qacc_h_2_stateArgs[] = {
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_qacc_h_3_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_qacc_h_3_stateArgs[] = {
+  { { STATE_QACC_H }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_qacc_h_3_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_qacc_h_3_stateArgs[] = {
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_qacc_h_4_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_qacc_h_4_stateArgs[] = {
+  { { STATE_QACC_H }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_qacc_h_4_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_qacc_h_4_stateArgs[] = {
+  { { STATE_QACC_H }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_qacc_l_0_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_qacc_l_0_stateArgs[] = {
+  { { STATE_QACC_L }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_qacc_l_0_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_qacc_l_0_stateArgs[] = {
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_qacc_l_1_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_qacc_l_1_stateArgs[] = {
+  { { STATE_QACC_L }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_qacc_l_1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_qacc_l_1_stateArgs[] = {
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_qacc_l_2_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_qacc_l_2_stateArgs[] = {
+  { { STATE_QACC_L }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_qacc_l_2_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_qacc_l_2_stateArgs[] = {
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_qacc_l_3_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_qacc_l_3_stateArgs[] = {
+  { { STATE_QACC_L }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_qacc_l_3_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_qacc_l_3_stateArgs[] = {
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_qacc_l_4_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_qacc_l_4_stateArgs[] = {
+  { { STATE_QACC_L }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_qacc_l_4_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_qacc_l_4_stateArgs[] = {
+  { { STATE_QACC_L }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_gpio_out_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_gpio_out_stateArgs[] = {
+  { { STATE_GPIO_OUT }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_gpio_out_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_gpio_out_stateArgs[] = {
+  { { STATE_GPIO_OUT }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_sar_byte_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_sar_byte_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_sar_byte_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_sar_byte_stateArgs[] = {
+  { { STATE_SAR_BYTE }, 'o' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_fft_bit_width_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_fft_bit_width_stateArgs[] = {
+  { { STATE_FFT_BIT_WIDTH }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_fft_bit_width_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_fft_bit_width_stateArgs[] = {
+  { { STATE_FFT_BIT_WIDTH }, 'o' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_ua_state_0_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_ua_state_0_stateArgs[] = {
+  { { STATE_UA_STATE }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ua_state_0_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ua_state_0_stateArgs[] = {
+  { { STATE_UA_STATE }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_ua_state_1_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_ua_state_1_stateArgs[] = {
+  { { STATE_UA_STATE }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ua_state_1_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ua_state_1_stateArgs[] = {
+  { { STATE_UA_STATE }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_ua_state_2_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_ua_state_2_stateArgs[] = {
+  { { STATE_UA_STATE }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ua_state_2_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ua_state_2_stateArgs[] = {
+  { { STATE_UA_STATE }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_ua_state_3_args[] = {
+  { { OPERAND_arr }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_ua_state_3_stateArgs[] = {
+  { { STATE_UA_STATE }, 'i' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ua_state_3_args[] = {
+  { { OPERAND_art }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_ua_state_3_stateArgs[] = {
+  { { STATE_UA_STATE }, 'm' },
+  { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_iclass_internal iclasses[] = {
+  { 3, Iclass_LSI_args,
+    1, Iclass_LSI_stateArgs, 0, 0 },
+  { 3, Iclass_LSIP_args,
+    1, Iclass_LSIP_stateArgs, 0, 0 },
+  { 3, Iclass_LSX_args,
+    1, Iclass_LSX_stateArgs, 0, 0 },
+  { 3, Iclass_LSXP_args,
+    1, Iclass_LSXP_stateArgs, 0, 0 },
+  { 3, Iclass_SSI_args,
+    1, Iclass_SSI_stateArgs, 0, 0 },
+  { 3, Iclass_SSIP_args,
+    1, Iclass_SSIP_stateArgs, 0, 0 },
+  { 3, Iclass_SSX_args,
+    1, Iclass_SSX_stateArgs, 0, 0 },
+  { 3, Iclass_SSXP_args,
+    1, Iclass_SSXP_stateArgs, 0, 0 },
+  { 2, Iclass_ABS_S_args,
+    1, Iclass_ABS_S_stateArgs, 0, 0 },
+  { 2, Iclass_NEG_S_args,
+    1, Iclass_NEG_S_stateArgs, 0, 0 },
+  { 2, Iclass_MOV_S_args,
+    1, Iclass_MOV_S_stateArgs, 0, 0 },
+  { 3, Iclass_MOVEQZ_S_args,
+    1, Iclass_MOVEQZ_S_stateArgs, 0, 0 },
+  { 3, Iclass_MOVNEZ_S_args,
+    1, Iclass_MOVNEZ_S_stateArgs, 0, 0 },
+  { 3, Iclass_MOVLTZ_S_args,
+    1, Iclass_MOVLTZ_S_stateArgs, 0, 0 },
+  { 3, Iclass_MOVGEZ_S_args,
+    1, Iclass_MOVGEZ_S_stateArgs, 0, 0 },
+  { 3, Iclass_MOVF_S_args,
+    1, Iclass_MOVF_S_stateArgs, 0, 0 },
+  { 3, Iclass_MOVT_S_args,
+    1, Iclass_MOVT_S_stateArgs, 0, 0 },
+  { 2, Iclass_WFR_args,
+    1, Iclass_WFR_stateArgs, 0, 0 },
+  { 2, Iclass_RFR_args,
+    1, Iclass_RFR_stateArgs, 0, 0 },
+  { 3, Iclass_ROUND_S_args,
+    3, Iclass_ROUND_S_stateArgs, 0, 0 },
+  { 3, Iclass_CEIL_S_args,
+    3, Iclass_CEIL_S_stateArgs, 0, 0 },
+  { 3, Iclass_FLOOR_S_args,
+    3, Iclass_FLOOR_S_stateArgs, 0, 0 },
+  { 3, Iclass_TRUNC_S_args,
+    3, Iclass_TRUNC_S_stateArgs, 0, 0 },
+  { 3, Iclass_UTRUNC_S_args,
+    3, Iclass_UTRUNC_S_stateArgs, 0, 0 },
+  { 3, Iclass_FLOAT_S_args,
+    3, Iclass_FLOAT_S_stateArgs, 0, 0 },
+  { 3, Iclass_UFLOAT_S_args,
+    3, Iclass_UFLOAT_S_stateArgs, 0, 0 },
+  { 3, Iclass_UN_S_args,
+    2, Iclass_UN_S_stateArgs, 0, 0 },
+  { 3, Iclass_ULT_S_args,
+    2, Iclass_ULT_S_stateArgs, 0, 0 },
+  { 3, Iclass_ULE_S_args,
+    2, Iclass_ULE_S_stateArgs, 0, 0 },
+  { 3, Iclass_UEQ_S_args,
+    2, Iclass_UEQ_S_stateArgs, 0, 0 },
+  { 3, Iclass_OLT_S_args,
+    2, Iclass_OLT_S_stateArgs, 0, 0 },
+  { 3, Iclass_OLE_S_args,
+    2, Iclass_OLE_S_stateArgs, 0, 0 },
+  { 3, Iclass_OEQ_S_args,
+    2, Iclass_OEQ_S_stateArgs, 0, 0 },
+  { 3, Iclass_ADD_S_args,
+    6, Iclass_ADD_S_stateArgs, 0, 0 },
+  { 3, Iclass_SUB_S_args,
+    6, Iclass_SUB_S_stateArgs, 0, 0 },
+  { 3, Iclass_MUL_S_args,
+    6, Iclass_MUL_S_stateArgs, 0, 0 },
+  { 3, Iclass_MADD_S_args,
+    6, Iclass_MADD_S_stateArgs, 0, 0 },
+  { 3, Iclass_MSUB_S_args,
+    6, Iclass_MSUB_S_stateArgs, 0, 0 },
+  { 2, Iclass_SQRT0_S_args,
+    1, Iclass_SQRT0_S_stateArgs, 0, 0 },
+  { 2, Iclass_DIV0_S_args,
+    1, Iclass_DIV0_S_stateArgs, 0, 0 },
+  { 2, Iclass_RECIP0_S_args,
+    3, Iclass_RECIP0_S_stateArgs, 0, 0 },
+  { 2, Iclass_RSQRT0_S_args,
+    3, Iclass_RSQRT0_S_stateArgs, 0, 0 },
+  { 3, Iclass_MADDN_S_args,
+    1, Iclass_MADDN_S_stateArgs, 0, 0 },
+  { 3, Iclass_DIVN_S_args,
+    5, Iclass_DIVN_S_stateArgs, 0, 0 },
+  { 2, Iclass_CONST_S_args,
+    1, Iclass_CONST_S_stateArgs, 0, 0 },
+  { 2, Iclass_NEXP01_S_args,
+    1, Iclass_NEXP01_S_stateArgs, 0, 0 },
+  { 2, Iclass_ADDEXP_S_args,
+    1, Iclass_ADDEXP_S_stateArgs, 0, 0 },
+  { 2, Iclass_ADDEXPM_S_args,
+    1, Iclass_ADDEXPM_S_stateArgs, 0, 0 },
+  { 2, Iclass_MKDADJ_S_args,
+    3, Iclass_MKDADJ_S_stateArgs, 0, 0 },
+  { 2, Iclass_MKSADJ_S_args,
+    2, Iclass_MKSADJ_S_stateArgs, 0, 0 },
+  { 0, 0 /* xt_iclass_excw */,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_rfe */,
+    2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
+  { 0, 0 /* xt_iclass_rfde */,
+    1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
+  { 0, 0 /* xt_iclass_syscall */,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_call12_args,
+    1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_call8_args,
+    1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_call4_args,
+    1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_callx12_args,
+    1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_callx8_args,
+    1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_callx4_args,
+    1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_entry_args,
+    5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_movsp_args,
+    2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rotw_args,
+    1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_retw_args,
+    5, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
+  { 0, 0 /* xt_iclass_rfwou */,
+    5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_l32e_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_s32e_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_windowbase_args,
+    1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_windowbase_args,
+    1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_windowbase_args,
+    1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_windowstart_args,
+    1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_windowstart_args,
+    1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_windowstart_args,
+    1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_add_n_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_addi_n_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_bz6_args,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_ill_n */,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_loadi4_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_mov_n_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_movi_n_args,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_nopn */,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_retn_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_storei4_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_rur_threadptr_args,
+    1, Iclass_rur_threadptr_stateArgs, 0, 0 },
+  { 1, Iclass_wur_threadptr_args,
+    1, Iclass_wur_threadptr_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_addi_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_addmi_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_addsub_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_bit_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_bsi8_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_bsi8b_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_bsi8u_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_bst8_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_bsz12_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_call0_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_callx0_args,
+    0, 0, 0, 0 },
+  { 4, Iclass_xt_iclass_exti_args,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_ill */,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_jump_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_jumpx_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_l16ui_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_l16si_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_l32i_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_l32r_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_l8i_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_loop_args,
+    3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_loopz_args,
+    3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_movi_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_movz_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_neg_args,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_nop */,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_return_args,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_simcall */,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_s16i_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_s32i_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_s32nb_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_s8i_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_sar_args,
+    1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_sari_args,
+    1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_shifts_args,
+    1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_shiftst_args,
+    1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_shiftt_args,
+    1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_slli_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_srai_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_srli_args,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_memw */,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_extw */,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_isync */,
+    0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_sync */,
+    1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_rsil_args,
+    6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_lend_args,
+    1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_lend_args,
+    1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_lend_args,
+    1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_lcount_args,
+    1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_lcount_args,
+    2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_lcount_args,
+    2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_lbeg_args,
+    1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_lbeg_args,
+    1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_lbeg_args,
+    1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_sar_args,
+    1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_sar_args,
+    2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_sar_args,
+    1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_memctl_args,
+    1, Iclass_xt_iclass_rsr_memctl_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_memctl_args,
+    1, Iclass_xt_iclass_wsr_memctl_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_memctl_args,
+    1, Iclass_xt_iclass_xsr_memctl_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_litbase_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_litbase_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_litbase_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_configid0_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_configid0_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_configid1_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ps_args,
+    6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ps_args,
+    6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ps_args,
+    6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_epc1_args,
+    1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_epc1_args,
+    1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_epc1_args,
+    1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_excsave1_args,
+    1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_excsave1_args,
+    1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_excsave1_args,
+    1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_epc2_args,
+    1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_epc2_args,
+    1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_epc2_args,
+    1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_excsave2_args,
+    1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_excsave2_args,
+    1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_excsave2_args,
+    1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_epc3_args,
+    1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_epc3_args,
+    1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_epc3_args,
+    1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_excsave3_args,
+    1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_excsave3_args,
+    1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_excsave3_args,
+    1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_epc4_args,
+    1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_epc4_args,
+    1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_epc4_args,
+    1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_excsave4_args,
+    1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_excsave4_args,
+    1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_excsave4_args,
+    1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_epc5_args,
+    1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_epc5_args,
+    1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_epc5_args,
+    1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_excsave5_args,
+    1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_excsave5_args,
+    1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_excsave5_args,
+    1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_epc6_args,
+    1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_epc6_args,
+    1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_epc6_args,
+    1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_excsave6_args,
+    1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_excsave6_args,
+    1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_excsave6_args,
+    1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_epc7_args,
+    1, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_epc7_args,
+    1, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_epc7_args,
+    1, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_excsave7_args,
+    1, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_excsave7_args,
+    1, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_excsave7_args,
+    1, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_eps2_args,
+    1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_eps2_args,
+    1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_eps2_args,
+    1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_eps3_args,
+    1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_eps3_args,
+    1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_eps3_args,
+    1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_eps4_args,
+    1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_eps4_args,
+    1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_eps4_args,
+    1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_eps5_args,
+    1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_eps5_args,
+    1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_eps5_args,
+    1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_eps6_args,
+    1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_eps6_args,
+    1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_eps6_args,
+    1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_eps7_args,
+    1, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_eps7_args,
+    1, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_eps7_args,
+    1, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_excvaddr_args,
+    1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_excvaddr_args,
+    1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_excvaddr_args,
+    1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_depc_args,
+    1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_depc_args,
+    1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_depc_args,
+    1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_exccause_args,
+    2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_exccause_args,
+    1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_exccause_args,
+    1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_misc0_args,
+    1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_misc0_args,
+    1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_misc0_args,
+    1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_misc1_args,
+    1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_misc1_args,
+    1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_misc1_args,
+    1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_misc2_args,
+    1, Iclass_xt_iclass_rsr_misc2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_misc2_args,
+    1, Iclass_xt_iclass_wsr_misc2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_misc2_args,
+    1, Iclass_xt_iclass_xsr_misc2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_misc3_args,
+    1, Iclass_xt_iclass_rsr_misc3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_misc3_args,
+    1, Iclass_xt_iclass_wsr_misc3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_misc3_args,
+    1, Iclass_xt_iclass_xsr_misc3_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_prid_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_vecbase_args,
+    1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_vecbase_args,
+    1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_vecbase_args,
+    1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_salt_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_mul16_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_mul32_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_mul32h_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_mac16_aa_args,
+    1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_mac16_ad_args,
+    1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_mac16_da_args,
+    1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_mac16_dd_args,
+    1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_mac16a_aa_args,
+    1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_mac16a_ad_args,
+    1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_mac16a_da_args,
+    1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_mac16a_dd_args,
+    1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
+  { 4, Iclass_xt_iclass_mac16al_da_args,
+    1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
+  { 4, Iclass_xt_iclass_mac16al_dd_args,
+    1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_mac16_l_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_rsr_m0_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_wsr_m0_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_xsr_m0_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_rsr_m1_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_wsr_m1_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_xsr_m1_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_rsr_m2_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_wsr_m2_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_xsr_m2_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_rsr_m3_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_wsr_m3_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_xsr_m3_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_acclo_args,
+    1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_acclo_args,
+    1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_acclo_args,
+    1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_acchi_args,
+    1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_acchi_args,
+    1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_acchi_args,
+    1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rfi_args,
+    20, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wait_args,
+    1, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_interrupt_args,
+    1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_intset_args,
+    2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_intclear_args,
+    2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_intenable_args,
+    1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_intenable_args,
+    1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_intenable_args,
+    1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_break_args,
+    2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_break_n_args,
+    2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
+    1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
+    2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
+    2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
+    1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
+    2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
+    2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
+    1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
+    2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
+    2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
+    1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
+    2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
+    2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
+    1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
+    1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
+    1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
+    1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
+    1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
+    1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
+    1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
+    1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
+    1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_debugcause_args,
+    2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_debugcause_args,
+    2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_debugcause_args,
+    2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_icount_args,
+    1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_icount_args,
+    2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_icount_args,
+    2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_icountlevel_args,
+    1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_icountlevel_args,
+    1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_icountlevel_args,
+    1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ddr_args,
+    1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ddr_args,
+    2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ddr_args,
+    2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_lddr32_p_args,
+    3, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_sddr32_p_args,
+    2, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rfdo_args,
+    9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
+  { 0, 0 /* xt_iclass_rfdd */,
+    1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_mmid_args,
+    1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_bbool1_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_bbool4_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_bbool8_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_bbranch_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_bmove_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_RSR_BR_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_WSR_BR_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_XSR_BR_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ccount_args,
+    1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ccount_args,
+    2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ccount_args,
+    2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ccompare0_args,
+    1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ccompare0_args,
+    2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ccompare0_args,
+    2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ccompare1_args,
+    1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ccompare1_args,
+    2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ccompare1_args,
+    2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_ccompare2_args,
+    1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_ccompare2_args,
+    2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_ccompare2_args,
+    2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_idtlb_args,
+    1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
+  { 2, Iclass_xt_iclass_rdtlb_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_wdtlb_args,
+    1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_iitlb_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_ritlb_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_witlb_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_cpenable_args,
+    1, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_cpenable_args,
+    1, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_cpenable_args,
+    1, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_clamp_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_minmax_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_nsa_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_sx_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_l32ai_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_s32ri_args,
+    0, 0, 0, 0 },
+  { 3, Iclass_xt_iclass_s32c1i_args,
+    3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_scompare1_args,
+    1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_scompare1_args,
+    1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_scompare1_args,
+    1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_atomctl_args,
+    1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_atomctl_args,
+    2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_atomctl_args,
+    2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
+  { 3, Iclass_xt_iclass_div_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_eraccess_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_eraccess_args,
+    0, 0, 0, 0 },
+  { 1, Iclass_xt_iclass_xsr_eraccess_args,
+    0, 0, 0, 0 },
+  { 2, Iclass_xt_iclass_rer_args,
+    1, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs },
+  { 2, Iclass_xt_iclass_wer_args,
+    1, Iclass_xt_iclass_wer_stateArgs, 2, Iclass_xt_iclass_wer_intfArgs },
+  { 1, Iclass_rur_fcr_args,
+    9, Iclass_rur_fcr_stateArgs, 0, 0 },
+  { 1, Iclass_wur_fcr_args,
+    9, Iclass_wur_fcr_stateArgs, 0, 0 },
+  { 1, Iclass_rur_fsr_args,
+    8, Iclass_rur_fsr_stateArgs, 0, 0 },
+  { 1, Iclass_wur_fsr_args,
+    8, Iclass_wur_fsr_stateArgs, 0, 0 },
+  { 3, Iclass_st_QR_args,
+    1, Iclass_st_QR_stateArgs, 0, 0 },
+  { 3, Iclass_ld_QR_args,
+    1, Iclass_ld_QR_stateArgs, 0, 0 },
+  { 2, Iclass_mv_QR_args,
+    1, Iclass_mv_QR_stateArgs, 0, 0 },
+  { 2, Iclass_EE_WR_MASK_GPIO_OUT_args,
+    1, Iclass_EE_WR_MASK_GPIO_OUT_stateArgs, 0, 0 },
+  { 1, Iclass_EE_SET_BIT_GPIO_OUT_args,
+    1, Iclass_EE_SET_BIT_GPIO_OUT_stateArgs, 0, 0 },
+  { 1, Iclass_EE_CLR_BIT_GPIO_OUT_args,
+    1, Iclass_EE_CLR_BIT_GPIO_OUT_stateArgs, 0, 0 },
+  { 1, Iclass_EE_GET_GPIO_IN_args,
+    0, 0, 1, Iclass_EE_GET_GPIO_IN_intfArgs },
+  { 3, Iclass_EE_VLD_128_IP_args,
+    1, Iclass_EE_VLD_128_IP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VLD_128_XP_args,
+    1, Iclass_EE_VLD_128_XP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VLD_H_64_IP_args,
+    1, Iclass_EE_VLD_H_64_IP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VLD_H_64_XP_args,
+    1, Iclass_EE_VLD_H_64_XP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VLD_L_64_IP_args,
+    1, Iclass_EE_VLD_L_64_IP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VLD_L_64_XP_args,
+    1, Iclass_EE_VLD_L_64_XP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VLDBC_16_IP_args,
+    1, Iclass_EE_VLDBC_16_IP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_VLDBC_16_args,
+    1, Iclass_EE_VLDBC_16_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VLDBC_16_XP_args,
+    1, Iclass_EE_VLDBC_16_XP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VLDBC_32_IP_args,
+    1, Iclass_EE_VLDBC_32_IP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_VLDBC_32_args,
+    1, Iclass_EE_VLDBC_32_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VLDBC_32_XP_args,
+    1, Iclass_EE_VLDBC_32_XP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VLDBC_8_IP_args,
+    1, Iclass_EE_VLDBC_8_IP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_VLDBC_8_args,
+    1, Iclass_EE_VLDBC_8_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VLDBC_8_XP_args,
+    1, Iclass_EE_VLDBC_8_XP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VLDHBC_16_INCP_args,
+    1, Iclass_EE_VLDHBC_16_INCP_stateArgs, 0, 0 },
+  { 6, Iclass_EE_LDF_128_IP_args,
+    1, Iclass_EE_LDF_128_IP_stateArgs, 0, 0 },
+  { 6, Iclass_EE_LDF_128_XP_args,
+    1, Iclass_EE_LDF_128_XP_stateArgs, 0, 0 },
+  { 4, Iclass_EE_LDF_64_IP_args,
+    1, Iclass_EE_LDF_64_IP_stateArgs, 0, 0 },
+  { 4, Iclass_EE_LDF_64_XP_args,
+    1, Iclass_EE_LDF_64_XP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_LD_128_USAR_IP_args,
+    2, Iclass_EE_LD_128_USAR_IP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_LD_128_USAR_XP_args,
+    2, Iclass_EE_LD_128_USAR_XP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_LDQA_S16_128_IP_args,
+    3, Iclass_EE_LDQA_S16_128_IP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_LDQA_S16_128_XP_args,
+    3, Iclass_EE_LDQA_S16_128_XP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_LDQA_S8_128_IP_args,
+    3, Iclass_EE_LDQA_S8_128_IP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_LDQA_S8_128_XP_args,
+    3, Iclass_EE_LDQA_S8_128_XP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_LDQA_U16_128_IP_args,
+    3, Iclass_EE_LDQA_U16_128_IP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_LDQA_U16_128_XP_args,
+    3, Iclass_EE_LDQA_U16_128_XP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_LDQA_U8_128_IP_args,
+    3, Iclass_EE_LDQA_U8_128_IP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_LDQA_U8_128_XP_args,
+    3, Iclass_EE_LDQA_U8_128_XP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_LD_QACC_H_H_32_IP_args,
+    2, Iclass_EE_LD_QACC_H_H_32_IP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_LD_QACC_H_L_128_IP_args,
+    2, Iclass_EE_LD_QACC_H_L_128_IP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_LD_QACC_L_H_32_IP_args,
+    2, Iclass_EE_LD_QACC_L_H_32_IP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_LD_QACC_L_L_128_IP_args,
+    2, Iclass_EE_LD_QACC_L_L_128_IP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_LD_ACCX_IP_args,
+    2, Iclass_EE_LD_ACCX_IP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_LDXQ_32_args,
+    1, Iclass_EE_LDXQ_32_stateArgs, 0, 0 },
+  { 2, Iclass_EE_LD_UA_STATE_IP_args,
+    2, Iclass_EE_LD_UA_STATE_IP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_ST_UA_STATE_IP_args,
+    2, Iclass_EE_ST_UA_STATE_IP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VST_128_IP_args,
+    1, Iclass_EE_VST_128_IP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VST_128_XP_args,
+    1, Iclass_EE_VST_128_XP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VST_H_64_IP_args,
+    1, Iclass_EE_VST_H_64_IP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VST_H_64_XP_args,
+    1, Iclass_EE_VST_H_64_XP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VST_L_64_IP_args,
+    1, Iclass_EE_VST_L_64_IP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VST_L_64_XP_args,
+    1, Iclass_EE_VST_L_64_XP_stateArgs, 0, 0 },
+  { 6, Iclass_EE_STF_128_IP_args,
+    1, Iclass_EE_STF_128_IP_stateArgs, 0, 0 },
+  { 6, Iclass_EE_STF_128_XP_args,
+    1, Iclass_EE_STF_128_XP_stateArgs, 0, 0 },
+  { 4, Iclass_EE_STF_64_IP_args,
+    1, Iclass_EE_STF_64_IP_stateArgs, 0, 0 },
+  { 4, Iclass_EE_STF_64_XP_args,
+    1, Iclass_EE_STF_64_XP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_ST_QACC_H_H_32_IP_args,
+    2, Iclass_EE_ST_QACC_H_H_32_IP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_ST_QACC_H_L_128_IP_args,
+    2, Iclass_EE_ST_QACC_H_L_128_IP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_ST_QACC_L_H_32_IP_args,
+    2, Iclass_EE_ST_QACC_L_H_32_IP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_ST_QACC_L_L_128_IP_args,
+    2, Iclass_EE_ST_QACC_L_L_128_IP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_ST_ACCX_IP_args,
+    2, Iclass_EE_ST_ACCX_IP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_STXQ_32_args,
+    1, Iclass_EE_STXQ_32_stateArgs, 0, 0 },
+  { 3, Iclass_EE_MOVI_32_A_args,
+    1, Iclass_EE_MOVI_32_A_stateArgs, 0, 0 },
+  { 3, Iclass_EE_MOVI_32_Q_args,
+    1, Iclass_EE_MOVI_32_Q_stateArgs, 0, 0 },
+  { 2, Iclass_EE_VZIP_16_args,
+    1, Iclass_EE_VZIP_16_stateArgs, 0, 0 },
+  { 2, Iclass_EE_VZIP_32_args,
+    1, Iclass_EE_VZIP_32_stateArgs, 0, 0 },
+  { 2, Iclass_EE_VZIP_8_args,
+    1, Iclass_EE_VZIP_8_stateArgs, 0, 0 },
+  { 2, Iclass_EE_VUNZIP_16_args,
+    1, Iclass_EE_VUNZIP_16_stateArgs, 0, 0 },
+  { 2, Iclass_EE_VUNZIP_32_args,
+    1, Iclass_EE_VUNZIP_32_stateArgs, 0, 0 },
+  { 2, Iclass_EE_VUNZIP_8_args,
+    1, Iclass_EE_VUNZIP_8_stateArgs, 0, 0 },
+  { 0, 0 /* EE_ZERO_ACCX */,
+    2, Iclass_EE_ZERO_ACCX_stateArgs, 0, 0 },
+  { 0, 0 /* EE_ZERO_QACC */,
+    3, Iclass_EE_ZERO_QACC_stateArgs, 0, 0 },
+  { 1, Iclass_EE_ZERO_Q_args,
+    1, Iclass_EE_ZERO_Q_stateArgs, 0, 0 },
+  { 1, Iclass_EE_MOV_S16_QACC_args,
+    3, Iclass_EE_MOV_S16_QACC_stateArgs, 0, 0 },
+  { 1, Iclass_EE_MOV_S8_QACC_args,
+    3, Iclass_EE_MOV_S8_QACC_stateArgs, 0, 0 },
+  { 1, Iclass_EE_MOV_U16_QACC_args,
+    3, Iclass_EE_MOV_U16_QACC_stateArgs, 0, 0 },
+  { 1, Iclass_EE_MOV_U8_QACC_args,
+    3, Iclass_EE_MOV_U8_QACC_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VADDS_S16_LD_INCP_args,
+    1, Iclass_EE_VADDS_S16_LD_INCP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VADDS_S16_ST_INCP_args,
+    1, Iclass_EE_VADDS_S16_ST_INCP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VADDS_S16_args,
+    1, Iclass_EE_VADDS_S16_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VADDS_S32_LD_INCP_args,
+    1, Iclass_EE_VADDS_S32_LD_INCP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VADDS_S32_ST_INCP_args,
+    1, Iclass_EE_VADDS_S32_ST_INCP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VADDS_S32_args,
+    1, Iclass_EE_VADDS_S32_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VADDS_S8_LD_INCP_args,
+    1, Iclass_EE_VADDS_S8_LD_INCP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VADDS_S8_ST_INCP_args,
+    1, Iclass_EE_VADDS_S8_ST_INCP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VADDS_S8_args,
+    1, Iclass_EE_VADDS_S8_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VSUBS_S16_LD_INCP_args,
+    1, Iclass_EE_VSUBS_S16_LD_INCP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VSUBS_S16_ST_INCP_args,
+    1, Iclass_EE_VSUBS_S16_ST_INCP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VSUBS_S16_args,
+    1, Iclass_EE_VSUBS_S16_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VSUBS_S32_LD_INCP_args,
+    1, Iclass_EE_VSUBS_S32_LD_INCP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VSUBS_S32_ST_INCP_args,
+    1, Iclass_EE_VSUBS_S32_ST_INCP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VSUBS_S32_args,
+    1, Iclass_EE_VSUBS_S32_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VSUBS_S8_LD_INCP_args,
+    1, Iclass_EE_VSUBS_S8_LD_INCP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VSUBS_S8_ST_INCP_args,
+    1, Iclass_EE_VSUBS_S8_ST_INCP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VSUBS_S8_args,
+    1, Iclass_EE_VSUBS_S8_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMUL_S16_LD_INCP_args,
+    2, Iclass_EE_VMUL_S16_LD_INCP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMUL_S16_ST_INCP_args,
+    2, Iclass_EE_VMUL_S16_ST_INCP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VMUL_S16_args,
+    2, Iclass_EE_VMUL_S16_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMUL_S8_LD_INCP_args,
+    2, Iclass_EE_VMUL_S8_LD_INCP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMUL_S8_ST_INCP_args,
+    2, Iclass_EE_VMUL_S8_ST_INCP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VMUL_S8_args,
+    2, Iclass_EE_VMUL_S8_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMUL_U16_LD_INCP_args,
+    2, Iclass_EE_VMUL_U16_LD_INCP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMUL_U16_ST_INCP_args,
+    2, Iclass_EE_VMUL_U16_ST_INCP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VMUL_U16_args,
+    2, Iclass_EE_VMUL_U16_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMUL_U8_LD_INCP_args,
+    2, Iclass_EE_VMUL_U8_LD_INCP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMUL_U8_ST_INCP_args,
+    2, Iclass_EE_VMUL_U8_ST_INCP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VMUL_U8_args,
+    2, Iclass_EE_VMUL_U8_stateArgs, 0, 0 },
+  { 6, Iclass_EE_CMUL_S16_LD_INCP_args,
+    2, Iclass_EE_CMUL_S16_LD_INCP_stateArgs, 0, 0 },
+  { 6, Iclass_EE_CMUL_S16_ST_INCP_args,
+    2, Iclass_EE_CMUL_S16_ST_INCP_stateArgs, 0, 0 },
+  { 4, Iclass_EE_CMUL_S16_args,
+    2, Iclass_EE_CMUL_S16_stateArgs, 0, 0 },
+  { 7, Iclass_EE_VMULAS_S16_ACCX_LD_IP_QUP_args,
+    3, Iclass_EE_VMULAS_S16_ACCX_LD_IP_QUP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMULAS_S16_ACCX_LD_IP_args,
+    2, Iclass_EE_VMULAS_S16_ACCX_LD_IP_stateArgs, 0, 0 },
+  { 7, Iclass_EE_VMULAS_S16_ACCX_LD_XP_QUP_args,
+    3, Iclass_EE_VMULAS_S16_ACCX_LD_XP_QUP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMULAS_S16_ACCX_LD_XP_args,
+    2, Iclass_EE_VMULAS_S16_ACCX_LD_XP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_VMULAS_S16_ACCX_args,
+    2, Iclass_EE_VMULAS_S16_ACCX_stateArgs, 0, 0 },
+  { 7, Iclass_EE_VMULAS_S8_ACCX_LD_IP_QUP_args,
+    3, Iclass_EE_VMULAS_S8_ACCX_LD_IP_QUP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMULAS_S8_ACCX_LD_IP_args,
+    2, Iclass_EE_VMULAS_S8_ACCX_LD_IP_stateArgs, 0, 0 },
+  { 7, Iclass_EE_VMULAS_S8_ACCX_LD_XP_QUP_args,
+    3, Iclass_EE_VMULAS_S8_ACCX_LD_XP_QUP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMULAS_S8_ACCX_LD_XP_args,
+    2, Iclass_EE_VMULAS_S8_ACCX_LD_XP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_VMULAS_S8_ACCX_args,
+    2, Iclass_EE_VMULAS_S8_ACCX_stateArgs, 0, 0 },
+  { 7, Iclass_EE_VMULAS_U16_ACCX_LD_IP_QUP_args,
+    3, Iclass_EE_VMULAS_U16_ACCX_LD_IP_QUP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMULAS_U16_ACCX_LD_IP_args,
+    2, Iclass_EE_VMULAS_U16_ACCX_LD_IP_stateArgs, 0, 0 },
+  { 7, Iclass_EE_VMULAS_U16_ACCX_LD_XP_QUP_args,
+    3, Iclass_EE_VMULAS_U16_ACCX_LD_XP_QUP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMULAS_U16_ACCX_LD_XP_args,
+    2, Iclass_EE_VMULAS_U16_ACCX_LD_XP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_VMULAS_U16_ACCX_args,
+    2, Iclass_EE_VMULAS_U16_ACCX_stateArgs, 0, 0 },
+  { 7, Iclass_EE_VMULAS_U8_ACCX_LD_IP_QUP_args,
+    3, Iclass_EE_VMULAS_U8_ACCX_LD_IP_QUP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMULAS_U8_ACCX_LD_IP_args,
+    2, Iclass_EE_VMULAS_U8_ACCX_LD_IP_stateArgs, 0, 0 },
+  { 7, Iclass_EE_VMULAS_U8_ACCX_LD_XP_QUP_args,
+    3, Iclass_EE_VMULAS_U8_ACCX_LD_XP_QUP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMULAS_U8_ACCX_LD_XP_args,
+    2, Iclass_EE_VMULAS_U8_ACCX_LD_XP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_VMULAS_U8_ACCX_args,
+    2, Iclass_EE_VMULAS_U8_ACCX_stateArgs, 0, 0 },
+  { 6, Iclass_EE_VMULAS_S16_QACC_LDBC_INCP_QUP_args,
+    4, Iclass_EE_VMULAS_S16_QACC_LDBC_INCP_QUP_stateArgs, 0, 0 },
+  { 4, Iclass_EE_VMULAS_S16_QACC_LDBC_INCP_args,
+    3, Iclass_EE_VMULAS_S16_QACC_LDBC_INCP_stateArgs, 0, 0 },
+  { 7, Iclass_EE_VMULAS_S16_QACC_LD_IP_QUP_args,
+    4, Iclass_EE_VMULAS_S16_QACC_LD_IP_QUP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMULAS_S16_QACC_LD_IP_args,
+    3, Iclass_EE_VMULAS_S16_QACC_LD_IP_stateArgs, 0, 0 },
+  { 7, Iclass_EE_VMULAS_S16_QACC_LD_XP_QUP_args,
+    4, Iclass_EE_VMULAS_S16_QACC_LD_XP_QUP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMULAS_S16_QACC_LD_XP_args,
+    3, Iclass_EE_VMULAS_S16_QACC_LD_XP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_VMULAS_S16_QACC_args,
+    3, Iclass_EE_VMULAS_S16_QACC_stateArgs, 0, 0 },
+  { 6, Iclass_EE_VMULAS_S8_QACC_LDBC_INCP_QUP_args,
+    4, Iclass_EE_VMULAS_S8_QACC_LDBC_INCP_QUP_stateArgs, 0, 0 },
+  { 4, Iclass_EE_VMULAS_S8_QACC_LDBC_INCP_args,
+    3, Iclass_EE_VMULAS_S8_QACC_LDBC_INCP_stateArgs, 0, 0 },
+  { 7, Iclass_EE_VMULAS_S8_QACC_LD_IP_QUP_args,
+    4, Iclass_EE_VMULAS_S8_QACC_LD_IP_QUP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMULAS_S8_QACC_LD_IP_args,
+    3, Iclass_EE_VMULAS_S8_QACC_LD_IP_stateArgs, 0, 0 },
+  { 7, Iclass_EE_VMULAS_S8_QACC_LD_XP_QUP_args,
+    4, Iclass_EE_VMULAS_S8_QACC_LD_XP_QUP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMULAS_S8_QACC_LD_XP_args,
+    3, Iclass_EE_VMULAS_S8_QACC_LD_XP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_VMULAS_S8_QACC_args,
+    3, Iclass_EE_VMULAS_S8_QACC_stateArgs, 0, 0 },
+  { 6, Iclass_EE_VMULAS_U16_QACC_LDBC_INCP_QUP_args,
+    4, Iclass_EE_VMULAS_U16_QACC_LDBC_INCP_QUP_stateArgs, 0, 0 },
+  { 4, Iclass_EE_VMULAS_U16_QACC_LDBC_INCP_args,
+    3, Iclass_EE_VMULAS_U16_QACC_LDBC_INCP_stateArgs, 0, 0 },
+  { 7, Iclass_EE_VMULAS_U16_QACC_LD_IP_QUP_args,
+    4, Iclass_EE_VMULAS_U16_QACC_LD_IP_QUP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMULAS_U16_QACC_LD_IP_args,
+    3, Iclass_EE_VMULAS_U16_QACC_LD_IP_stateArgs, 0, 0 },
+  { 7, Iclass_EE_VMULAS_U16_QACC_LD_XP_QUP_args,
+    4, Iclass_EE_VMULAS_U16_QACC_LD_XP_QUP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMULAS_U16_QACC_LD_XP_args,
+    3, Iclass_EE_VMULAS_U16_QACC_LD_XP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_VMULAS_U16_QACC_args,
+    3, Iclass_EE_VMULAS_U16_QACC_stateArgs, 0, 0 },
+  { 6, Iclass_EE_VMULAS_U8_QACC_LDBC_INCP_QUP_args,
+    4, Iclass_EE_VMULAS_U8_QACC_LDBC_INCP_QUP_stateArgs, 0, 0 },
+  { 4, Iclass_EE_VMULAS_U8_QACC_LDBC_INCP_args,
+    3, Iclass_EE_VMULAS_U8_QACC_LDBC_INCP_stateArgs, 0, 0 },
+  { 7, Iclass_EE_VMULAS_U8_QACC_LD_IP_QUP_args,
+    4, Iclass_EE_VMULAS_U8_QACC_LD_IP_QUP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMULAS_U8_QACC_LD_IP_args,
+    3, Iclass_EE_VMULAS_U8_QACC_LD_IP_stateArgs, 0, 0 },
+  { 7, Iclass_EE_VMULAS_U8_QACC_LD_XP_QUP_args,
+    4, Iclass_EE_VMULAS_U8_QACC_LD_XP_QUP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMULAS_U8_QACC_LD_XP_args,
+    3, Iclass_EE_VMULAS_U8_QACC_LD_XP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_VMULAS_U8_QACC_args,
+    3, Iclass_EE_VMULAS_U8_QACC_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VSMULAS_S16_QACC_LD_INCP_args,
+    3, Iclass_EE_VSMULAS_S16_QACC_LD_INCP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VSMULAS_S16_QACC_args,
+    3, Iclass_EE_VSMULAS_S16_QACC_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VSMULAS_S8_QACC_LD_INCP_args,
+    3, Iclass_EE_VSMULAS_S8_QACC_LD_INCP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VSMULAS_S8_QACC_args,
+    3, Iclass_EE_VSMULAS_S8_QACC_stateArgs, 0, 0 },
+  { 3, Iclass_EE_SRCMB_S16_QACC_args,
+    3, Iclass_EE_SRCMB_S16_QACC_stateArgs, 0, 0 },
+  { 3, Iclass_EE_SRCMB_S8_QACC_args,
+    3, Iclass_EE_SRCMB_S8_QACC_stateArgs, 0, 0 },
+  { 3, Iclass_EE_SRS_ACCX_args,
+    2, Iclass_EE_SRS_ACCX_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VRELU_S16_args,
+    1, Iclass_EE_VRELU_S16_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VRELU_S8_args,
+    1, Iclass_EE_VRELU_S8_stateArgs, 0, 0 },
+  { 4, Iclass_EE_VPRELU_S16_args,
+    1, Iclass_EE_VPRELU_S16_stateArgs, 0, 0 },
+  { 4, Iclass_EE_VPRELU_S8_args,
+    1, Iclass_EE_VPRELU_S8_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMAX_S16_LD_INCP_args,
+    1, Iclass_EE_VMAX_S16_LD_INCP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMAX_S16_ST_INCP_args,
+    1, Iclass_EE_VMAX_S16_ST_INCP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VMAX_S16_args,
+    1, Iclass_EE_VMAX_S16_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMAX_S32_LD_INCP_args,
+    1, Iclass_EE_VMAX_S32_LD_INCP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMAX_S32_ST_INCP_args,
+    1, Iclass_EE_VMAX_S32_ST_INCP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VMAX_S32_args,
+    1, Iclass_EE_VMAX_S32_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMAX_S8_LD_INCP_args,
+    1, Iclass_EE_VMAX_S8_LD_INCP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMAX_S8_ST_INCP_args,
+    1, Iclass_EE_VMAX_S8_ST_INCP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VMAX_S8_args,
+    1, Iclass_EE_VMAX_S8_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMIN_S16_LD_INCP_args,
+    1, Iclass_EE_VMIN_S16_LD_INCP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMIN_S16_ST_INCP_args,
+    1, Iclass_EE_VMIN_S16_ST_INCP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VMIN_S16_args,
+    1, Iclass_EE_VMIN_S16_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMIN_S32_LD_INCP_args,
+    1, Iclass_EE_VMIN_S32_LD_INCP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMIN_S32_ST_INCP_args,
+    1, Iclass_EE_VMIN_S32_ST_INCP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VMIN_S32_args,
+    1, Iclass_EE_VMIN_S32_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMIN_S8_LD_INCP_args,
+    1, Iclass_EE_VMIN_S8_LD_INCP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_VMIN_S8_ST_INCP_args,
+    1, Iclass_EE_VMIN_S8_ST_INCP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VMIN_S8_args,
+    1, Iclass_EE_VMIN_S8_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VCMP_EQ_S16_args,
+    1, Iclass_EE_VCMP_EQ_S16_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VCMP_EQ_S32_args,
+    1, Iclass_EE_VCMP_EQ_S32_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VCMP_EQ_S8_args,
+    1, Iclass_EE_VCMP_EQ_S8_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VCMP_GT_S16_args,
+    1, Iclass_EE_VCMP_GT_S16_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VCMP_GT_S32_args,
+    1, Iclass_EE_VCMP_GT_S32_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VCMP_GT_S8_args,
+    1, Iclass_EE_VCMP_GT_S8_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VCMP_LT_S16_args,
+    1, Iclass_EE_VCMP_LT_S16_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VCMP_LT_S32_args,
+    1, Iclass_EE_VCMP_LT_S32_stateArgs, 0, 0 },
+  { 3, Iclass_EE_VCMP_LT_S8_args,
+    1, Iclass_EE_VCMP_LT_S8_stateArgs, 0, 0 },
+  { 3, Iclass_EE_ANDQ_args,
+    1, Iclass_EE_ANDQ_stateArgs, 0, 0 },
+  { 2, Iclass_EE_NOTQ_args,
+    1, Iclass_EE_NOTQ_stateArgs, 0, 0 },
+  { 3, Iclass_EE_ORQ_args,
+    1, Iclass_EE_ORQ_stateArgs, 0, 0 },
+  { 3, Iclass_EE_XORQ_args,
+    1, Iclass_EE_XORQ_stateArgs, 0, 0 },
+  { 3, Iclass_EE_SLCI_2Q_args,
+    1, Iclass_EE_SLCI_2Q_stateArgs, 0, 0 },
+  { 4, Iclass_EE_SLCXXP_2Q_args,
+    1, Iclass_EE_SLCXXP_2Q_stateArgs, 0, 0 },
+  { 3, Iclass_EE_SRCI_2Q_args,
+    1, Iclass_EE_SRCI_2Q_stateArgs, 0, 0 },
+  { 3, Iclass_EE_SRCQ_128_ST_INCP_args,
+    2, Iclass_EE_SRCQ_128_ST_INCP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_SRC_Q_LD_IP_args,
+    2, Iclass_EE_SRC_Q_LD_IP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_SRC_Q_LD_XP_args,
+    2, Iclass_EE_SRC_Q_LD_XP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_SRC_Q_QUP_args,
+    2, Iclass_EE_SRC_Q_QUP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_SRC_Q_args,
+    2, Iclass_EE_SRC_Q_stateArgs, 0, 0 },
+  { 4, Iclass_EE_SRCXXP_2Q_args,
+    1, Iclass_EE_SRCXXP_2Q_stateArgs, 0, 0 },
+  { 2, Iclass_EE_VSL_32_args,
+    2, Iclass_EE_VSL_32_stateArgs, 0, 0 },
+  { 2, Iclass_EE_VSR_32_args,
+    2, Iclass_EE_VSR_32_stateArgs, 0, 0 },
+  { 5, Iclass_EE_FFT_R2BF_S16_ST_INCP_args,
+    1, Iclass_EE_FFT_R2BF_S16_ST_INCP_stateArgs, 0, 0 },
+  { 5, Iclass_EE_FFT_R2BF_S16_args,
+    1, Iclass_EE_FFT_R2BF_S16_stateArgs, 0, 0 },
+  { 7, Iclass_EE_FFT_CMUL_S16_LD_XP_args,
+    2, Iclass_EE_FFT_CMUL_S16_LD_XP_stateArgs, 0, 0 },
+  { 8, Iclass_EE_FFT_CMUL_S16_ST_XP_args,
+    2, Iclass_EE_FFT_CMUL_S16_ST_XP_stateArgs, 0, 0 },
+  { 2, Iclass_EE_BITREV_args,
+    2, Iclass_EE_BITREV_stateArgs, 0, 0 },
+  { 8, Iclass_EE_FFT_AMS_S16_LD_INCP_args,
+    2, Iclass_EE_FFT_AMS_S16_LD_INCP_stateArgs, 0, 0 },
+  { 8, Iclass_EE_FFT_AMS_S16_LD_INCP_UAUP_args,
+    4, Iclass_EE_FFT_AMS_S16_LD_INCP_UAUP_stateArgs, 0, 0 },
+  { 8, Iclass_EE_FFT_AMS_S16_LD_R32_DECP_args,
+    2, Iclass_EE_FFT_AMS_S16_LD_R32_DECP_stateArgs, 0, 0 },
+  { 8, Iclass_EE_FFT_AMS_S16_ST_INCP_args,
+    2, Iclass_EE_FFT_AMS_S16_ST_INCP_stateArgs, 0, 0 },
+  { 3, Iclass_EE_FFT_VST_R32_DECP_args,
+    1, Iclass_EE_FFT_VST_R32_DECP_stateArgs, 0, 0 },
+  { 1, Iclass_rur_accx_0_args,
+    2, Iclass_rur_accx_0_stateArgs, 0, 0 },
+  { 1, Iclass_wur_accx_0_args,
+    2, Iclass_wur_accx_0_stateArgs, 0, 0 },
+  { 1, Iclass_rur_accx_1_args,
+    2, Iclass_rur_accx_1_stateArgs, 0, 0 },
+  { 1, Iclass_wur_accx_1_args,
+    2, Iclass_wur_accx_1_stateArgs, 0, 0 },
+  { 1, Iclass_rur_qacc_h_0_args,
+    2, Iclass_rur_qacc_h_0_stateArgs, 0, 0 },
+  { 1, Iclass_wur_qacc_h_0_args,
+    2, Iclass_wur_qacc_h_0_stateArgs, 0, 0 },
+  { 1, Iclass_rur_qacc_h_1_args,
+    2, Iclass_rur_qacc_h_1_stateArgs, 0, 0 },
+  { 1, Iclass_wur_qacc_h_1_args,
+    2, Iclass_wur_qacc_h_1_stateArgs, 0, 0 },
+  { 1, Iclass_rur_qacc_h_2_args,
+    2, Iclass_rur_qacc_h_2_stateArgs, 0, 0 },
+  { 1, Iclass_wur_qacc_h_2_args,
+    2, Iclass_wur_qacc_h_2_stateArgs, 0, 0 },
+  { 1, Iclass_rur_qacc_h_3_args,
+    2, Iclass_rur_qacc_h_3_stateArgs, 0, 0 },
+  { 1, Iclass_wur_qacc_h_3_args,
+    2, Iclass_wur_qacc_h_3_stateArgs, 0, 0 },
+  { 1, Iclass_rur_qacc_h_4_args,
+    2, Iclass_rur_qacc_h_4_stateArgs, 0, 0 },
+  { 1, Iclass_wur_qacc_h_4_args,
+    2, Iclass_wur_qacc_h_4_stateArgs, 0, 0 },
+  { 1, Iclass_rur_qacc_l_0_args,
+    2, Iclass_rur_qacc_l_0_stateArgs, 0, 0 },
+  { 1, Iclass_wur_qacc_l_0_args,
+    2, Iclass_wur_qacc_l_0_stateArgs, 0, 0 },
+  { 1, Iclass_rur_qacc_l_1_args,
+    2, Iclass_rur_qacc_l_1_stateArgs, 0, 0 },
+  { 1, Iclass_wur_qacc_l_1_args,
+    2, Iclass_wur_qacc_l_1_stateArgs, 0, 0 },
+  { 1, Iclass_rur_qacc_l_2_args,
+    2, Iclass_rur_qacc_l_2_stateArgs, 0, 0 },
+  { 1, Iclass_wur_qacc_l_2_args,
+    2, Iclass_wur_qacc_l_2_stateArgs, 0, 0 },
+  { 1, Iclass_rur_qacc_l_3_args,
+    2, Iclass_rur_qacc_l_3_stateArgs, 0, 0 },
+  { 1, Iclass_wur_qacc_l_3_args,
+    2, Iclass_wur_qacc_l_3_stateArgs, 0, 0 },
+  { 1, Iclass_rur_qacc_l_4_args,
+    2, Iclass_rur_qacc_l_4_stateArgs, 0, 0 },
+  { 1, Iclass_wur_qacc_l_4_args,
+    2, Iclass_wur_qacc_l_4_stateArgs, 0, 0 },
+  { 1, Iclass_rur_gpio_out_args,
+    1, Iclass_rur_gpio_out_stateArgs, 0, 0 },
+  { 1, Iclass_wur_gpio_out_args,
+    1, Iclass_wur_gpio_out_stateArgs, 0, 0 },
+  { 1, Iclass_rur_sar_byte_args,
+    2, Iclass_rur_sar_byte_stateArgs, 0, 0 },
+  { 1, Iclass_wur_sar_byte_args,
+    2, Iclass_wur_sar_byte_stateArgs, 0, 0 },
+  { 1, Iclass_rur_fft_bit_width_args,
+    2, Iclass_rur_fft_bit_width_stateArgs, 0, 0 },
+  { 1, Iclass_wur_fft_bit_width_args,
+    2, Iclass_wur_fft_bit_width_stateArgs, 0, 0 },
+  { 1, Iclass_rur_ua_state_0_args,
+    2, Iclass_rur_ua_state_0_stateArgs, 0, 0 },
+  { 1, Iclass_wur_ua_state_0_args,
+    2, Iclass_wur_ua_state_0_stateArgs, 0, 0 },
+  { 1, Iclass_rur_ua_state_1_args,
+    2, Iclass_rur_ua_state_1_stateArgs, 0, 0 },
+  { 1, Iclass_wur_ua_state_1_args,
+    2, Iclass_wur_ua_state_1_stateArgs, 0, 0 },
+  { 1, Iclass_rur_ua_state_2_args,
+    2, Iclass_rur_ua_state_2_stateArgs, 0, 0 },
+  { 1, Iclass_wur_ua_state_2_args,
+    2, Iclass_wur_ua_state_2_stateArgs, 0, 0 },
+  { 1, Iclass_rur_ua_state_3_args,
+    2, Iclass_rur_ua_state_3_stateArgs, 0, 0 },
+  { 1, Iclass_wur_ua_state_3_args,
+    2, Iclass_wur_ua_state_3_stateArgs, 0, 0 }
+};
+
+enum xtensa_iclass_id {
+  ICLASS_LSI,
+  ICLASS_LSIP,
+  ICLASS_LSX,
+  ICLASS_LSXP,
+  ICLASS_SSI,
+  ICLASS_SSIP,
+  ICLASS_SSX,
+  ICLASS_SSXP,
+  ICLASS_ABS_S,
+  ICLASS_NEG_S,
+  ICLASS_MOV_S,
+  ICLASS_MOVEQZ_S,
+  ICLASS_MOVNEZ_S,
+  ICLASS_MOVLTZ_S,
+  ICLASS_MOVGEZ_S,
+  ICLASS_MOVF_S,
+  ICLASS_MOVT_S,
+  ICLASS_WFR,
+  ICLASS_RFR,
+  ICLASS_ROUND_S,
+  ICLASS_CEIL_S,
+  ICLASS_FLOOR_S,
+  ICLASS_TRUNC_S,
+  ICLASS_UTRUNC_S,
+  ICLASS_FLOAT_S,
+  ICLASS_UFLOAT_S,
+  ICLASS_UN_S,
+  ICLASS_ULT_S,
+  ICLASS_ULE_S,
+  ICLASS_UEQ_S,
+  ICLASS_OLT_S,
+  ICLASS_OLE_S,
+  ICLASS_OEQ_S,
+  ICLASS_ADD_S,
+  ICLASS_SUB_S,
+  ICLASS_MUL_S,
+  ICLASS_MADD_S,
+  ICLASS_MSUB_S,
+  ICLASS_SQRT0_S,
+  ICLASS_DIV0_S,
+  ICLASS_RECIP0_S,
+  ICLASS_RSQRT0_S,
+  ICLASS_MADDN_S,
+  ICLASS_DIVN_S,
+  ICLASS_CONST_S,
+  ICLASS_NEXP01_S,
+  ICLASS_ADDEXP_S,
+  ICLASS_ADDEXPM_S,
+  ICLASS_MKDADJ_S,
+  ICLASS_MKSADJ_S,
+  ICLASS_xt_iclass_excw,
+  ICLASS_xt_iclass_rfe,
+  ICLASS_xt_iclass_rfde,
+  ICLASS_xt_iclass_syscall,
+  ICLASS_xt_iclass_call12,
+  ICLASS_xt_iclass_call8,
+  ICLASS_xt_iclass_call4,
+  ICLASS_xt_iclass_callx12,
+  ICLASS_xt_iclass_callx8,
+  ICLASS_xt_iclass_callx4,
+  ICLASS_xt_iclass_entry,
+  ICLASS_xt_iclass_movsp,
+  ICLASS_xt_iclass_rotw,
+  ICLASS_xt_iclass_retw,
+  ICLASS_xt_iclass_rfwou,
+  ICLASS_xt_iclass_l32e,
+  ICLASS_xt_iclass_s32e,
+  ICLASS_xt_iclass_rsr_windowbase,
+  ICLASS_xt_iclass_wsr_windowbase,
+  ICLASS_xt_iclass_xsr_windowbase,
+  ICLASS_xt_iclass_rsr_windowstart,
+  ICLASS_xt_iclass_wsr_windowstart,
+  ICLASS_xt_iclass_xsr_windowstart,
+  ICLASS_xt_iclass_add_n,
+  ICLASS_xt_iclass_addi_n,
+  ICLASS_xt_iclass_bz6,
+  ICLASS_xt_iclass_ill_n,
+  ICLASS_xt_iclass_loadi4,
+  ICLASS_xt_iclass_mov_n,
+  ICLASS_xt_iclass_movi_n,
+  ICLASS_xt_iclass_nopn,
+  ICLASS_xt_iclass_retn,
+  ICLASS_xt_iclass_storei4,
+  ICLASS_rur_threadptr,
+  ICLASS_wur_threadptr,
+  ICLASS_xt_iclass_addi,
+  ICLASS_xt_iclass_addmi,
+  ICLASS_xt_iclass_addsub,
+  ICLASS_xt_iclass_bit,
+  ICLASS_xt_iclass_bsi8,
+  ICLASS_xt_iclass_bsi8b,
+  ICLASS_xt_iclass_bsi8u,
+  ICLASS_xt_iclass_bst8,
+  ICLASS_xt_iclass_bsz12,
+  ICLASS_xt_iclass_call0,
+  ICLASS_xt_iclass_callx0,
+  ICLASS_xt_iclass_exti,
+  ICLASS_xt_iclass_ill,
+  ICLASS_xt_iclass_jump,
+  ICLASS_xt_iclass_jumpx,
+  ICLASS_xt_iclass_l16ui,
+  ICLASS_xt_iclass_l16si,
+  ICLASS_xt_iclass_l32i,
+  ICLASS_xt_iclass_l32r,
+  ICLASS_xt_iclass_l8i,
+  ICLASS_xt_iclass_loop,
+  ICLASS_xt_iclass_loopz,
+  ICLASS_xt_iclass_movi,
+  ICLASS_xt_iclass_movz,
+  ICLASS_xt_iclass_neg,
+  ICLASS_xt_iclass_nop,
+  ICLASS_xt_iclass_return,
+  ICLASS_xt_iclass_simcall,
+  ICLASS_xt_iclass_s16i,
+  ICLASS_xt_iclass_s32i,
+  ICLASS_xt_iclass_s32nb,
+  ICLASS_xt_iclass_s8i,
+  ICLASS_xt_iclass_sar,
+  ICLASS_xt_iclass_sari,
+  ICLASS_xt_iclass_shifts,
+  ICLASS_xt_iclass_shiftst,
+  ICLASS_xt_iclass_shiftt,
+  ICLASS_xt_iclass_slli,
+  ICLASS_xt_iclass_srai,
+  ICLASS_xt_iclass_srli,
+  ICLASS_xt_iclass_memw,
+  ICLASS_xt_iclass_extw,
+  ICLASS_xt_iclass_isync,
+  ICLASS_xt_iclass_sync,
+  ICLASS_xt_iclass_rsil,
+  ICLASS_xt_iclass_rsr_lend,
+  ICLASS_xt_iclass_wsr_lend,
+  ICLASS_xt_iclass_xsr_lend,
+  ICLASS_xt_iclass_rsr_lcount,
+  ICLASS_xt_iclass_wsr_lcount,
+  ICLASS_xt_iclass_xsr_lcount,
+  ICLASS_xt_iclass_rsr_lbeg,
+  ICLASS_xt_iclass_wsr_lbeg,
+  ICLASS_xt_iclass_xsr_lbeg,
+  ICLASS_xt_iclass_rsr_sar,
+  ICLASS_xt_iclass_wsr_sar,
+  ICLASS_xt_iclass_xsr_sar,
+  ICLASS_xt_iclass_rsr_memctl,
+  ICLASS_xt_iclass_wsr_memctl,
+  ICLASS_xt_iclass_xsr_memctl,
+  ICLASS_xt_iclass_rsr_litbase,
+  ICLASS_xt_iclass_wsr_litbase,
+  ICLASS_xt_iclass_xsr_litbase,
+  ICLASS_xt_iclass_rsr_configid0,
+  ICLASS_xt_iclass_wsr_configid0,
+  ICLASS_xt_iclass_rsr_configid1,
+  ICLASS_xt_iclass_rsr_ps,
+  ICLASS_xt_iclass_wsr_ps,
+  ICLASS_xt_iclass_xsr_ps,
+  ICLASS_xt_iclass_rsr_epc1,
+  ICLASS_xt_iclass_wsr_epc1,
+  ICLASS_xt_iclass_xsr_epc1,
+  ICLASS_xt_iclass_rsr_excsave1,
+  ICLASS_xt_iclass_wsr_excsave1,
+  ICLASS_xt_iclass_xsr_excsave1,
+  ICLASS_xt_iclass_rsr_epc2,
+  ICLASS_xt_iclass_wsr_epc2,
+  ICLASS_xt_iclass_xsr_epc2,
+  ICLASS_xt_iclass_rsr_excsave2,
+  ICLASS_xt_iclass_wsr_excsave2,
+  ICLASS_xt_iclass_xsr_excsave2,
+  ICLASS_xt_iclass_rsr_epc3,
+  ICLASS_xt_iclass_wsr_epc3,
+  ICLASS_xt_iclass_xsr_epc3,
+  ICLASS_xt_iclass_rsr_excsave3,
+  ICLASS_xt_iclass_wsr_excsave3,
+  ICLASS_xt_iclass_xsr_excsave3,
+  ICLASS_xt_iclass_rsr_epc4,
+  ICLASS_xt_iclass_wsr_epc4,
+  ICLASS_xt_iclass_xsr_epc4,
+  ICLASS_xt_iclass_rsr_excsave4,
+  ICLASS_xt_iclass_wsr_excsave4,
+  ICLASS_xt_iclass_xsr_excsave4,
+  ICLASS_xt_iclass_rsr_epc5,
+  ICLASS_xt_iclass_wsr_epc5,
+  ICLASS_xt_iclass_xsr_epc5,
+  ICLASS_xt_iclass_rsr_excsave5,
+  ICLASS_xt_iclass_wsr_excsave5,
+  ICLASS_xt_iclass_xsr_excsave5,
+  ICLASS_xt_iclass_rsr_epc6,
+  ICLASS_xt_iclass_wsr_epc6,
+  ICLASS_xt_iclass_xsr_epc6,
+  ICLASS_xt_iclass_rsr_excsave6,
+  ICLASS_xt_iclass_wsr_excsave6,
+  ICLASS_xt_iclass_xsr_excsave6,
+  ICLASS_xt_iclass_rsr_epc7,
+  ICLASS_xt_iclass_wsr_epc7,
+  ICLASS_xt_iclass_xsr_epc7,
+  ICLASS_xt_iclass_rsr_excsave7,
+  ICLASS_xt_iclass_wsr_excsave7,
+  ICLASS_xt_iclass_xsr_excsave7,
+  ICLASS_xt_iclass_rsr_eps2,
+  ICLASS_xt_iclass_wsr_eps2,
+  ICLASS_xt_iclass_xsr_eps2,
+  ICLASS_xt_iclass_rsr_eps3,
+  ICLASS_xt_iclass_wsr_eps3,
+  ICLASS_xt_iclass_xsr_eps3,
+  ICLASS_xt_iclass_rsr_eps4,
+  ICLASS_xt_iclass_wsr_eps4,
+  ICLASS_xt_iclass_xsr_eps4,
+  ICLASS_xt_iclass_rsr_eps5,
+  ICLASS_xt_iclass_wsr_eps5,
+  ICLASS_xt_iclass_xsr_eps5,
+  ICLASS_xt_iclass_rsr_eps6,
+  ICLASS_xt_iclass_wsr_eps6,
+  ICLASS_xt_iclass_xsr_eps6,
+  ICLASS_xt_iclass_rsr_eps7,
+  ICLASS_xt_iclass_wsr_eps7,
+  ICLASS_xt_iclass_xsr_eps7,
+  ICLASS_xt_iclass_rsr_excvaddr,
+  ICLASS_xt_iclass_wsr_excvaddr,
+  ICLASS_xt_iclass_xsr_excvaddr,
+  ICLASS_xt_iclass_rsr_depc,
+  ICLASS_xt_iclass_wsr_depc,
+  ICLASS_xt_iclass_xsr_depc,
+  ICLASS_xt_iclass_rsr_exccause,
+  ICLASS_xt_iclass_wsr_exccause,
+  ICLASS_xt_iclass_xsr_exccause,
+  ICLASS_xt_iclass_rsr_misc0,
+  ICLASS_xt_iclass_wsr_misc0,
+  ICLASS_xt_iclass_xsr_misc0,
+  ICLASS_xt_iclass_rsr_misc1,
+  ICLASS_xt_iclass_wsr_misc1,
+  ICLASS_xt_iclass_xsr_misc1,
+  ICLASS_xt_iclass_rsr_misc2,
+  ICLASS_xt_iclass_wsr_misc2,
+  ICLASS_xt_iclass_xsr_misc2,
+  ICLASS_xt_iclass_rsr_misc3,
+  ICLASS_xt_iclass_wsr_misc3,
+  ICLASS_xt_iclass_xsr_misc3,
+  ICLASS_xt_iclass_rsr_prid,
+  ICLASS_xt_iclass_rsr_vecbase,
+  ICLASS_xt_iclass_wsr_vecbase,
+  ICLASS_xt_iclass_xsr_vecbase,
+  ICLASS_xt_iclass_salt,
+  ICLASS_xt_mul16,
+  ICLASS_xt_mul32,
+  ICLASS_xt_mul32h,
+  ICLASS_xt_iclass_mac16_aa,
+  ICLASS_xt_iclass_mac16_ad,
+  ICLASS_xt_iclass_mac16_da,
+  ICLASS_xt_iclass_mac16_dd,
+  ICLASS_xt_iclass_mac16a_aa,
+  ICLASS_xt_iclass_mac16a_ad,
+  ICLASS_xt_iclass_mac16a_da,
+  ICLASS_xt_iclass_mac16a_dd,
+  ICLASS_xt_iclass_mac16al_da,
+  ICLASS_xt_iclass_mac16al_dd,
+  ICLASS_xt_iclass_mac16_l,
+  ICLASS_xt_iclass_rsr_m0,
+  ICLASS_xt_iclass_wsr_m0,
+  ICLASS_xt_iclass_xsr_m0,
+  ICLASS_xt_iclass_rsr_m1,
+  ICLASS_xt_iclass_wsr_m1,
+  ICLASS_xt_iclass_xsr_m1,
+  ICLASS_xt_iclass_rsr_m2,
+  ICLASS_xt_iclass_wsr_m2,
+  ICLASS_xt_iclass_xsr_m2,
+  ICLASS_xt_iclass_rsr_m3,
+  ICLASS_xt_iclass_wsr_m3,
+  ICLASS_xt_iclass_xsr_m3,
+  ICLASS_xt_iclass_rsr_acclo,
+  ICLASS_xt_iclass_wsr_acclo,
+  ICLASS_xt_iclass_xsr_acclo,
+  ICLASS_xt_iclass_rsr_acchi,
+  ICLASS_xt_iclass_wsr_acchi,
+  ICLASS_xt_iclass_xsr_acchi,
+  ICLASS_xt_iclass_rfi,
+  ICLASS_xt_iclass_wait,
+  ICLASS_xt_iclass_rsr_interrupt,
+  ICLASS_xt_iclass_wsr_intset,
+  ICLASS_xt_iclass_wsr_intclear,
+  ICLASS_xt_iclass_rsr_intenable,
+  ICLASS_xt_iclass_wsr_intenable,
+  ICLASS_xt_iclass_xsr_intenable,
+  ICLASS_xt_iclass_break,
+  ICLASS_xt_iclass_break_n,
+  ICLASS_xt_iclass_rsr_dbreaka0,
+  ICLASS_xt_iclass_wsr_dbreaka0,
+  ICLASS_xt_iclass_xsr_dbreaka0,
+  ICLASS_xt_iclass_rsr_dbreakc0,
+  ICLASS_xt_iclass_wsr_dbreakc0,
+  ICLASS_xt_iclass_xsr_dbreakc0,
+  ICLASS_xt_iclass_rsr_dbreaka1,
+  ICLASS_xt_iclass_wsr_dbreaka1,
+  ICLASS_xt_iclass_xsr_dbreaka1,
+  ICLASS_xt_iclass_rsr_dbreakc1,
+  ICLASS_xt_iclass_wsr_dbreakc1,
+  ICLASS_xt_iclass_xsr_dbreakc1,
+  ICLASS_xt_iclass_rsr_ibreaka0,
+  ICLASS_xt_iclass_wsr_ibreaka0,
+  ICLASS_xt_iclass_xsr_ibreaka0,
+  ICLASS_xt_iclass_rsr_ibreaka1,
+  ICLASS_xt_iclass_wsr_ibreaka1,
+  ICLASS_xt_iclass_xsr_ibreaka1,
+  ICLASS_xt_iclass_rsr_ibreakenable,
+  ICLASS_xt_iclass_wsr_ibreakenable,
+  ICLASS_xt_iclass_xsr_ibreakenable,
+  ICLASS_xt_iclass_rsr_debugcause,
+  ICLASS_xt_iclass_wsr_debugcause,
+  ICLASS_xt_iclass_xsr_debugcause,
+  ICLASS_xt_iclass_rsr_icount,
+  ICLASS_xt_iclass_wsr_icount,
+  ICLASS_xt_iclass_xsr_icount,
+  ICLASS_xt_iclass_rsr_icountlevel,
+  ICLASS_xt_iclass_wsr_icountlevel,
+  ICLASS_xt_iclass_xsr_icountlevel,
+  ICLASS_xt_iclass_rsr_ddr,
+  ICLASS_xt_iclass_wsr_ddr,
+  ICLASS_xt_iclass_xsr_ddr,
+  ICLASS_xt_iclass_lddr32_p,
+  ICLASS_xt_iclass_sddr32_p,
+  ICLASS_xt_iclass_rfdo,
+  ICLASS_xt_iclass_rfdd,
+  ICLASS_xt_iclass_wsr_mmid,
+  ICLASS_xt_iclass_bbool1,
+  ICLASS_xt_iclass_bbool4,
+  ICLASS_xt_iclass_bbool8,
+  ICLASS_xt_iclass_bbranch,
+  ICLASS_xt_iclass_bmove,
+  ICLASS_xt_iclass_RSR_BR,
+  ICLASS_xt_iclass_WSR_BR,
+  ICLASS_xt_iclass_XSR_BR,
+  ICLASS_xt_iclass_rsr_ccount,
+  ICLASS_xt_iclass_wsr_ccount,
+  ICLASS_xt_iclass_xsr_ccount,
+  ICLASS_xt_iclass_rsr_ccompare0,
+  ICLASS_xt_iclass_wsr_ccompare0,
+  ICLASS_xt_iclass_xsr_ccompare0,
+  ICLASS_xt_iclass_rsr_ccompare1,
+  ICLASS_xt_iclass_wsr_ccompare1,
+  ICLASS_xt_iclass_xsr_ccompare1,
+  ICLASS_xt_iclass_rsr_ccompare2,
+  ICLASS_xt_iclass_wsr_ccompare2,
+  ICLASS_xt_iclass_xsr_ccompare2,
+  ICLASS_xt_iclass_idtlb,
+  ICLASS_xt_iclass_rdtlb,
+  ICLASS_xt_iclass_wdtlb,
+  ICLASS_xt_iclass_iitlb,
+  ICLASS_xt_iclass_ritlb,
+  ICLASS_xt_iclass_witlb,
+  ICLASS_xt_iclass_rsr_cpenable,
+  ICLASS_xt_iclass_wsr_cpenable,
+  ICLASS_xt_iclass_xsr_cpenable,
+  ICLASS_xt_iclass_clamp,
+  ICLASS_xt_iclass_minmax,
+  ICLASS_xt_iclass_nsa,
+  ICLASS_xt_iclass_sx,
+  ICLASS_xt_iclass_l32ai,
+  ICLASS_xt_iclass_s32ri,
+  ICLASS_xt_iclass_s32c1i,
+  ICLASS_xt_iclass_rsr_scompare1,
+  ICLASS_xt_iclass_wsr_scompare1,
+  ICLASS_xt_iclass_xsr_scompare1,
+  ICLASS_xt_iclass_rsr_atomctl,
+  ICLASS_xt_iclass_wsr_atomctl,
+  ICLASS_xt_iclass_xsr_atomctl,
+  ICLASS_xt_iclass_div,
+  ICLASS_xt_iclass_rsr_eraccess,
+  ICLASS_xt_iclass_wsr_eraccess,
+  ICLASS_xt_iclass_xsr_eraccess,
+  ICLASS_xt_iclass_rer,
+  ICLASS_xt_iclass_wer,
+  ICLASS_rur_fcr,
+  ICLASS_wur_fcr,
+  ICLASS_rur_fsr,
+  ICLASS_wur_fsr,
+  ICLASS_st_QR,
+  ICLASS_ld_QR,
+  ICLASS_mv_QR,
+  ICLASS_EE_WR_MASK_GPIO_OUT,
+  ICLASS_EE_SET_BIT_GPIO_OUT,
+  ICLASS_EE_CLR_BIT_GPIO_OUT,
+  ICLASS_EE_GET_GPIO_IN,
+  ICLASS_EE_VLD_128_IP,
+  ICLASS_EE_VLD_128_XP,
+  ICLASS_EE_VLD_H_64_IP,
+  ICLASS_EE_VLD_H_64_XP,
+  ICLASS_EE_VLD_L_64_IP,
+  ICLASS_EE_VLD_L_64_XP,
+  ICLASS_EE_VLDBC_16_IP,
+  ICLASS_EE_VLDBC_16,
+  ICLASS_EE_VLDBC_16_XP,
+  ICLASS_EE_VLDBC_32_IP,
+  ICLASS_EE_VLDBC_32,
+  ICLASS_EE_VLDBC_32_XP,
+  ICLASS_EE_VLDBC_8_IP,
+  ICLASS_EE_VLDBC_8,
+  ICLASS_EE_VLDBC_8_XP,
+  ICLASS_EE_VLDHBC_16_INCP,
+  ICLASS_EE_LDF_128_IP,
+  ICLASS_EE_LDF_128_XP,
+  ICLASS_EE_LDF_64_IP,
+  ICLASS_EE_LDF_64_XP,
+  ICLASS_EE_LD_128_USAR_IP,
+  ICLASS_EE_LD_128_USAR_XP,
+  ICLASS_EE_LDQA_S16_128_IP,
+  ICLASS_EE_LDQA_S16_128_XP,
+  ICLASS_EE_LDQA_S8_128_IP,
+  ICLASS_EE_LDQA_S8_128_XP,
+  ICLASS_EE_LDQA_U16_128_IP,
+  ICLASS_EE_LDQA_U16_128_XP,
+  ICLASS_EE_LDQA_U8_128_IP,
+  ICLASS_EE_LDQA_U8_128_XP,
+  ICLASS_EE_LD_QACC_H_H_32_IP,
+  ICLASS_EE_LD_QACC_H_L_128_IP,
+  ICLASS_EE_LD_QACC_L_H_32_IP,
+  ICLASS_EE_LD_QACC_L_L_128_IP,
+  ICLASS_EE_LD_ACCX_IP,
+  ICLASS_EE_LDXQ_32,
+  ICLASS_EE_LD_UA_STATE_IP,
+  ICLASS_EE_ST_UA_STATE_IP,
+  ICLASS_EE_VST_128_IP,
+  ICLASS_EE_VST_128_XP,
+  ICLASS_EE_VST_H_64_IP,
+  ICLASS_EE_VST_H_64_XP,
+  ICLASS_EE_VST_L_64_IP,
+  ICLASS_EE_VST_L_64_XP,
+  ICLASS_EE_STF_128_IP,
+  ICLASS_EE_STF_128_XP,
+  ICLASS_EE_STF_64_IP,
+  ICLASS_EE_STF_64_XP,
+  ICLASS_EE_ST_QACC_H_H_32_IP,
+  ICLASS_EE_ST_QACC_H_L_128_IP,
+  ICLASS_EE_ST_QACC_L_H_32_IP,
+  ICLASS_EE_ST_QACC_L_L_128_IP,
+  ICLASS_EE_ST_ACCX_IP,
+  ICLASS_EE_STXQ_32,
+  ICLASS_EE_MOVI_32_A,
+  ICLASS_EE_MOVI_32_Q,
+  ICLASS_EE_VZIP_16,
+  ICLASS_EE_VZIP_32,
+  ICLASS_EE_VZIP_8,
+  ICLASS_EE_VUNZIP_16,
+  ICLASS_EE_VUNZIP_32,
+  ICLASS_EE_VUNZIP_8,
+  ICLASS_EE_ZERO_ACCX,
+  ICLASS_EE_ZERO_QACC,
+  ICLASS_EE_ZERO_Q,
+  ICLASS_EE_MOV_S16_QACC,
+  ICLASS_EE_MOV_S8_QACC,
+  ICLASS_EE_MOV_U16_QACC,
+  ICLASS_EE_MOV_U8_QACC,
+  ICLASS_EE_VADDS_S16_LD_INCP,
+  ICLASS_EE_VADDS_S16_ST_INCP,
+  ICLASS_EE_VADDS_S16,
+  ICLASS_EE_VADDS_S32_LD_INCP,
+  ICLASS_EE_VADDS_S32_ST_INCP,
+  ICLASS_EE_VADDS_S32,
+  ICLASS_EE_VADDS_S8_LD_INCP,
+  ICLASS_EE_VADDS_S8_ST_INCP,
+  ICLASS_EE_VADDS_S8,
+  ICLASS_EE_VSUBS_S16_LD_INCP,
+  ICLASS_EE_VSUBS_S16_ST_INCP,
+  ICLASS_EE_VSUBS_S16,
+  ICLASS_EE_VSUBS_S32_LD_INCP,
+  ICLASS_EE_VSUBS_S32_ST_INCP,
+  ICLASS_EE_VSUBS_S32,
+  ICLASS_EE_VSUBS_S8_LD_INCP,
+  ICLASS_EE_VSUBS_S8_ST_INCP,
+  ICLASS_EE_VSUBS_S8,
+  ICLASS_EE_VMUL_S16_LD_INCP,
+  ICLASS_EE_VMUL_S16_ST_INCP,
+  ICLASS_EE_VMUL_S16,
+  ICLASS_EE_VMUL_S8_LD_INCP,
+  ICLASS_EE_VMUL_S8_ST_INCP,
+  ICLASS_EE_VMUL_S8,
+  ICLASS_EE_VMUL_U16_LD_INCP,
+  ICLASS_EE_VMUL_U16_ST_INCP,
+  ICLASS_EE_VMUL_U16,
+  ICLASS_EE_VMUL_U8_LD_INCP,
+  ICLASS_EE_VMUL_U8_ST_INCP,
+  ICLASS_EE_VMUL_U8,
+  ICLASS_EE_CMUL_S16_LD_INCP,
+  ICLASS_EE_CMUL_S16_ST_INCP,
+  ICLASS_EE_CMUL_S16,
+  ICLASS_EE_VMULAS_S16_ACCX_LD_IP_QUP,
+  ICLASS_EE_VMULAS_S16_ACCX_LD_IP,
+  ICLASS_EE_VMULAS_S16_ACCX_LD_XP_QUP,
+  ICLASS_EE_VMULAS_S16_ACCX_LD_XP,
+  ICLASS_EE_VMULAS_S16_ACCX,
+  ICLASS_EE_VMULAS_S8_ACCX_LD_IP_QUP,
+  ICLASS_EE_VMULAS_S8_ACCX_LD_IP,
+  ICLASS_EE_VMULAS_S8_ACCX_LD_XP_QUP,
+  ICLASS_EE_VMULAS_S8_ACCX_LD_XP,
+  ICLASS_EE_VMULAS_S8_ACCX,
+  ICLASS_EE_VMULAS_U16_ACCX_LD_IP_QUP,
+  ICLASS_EE_VMULAS_U16_ACCX_LD_IP,
+  ICLASS_EE_VMULAS_U16_ACCX_LD_XP_QUP,
+  ICLASS_EE_VMULAS_U16_ACCX_LD_XP,
+  ICLASS_EE_VMULAS_U16_ACCX,
+  ICLASS_EE_VMULAS_U8_ACCX_LD_IP_QUP,
+  ICLASS_EE_VMULAS_U8_ACCX_LD_IP,
+  ICLASS_EE_VMULAS_U8_ACCX_LD_XP_QUP,
+  ICLASS_EE_VMULAS_U8_ACCX_LD_XP,
+  ICLASS_EE_VMULAS_U8_ACCX,
+  ICLASS_EE_VMULAS_S16_QACC_LDBC_INCP_QUP,
+  ICLASS_EE_VMULAS_S16_QACC_LDBC_INCP,
+  ICLASS_EE_VMULAS_S16_QACC_LD_IP_QUP,
+  ICLASS_EE_VMULAS_S16_QACC_LD_IP,
+  ICLASS_EE_VMULAS_S16_QACC_LD_XP_QUP,
+  ICLASS_EE_VMULAS_S16_QACC_LD_XP,
+  ICLASS_EE_VMULAS_S16_QACC,
+  ICLASS_EE_VMULAS_S8_QACC_LDBC_INCP_QUP,
+  ICLASS_EE_VMULAS_S8_QACC_LDBC_INCP,
+  ICLASS_EE_VMULAS_S8_QACC_LD_IP_QUP,
+  ICLASS_EE_VMULAS_S8_QACC_LD_IP,
+  ICLASS_EE_VMULAS_S8_QACC_LD_XP_QUP,
+  ICLASS_EE_VMULAS_S8_QACC_LD_XP,
+  ICLASS_EE_VMULAS_S8_QACC,
+  ICLASS_EE_VMULAS_U16_QACC_LDBC_INCP_QUP,
+  ICLASS_EE_VMULAS_U16_QACC_LDBC_INCP,
+  ICLASS_EE_VMULAS_U16_QACC_LD_IP_QUP,
+  ICLASS_EE_VMULAS_U16_QACC_LD_IP,
+  ICLASS_EE_VMULAS_U16_QACC_LD_XP_QUP,
+  ICLASS_EE_VMULAS_U16_QACC_LD_XP,
+  ICLASS_EE_VMULAS_U16_QACC,
+  ICLASS_EE_VMULAS_U8_QACC_LDBC_INCP_QUP,
+  ICLASS_EE_VMULAS_U8_QACC_LDBC_INCP,
+  ICLASS_EE_VMULAS_U8_QACC_LD_IP_QUP,
+  ICLASS_EE_VMULAS_U8_QACC_LD_IP,
+  ICLASS_EE_VMULAS_U8_QACC_LD_XP_QUP,
+  ICLASS_EE_VMULAS_U8_QACC_LD_XP,
+  ICLASS_EE_VMULAS_U8_QACC,
+  ICLASS_EE_VSMULAS_S16_QACC_LD_INCP,
+  ICLASS_EE_VSMULAS_S16_QACC,
+  ICLASS_EE_VSMULAS_S8_QACC_LD_INCP,
+  ICLASS_EE_VSMULAS_S8_QACC,
+  ICLASS_EE_SRCMB_S16_QACC,
+  ICLASS_EE_SRCMB_S8_QACC,
+  ICLASS_EE_SRS_ACCX,
+  ICLASS_EE_VRELU_S16,
+  ICLASS_EE_VRELU_S8,
+  ICLASS_EE_VPRELU_S16,
+  ICLASS_EE_VPRELU_S8,
+  ICLASS_EE_VMAX_S16_LD_INCP,
+  ICLASS_EE_VMAX_S16_ST_INCP,
+  ICLASS_EE_VMAX_S16,
+  ICLASS_EE_VMAX_S32_LD_INCP,
+  ICLASS_EE_VMAX_S32_ST_INCP,
+  ICLASS_EE_VMAX_S32,
+  ICLASS_EE_VMAX_S8_LD_INCP,
+  ICLASS_EE_VMAX_S8_ST_INCP,
+  ICLASS_EE_VMAX_S8,
+  ICLASS_EE_VMIN_S16_LD_INCP,
+  ICLASS_EE_VMIN_S16_ST_INCP,
+  ICLASS_EE_VMIN_S16,
+  ICLASS_EE_VMIN_S32_LD_INCP,
+  ICLASS_EE_VMIN_S32_ST_INCP,
+  ICLASS_EE_VMIN_S32,
+  ICLASS_EE_VMIN_S8_LD_INCP,
+  ICLASS_EE_VMIN_S8_ST_INCP,
+  ICLASS_EE_VMIN_S8,
+  ICLASS_EE_VCMP_EQ_S16,
+  ICLASS_EE_VCMP_EQ_S32,
+  ICLASS_EE_VCMP_EQ_S8,
+  ICLASS_EE_VCMP_GT_S16,
+  ICLASS_EE_VCMP_GT_S32,
+  ICLASS_EE_VCMP_GT_S8,
+  ICLASS_EE_VCMP_LT_S16,
+  ICLASS_EE_VCMP_LT_S32,
+  ICLASS_EE_VCMP_LT_S8,
+  ICLASS_EE_ANDQ,
+  ICLASS_EE_NOTQ,
+  ICLASS_EE_ORQ,
+  ICLASS_EE_XORQ,
+  ICLASS_EE_SLCI_2Q,
+  ICLASS_EE_SLCXXP_2Q,
+  ICLASS_EE_SRCI_2Q,
+  ICLASS_EE_SRCQ_128_ST_INCP,
+  ICLASS_EE_SRC_Q_LD_IP,
+  ICLASS_EE_SRC_Q_LD_XP,
+  ICLASS_EE_SRC_Q_QUP,
+  ICLASS_EE_SRC_Q,
+  ICLASS_EE_SRCXXP_2Q,
+  ICLASS_EE_VSL_32,
+  ICLASS_EE_VSR_32,
+  ICLASS_EE_FFT_R2BF_S16_ST_INCP,
+  ICLASS_EE_FFT_R2BF_S16,
+  ICLASS_EE_FFT_CMUL_S16_LD_XP,
+  ICLASS_EE_FFT_CMUL_S16_ST_XP,
+  ICLASS_EE_BITREV,
+  ICLASS_EE_FFT_AMS_S16_LD_INCP,
+  ICLASS_EE_FFT_AMS_S16_LD_INCP_UAUP,
+  ICLASS_EE_FFT_AMS_S16_LD_R32_DECP,
+  ICLASS_EE_FFT_AMS_S16_ST_INCP,
+  ICLASS_EE_FFT_VST_R32_DECP,
+  ICLASS_rur_accx_0,
+  ICLASS_wur_accx_0,
+  ICLASS_rur_accx_1,
+  ICLASS_wur_accx_1,
+  ICLASS_rur_qacc_h_0,
+  ICLASS_wur_qacc_h_0,
+  ICLASS_rur_qacc_h_1,
+  ICLASS_wur_qacc_h_1,
+  ICLASS_rur_qacc_h_2,
+  ICLASS_wur_qacc_h_2,
+  ICLASS_rur_qacc_h_3,
+  ICLASS_wur_qacc_h_3,
+  ICLASS_rur_qacc_h_4,
+  ICLASS_wur_qacc_h_4,
+  ICLASS_rur_qacc_l_0,
+  ICLASS_wur_qacc_l_0,
+  ICLASS_rur_qacc_l_1,
+  ICLASS_wur_qacc_l_1,
+  ICLASS_rur_qacc_l_2,
+  ICLASS_wur_qacc_l_2,
+  ICLASS_rur_qacc_l_3,
+  ICLASS_wur_qacc_l_3,
+  ICLASS_rur_qacc_l_4,
+  ICLASS_wur_qacc_l_4,
+  ICLASS_rur_gpio_out,
+  ICLASS_wur_gpio_out,
+  ICLASS_rur_sar_byte,
+  ICLASS_wur_sar_byte,
+  ICLASS_rur_fft_bit_width,
+  ICLASS_wur_fft_bit_width,
+  ICLASS_rur_ua_state_0,
+  ICLASS_wur_ua_state_0,
+  ICLASS_rur_ua_state_1,
+  ICLASS_wur_ua_state_1,
+  ICLASS_rur_ua_state_2,
+  ICLASS_wur_ua_state_2,
+  ICLASS_rur_ua_state_3,
+  ICLASS_wur_ua_state_3
+};
+
+\f
+/*  Opcode encodings.  */
+
+static void
+Opcode_lsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3;
+}
+
+static void
+Opcode_lsip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8003;
+}
+
+static void
+Opcode_lsx_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x80000;
+}
+
+static void
+Opcode_lsxp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x180000;
+}
+
+static void
+Opcode_ssi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x4003;
+}
+
+static void
+Opcode_ssip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc003;
+}
+
+static void
+Opcode_ssx_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x480000;
+}
+
+static void
+Opcode_ssxp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x580000;
+}
+
+static void
+Opcode_abs_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa0010;
+}
+
+static void
+Opcode_neg_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa0060;
+}
+
+static void
+Opcode_mov_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa0000;
+}
+
+static void
+Opcode_moveqz_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8b0000;
+}
+
+static void
+Opcode_movnez_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x9b0000;
+}
+
+static void
+Opcode_movltz_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xab0000;
+}
+
+static void
+Opcode_movgez_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xbb0000;
+}
+
+static void
+Opcode_movf_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcb0000;
+}
+
+static void
+Opcode_movt_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xdb0000;
+}
+
+static void
+Opcode_wfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa0050;
+}
+
+static void
+Opcode_rfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa0040;
+}
+
+static void
+Opcode_round_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8a0000;
+}
+
+static void
+Opcode_ceil_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xba0000;
+}
+
+static void
+Opcode_floor_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xaa0000;
+}
+
+static void
+Opcode_trunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x9a0000;
+}
+
+static void
+Opcode_utrunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xea0000;
+}
+
+static void
+Opcode_float_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xca0000;
+}
+
+static void
+Opcode_ufloat_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xda0000;
+}
+
+static void
+Opcode_un_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1b0000;
+}
+
+static void
+Opcode_ult_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x5b0000;
+}
+
+static void
+Opcode_ule_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x7b0000;
+}
+
+static void
+Opcode_ueq_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b0000;
+}
+
+static void
+Opcode_olt_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x4b0000;
+}
+
+static void
+Opcode_ole_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6b0000;
+}
+
+static void
+Opcode_oeq_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2b0000;
+}
+
+static void
+Opcode_add_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa0000;
+}
+
+static void
+Opcode_sub_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1a0000;
+}
+
+static void
+Opcode_mul_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2a0000;
+}
+
+static void
+Opcode_madd_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x4a0000;
+}
+
+static void
+Opcode_msub_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x5a0000;
+}
+
+static void
+Opcode_sqrt0_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa0090;
+}
+
+static void
+Opcode_div0_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa0070;
+}
+
+static void
+Opcode_recip0_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa0080;
+}
+
+static void
+Opcode_rsqrt0_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa00a0;
+}
+
+static void
+Opcode_maddn_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6a0000;
+}
+
+static void
+Opcode_divn_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x7a0000;
+}
+
+static void
+Opcode_const_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa0030;
+}
+
+static void
+Opcode_nexp01_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa00b0;
+}
+
+static void
+Opcode_addexp_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa00e0;
+}
+
+static void
+Opcode_addexpm_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa00f0;
+}
+
+static void
+Opcode_mkdadj_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa00d0;
+}
+
+static void
+Opcode_mksadj_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xfa00c0;
+}
+
+static void
+Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2080;
+}
+
+static void
+Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3000;
+}
+
+static void
+Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3200;
+}
+
+static void
+Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x5000;
+}
+
+static void
+Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x35;
+}
+
+static void
+Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x25;
+}
+
+static void
+Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x15;
+}
+
+static void
+Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf0;
+}
+
+static void
+Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe0;
+}
+
+static void
+Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd0;
+}
+
+static void
+Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x36;
+}
+
+static void
+Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1000;
+}
+
+static void
+Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x408000;
+}
+
+static void
+Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x90;
+}
+
+static void
+Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf01d;
+}
+
+static void
+Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3400;
+}
+
+static void
+Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3500;
+}
+
+static void
+Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x90000;
+}
+
+static void
+Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x490000;
+}
+
+static void
+Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x34800;
+}
+
+static void
+Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x134800;
+}
+
+static void
+Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x614800;
+}
+
+static void
+Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x34900;
+}
+
+static void
+Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x134900;
+}
+
+static void
+Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x614900;
+}
+
+static void
+Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa;
+}
+
+static void
+Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb;
+}
+
+static void
+Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8c;
+}
+
+static void
+Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcc;
+}
+
+static void
+Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf06d;
+}
+
+static void
+Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8;
+}
+
+static void
+Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd;
+}
+
+static void
+Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc;
+}
+
+static void
+Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf03d;
+}
+
+static void
+Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf00d;
+}
+
+static void
+Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x9;
+}
+
+static void
+Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe30e70;
+}
+
+static void
+Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf3e700;
+}
+
+static void
+Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc002;
+}
+
+static void
+Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd002;
+}
+
+static void
+Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x800000;
+}
+
+static void
+Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc00000;
+}
+
+static void
+Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x900000;
+}
+
+static void
+Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa00000;
+}
+
+static void
+Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb00000;
+}
+
+static void
+Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd00000;
+}
+
+static void
+Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe00000;
+}
+
+static void
+Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf00000;
+}
+
+static void
+Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x100000;
+}
+
+static void
+Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x200000;
+}
+
+static void
+Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x300000;
+}
+
+static void
+Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x26;
+}
+
+static void
+Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x66;
+}
+
+static void
+Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe6;
+}
+
+static void
+Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa6;
+}
+
+static void
+Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6007;
+}
+
+static void
+Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe007;
+}
+
+static void
+Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf6;
+}
+
+static void
+Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb6;
+}
+
+static void
+Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1007;
+}
+
+static void
+Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x9007;
+}
+
+static void
+Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa007;
+}
+
+static void
+Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2007;
+}
+
+static void
+Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb007;
+}
+
+static void
+Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3007;
+}
+
+static void
+Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8007;
+}
+
+static void
+Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x7;
+}
+
+static void
+Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x4007;
+}
+
+static void
+Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc007;
+}
+
+static void
+Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x5007;
+}
+
+static void
+Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd007;
+}
+
+static void
+Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x16;
+}
+
+static void
+Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x56;
+}
+
+static void
+Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd6;
+}
+
+static void
+Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x96;
+}
+
+static void
+Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x5;
+}
+
+static void
+Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc0;
+}
+
+static void
+Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x40000;
+}
+
+static void
+Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0;
+}
+
+static void
+Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6;
+}
+
+static void
+Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa0;
+}
+
+static void
+Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1002;
+}
+
+static void
+Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x9002;
+}
+
+static void
+Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2002;
+}
+
+static void
+Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1;
+}
+
+static void
+Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2;
+}
+
+static void
+Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8076;
+}
+
+static void
+Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x9076;
+}
+
+static void
+Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa076;
+}
+
+static void
+Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa002;
+}
+
+static void
+Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x830000;
+}
+
+static void
+Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x930000;
+}
+
+static void
+Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa30000;
+}
+
+static void
+Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb30000;
+}
+
+static void
+Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x600000;
+}
+
+static void
+Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x600100;
+}
+
+static void
+Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x20f0;
+}
+
+static void
+Opcode_nop_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1cc20000;
+}
+
+static void
+Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x80;
+}
+
+static void
+Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x5100;
+}
+
+static void
+Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x5002;
+}
+
+static void
+Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6002;
+}
+
+static void
+Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x590000;
+}
+
+static void
+Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x4002;
+}
+
+static void
+Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x400000;
+}
+
+static void
+Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x401000;
+}
+
+static void
+Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x402000;
+}
+
+static void
+Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x403000;
+}
+
+static void
+Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x404000;
+}
+
+static void
+Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa10000;
+}
+
+static void
+Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x810000;
+}
+
+static void
+Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x910000;
+}
+
+static void
+Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb10000;
+}
+
+static void
+Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x10000;
+}
+
+static void
+Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x210000;
+}
+
+static void
+Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x410000;
+}
+
+static void
+Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x20c0;
+}
+
+static void
+Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x20d0;
+}
+
+static void
+Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2000;
+}
+
+static void
+Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2010;
+}
+
+static void
+Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2020;
+}
+
+static void
+Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2030;
+}
+
+static void
+Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6000;
+}
+
+static void
+Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x30100;
+}
+
+static void
+Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x130100;
+}
+
+static void
+Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x610100;
+}
+
+static void
+Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x30200;
+}
+
+static void
+Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x130200;
+}
+
+static void
+Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x610200;
+}
+
+static void
+Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x30000;
+}
+
+static void
+Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x130000;
+}
+
+static void
+Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x610000;
+}
+
+static void
+Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x30300;
+}
+
+static void
+Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x130300;
+}
+
+static void
+Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x610300;
+}
+
+static void
+Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x36100;
+}
+
+static void
+Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x136100;
+}
+
+static void
+Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x616100;
+}
+
+static void
+Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x30500;
+}
+
+static void
+Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x130500;
+}
+
+static void
+Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x610500;
+}
+
+static void
+Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b000;
+}
+
+static void
+Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13b000;
+}
+
+static void
+Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d000;
+}
+
+static void
+Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3e600;
+}
+
+static void
+Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13e600;
+}
+
+static void
+Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61e600;
+}
+
+static void
+Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b100;
+}
+
+static void
+Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13b100;
+}
+
+static void
+Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61b100;
+}
+
+static void
+Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d100;
+}
+
+static void
+Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13d100;
+}
+
+static void
+Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61d100;
+}
+
+static void
+Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b200;
+}
+
+static void
+Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13b200;
+}
+
+static void
+Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61b200;
+}
+
+static void
+Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d200;
+}
+
+static void
+Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13d200;
+}
+
+static void
+Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61d200;
+}
+
+static void
+Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b300;
+}
+
+static void
+Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13b300;
+}
+
+static void
+Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61b300;
+}
+
+static void
+Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d300;
+}
+
+static void
+Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13d300;
+}
+
+static void
+Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61d300;
+}
+
+static void
+Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b400;
+}
+
+static void
+Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13b400;
+}
+
+static void
+Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61b400;
+}
+
+static void
+Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d400;
+}
+
+static void
+Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13d400;
+}
+
+static void
+Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61d400;
+}
+
+static void
+Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b500;
+}
+
+static void
+Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13b500;
+}
+
+static void
+Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61b500;
+}
+
+static void
+Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d500;
+}
+
+static void
+Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13d500;
+}
+
+static void
+Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61d500;
+}
+
+static void
+Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b600;
+}
+
+static void
+Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13b600;
+}
+
+static void
+Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61b600;
+}
+
+static void
+Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d600;
+}
+
+static void
+Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13d600;
+}
+
+static void
+Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61d600;
+}
+
+static void
+Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b700;
+}
+
+static void
+Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13b700;
+}
+
+static void
+Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61b700;
+}
+
+static void
+Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d700;
+}
+
+static void
+Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13d700;
+}
+
+static void
+Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61d700;
+}
+
+static void
+Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3c200;
+}
+
+static void
+Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13c200;
+}
+
+static void
+Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61c200;
+}
+
+static void
+Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3c300;
+}
+
+static void
+Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13c300;
+}
+
+static void
+Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61c300;
+}
+
+static void
+Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3c400;
+}
+
+static void
+Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13c400;
+}
+
+static void
+Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61c400;
+}
+
+static void
+Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3c500;
+}
+
+static void
+Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13c500;
+}
+
+static void
+Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61c500;
+}
+
+static void
+Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3c600;
+}
+
+static void
+Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13c600;
+}
+
+static void
+Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61c600;
+}
+
+static void
+Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3c700;
+}
+
+static void
+Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13c700;
+}
+
+static void
+Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61c700;
+}
+
+static void
+Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3ee00;
+}
+
+static void
+Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13ee00;
+}
+
+static void
+Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61ee00;
+}
+
+static void
+Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3c000;
+}
+
+static void
+Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13c000;
+}
+
+static void
+Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61c000;
+}
+
+static void
+Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3e800;
+}
+
+static void
+Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13e800;
+}
+
+static void
+Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61e800;
+}
+
+static void
+Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3f400;
+}
+
+static void
+Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13f400;
+}
+
+static void
+Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61f400;
+}
+
+static void
+Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3f500;
+}
+
+static void
+Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13f500;
+}
+
+static void
+Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61f500;
+}
+
+static void
+Opcode_rsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3f600;
+}
+
+static void
+Opcode_wsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13f600;
+}
+
+static void
+Opcode_xsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61f600;
+}
+
+static void
+Opcode_rsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3f700;
+}
+
+static void
+Opcode_wsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13f700;
+}
+
+static void
+Opcode_xsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61f700;
+}
+
+static void
+Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3eb00;
+}
+
+static void
+Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3e700;
+}
+
+static void
+Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13e700;
+}
+
+static void
+Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61e700;
+}
+
+static void
+Opcode_salt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x720000;
+}
+
+static void
+Opcode_saltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x620000;
+}
+
+static void
+Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc10000;
+}
+
+static void
+Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd10000;
+}
+
+static void
+Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x820000;
+}
+
+static void
+Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa20000;
+}
+
+static void
+Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb20000;
+}
+
+static void
+Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x740004;
+}
+
+static void
+Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x750004;
+}
+
+static void
+Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x760004;
+}
+
+static void
+Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x770004;
+}
+
+static void
+Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x700004;
+}
+
+static void
+Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x710004;
+}
+
+static void
+Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x720004;
+}
+
+static void
+Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x730004;
+}
+
+static void
+Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x340004;
+}
+
+static void
+Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x350004;
+}
+
+static void
+Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x360004;
+}
+
+static void
+Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x370004;
+}
+
+static void
+Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x640004;
+}
+
+static void
+Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x650004;
+}
+
+static void
+Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x660004;
+}
+
+static void
+Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x670004;
+}
+
+static void
+Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x240004;
+}
+
+static void
+Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x250004;
+}
+
+static void
+Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x260004;
+}
+
+static void
+Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x270004;
+}
+
+static void
+Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x780004;
+}
+
+static void
+Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x790004;
+}
+
+static void
+Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x7a0004;
+}
+
+static void
+Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x7b0004;
+}
+
+static void
+Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x7c0004;
+}
+
+static void
+Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x7d0004;
+}
+
+static void
+Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x7e0004;
+}
+
+static void
+Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x7f0004;
+}
+
+static void
+Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x380004;
+}
+
+static void
+Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x390004;
+}
+
+static void
+Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3a0004;
+}
+
+static void
+Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3b0004;
+}
+
+static void
+Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3c0004;
+}
+
+static void
+Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3d0004;
+}
+
+static void
+Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3e0004;
+}
+
+static void
+Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3f0004;
+}
+
+static void
+Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x680004;
+}
+
+static void
+Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x690004;
+}
+
+static void
+Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6a0004;
+}
+
+static void
+Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6b0004;
+}
+
+static void
+Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6c0004;
+}
+
+static void
+Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6d0004;
+}
+
+static void
+Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6e0004;
+}
+
+static void
+Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6f0004;
+}
+
+static void
+Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x280004;
+}
+
+static void
+Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x290004;
+}
+
+static void
+Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2a0004;
+}
+
+static void
+Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2b0004;
+}
+
+static void
+Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2c0004;
+}
+
+static void
+Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2d0004;
+}
+
+static void
+Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2e0004;
+}
+
+static void
+Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2f0004;
+}
+
+static void
+Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x580004;
+}
+
+static void
+Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x480004;
+}
+
+static void
+Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x590004;
+}
+
+static void
+Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x490004;
+}
+
+static void
+Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x5a0004;
+}
+
+static void
+Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x4a0004;
+}
+
+static void
+Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x5b0004;
+}
+
+static void
+Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x4b0004;
+}
+
+static void
+Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x180004;
+}
+
+static void
+Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x80004;
+}
+
+static void
+Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x190004;
+}
+
+static void
+Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x90004;
+}
+
+static void
+Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1a0004;
+}
+
+static void
+Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa0004;
+}
+
+static void
+Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1b0004;
+}
+
+static void
+Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb0004;
+}
+
+static void
+Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x900004;
+}
+
+static void
+Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x800004;
+}
+
+static void
+Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x32000;
+}
+
+static void
+Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x132000;
+}
+
+static void
+Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x612000;
+}
+
+static void
+Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x32100;
+}
+
+static void
+Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x132100;
+}
+
+static void
+Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x612100;
+}
+
+static void
+Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x32200;
+}
+
+static void
+Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x132200;
+}
+
+static void
+Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x612200;
+}
+
+static void
+Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x32300;
+}
+
+static void
+Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x132300;
+}
+
+static void
+Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x612300;
+}
+
+static void
+Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x31000;
+}
+
+static void
+Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x131000;
+}
+
+static void
+Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x611000;
+}
+
+static void
+Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x31100;
+}
+
+static void
+Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x131100;
+}
+
+static void
+Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x611100;
+}
+
+static void
+Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3010;
+}
+
+static void
+Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x7000;
+}
+
+static void
+Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3e200;
+}
+
+static void
+Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13e200;
+}
+
+static void
+Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13e300;
+}
+
+static void
+Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3e400;
+}
+
+static void
+Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13e400;
+}
+
+static void
+Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61e400;
+}
+
+static void
+Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x4000;
+}
+
+static void
+Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf02d;
+}
+
+static void
+Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x39000;
+}
+
+static void
+Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x139000;
+}
+
+static void
+Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x619000;
+}
+
+static void
+Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3a000;
+}
+
+static void
+Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13a000;
+}
+
+static void
+Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61a000;
+}
+
+static void
+Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x39100;
+}
+
+static void
+Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x139100;
+}
+
+static void
+Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x619100;
+}
+
+static void
+Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3a100;
+}
+
+static void
+Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13a100;
+}
+
+static void
+Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61a100;
+}
+
+static void
+Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x38000;
+}
+
+static void
+Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x138000;
+}
+
+static void
+Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x618000;
+}
+
+static void
+Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x38100;
+}
+
+static void
+Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x138100;
+}
+
+static void
+Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x618100;
+}
+
+static void
+Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x36000;
+}
+
+static void
+Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x136000;
+}
+
+static void
+Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x616000;
+}
+
+static void
+Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3e900;
+}
+
+static void
+Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13e900;
+}
+
+static void
+Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61e900;
+}
+
+static void
+Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3ec00;
+}
+
+static void
+Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13ec00;
+}
+
+static void
+Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61ec00;
+}
+
+static void
+Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3ed00;
+}
+
+static void
+Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13ed00;
+}
+
+static void
+Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61ed00;
+}
+
+static void
+Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x36800;
+}
+
+static void
+Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x136800;
+}
+
+static void
+Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x616800;
+}
+
+static void
+Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x70e0;
+}
+
+static void
+Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x70f0;
+}
+
+static void
+Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf1e000;
+}
+
+static void
+Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf1e010;
+}
+
+static void
+Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x135900;
+}
+
+static void
+Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x20000;
+}
+
+static void
+Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x120000;
+}
+
+static void
+Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x220000;
+}
+
+static void
+Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x320000;
+}
+
+static void
+Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x420000;
+}
+
+static void
+Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8000;
+}
+
+static void
+Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x9000;
+}
+
+static void
+Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa000;
+}
+
+static void
+Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb000;
+}
+
+static void
+Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x76;
+}
+
+static void
+Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1076;
+}
+
+static void
+Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc30000;
+}
+
+static void
+Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd30000;
+}
+
+static void
+Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x30400;
+}
+
+static void
+Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x130400;
+}
+
+static void
+Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x610400;
+}
+
+static void
+Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3ea00;
+}
+
+static void
+Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13ea00;
+}
+
+static void
+Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61ea00;
+}
+
+static void
+Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3f000;
+}
+
+static void
+Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13f000;
+}
+
+static void
+Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61f000;
+}
+
+static void
+Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3f100;
+}
+
+static void
+Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13f100;
+}
+
+static void
+Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61f100;
+}
+
+static void
+Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3f200;
+}
+
+static void
+Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13f200;
+}
+
+static void
+Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61f200;
+}
+
+static void
+Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x50c000;
+}
+
+static void
+Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x50d000;
+}
+
+static void
+Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x50b000;
+}
+
+static void
+Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x50f000;
+}
+
+static void
+Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x50e000;
+}
+
+static void
+Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x504000;
+}
+
+static void
+Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x505000;
+}
+
+static void
+Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x503000;
+}
+
+static void
+Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x507000;
+}
+
+static void
+Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x506000;
+}
+
+static void
+Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x3e000;
+}
+
+static void
+Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13e000;
+}
+
+static void
+Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x61e000;
+}
+
+static void
+Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x330000;
+}
+
+static void
+Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x430000;
+}
+
+static void
+Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x530000;
+}
+
+static void
+Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x630000;
+}
+
+static void
+Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x730000;
+}
+
+static void
+Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x40e000;
+}
+
+static void
+Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x40f000;
+}
+
+static void
+Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x230000;
+}
+
+static void
+Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xb002;
+}
+
+static void
+Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf002;
+}
+
+static void
+Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe002;
+}
+
+static void
+Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x30c00;
+}
+
+static void
+Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x130c00;
+}
+
+static void
+Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x610c00;
+}
+
+static void
+Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x36300;
+}
+
+static void
+Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x136300;
+}
+
+static void
+Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x616300;
+}
+
+static void
+Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc20000;
+}
+
+static void
+Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd20000;
+}
+
+static void
+Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe20000;
+}
+
+static void
+Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf20000;
+}
+
+static void
+Opcode_rsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x35f00;
+}
+
+static void
+Opcode_wsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x135f00;
+}
+
+static void
+Opcode_xsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x615f00;
+}
+
+static void
+Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x406000;
+}
+
+static void
+Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x407000;
+}
+
+static void
+Opcode_rur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe30e80;
+}
+
+static void
+Opcode_wur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf3e800;
+}
+
+static void
+Opcode_rur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe30e90;
+}
+
+static void
+Opcode_wur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf3e900;
+}
+
+static void
+Opcode_st_qr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd6004;
+}
+
+static void
+Opcode_ld_qr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd2004;
+}
+
+static void
+Opcode_mv_qr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8f0004;
+}
+
+static void
+Opcode_ee_wr_mask_gpio_out_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x724004;
+}
+
+static void
+Opcode_ee_set_bit_gpio_out_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x754004;
+}
+
+static void
+Opcode_ee_clr_bit_gpio_out_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x764004;
+}
+
+static void
+Opcode_ee_get_gpio_in_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x650804;
+}
+
+static void
+Opcode_ee_vld_128_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x830004;
+}
+
+static void
+Opcode_ee_vld_128_xp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8d2004;
+}
+
+static void
+Opcode_ee_vld_h_64_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x880004;
+}
+
+static void
+Opcode_ee_vld_h_64_xp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8d6004;
+}
+
+static void
+Opcode_ee_vld_l_64_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x890004;
+}
+
+static void
+Opcode_ee_vld_l_64_xp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8d3004;
+}
+
+static void
+Opcode_ee_vldbc_16_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x850004;
+}
+
+static void
+Opcode_ee_vldbc_16_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd7304;
+}
+
+static void
+Opcode_ee_vldbc_16_xp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8d4004;
+}
+
+static void
+Opcode_ee_vldbc_32_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x820004;
+}
+
+static void
+Opcode_ee_vldbc_32_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd7704;
+}
+
+static void
+Opcode_ee_vldbc_32_xp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8d1004;
+}
+
+static void
+Opcode_ee_vldbc_8_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc50004;
+}
+
+static void
+Opcode_ee_vldbc_8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd3b04;
+}
+
+static void
+Opcode_ee_vldbc_8_xp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8d5004;
+}
+
+static void
+Opcode_ee_vldhbc_16_incp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcc0204;
+}
+
+static void
+Opcode_ee_ldf_128_ip_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x10000000;
+}
+
+static void
+Opcode_ee_ldf_128_xp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x11000000;
+}
+
+static void
+Opcode_ee_ldf_64_ip_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c000040;
+}
+
+static void
+Opcode_ee_ldf_64_xp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x60000;
+}
+
+static void
+Opcode_ee_ld_128_usar_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x810004;
+}
+
+static void
+Opcode_ee_ld_128_usar_xp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8d0004;
+}
+
+static void
+Opcode_ee_ldqa_s16_128_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x10004;
+}
+
+static void
+Opcode_ee_ldqa_s16_128_xp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x7e4004;
+}
+
+static void
+Opcode_ee_ldqa_s8_128_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x110004;
+}
+
+static void
+Opcode_ee_ldqa_s8_128_xp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x714004;
+}
+
+static void
+Opcode_ee_ldqa_u16_128_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x50004;
+}
+
+static void
+Opcode_ee_ldqa_u16_128_xp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x7a4004;
+}
+
+static void
+Opcode_ee_ldqa_u8_128_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x150004;
+}
+
+static void
+Opcode_ee_ldqa_u8_128_xp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x704004;
+}
+
+static void
+Opcode_ee_ld_qacc_h_h_32_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1e0004;
+}
+
+static void
+Opcode_ee_ld_qacc_h_l_128_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x60004;
+}
+
+static void
+Opcode_ee_ld_qacc_l_h_32_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x160004;
+}
+
+static void
+Opcode_ee_ld_qacc_l_l_128_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x4;
+}
+
+static void
+Opcode_ee_ld_accx_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe0004;
+}
+
+static void
+Opcode_ee_ldxq_32_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c0007d0;
+}
+
+static void
+Opcode_ee_ld_ua_state_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x100004;
+}
+
+static void
+Opcode_ee_st_ua_state_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c0004;
+}
+
+static void
+Opcode_ee_vst_128_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8a0004;
+}
+
+static void
+Opcode_ee_vst_128_xp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8d7004;
+}
+
+static void
+Opcode_ee_vst_h_64_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8b0004;
+}
+
+static void
+Opcode_ee_vst_h_64_xp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd0004;
+}
+
+static void
+Opcode_ee_vst_l_64_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x840004;
+}
+
+static void
+Opcode_ee_vst_l_64_xp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd4004;
+}
+
+static void
+Opcode_ee_stf_128_ip_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x12000000;
+}
+
+static void
+Opcode_ee_stf_128_xp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x13000000;
+}
+
+static void
+Opcode_ee_stf_64_ip_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c000060;
+}
+
+static void
+Opcode_ee_stf_64_xp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x70000;
+}
+
+static void
+Opcode_ee_st_qacc_h_h_32_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x120004;
+}
+
+static void
+Opcode_ee_st_qacc_h_l_128_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xd0004;
+}
+
+static void
+Opcode_ee_st_qacc_l_h_32_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1d0004;
+}
+
+static void
+Opcode_ee_st_qacc_l_l_128_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc0004;
+}
+
+static void
+Opcode_ee_st_accx_ip_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x20004;
+}
+
+static void
+Opcode_ee_stxq_32_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1cc00000;
+}
+
+static void
+Opcode_ee_movi_32_a_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd7104;
+}
+
+static void
+Opcode_ee_movi_32_q_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd3204;
+}
+
+static void
+Opcode_ee_vzip_16_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcc03b4;
+}
+
+static void
+Opcode_ee_vzip_32_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcc03c4;
+}
+
+static void
+Opcode_ee_vzip_8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcc03d4;
+}
+
+static void
+Opcode_ee_vunzip_16_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcc0384;
+}
+
+static void
+Opcode_ee_vunzip_32_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcc0394;
+}
+
+static void
+Opcode_ee_vunzip_8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcc03a4;
+}
+
+static void
+Opcode_ee_zero_accx_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x250804;
+}
+
+static void
+Opcode_ee_zero_qacc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x250844;
+}
+
+static void
+Opcode_ee_zero_q_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd7fa4;
+}
+
+static void
+Opcode_ee_mov_s16_qacc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd7f24;
+}
+
+static void
+Opcode_ee_mov_s8_qacc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd7f34;
+}
+
+static void
+Opcode_ee_mov_u16_qacc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd7f64;
+}
+
+static void
+Opcode_ee_mov_u8_qacc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd7f74;
+}
+
+static void
+Opcode_ee_vadds_s16_ld_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c0002d0;
+}
+
+static void
+Opcode_ee_vadds_s16_st_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c900000;
+}
+
+static void
+Opcode_ee_vadds_s16_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e0064;
+}
+
+static void
+Opcode_ee_vadds_s32_ld_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c0003d0;
+}
+
+static void
+Opcode_ee_vadds_s32_st_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c900010;
+}
+
+static void
+Opcode_ee_vadds_s32_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e0074;
+}
+
+static void
+Opcode_ee_vadds_s8_ld_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c0001c0;
+}
+
+static void
+Opcode_ee_vadds_s8_st_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c900020;
+}
+
+static void
+Opcode_ee_vadds_s8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e0084;
+}
+
+static void
+Opcode_ee_vsubs_s16_ld_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c0004d0;
+}
+
+static void
+Opcode_ee_vsubs_s16_st_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1d100010;
+}
+
+static void
+Opcode_ee_vsubs_s16_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e20d4;
+}
+
+static void
+Opcode_ee_vsubs_s32_ld_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c0005d0;
+}
+
+static void
+Opcode_ee_vsubs_s32_st_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1d100020;
+}
+
+static void
+Opcode_ee_vsubs_s32_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e20e4;
+}
+
+static void
+Opcode_ee_vsubs_s8_ld_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c0006d0;
+}
+
+static void
+Opcode_ee_vsubs_s8_st_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1d100030;
+}
+
+static void
+Opcode_ee_vsubs_s8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e20f4;
+}
+
+static void
+Opcode_ee_vmul_s16_ld_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c0003f0;
+}
+
+static void
+Opcode_ee_vmul_s16_st_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1cb00020;
+}
+
+static void
+Opcode_ee_vmul_s16_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e2084;
+}
+
+static void
+Opcode_ee_vmul_s8_ld_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c0004c0;
+}
+
+static void
+Opcode_ee_vmul_s8_st_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1ca00030;
+}
+
+static void
+Opcode_ee_vmul_s8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e2094;
+}
+
+static void
+Opcode_ee_vmul_u16_ld_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c0005c0;
+}
+
+static void
+Opcode_ee_vmul_u16_st_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1cb00030;
+}
+
+static void
+Opcode_ee_vmul_u16_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e20a4;
+}
+
+static void
+Opcode_ee_vmul_u8_ld_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c0006c0;
+}
+
+static void
+Opcode_ee_vmul_u8_st_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1d100000;
+}
+
+static void
+Opcode_ee_vmul_u8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e20b4;
+}
+
+static void
+Opcode_ee_cmul_s16_ld_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c0000c0;
+}
+
+static void
+Opcode_ee_cmul_s16_st_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c800000;
+}
+
+static void
+Opcode_ee_cmul_s16_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e0004;
+}
+
+static void
+Opcode_ee_vmulas_s16_accx_ld_ip_qup_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0;
+}
+
+static void
+Opcode_ee_vmulas_s16_accx_ld_ip_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1e000000;
+}
+
+static void
+Opcode_ee_vmulas_s16_accx_ld_xp_qup_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x16000000;
+}
+
+static void
+Opcode_ee_vmulas_s16_accx_ld_xp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1e000100;
+}
+
+static void
+Opcode_ee_vmulas_s16_accx_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1a0084;
+}
+
+static void
+Opcode_ee_vmulas_s8_accx_ld_ip_qup_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x4000000;
+}
+
+static void
+Opcode_ee_vmulas_s8_accx_ld_ip_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1e040000;
+}
+
+static void
+Opcode_ee_vmulas_s8_accx_ld_xp_qup_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x17000000;
+}
+
+static void
+Opcode_ee_vmulas_s8_accx_ld_xp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1e040100;
+}
+
+static void
+Opcode_ee_vmulas_s8_accx_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1a00c4;
+}
+
+static void
+Opcode_ee_vmulas_u16_accx_ld_ip_qup_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8000000;
+}
+
+static void
+Opcode_ee_vmulas_u16_accx_ld_ip_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1e080000;
+}
+
+static void
+Opcode_ee_vmulas_u16_accx_ld_xp_qup_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x18000000;
+}
+
+static void
+Opcode_ee_vmulas_u16_accx_ld_xp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1e080100;
+}
+
+static void
+Opcode_ee_vmulas_u16_accx_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa0084;
+}
+
+static void
+Opcode_ee_vmulas_u8_accx_ld_ip_qup_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc000000;
+}
+
+static void
+Opcode_ee_vmulas_u8_accx_ld_ip_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1e0c0000;
+}
+
+static void
+Opcode_ee_vmulas_u8_accx_ld_xp_qup_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x19000000;
+}
+
+static void
+Opcode_ee_vmulas_u8_accx_ld_xp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1e0c0100;
+}
+
+static void
+Opcode_ee_vmulas_u8_accx_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa00c4;
+}
+
+static void
+Opcode_ee_vmulas_s16_qacc_ldbc_incp_qup_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c000080;
+}
+
+static void
+Opcode_ee_vmulas_s16_qacc_ldbc_incp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x870004;
+}
+
+static void
+Opcode_ee_vmulas_s16_qacc_ld_ip_qup_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x2000000;
+}
+
+static void
+Opcode_ee_vmulas_s16_qacc_ld_ip_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1e020000;
+}
+
+static void
+Opcode_ee_vmulas_s16_qacc_ld_xp_qup_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x16800000;
+}
+
+static void
+Opcode_ee_vmulas_s16_qacc_ld_xp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1e020100;
+}
+
+static void
+Opcode_ee_vmulas_s16_qacc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1a2084;
+}
+
+static void
+Opcode_ee_vmulas_s8_qacc_ldbc_incp_qup_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c000090;
+}
+
+static void
+Opcode_ee_vmulas_s8_qacc_ldbc_incp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa70004;
+}
+
+static void
+Opcode_ee_vmulas_s8_qacc_ld_ip_qup_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x6000000;
+}
+
+static void
+Opcode_ee_vmulas_s8_qacc_ld_ip_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1e060000;
+}
+
+static void
+Opcode_ee_vmulas_s8_qacc_ld_xp_qup_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x17800000;
+}
+
+static void
+Opcode_ee_vmulas_s8_qacc_ld_xp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1e060100;
+}
+
+static void
+Opcode_ee_vmulas_s8_qacc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1a20c4;
+}
+
+static void
+Opcode_ee_vmulas_u16_qacc_ldbc_incp_qup_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c0000a0;
+}
+
+static void
+Opcode_ee_vmulas_u16_qacc_ldbc_incp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc70004;
+}
+
+static void
+Opcode_ee_vmulas_u16_qacc_ld_ip_qup_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa000000;
+}
+
+static void
+Opcode_ee_vmulas_u16_qacc_ld_ip_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1e0a0000;
+}
+
+static void
+Opcode_ee_vmulas_u16_qacc_ld_xp_qup_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x18800000;
+}
+
+static void
+Opcode_ee_vmulas_u16_qacc_ld_xp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1e0a0100;
+}
+
+static void
+Opcode_ee_vmulas_u16_qacc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa2084;
+}
+
+static void
+Opcode_ee_vmulas_u8_qacc_ldbc_incp_qup_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c0000b0;
+}
+
+static void
+Opcode_ee_vmulas_u8_qacc_ldbc_incp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe70004;
+}
+
+static void
+Opcode_ee_vmulas_u8_qacc_ld_ip_qup_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe000000;
+}
+
+static void
+Opcode_ee_vmulas_u8_qacc_ld_ip_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1e0e0000;
+}
+
+static void
+Opcode_ee_vmulas_u8_qacc_ld_xp_qup_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x19800000;
+}
+
+static void
+Opcode_ee_vmulas_u8_qacc_ld_xp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1e0e0100;
+}
+
+static void
+Opcode_ee_vmulas_u8_qacc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xa20c4;
+}
+
+static void
+Opcode_ee_vsmulas_s16_qacc_ld_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c0007c0;
+}
+
+static void
+Opcode_ee_vsmulas_s16_qacc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e20c4;
+}
+
+static void
+Opcode_ee_vsmulas_s8_qacc_ld_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c0002c0;
+}
+
+static void
+Opcode_ee_vsmulas_s8_qacc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e0044;
+}
+
+static void
+Opcode_ee_srcmb_s16_qacc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd7204;
+}
+
+static void
+Opcode_ee_srcmb_s8_qacc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd7a04;
+}
+
+static void
+Opcode_ee_srs_accx_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x7e1004;
+}
+
+static void
+Opcode_ee_vrelu_s16_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd1004;
+}
+
+static void
+Opcode_ee_vrelu_s8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd5004;
+}
+
+static void
+Opcode_ee_vprelu_s16_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8c0004;
+}
+
+static void
+Opcode_ee_vprelu_s8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8c2004;
+}
+
+static void
+Opcode_ee_vmax_s16_ld_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c0001d0;
+}
+
+static void
+Opcode_ee_vmax_s16_st_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c900030;
+}
+
+static void
+Opcode_ee_vmax_s16_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e2024;
+}
+
+static void
+Opcode_ee_vmax_s32_ld_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c0001e0;
+}
+
+static void
+Opcode_ee_vmax_s32_st_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1ca00000;
+}
+
+static void
+Opcode_ee_vmax_s32_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e2034;
+}
+
+static void
+Opcode_ee_vmax_s8_ld_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c0001f0;
+}
+
+static void
+Opcode_ee_vmax_s8_st_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1cb00000;
+}
+
+static void
+Opcode_ee_vmax_s8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e2044;
+}
+
+static void
+Opcode_ee_vmin_s16_ld_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c0002e0;
+}
+
+static void
+Opcode_ee_vmin_s16_st_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1ca00010;
+}
+
+static void
+Opcode_ee_vmin_s16_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e2054;
+}
+
+static void
+Opcode_ee_vmin_s32_ld_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c0003e0;
+}
+
+static void
+Opcode_ee_vmin_s32_st_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1cb00010;
+}
+
+static void
+Opcode_ee_vmin_s32_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e2064;
+}
+
+static void
+Opcode_ee_vmin_s8_ld_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c0002f0;
+}
+
+static void
+Opcode_ee_vmin_s8_st_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1ca00020;
+}
+
+static void
+Opcode_ee_vmin_s8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e2074;
+}
+
+static void
+Opcode_ee_vcmp_eq_s16_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e0094;
+}
+
+static void
+Opcode_ee_vcmp_eq_s32_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e00a4;
+}
+
+static void
+Opcode_ee_vcmp_eq_s8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e00b4;
+}
+
+static void
+Opcode_ee_vcmp_gt_s16_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e00c4;
+}
+
+static void
+Opcode_ee_vcmp_gt_s32_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e00d4;
+}
+
+static void
+Opcode_ee_vcmp_gt_s8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e00e4;
+}
+
+static void
+Opcode_ee_vcmp_lt_s16_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e00f4;
+}
+
+static void
+Opcode_ee_vcmp_lt_s32_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e2004;
+}
+
+static void
+Opcode_ee_vcmp_lt_s8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x8e2014;
+}
+
+static void
+Opcode_ee_andq_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd3004;
+}
+
+static void
+Opcode_ee_notq_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd7f04;
+}
+
+static void
+Opcode_ee_orq_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd7004;
+}
+
+static void
+Opcode_ee_xorq_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd3104;
+}
+
+static void
+Opcode_ee_slci_2q_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcc0604;
+}
+
+static void
+Opcode_ee_slcxxp_2q_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x860004;
+}
+
+static void
+Opcode_ee_srci_2q_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcc0a04;
+}
+
+static void
+Opcode_ee_srcq_128_st_incp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcc0e04;
+}
+
+static void
+Opcode_ee_src_q_ld_ip_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1c000000;
+}
+
+static void
+Opcode_ee_src_q_ld_xp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1d000000;
+}
+
+static void
+Opcode_ee_src_q_qup_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcc0704;
+}
+
+static void
+Opcode_ee_src_q_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcc0304;
+}
+
+static void
+Opcode_ee_srcxxp_2q_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xc60004;
+}
+
+static void
+Opcode_ee_vsl_32_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd3f04;
+}
+
+static void
+Opcode_ee_vsr_32_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd3f84;
+}
+
+static void
+Opcode_ee_fft_r2bf_s16_st_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1d100040;
+}
+
+static void
+Opcode_ee_fft_r2bf_s16_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcc0004;
+}
+
+static void
+Opcode_ee_fft_cmul_s16_ld_xp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1b800000;
+}
+
+static void
+Opcode_ee_fft_cmul_s16_st_xp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x15000000;
+}
+
+static void
+Opcode_ee_bitrev_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd7b04;
+}
+
+static void
+Opcode_ee_fft_ams_s16_ld_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1a000000;
+}
+
+static void
+Opcode_ee_fft_ams_s16_ld_incp_uaup_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1a800000;
+}
+
+static void
+Opcode_ee_fft_ams_s16_ld_r32_decp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x1b000000;
+}
+
+static void
+Opcode_ee_fft_ams_s16_st_incp_Slot_slot_format_32_0_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x14000000;
+}
+
+static void
+Opcode_ee_fft_vst_r32_decp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xcd3304;
+}
+
+static void
+Opcode_rur_accx_0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe30000;
+}
+
+static void
+Opcode_wur_accx_0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf30000;
+}
+
+static void
+Opcode_rur_accx_1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe30010;
+}
+
+static void
+Opcode_wur_accx_1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf30100;
+}
+
+static void
+Opcode_rur_qacc_h_0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe30020;
+}
+
+static void
+Opcode_wur_qacc_h_0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf30200;
+}
+
+static void
+Opcode_rur_qacc_h_1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe30030;
+}
+
+static void
+Opcode_wur_qacc_h_1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf30300;
+}
+
+static void
+Opcode_rur_qacc_h_2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe30040;
+}
+
+static void
+Opcode_wur_qacc_h_2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf30400;
+}
+
+static void
+Opcode_rur_qacc_h_3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe30050;
+}
+
+static void
+Opcode_wur_qacc_h_3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf30500;
+}
+
+static void
+Opcode_rur_qacc_h_4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe30060;
+}
+
+static void
+Opcode_wur_qacc_h_4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf30600;
+}
+
+static void
+Opcode_rur_qacc_l_0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe30070;
+}
+
+static void
+Opcode_wur_qacc_l_0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf30700;
+}
+
+static void
+Opcode_rur_qacc_l_1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe30080;
+}
+
+static void
+Opcode_wur_qacc_l_1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf30800;
+}
+
+static void
+Opcode_rur_qacc_l_2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe30090;
+}
+
+static void
+Opcode_wur_qacc_l_2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf30900;
+}
+
+static void
+Opcode_rur_qacc_l_3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe300a0;
+}
+
+static void
+Opcode_wur_qacc_l_3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf30a00;
+}
+
+static void
+Opcode_rur_qacc_l_4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe300b0;
+}
+
+static void
+Opcode_wur_qacc_l_4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf30b00;
+}
+
+static void
+Opcode_rur_gpio_out_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe300c0;
+}
+
+static void
+Opcode_wur_gpio_out_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf30c00;
+}
+
+static void
+Opcode_rur_sar_byte_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe300d0;
+}
+
+static void
+Opcode_wur_sar_byte_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf30d00;
+}
+
+static void
+Opcode_rur_fft_bit_width_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe300e0;
+}
+
+static void
+Opcode_wur_fft_bit_width_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf30e00;
+}
+
+static void
+Opcode_rur_ua_state_0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe300f0;
+}
+
+static void
+Opcode_wur_ua_state_0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf30f00;
+}
+
+static void
+Opcode_rur_ua_state_1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe30100;
+}
+
+static void
+Opcode_wur_ua_state_1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf31000;
+}
+
+static void
+Opcode_rur_ua_state_2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe30110;
+}
+
+static void
+Opcode_wur_ua_state_2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf31100;
+}
+
+static void
+Opcode_rur_ua_state_3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xe30120;
+}
+
+static void
+Opcode_wur_ua_state_3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0xf31200;
+}
+
+static const xtensa_opcode_encode_fn Opcode_lsi_encode_fns[] = {
+  Opcode_lsi_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_lsip_encode_fns[] = {
+  Opcode_lsip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_lsx_encode_fns[] = {
+  Opcode_lsx_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_lsxp_encode_fns[] = {
+  Opcode_lsxp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ssi_encode_fns[] = {
+  Opcode_ssi_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ssip_encode_fns[] = {
+  Opcode_ssip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ssx_encode_fns[] = {
+  Opcode_ssx_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ssxp_encode_fns[] = {
+  Opcode_ssxp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_abs_s_encode_fns[] = {
+  Opcode_abs_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_neg_s_encode_fns[] = {
+  Opcode_neg_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mov_s_encode_fns[] = {
+  Opcode_mov_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_moveqz_s_encode_fns[] = {
+  Opcode_moveqz_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movnez_s_encode_fns[] = {
+  Opcode_movnez_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movltz_s_encode_fns[] = {
+  Opcode_movltz_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movgez_s_encode_fns[] = {
+  Opcode_movgez_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movf_s_encode_fns[] = {
+  Opcode_movf_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movt_s_encode_fns[] = {
+  Opcode_movt_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wfr_encode_fns[] = {
+  Opcode_wfr_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rfr_encode_fns[] = {
+  Opcode_rfr_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_round_s_encode_fns[] = {
+  Opcode_round_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ceil_s_encode_fns[] = {
+  Opcode_ceil_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_floor_s_encode_fns[] = {
+  Opcode_floor_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_trunc_s_encode_fns[] = {
+  Opcode_trunc_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_utrunc_s_encode_fns[] = {
+  Opcode_utrunc_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_float_s_encode_fns[] = {
+  Opcode_float_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ufloat_s_encode_fns[] = {
+  Opcode_ufloat_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_un_s_encode_fns[] = {
+  Opcode_un_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ult_s_encode_fns[] = {
+  Opcode_ult_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ule_s_encode_fns[] = {
+  Opcode_ule_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ueq_s_encode_fns[] = {
+  Opcode_ueq_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_olt_s_encode_fns[] = {
+  Opcode_olt_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ole_s_encode_fns[] = {
+  Opcode_ole_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_oeq_s_encode_fns[] = {
+  Opcode_oeq_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_add_s_encode_fns[] = {
+  Opcode_add_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_sub_s_encode_fns[] = {
+  Opcode_sub_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_s_encode_fns[] = {
+  Opcode_mul_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_madd_s_encode_fns[] = {
+  Opcode_madd_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_msub_s_encode_fns[] = {
+  Opcode_msub_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_sqrt0_s_encode_fns[] = {
+  Opcode_sqrt0_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_div0_s_encode_fns[] = {
+  Opcode_div0_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_recip0_s_encode_fns[] = {
+  Opcode_recip0_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsqrt0_s_encode_fns[] = {
+  Opcode_rsqrt0_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_maddn_s_encode_fns[] = {
+  Opcode_maddn_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_divn_s_encode_fns[] = {
+  Opcode_divn_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_const_s_encode_fns[] = {
+  Opcode_const_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_nexp01_s_encode_fns[] = {
+  Opcode_nexp01_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_addexp_s_encode_fns[] = {
+  Opcode_addexp_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_addexpm_s_encode_fns[] = {
+  Opcode_addexpm_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mkdadj_s_encode_fns[] = {
+  Opcode_mkdadj_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mksadj_s_encode_fns[] = {
+  Opcode_mksadj_s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
+  Opcode_excw_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
+  Opcode_rfe_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
+  Opcode_rfde_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
+  Opcode_syscall_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
+  Opcode_call12_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
+  Opcode_call8_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
+  Opcode_call4_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
+  Opcode_callx12_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
+  Opcode_callx8_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
+  Opcode_callx4_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
+  Opcode_entry_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
+  Opcode_movsp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
+  Opcode_rotw_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
+  Opcode_retw_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
+  0, 0, Opcode_retw_n_Slot_inst16b_encode, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
+  Opcode_rfwo_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
+  Opcode_rfwu_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
+  Opcode_l32e_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
+  Opcode_s32e_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
+  Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
+  Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
+  Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
+  Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
+  Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
+  Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
+  0, Opcode_add_n_Slot_inst16a_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
+  0, Opcode_addi_n_Slot_inst16a_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
+  0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
+  0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
+  0, 0, Opcode_ill_n_Slot_inst16b_encode, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
+  0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
+  0, 0, Opcode_mov_n_Slot_inst16b_encode, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
+  0, 0, Opcode_movi_n_Slot_inst16b_encode, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
+  0, 0, Opcode_nop_n_Slot_inst16b_encode, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
+  0, 0, Opcode_ret_n_Slot_inst16b_encode, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
+  0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
+  Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
+  Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
+  Opcode_addi_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
+  Opcode_addmi_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
+  Opcode_add_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
+  Opcode_sub_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
+  Opcode_addx2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
+  Opcode_addx4_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
+  Opcode_addx8_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
+  Opcode_subx2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
+  Opcode_subx4_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
+  Opcode_subx8_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
+  Opcode_and_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
+  Opcode_or_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
+  Opcode_xor_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
+  Opcode_beqi_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
+  Opcode_bnei_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
+  Opcode_bgei_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
+  Opcode_blti_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
+  Opcode_bbci_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
+  Opcode_bbsi_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
+  Opcode_bgeui_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
+  Opcode_bltui_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
+  Opcode_beq_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
+  Opcode_bne_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
+  Opcode_bge_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
+  Opcode_blt_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
+  Opcode_bgeu_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
+  Opcode_bltu_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
+  Opcode_bany_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
+  Opcode_bnone_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
+  Opcode_ball_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
+  Opcode_bnall_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
+  Opcode_bbc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
+  Opcode_bbs_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
+  Opcode_beqz_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
+  Opcode_bnez_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
+  Opcode_bgez_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
+  Opcode_bltz_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
+  Opcode_call0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
+  Opcode_callx0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
+  Opcode_extui_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
+  Opcode_ill_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
+  Opcode_j_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
+  Opcode_jx_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
+  Opcode_l16ui_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
+  Opcode_l16si_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
+  Opcode_l32i_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
+  Opcode_l32r_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
+  Opcode_l8ui_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
+  Opcode_loop_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
+  Opcode_loopnez_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
+  Opcode_loopgtz_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
+  Opcode_movi_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
+  Opcode_moveqz_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
+  Opcode_movnez_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
+  Opcode_movltz_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
+  Opcode_movgez_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
+  Opcode_neg_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
+  Opcode_abs_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
+  Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
+  Opcode_ret_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
+  Opcode_simcall_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
+  Opcode_s16i_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
+  Opcode_s32i_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = {
+  Opcode_s32nb_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
+  Opcode_s8i_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
+  Opcode_ssr_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
+  Opcode_ssl_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
+  Opcode_ssa8l_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
+  Opcode_ssa8b_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
+  Opcode_ssai_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
+  Opcode_sll_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
+  Opcode_src_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
+  Opcode_srl_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
+  Opcode_sra_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
+  Opcode_slli_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
+  Opcode_srai_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
+  Opcode_srli_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
+  Opcode_memw_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
+  Opcode_extw_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
+  Opcode_isync_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
+  Opcode_rsync_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
+  Opcode_esync_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
+  Opcode_dsync_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
+  Opcode_rsil_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
+  Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
+  Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
+  Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
+  Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
+  Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
+  Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
+  Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
+  Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
+  Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
+  Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
+  Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
+  Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = {
+  Opcode_rsr_memctl_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = {
+  Opcode_wsr_memctl_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = {
+  Opcode_xsr_memctl_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
+  Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
+  Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
+  Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = {
+  Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = {
+  Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = {
+  Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
+  Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
+  Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
+  Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
+  Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
+  Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
+  Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
+  Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
+  Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
+  Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
+  Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
+  Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
+  Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
+  Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
+  Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
+  Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
+  Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
+  Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
+  Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
+  Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
+  Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
+  Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
+  Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
+  Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
+  Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
+  Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
+  Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
+  Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
+  Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
+  Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
+  Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
+  Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
+  Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
+  Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
+  Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
+  Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
+  Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
+  Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
+  Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
+  Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
+  Opcode_rsr_epc7_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
+  Opcode_wsr_epc7_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
+  Opcode_xsr_epc7_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
+  Opcode_rsr_excsave7_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
+  Opcode_wsr_excsave7_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
+  Opcode_xsr_excsave7_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
+  Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
+  Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
+  Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
+  Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
+  Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
+  Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
+  Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
+  Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
+  Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
+  Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
+  Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
+  Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
+  Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
+  Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
+  Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
+  Opcode_rsr_eps7_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
+  Opcode_wsr_eps7_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
+  Opcode_xsr_eps7_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
+  Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
+  Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
+  Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
+  Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
+  Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
+  Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
+  Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
+  Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
+  Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
+  Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
+  Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
+  Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
+  Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
+  Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
+  Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_misc2_encode_fns[] = {
+  Opcode_rsr_misc2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_misc2_encode_fns[] = {
+  Opcode_wsr_misc2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_misc2_encode_fns[] = {
+  Opcode_xsr_misc2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_misc3_encode_fns[] = {
+  Opcode_rsr_misc3_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_misc3_encode_fns[] = {
+  Opcode_wsr_misc3_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_misc3_encode_fns[] = {
+  Opcode_xsr_misc3_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
+  Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
+  Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
+  Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
+  Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_salt_encode_fns[] = {
+  Opcode_salt_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_saltu_encode_fns[] = {
+  Opcode_saltu_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
+  Opcode_mul16u_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
+  Opcode_mul16s_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
+  Opcode_mull_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = {
+  Opcode_muluh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = {
+  Opcode_mulsh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
+  Opcode_mul_aa_ll_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
+  Opcode_mul_aa_hl_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
+  Opcode_mul_aa_lh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
+  Opcode_mul_aa_hh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
+  Opcode_umul_aa_ll_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
+  Opcode_umul_aa_hl_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
+  Opcode_umul_aa_lh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
+  Opcode_umul_aa_hh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
+  Opcode_mul_ad_ll_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
+  Opcode_mul_ad_hl_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
+  Opcode_mul_ad_lh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
+  Opcode_mul_ad_hh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
+  Opcode_mul_da_ll_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
+  Opcode_mul_da_hl_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
+  Opcode_mul_da_lh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
+  Opcode_mul_da_hh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
+  Opcode_mul_dd_ll_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
+  Opcode_mul_dd_hl_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
+  Opcode_mul_dd_lh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
+  Opcode_mul_dd_hh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
+  Opcode_mula_aa_ll_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
+  Opcode_mula_aa_hl_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
+  Opcode_mula_aa_lh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
+  Opcode_mula_aa_hh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
+  Opcode_muls_aa_ll_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
+  Opcode_muls_aa_hl_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
+  Opcode_muls_aa_lh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
+  Opcode_muls_aa_hh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
+  Opcode_mula_ad_ll_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
+  Opcode_mula_ad_hl_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
+  Opcode_mula_ad_lh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
+  Opcode_mula_ad_hh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
+  Opcode_muls_ad_ll_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
+  Opcode_muls_ad_hl_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
+  Opcode_muls_ad_lh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
+  Opcode_muls_ad_hh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
+  Opcode_mula_da_ll_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
+  Opcode_mula_da_hl_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
+  Opcode_mula_da_lh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
+  Opcode_mula_da_hh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
+  Opcode_muls_da_ll_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
+  Opcode_muls_da_hl_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
+  Opcode_muls_da_lh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
+  Opcode_muls_da_hh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
+  Opcode_mula_dd_ll_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
+  Opcode_mula_dd_hl_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
+  Opcode_mula_dd_lh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
+  Opcode_mula_dd_hh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
+  Opcode_muls_dd_ll_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
+  Opcode_muls_dd_hl_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
+  Opcode_muls_dd_lh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
+  Opcode_muls_dd_hh_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
+  Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
+  Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
+  Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
+  Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
+  Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
+  Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
+  Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
+  Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
+  Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
+  Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
+  Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
+  Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
+  Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
+  Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
+  Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
+  Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
+  Opcode_lddec_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
+  Opcode_ldinc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
+  Opcode_rsr_m0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
+  Opcode_wsr_m0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
+  Opcode_xsr_m0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
+  Opcode_rsr_m1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
+  Opcode_wsr_m1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
+  Opcode_xsr_m1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
+  Opcode_rsr_m2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
+  Opcode_wsr_m2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
+  Opcode_xsr_m2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
+  Opcode_rsr_m3_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
+  Opcode_wsr_m3_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
+  Opcode_xsr_m3_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
+  Opcode_rsr_acclo_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
+  Opcode_wsr_acclo_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
+  Opcode_xsr_acclo_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
+  Opcode_rsr_acchi_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
+  Opcode_wsr_acchi_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
+  Opcode_xsr_acchi_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
+  Opcode_rfi_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
+  Opcode_waiti_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
+  Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
+  Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
+  Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
+  Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
+  Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
+  Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
+  Opcode_break_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
+  0, 0, Opcode_break_n_Slot_inst16b_encode, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
+  Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
+  Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
+  Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
+  Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
+  Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
+  Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
+  Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
+  Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
+  Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
+  Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
+  Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
+  Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
+  Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
+  Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
+  Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
+  Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
+  Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
+  Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
+  Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
+  Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
+  Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
+  Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
+  Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
+  Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
+  Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
+  Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
+  Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
+  Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
+  Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
+  Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
+  Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
+  Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
+  Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = {
+  Opcode_lddr32_p_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = {
+  Opcode_sddr32_p_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
+  Opcode_rfdo_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
+  Opcode_rfdd_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
+  Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = {
+  Opcode_andb_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = {
+  Opcode_andbc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = {
+  Opcode_orb_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = {
+  Opcode_orbc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = {
+  Opcode_xorb_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = {
+  Opcode_any4_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = {
+  Opcode_all4_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = {
+  Opcode_any8_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = {
+  Opcode_all8_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = {
+  Opcode_bf_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = {
+  Opcode_bt_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = {
+  Opcode_movf_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = {
+  Opcode_movt_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = {
+  Opcode_rsr_br_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = {
+  Opcode_wsr_br_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = {
+  Opcode_xsr_br_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
+  Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
+  Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
+  Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
+  Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
+  Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
+  Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
+  Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
+  Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
+  Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
+  Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
+  Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
+  Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
+  Opcode_idtlb_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
+  Opcode_pdtlb_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
+  Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
+  Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
+  Opcode_wdtlb_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
+  Opcode_iitlb_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
+  Opcode_pitlb_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
+  Opcode_ritlb0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
+  Opcode_ritlb1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
+  Opcode_witlb_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
+  Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
+  Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
+  Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
+  Opcode_clamps_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
+  Opcode_min_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
+  Opcode_max_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
+  Opcode_minu_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
+  Opcode_maxu_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
+  Opcode_nsa_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
+  Opcode_nsau_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
+  Opcode_sext_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
+  Opcode_l32ai_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
+  Opcode_s32ri_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
+  Opcode_s32c1i_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
+  Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
+  Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
+  Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = {
+  Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = {
+  Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = {
+  Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
+  Opcode_quou_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
+  Opcode_quos_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
+  Opcode_remu_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
+  Opcode_rems_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rsr_eraccess_encode_fns[] = {
+  Opcode_rsr_eraccess_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wsr_eraccess_encode_fns[] = {
+  Opcode_wsr_eraccess_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_xsr_eraccess_encode_fns[] = {
+  Opcode_xsr_eraccess_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = {
+  Opcode_rer_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = {
+  Opcode_wer_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_fcr_encode_fns[] = {
+  Opcode_rur_fcr_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_fcr_encode_fns[] = {
+  Opcode_wur_fcr_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_fsr_encode_fns[] = {
+  Opcode_rur_fsr_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_fsr_encode_fns[] = {
+  Opcode_wur_fsr_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_st_qr_encode_fns[] = {
+  Opcode_st_qr_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ld_qr_encode_fns[] = {
+  Opcode_ld_qr_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_mv_qr_encode_fns[] = {
+  Opcode_mv_qr_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_wr_mask_gpio_out_encode_fns[] = {
+  Opcode_ee_wr_mask_gpio_out_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_set_bit_gpio_out_encode_fns[] = {
+  Opcode_ee_set_bit_gpio_out_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_clr_bit_gpio_out_encode_fns[] = {
+  Opcode_ee_clr_bit_gpio_out_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_get_gpio_in_encode_fns[] = {
+  Opcode_ee_get_gpio_in_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vld_128_ip_encode_fns[] = {
+  Opcode_ee_vld_128_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vld_128_xp_encode_fns[] = {
+  Opcode_ee_vld_128_xp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vld_h_64_ip_encode_fns[] = {
+  Opcode_ee_vld_h_64_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vld_h_64_xp_encode_fns[] = {
+  Opcode_ee_vld_h_64_xp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vld_l_64_ip_encode_fns[] = {
+  Opcode_ee_vld_l_64_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vld_l_64_xp_encode_fns[] = {
+  Opcode_ee_vld_l_64_xp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vldbc_16_ip_encode_fns[] = {
+  Opcode_ee_vldbc_16_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vldbc_16_encode_fns[] = {
+  Opcode_ee_vldbc_16_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vldbc_16_xp_encode_fns[] = {
+  Opcode_ee_vldbc_16_xp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vldbc_32_ip_encode_fns[] = {
+  Opcode_ee_vldbc_32_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vldbc_32_encode_fns[] = {
+  Opcode_ee_vldbc_32_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vldbc_32_xp_encode_fns[] = {
+  Opcode_ee_vldbc_32_xp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vldbc_8_ip_encode_fns[] = {
+  Opcode_ee_vldbc_8_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vldbc_8_encode_fns[] = {
+  Opcode_ee_vldbc_8_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vldbc_8_xp_encode_fns[] = {
+  Opcode_ee_vldbc_8_xp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vldhbc_16_incp_encode_fns[] = {
+  Opcode_ee_vldhbc_16_incp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_ldf_128_ip_encode_fns[] = {
+  0, 0, 0, Opcode_ee_ldf_128_ip_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_ldf_128_xp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_ldf_128_xp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_ldf_64_ip_encode_fns[] = {
+  0, 0, 0, Opcode_ee_ldf_64_ip_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_ldf_64_xp_encode_fns[] = {
+  Opcode_ee_ldf_64_xp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_ld_128_usar_ip_encode_fns[] = {
+  Opcode_ee_ld_128_usar_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_ld_128_usar_xp_encode_fns[] = {
+  Opcode_ee_ld_128_usar_xp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_ldqa_s16_128_ip_encode_fns[] = {
+  Opcode_ee_ldqa_s16_128_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_ldqa_s16_128_xp_encode_fns[] = {
+  Opcode_ee_ldqa_s16_128_xp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_ldqa_s8_128_ip_encode_fns[] = {
+  Opcode_ee_ldqa_s8_128_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_ldqa_s8_128_xp_encode_fns[] = {
+  Opcode_ee_ldqa_s8_128_xp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_ldqa_u16_128_ip_encode_fns[] = {
+  Opcode_ee_ldqa_u16_128_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_ldqa_u16_128_xp_encode_fns[] = {
+  Opcode_ee_ldqa_u16_128_xp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_ldqa_u8_128_ip_encode_fns[] = {
+  Opcode_ee_ldqa_u8_128_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_ldqa_u8_128_xp_encode_fns[] = {
+  Opcode_ee_ldqa_u8_128_xp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_ld_qacc_h_h_32_ip_encode_fns[] = {
+  Opcode_ee_ld_qacc_h_h_32_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_ld_qacc_h_l_128_ip_encode_fns[] = {
+  Opcode_ee_ld_qacc_h_l_128_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_ld_qacc_l_h_32_ip_encode_fns[] = {
+  Opcode_ee_ld_qacc_l_h_32_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_ld_qacc_l_l_128_ip_encode_fns[] = {
+  Opcode_ee_ld_qacc_l_l_128_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_ld_accx_ip_encode_fns[] = {
+  Opcode_ee_ld_accx_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_ldxq_32_encode_fns[] = {
+  0, 0, 0, Opcode_ee_ldxq_32_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_ld_ua_state_ip_encode_fns[] = {
+  Opcode_ee_ld_ua_state_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_st_ua_state_ip_encode_fns[] = {
+  Opcode_ee_st_ua_state_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vst_128_ip_encode_fns[] = {
+  Opcode_ee_vst_128_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vst_128_xp_encode_fns[] = {
+  Opcode_ee_vst_128_xp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vst_h_64_ip_encode_fns[] = {
+  Opcode_ee_vst_h_64_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vst_h_64_xp_encode_fns[] = {
+  Opcode_ee_vst_h_64_xp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vst_l_64_ip_encode_fns[] = {
+  Opcode_ee_vst_l_64_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vst_l_64_xp_encode_fns[] = {
+  Opcode_ee_vst_l_64_xp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_stf_128_ip_encode_fns[] = {
+  0, 0, 0, Opcode_ee_stf_128_ip_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_stf_128_xp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_stf_128_xp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_stf_64_ip_encode_fns[] = {
+  0, 0, 0, Opcode_ee_stf_64_ip_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_stf_64_xp_encode_fns[] = {
+  Opcode_ee_stf_64_xp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_st_qacc_h_h_32_ip_encode_fns[] = {
+  Opcode_ee_st_qacc_h_h_32_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_st_qacc_h_l_128_ip_encode_fns[] = {
+  Opcode_ee_st_qacc_h_l_128_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_st_qacc_l_h_32_ip_encode_fns[] = {
+  Opcode_ee_st_qacc_l_h_32_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_st_qacc_l_l_128_ip_encode_fns[] = {
+  Opcode_ee_st_qacc_l_l_128_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_st_accx_ip_encode_fns[] = {
+  Opcode_ee_st_accx_ip_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_stxq_32_encode_fns[] = {
+  0, 0, 0, Opcode_ee_stxq_32_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_movi_32_a_encode_fns[] = {
+  Opcode_ee_movi_32_a_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_movi_32_q_encode_fns[] = {
+  Opcode_ee_movi_32_q_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vzip_16_encode_fns[] = {
+  Opcode_ee_vzip_16_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vzip_32_encode_fns[] = {
+  Opcode_ee_vzip_32_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vzip_8_encode_fns[] = {
+  Opcode_ee_vzip_8_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vunzip_16_encode_fns[] = {
+  Opcode_ee_vunzip_16_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vunzip_32_encode_fns[] = {
+  Opcode_ee_vunzip_32_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vunzip_8_encode_fns[] = {
+  Opcode_ee_vunzip_8_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_zero_accx_encode_fns[] = {
+  Opcode_ee_zero_accx_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_zero_qacc_encode_fns[] = {
+  Opcode_ee_zero_qacc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_zero_q_encode_fns[] = {
+  Opcode_ee_zero_q_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_mov_s16_qacc_encode_fns[] = {
+  Opcode_ee_mov_s16_qacc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_mov_s8_qacc_encode_fns[] = {
+  Opcode_ee_mov_s8_qacc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_mov_u16_qacc_encode_fns[] = {
+  Opcode_ee_mov_u16_qacc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_mov_u8_qacc_encode_fns[] = {
+  Opcode_ee_mov_u8_qacc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vadds_s16_ld_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vadds_s16_ld_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vadds_s16_st_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vadds_s16_st_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vadds_s16_encode_fns[] = {
+  Opcode_ee_vadds_s16_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vadds_s32_ld_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vadds_s32_ld_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vadds_s32_st_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vadds_s32_st_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vadds_s32_encode_fns[] = {
+  Opcode_ee_vadds_s32_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vadds_s8_ld_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vadds_s8_ld_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vadds_s8_st_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vadds_s8_st_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vadds_s8_encode_fns[] = {
+  Opcode_ee_vadds_s8_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vsubs_s16_ld_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vsubs_s16_ld_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vsubs_s16_st_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vsubs_s16_st_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vsubs_s16_encode_fns[] = {
+  Opcode_ee_vsubs_s16_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vsubs_s32_ld_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vsubs_s32_ld_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vsubs_s32_st_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vsubs_s32_st_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vsubs_s32_encode_fns[] = {
+  Opcode_ee_vsubs_s32_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vsubs_s8_ld_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vsubs_s8_ld_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vsubs_s8_st_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vsubs_s8_st_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vsubs_s8_encode_fns[] = {
+  Opcode_ee_vsubs_s8_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmul_s16_ld_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmul_s16_ld_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmul_s16_st_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmul_s16_st_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmul_s16_encode_fns[] = {
+  Opcode_ee_vmul_s16_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmul_s8_ld_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmul_s8_ld_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmul_s8_st_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmul_s8_st_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmul_s8_encode_fns[] = {
+  Opcode_ee_vmul_s8_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmul_u16_ld_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmul_u16_ld_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmul_u16_st_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmul_u16_st_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmul_u16_encode_fns[] = {
+  Opcode_ee_vmul_u16_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmul_u8_ld_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmul_u8_ld_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmul_u8_st_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmul_u8_st_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmul_u8_encode_fns[] = {
+  Opcode_ee_vmul_u8_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_cmul_s16_ld_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_cmul_s16_ld_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_cmul_s16_st_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_cmul_s16_st_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_cmul_s16_encode_fns[] = {
+  Opcode_ee_cmul_s16_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_s16_accx_ld_ip_qup_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_s16_accx_ld_ip_qup_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_s16_accx_ld_ip_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_s16_accx_ld_ip_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_s16_accx_ld_xp_qup_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_s16_accx_ld_xp_qup_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_s16_accx_ld_xp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_s16_accx_ld_xp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_s16_accx_encode_fns[] = {
+  Opcode_ee_vmulas_s16_accx_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_s8_accx_ld_ip_qup_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_s8_accx_ld_ip_qup_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_s8_accx_ld_ip_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_s8_accx_ld_ip_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_s8_accx_ld_xp_qup_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_s8_accx_ld_xp_qup_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_s8_accx_ld_xp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_s8_accx_ld_xp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_s8_accx_encode_fns[] = {
+  Opcode_ee_vmulas_s8_accx_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_u16_accx_ld_ip_qup_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_u16_accx_ld_ip_qup_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_u16_accx_ld_ip_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_u16_accx_ld_ip_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_u16_accx_ld_xp_qup_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_u16_accx_ld_xp_qup_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_u16_accx_ld_xp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_u16_accx_ld_xp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_u16_accx_encode_fns[] = {
+  Opcode_ee_vmulas_u16_accx_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_u8_accx_ld_ip_qup_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_u8_accx_ld_ip_qup_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_u8_accx_ld_ip_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_u8_accx_ld_ip_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_u8_accx_ld_xp_qup_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_u8_accx_ld_xp_qup_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_u8_accx_ld_xp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_u8_accx_ld_xp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_u8_accx_encode_fns[] = {
+  Opcode_ee_vmulas_u8_accx_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_s16_qacc_ldbc_incp_qup_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_s16_qacc_ldbc_incp_qup_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_s16_qacc_ldbc_incp_encode_fns[] = {
+  Opcode_ee_vmulas_s16_qacc_ldbc_incp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_s16_qacc_ld_ip_qup_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_s16_qacc_ld_ip_qup_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_s16_qacc_ld_ip_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_s16_qacc_ld_ip_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_s16_qacc_ld_xp_qup_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_s16_qacc_ld_xp_qup_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_s16_qacc_ld_xp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_s16_qacc_ld_xp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_s16_qacc_encode_fns[] = {
+  Opcode_ee_vmulas_s16_qacc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_s8_qacc_ldbc_incp_qup_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_s8_qacc_ldbc_incp_qup_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_s8_qacc_ldbc_incp_encode_fns[] = {
+  Opcode_ee_vmulas_s8_qacc_ldbc_incp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_s8_qacc_ld_ip_qup_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_s8_qacc_ld_ip_qup_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_s8_qacc_ld_ip_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_s8_qacc_ld_ip_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_s8_qacc_ld_xp_qup_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_s8_qacc_ld_xp_qup_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_s8_qacc_ld_xp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_s8_qacc_ld_xp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_s8_qacc_encode_fns[] = {
+  Opcode_ee_vmulas_s8_qacc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_u16_qacc_ldbc_incp_qup_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_u16_qacc_ldbc_incp_qup_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_u16_qacc_ldbc_incp_encode_fns[] = {
+  Opcode_ee_vmulas_u16_qacc_ldbc_incp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_u16_qacc_ld_ip_qup_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_u16_qacc_ld_ip_qup_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_u16_qacc_ld_ip_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_u16_qacc_ld_ip_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_u16_qacc_ld_xp_qup_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_u16_qacc_ld_xp_qup_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_u16_qacc_ld_xp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_u16_qacc_ld_xp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_u16_qacc_encode_fns[] = {
+  Opcode_ee_vmulas_u16_qacc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_u8_qacc_ldbc_incp_qup_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_u8_qacc_ldbc_incp_qup_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_u8_qacc_ldbc_incp_encode_fns[] = {
+  Opcode_ee_vmulas_u8_qacc_ldbc_incp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_u8_qacc_ld_ip_qup_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_u8_qacc_ld_ip_qup_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_u8_qacc_ld_ip_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_u8_qacc_ld_ip_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_u8_qacc_ld_xp_qup_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_u8_qacc_ld_xp_qup_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_u8_qacc_ld_xp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmulas_u8_qacc_ld_xp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmulas_u8_qacc_encode_fns[] = {
+  Opcode_ee_vmulas_u8_qacc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vsmulas_s16_qacc_ld_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vsmulas_s16_qacc_ld_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vsmulas_s16_qacc_encode_fns[] = {
+  Opcode_ee_vsmulas_s16_qacc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vsmulas_s8_qacc_ld_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vsmulas_s8_qacc_ld_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vsmulas_s8_qacc_encode_fns[] = {
+  Opcode_ee_vsmulas_s8_qacc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_srcmb_s16_qacc_encode_fns[] = {
+  Opcode_ee_srcmb_s16_qacc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_srcmb_s8_qacc_encode_fns[] = {
+  Opcode_ee_srcmb_s8_qacc_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_srs_accx_encode_fns[] = {
+  Opcode_ee_srs_accx_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vrelu_s16_encode_fns[] = {
+  Opcode_ee_vrelu_s16_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vrelu_s8_encode_fns[] = {
+  Opcode_ee_vrelu_s8_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vprelu_s16_encode_fns[] = {
+  Opcode_ee_vprelu_s16_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vprelu_s8_encode_fns[] = {
+  Opcode_ee_vprelu_s8_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmax_s16_ld_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmax_s16_ld_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmax_s16_st_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmax_s16_st_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmax_s16_encode_fns[] = {
+  Opcode_ee_vmax_s16_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmax_s32_ld_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmax_s32_ld_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmax_s32_st_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmax_s32_st_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmax_s32_encode_fns[] = {
+  Opcode_ee_vmax_s32_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmax_s8_ld_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmax_s8_ld_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmax_s8_st_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmax_s8_st_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmax_s8_encode_fns[] = {
+  Opcode_ee_vmax_s8_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmin_s16_ld_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmin_s16_ld_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmin_s16_st_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmin_s16_st_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmin_s16_encode_fns[] = {
+  Opcode_ee_vmin_s16_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmin_s32_ld_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmin_s32_ld_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmin_s32_st_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmin_s32_st_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmin_s32_encode_fns[] = {
+  Opcode_ee_vmin_s32_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmin_s8_ld_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmin_s8_ld_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmin_s8_st_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_vmin_s8_st_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vmin_s8_encode_fns[] = {
+  Opcode_ee_vmin_s8_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vcmp_eq_s16_encode_fns[] = {
+  Opcode_ee_vcmp_eq_s16_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vcmp_eq_s32_encode_fns[] = {
+  Opcode_ee_vcmp_eq_s32_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vcmp_eq_s8_encode_fns[] = {
+  Opcode_ee_vcmp_eq_s8_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vcmp_gt_s16_encode_fns[] = {
+  Opcode_ee_vcmp_gt_s16_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vcmp_gt_s32_encode_fns[] = {
+  Opcode_ee_vcmp_gt_s32_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vcmp_gt_s8_encode_fns[] = {
+  Opcode_ee_vcmp_gt_s8_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vcmp_lt_s16_encode_fns[] = {
+  Opcode_ee_vcmp_lt_s16_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vcmp_lt_s32_encode_fns[] = {
+  Opcode_ee_vcmp_lt_s32_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vcmp_lt_s8_encode_fns[] = {
+  Opcode_ee_vcmp_lt_s8_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_andq_encode_fns[] = {
+  Opcode_ee_andq_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_notq_encode_fns[] = {
+  Opcode_ee_notq_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_orq_encode_fns[] = {
+  Opcode_ee_orq_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_xorq_encode_fns[] = {
+  Opcode_ee_xorq_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_slci_2q_encode_fns[] = {
+  Opcode_ee_slci_2q_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_slcxxp_2q_encode_fns[] = {
+  Opcode_ee_slcxxp_2q_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_srci_2q_encode_fns[] = {
+  Opcode_ee_srci_2q_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_srcq_128_st_incp_encode_fns[] = {
+  Opcode_ee_srcq_128_st_incp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_src_q_ld_ip_encode_fns[] = {
+  0, 0, 0, Opcode_ee_src_q_ld_ip_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_src_q_ld_xp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_src_q_ld_xp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_src_q_qup_encode_fns[] = {
+  Opcode_ee_src_q_qup_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_src_q_encode_fns[] = {
+  Opcode_ee_src_q_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_srcxxp_2q_encode_fns[] = {
+  Opcode_ee_srcxxp_2q_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vsl_32_encode_fns[] = {
+  Opcode_ee_vsl_32_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_vsr_32_encode_fns[] = {
+  Opcode_ee_vsr_32_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_fft_r2bf_s16_st_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_fft_r2bf_s16_st_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_fft_r2bf_s16_encode_fns[] = {
+  Opcode_ee_fft_r2bf_s16_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_fft_cmul_s16_ld_xp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_fft_cmul_s16_ld_xp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_fft_cmul_s16_st_xp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_fft_cmul_s16_st_xp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_bitrev_encode_fns[] = {
+  Opcode_ee_bitrev_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_fft_ams_s16_ld_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_fft_ams_s16_ld_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_fft_ams_s16_ld_incp_uaup_encode_fns[] = {
+  0, 0, 0, Opcode_ee_fft_ams_s16_ld_incp_uaup_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_fft_ams_s16_ld_r32_decp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_fft_ams_s16_ld_r32_decp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_fft_ams_s16_st_incp_encode_fns[] = {
+  0, 0, 0, Opcode_ee_fft_ams_s16_st_incp_Slot_slot_format_32_0_encode
+};
+
+static const xtensa_opcode_encode_fn Opcode_ee_fft_vst_r32_decp_encode_fns[] = {
+  Opcode_ee_fft_vst_r32_decp_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_accx_0_encode_fns[] = {
+  Opcode_rur_accx_0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_accx_0_encode_fns[] = {
+  Opcode_wur_accx_0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_accx_1_encode_fns[] = {
+  Opcode_rur_accx_1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_accx_1_encode_fns[] = {
+  Opcode_wur_accx_1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_qacc_h_0_encode_fns[] = {
+  Opcode_rur_qacc_h_0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_qacc_h_0_encode_fns[] = {
+  Opcode_wur_qacc_h_0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_qacc_h_1_encode_fns[] = {
+  Opcode_rur_qacc_h_1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_qacc_h_1_encode_fns[] = {
+  Opcode_wur_qacc_h_1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_qacc_h_2_encode_fns[] = {
+  Opcode_rur_qacc_h_2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_qacc_h_2_encode_fns[] = {
+  Opcode_wur_qacc_h_2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_qacc_h_3_encode_fns[] = {
+  Opcode_rur_qacc_h_3_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_qacc_h_3_encode_fns[] = {
+  Opcode_wur_qacc_h_3_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_qacc_h_4_encode_fns[] = {
+  Opcode_rur_qacc_h_4_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_qacc_h_4_encode_fns[] = {
+  Opcode_wur_qacc_h_4_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_qacc_l_0_encode_fns[] = {
+  Opcode_rur_qacc_l_0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_qacc_l_0_encode_fns[] = {
+  Opcode_wur_qacc_l_0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_qacc_l_1_encode_fns[] = {
+  Opcode_rur_qacc_l_1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_qacc_l_1_encode_fns[] = {
+  Opcode_wur_qacc_l_1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_qacc_l_2_encode_fns[] = {
+  Opcode_rur_qacc_l_2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_qacc_l_2_encode_fns[] = {
+  Opcode_wur_qacc_l_2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_qacc_l_3_encode_fns[] = {
+  Opcode_rur_qacc_l_3_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_qacc_l_3_encode_fns[] = {
+  Opcode_wur_qacc_l_3_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_qacc_l_4_encode_fns[] = {
+  Opcode_rur_qacc_l_4_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_qacc_l_4_encode_fns[] = {
+  Opcode_wur_qacc_l_4_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_gpio_out_encode_fns[] = {
+  Opcode_rur_gpio_out_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_gpio_out_encode_fns[] = {
+  Opcode_wur_gpio_out_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_sar_byte_encode_fns[] = {
+  Opcode_rur_sar_byte_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_sar_byte_encode_fns[] = {
+  Opcode_wur_sar_byte_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_fft_bit_width_encode_fns[] = {
+  Opcode_rur_fft_bit_width_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_fft_bit_width_encode_fns[] = {
+  Opcode_wur_fft_bit_width_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_ua_state_0_encode_fns[] = {
+  Opcode_rur_ua_state_0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_ua_state_0_encode_fns[] = {
+  Opcode_wur_ua_state_0_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_ua_state_1_encode_fns[] = {
+  Opcode_rur_ua_state_1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_ua_state_1_encode_fns[] = {
+  Opcode_wur_ua_state_1_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_ua_state_2_encode_fns[] = {
+  Opcode_rur_ua_state_2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_ua_state_2_encode_fns[] = {
+  Opcode_wur_ua_state_2_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_rur_ua_state_3_encode_fns[] = {
+  Opcode_rur_ua_state_3_Slot_inst_encode, 0, 0, 0
+};
+
+static const xtensa_opcode_encode_fn Opcode_wur_ua_state_3_encode_fns[] = {
+  Opcode_wur_ua_state_3_Slot_inst_encode, 0, 0, 0
+};
+
+\f
+/* Opcode table.  */
+
+static xtensa_funcUnit_use Opcode_ee_vld_128_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vld_128_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vld_h_64_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vld_h_64_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vld_l_64_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vld_l_64_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vldbc_16_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vldbc_16_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vldbc_16_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vldbc_32_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vldbc_32_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vldbc_32_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vldbc_8_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vldbc_8_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vldbc_8_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vldhbc_16_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_ldf_128_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_ldf_128_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_ldf_64_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_ldf_64_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_ld_128_usar_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_ld_128_usar_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_ldqa_s16_128_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_ldqa_s16_128_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_ldqa_s8_128_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_ldqa_s8_128_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_ldqa_u16_128_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_ldqa_u16_128_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_ldqa_u8_128_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_ldqa_u8_128_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_ld_qacc_h_h_32_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_ld_qacc_h_l_128_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_ld_qacc_l_h_32_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_ld_qacc_l_l_128_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_ld_accx_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_ldxq_32_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_ld_ua_state_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_st_ua_state_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vst_128_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vst_128_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vst_h_64_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vst_h_64_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vst_l_64_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vst_l_64_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_stf_128_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_stf_128_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_stf_64_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_stf_64_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_st_qacc_h_h_32_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_st_qacc_h_l_128_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_st_qacc_l_h_32_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_st_qacc_l_l_128_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_st_accx_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_stxq_32_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vadds_s16_ld_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vadds_s16_st_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vadds_s16_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vadds_s32_ld_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vadds_s32_st_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vadds_s32_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vadds_s8_ld_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vadds_s8_st_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vadds_s8_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vsubs_s16_ld_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vsubs_s16_st_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vsubs_s16_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vsubs_s32_ld_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vsubs_s32_st_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vsubs_s32_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vsubs_s8_ld_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vsubs_s8_st_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vsubs_s8_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmul_s16_ld_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmul_s16_st_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmul_s16_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmul_s8_ld_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmul_s8_st_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmul_s8_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmul_u16_ld_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmul_u16_st_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmul_u16_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmul_u8_ld_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmul_u8_st_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmul_u8_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_cmul_s16_ld_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_cmul_s16_st_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_cmul_s16_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_s16_accx_ld_ip_qup_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_s16_accx_ld_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_s16_accx_ld_xp_qup_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_s16_accx_ld_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_s16_accx_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_s8_accx_ld_ip_qup_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_s8_accx_ld_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_s8_accx_ld_xp_qup_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_s8_accx_ld_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_s8_accx_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_u16_accx_ld_ip_qup_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_u16_accx_ld_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_u16_accx_ld_xp_qup_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_u16_accx_ld_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_u16_accx_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_u8_accx_ld_ip_qup_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_u8_accx_ld_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_u8_accx_ld_xp_qup_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_u8_accx_ld_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_u8_accx_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_s16_qacc_ldbc_incp_qup_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_s16_qacc_ldbc_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_s16_qacc_ld_ip_qup_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_s16_qacc_ld_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_s16_qacc_ld_xp_qup_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_s16_qacc_ld_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_s16_qacc_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_s8_qacc_ldbc_incp_qup_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_s8_qacc_ldbc_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_s8_qacc_ld_ip_qup_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_s8_qacc_ld_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_s8_qacc_ld_xp_qup_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_s8_qacc_ld_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_s8_qacc_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_u16_qacc_ldbc_incp_qup_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_u16_qacc_ldbc_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_u16_qacc_ld_ip_qup_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_u16_qacc_ld_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_u16_qacc_ld_xp_qup_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_u16_qacc_ld_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_u16_qacc_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_u8_qacc_ldbc_incp_qup_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_u8_qacc_ldbc_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_u8_qacc_ld_ip_qup_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_u8_qacc_ld_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_u8_qacc_ld_xp_qup_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_u8_qacc_ld_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmulas_u8_qacc_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vsmulas_s16_qacc_ld_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vsmulas_s16_qacc_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vsmulas_s8_qacc_ld_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vsmulas_s8_qacc_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_srcmb_s16_qacc_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 1 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 1 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 1 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s40x2_0, 1 },
+  { FUNCUNIT_func_addsub_s40x2_1, 1 },
+  { FUNCUNIT_func_addsub_s40x2_2, 1 },
+  { FUNCUNIT_func_addsub_s40x2_3, 1 },
+  { FUNCUNIT_func_addsub_s40x2_4, 1 },
+  { FUNCUNIT_func_addsub_s40x2_5, 1 },
+  { FUNCUNIT_func_addsub_s40x2_6, 1 },
+  { FUNCUNIT_func_addsub_s40x2_7, 1 },
+  { FUNCUNIT_func_shift_s40rs_slot_end_0, 1 },
+  { FUNCUNIT_func_shift_s40rs_slot_end_1, 1 },
+  { FUNCUNIT_func_shift_s40rs_slot_end_2, 1 },
+  { FUNCUNIT_func_shift_s40rs_slot_end_3, 1 },
+  { FUNCUNIT_func_shift_s40rs_slot_end_4, 1 },
+  { FUNCUNIT_func_shift_s40rs_slot_end_5, 1 },
+  { FUNCUNIT_func_shift_s40rs_slot_end_6, 1 },
+  { FUNCUNIT_func_shift_s40rs_slot_end_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_srcmb_s8_qacc_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 1 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 1 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 1 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s40x2_0, 1 },
+  { FUNCUNIT_func_addsub_s40x2_1, 1 },
+  { FUNCUNIT_func_addsub_s40x2_2, 1 },
+  { FUNCUNIT_func_addsub_s40x2_3, 1 },
+  { FUNCUNIT_func_addsub_s40x2_4, 1 },
+  { FUNCUNIT_func_addsub_s40x2_5, 1 },
+  { FUNCUNIT_func_addsub_s40x2_6, 1 },
+  { FUNCUNIT_func_addsub_s40x2_7, 1 },
+  { FUNCUNIT_func_shift_s40rs_slot_end_0, 1 },
+  { FUNCUNIT_func_shift_s40rs_slot_end_1, 1 },
+  { FUNCUNIT_func_shift_s40rs_slot_end_2, 1 },
+  { FUNCUNIT_func_shift_s40rs_slot_end_3, 1 },
+  { FUNCUNIT_func_shift_s40rs_slot_end_4, 1 },
+  { FUNCUNIT_func_shift_s40rs_slot_end_5, 1 },
+  { FUNCUNIT_func_shift_s40rs_slot_end_6, 1 },
+  { FUNCUNIT_func_shift_s40rs_slot_end_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_srs_accx_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s40x2_0, 1 },
+  { FUNCUNIT_func_shift_s40rs_slot_end_0, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vrelu_s16_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vrelu_s8_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vprelu_s16_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vprelu_s8_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmax_s16_ld_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmax_s16_st_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmax_s16_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmax_s32_ld_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmax_s32_st_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmax_s32_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmax_s8_ld_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmax_s8_st_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmax_s8_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmin_s16_ld_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmin_s16_st_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmin_s16_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmin_s32_ld_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmin_s32_st_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmin_s32_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmin_s8_ld_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmin_s8_st_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vmin_s8_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vcmp_eq_s16_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vcmp_eq_s32_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vcmp_eq_s8_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vcmp_gt_s16_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vcmp_gt_s32_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vcmp_gt_s8_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vcmp_lt_s16_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vcmp_lt_s32_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vcmp_lt_s8_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_0, 1 },
+  { FUNCUNIT_func_addsub_s8x2_1, 1 },
+  { FUNCUNIT_func_addsub_s8x2_2, 1 },
+  { FUNCUNIT_func_addsub_s8x2_3, 1 },
+  { FUNCUNIT_func_addsub_s8x2_4, 1 },
+  { FUNCUNIT_func_addsub_s8x2_5, 1 },
+  { FUNCUNIT_func_addsub_s8x2_6, 1 },
+  { FUNCUNIT_func_addsub_s8x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_0, 1 },
+  { FUNCUNIT_func_mul_s8xs8_1, 1 },
+  { FUNCUNIT_func_mul_s8xs8_2, 1 },
+  { FUNCUNIT_func_mul_s8xs8_3, 1 },
+  { FUNCUNIT_func_mul_s8xs8_4, 1 },
+  { FUNCUNIT_func_mul_s8xs8_5, 1 },
+  { FUNCUNIT_func_mul_s8xs8_6, 1 },
+  { FUNCUNIT_func_mul_s8xs8_7, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_4, 1 },
+  { FUNCUNIT_func_mul_s16xs16_5, 1 },
+  { FUNCUNIT_func_mul_s16xs16_6, 1 },
+  { FUNCUNIT_func_mul_s16xs16_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_extra, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_2, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 2 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_0, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_1, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_2, 2 },
+  { FUNCUNIT_func_addsub_s20x2_slot_end_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_7, 2 },
+  { FUNCUNIT_func_addsub_s40x2_6, 2 },
+  { FUNCUNIT_func_addsub_s40x2_5, 2 },
+  { FUNCUNIT_func_addsub_s40x2_4, 2 },
+  { FUNCUNIT_func_addsub_s40x2_3, 2 },
+  { FUNCUNIT_func_addsub_s40x2_2, 2 },
+  { FUNCUNIT_func_addsub_s40x2_1, 2 },
+  { FUNCUNIT_func_addsub_s40x2_0, 2 },
+  { FUNCUNIT_func_shift_s16rs8_0, 1 },
+  { FUNCUNIT_func_shift_s16rs8_1, 1 },
+  { FUNCUNIT_func_shift_s16rs8_2, 1 },
+  { FUNCUNIT_func_shift_s16rs8_3, 1 },
+  { FUNCUNIT_func_shift_s16rs8_4, 1 },
+  { FUNCUNIT_func_shift_s16rs8_5, 1 },
+  { FUNCUNIT_func_shift_s16rs8_6, 1 },
+  { FUNCUNIT_func_shift_s16rs8_7, 1 },
+  { FUNCUNIT_func_shift_s16rs8_8, 1 },
+  { FUNCUNIT_func_shift_s16rs8_9, 1 },
+  { FUNCUNIT_func_shift_s16rs8_10, 1 },
+  { FUNCUNIT_func_shift_s16rs8_11, 1 },
+  { FUNCUNIT_func_shift_s16rs8_12, 1 },
+  { FUNCUNIT_func_shift_s16rs8_13, 1 },
+  { FUNCUNIT_func_shift_s16rs8_14, 1 },
+  { FUNCUNIT_func_shift_s16rs8_15, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 2 },
+  { FUNCUNIT_func_shift_s32rs16_1, 2 },
+  { FUNCUNIT_func_shift_s32rs16_2, 2 },
+  { FUNCUNIT_func_shift_s32rs16_3, 2 },
+  { FUNCUNIT_func_shift_s32rs16_4, 1 },
+  { FUNCUNIT_func_shift_s32rs16_5, 1 },
+  { FUNCUNIT_func_shift_s32rs16_6, 1 },
+  { FUNCUNIT_func_shift_s32rs16_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_slci_2q_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_slcxxp_2q_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_srci_2q_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_srcq_128_st_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_src_q_ld_ip_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_src_q_ld_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_src_q_qup_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_src_q_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_srcxxp_2q_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vsl_32_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_vsr_32_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_fft_r2bf_s16_st_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_fft_r2bf_s16_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_2, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_4, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_5, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_6, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot0_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_fft_cmul_s16_ld_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 1 },
+  { FUNCUNIT_func_shift_s32rs16_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_fft_cmul_s16_st_xp_funcUnit_uses[] = {
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 1 },
+  { FUNCUNIT_func_shift_s32rs16_1, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_bitrev_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_fft_ams_s16_ld_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 1 },
+  { FUNCUNIT_func_shift_s32rs16_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_fft_ams_s16_ld_incp_uaup_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 1 },
+  { FUNCUNIT_func_shift_s32rs16_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_fft_ams_s16_ld_r32_decp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 1 },
+  { FUNCUNIT_func_shift_s32rs16_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_fft_ams_s16_st_incp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 },
+  { FUNCUNIT_func_addsub_s16x2_0, 1 },
+  { FUNCUNIT_func_addsub_s16x2_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_2, 1 },
+  { FUNCUNIT_func_addsub_s16x2_3, 1 },
+  { FUNCUNIT_func_mul_s16xs16_0, 1 },
+  { FUNCUNIT_func_mul_s16xs16_1, 1 },
+  { FUNCUNIT_func_mul_s16xs16_2, 1 },
+  { FUNCUNIT_func_mul_s16xs16_3, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_0, 1 },
+  { FUNCUNIT_func_addsub_s32x2_slot1_1, 1 },
+  { FUNCUNIT_func_shift_s32rs16_0, 1 },
+  { FUNCUNIT_func_shift_s32rs16_1, 1 },
+  { FUNCUNIT_func_addsub_s16x2_4, 1 },
+  { FUNCUNIT_func_addsub_s16x2_5, 1 },
+  { FUNCUNIT_func_addsub_s16x2_6, 1 },
+  { FUNCUNIT_func_addsub_s16x2_7, 1 }
+};
+
+static xtensa_funcUnit_use Opcode_ee_fft_vst_r32_decp_funcUnit_uses[] = {
+  { FUNCUNIT_func_addsub_s32x2_slot1_3, 1 }
+};
+
+static xtensa_opcode_internal opcodes[] = {
+  { "lsi", ICLASS_LSI,
+    0,
+    Opcode_lsi_encode_fns, 0, 0 },
+  { "lsip", ICLASS_LSIP,
+    0,
+    Opcode_lsip_encode_fns, 0, 0 },
+  { "lsx", ICLASS_LSX,
+    0,
+    Opcode_lsx_encode_fns, 0, 0 },
+  { "lsxp", ICLASS_LSXP,
+    0,
+    Opcode_lsxp_encode_fns, 0, 0 },
+  { "ssi", ICLASS_SSI,
+    0,
+    Opcode_ssi_encode_fns, 0, 0 },
+  { "ssip", ICLASS_SSIP,
+    0,
+    Opcode_ssip_encode_fns, 0, 0 },
+  { "ssx", ICLASS_SSX,
+    0,
+    Opcode_ssx_encode_fns, 0, 0 },
+  { "ssxp", ICLASS_SSXP,
+    0,
+    Opcode_ssxp_encode_fns, 0, 0 },
+  { "abs.s", ICLASS_ABS_S,
+    0,
+    Opcode_abs_s_encode_fns, 0, 0 },
+  { "neg.s", ICLASS_NEG_S,
+    0,
+    Opcode_neg_s_encode_fns, 0, 0 },
+  { "mov.s", ICLASS_MOV_S,
+    0,
+    Opcode_mov_s_encode_fns, 0, 0 },
+  { "moveqz.s", ICLASS_MOVEQZ_S,
+    0,
+    Opcode_moveqz_s_encode_fns, 0, 0 },
+  { "movnez.s", ICLASS_MOVNEZ_S,
+    0,
+    Opcode_movnez_s_encode_fns, 0, 0 },
+  { "movltz.s", ICLASS_MOVLTZ_S,
+    0,
+    Opcode_movltz_s_encode_fns, 0, 0 },
+  { "movgez.s", ICLASS_MOVGEZ_S,
+    0,
+    Opcode_movgez_s_encode_fns, 0, 0 },
+  { "movf.s", ICLASS_MOVF_S,
+    0,
+    Opcode_movf_s_encode_fns, 0, 0 },
+  { "movt.s", ICLASS_MOVT_S,
+    0,
+    Opcode_movt_s_encode_fns, 0, 0 },
+  { "wfr", ICLASS_WFR,
+    0,
+    Opcode_wfr_encode_fns, 0, 0 },
+  { "rfr", ICLASS_RFR,
+    0,
+    Opcode_rfr_encode_fns, 0, 0 },
+  { "round.s", ICLASS_ROUND_S,
+    0,
+    Opcode_round_s_encode_fns, 0, 0 },
+  { "ceil.s", ICLASS_CEIL_S,
+    0,
+    Opcode_ceil_s_encode_fns, 0, 0 },
+  { "floor.s", ICLASS_FLOOR_S,
+    0,
+    Opcode_floor_s_encode_fns, 0, 0 },
+  { "trunc.s", ICLASS_TRUNC_S,
+    0,
+    Opcode_trunc_s_encode_fns, 0, 0 },
+  { "utrunc.s", ICLASS_UTRUNC_S,
+    0,
+    Opcode_utrunc_s_encode_fns, 0, 0 },
+  { "float.s", ICLASS_FLOAT_S,
+    0,
+    Opcode_float_s_encode_fns, 0, 0 },
+  { "ufloat.s", ICLASS_UFLOAT_S,
+    0,
+    Opcode_ufloat_s_encode_fns, 0, 0 },
+  { "un.s", ICLASS_UN_S,
+    0,
+    Opcode_un_s_encode_fns, 0, 0 },
+  { "ult.s", ICLASS_ULT_S,
+    0,
+    Opcode_ult_s_encode_fns, 0, 0 },
+  { "ule.s", ICLASS_ULE_S,
+    0,
+    Opcode_ule_s_encode_fns, 0, 0 },
+  { "ueq.s", ICLASS_UEQ_S,
+    0,
+    Opcode_ueq_s_encode_fns, 0, 0 },
+  { "olt.s", ICLASS_OLT_S,
+    0,
+    Opcode_olt_s_encode_fns, 0, 0 },
+  { "ole.s", ICLASS_OLE_S,
+    0,
+    Opcode_ole_s_encode_fns, 0, 0 },
+  { "oeq.s", ICLASS_OEQ_S,
+    0,
+    Opcode_oeq_s_encode_fns, 0, 0 },
+  { "add.s", ICLASS_ADD_S,
+    0,
+    Opcode_add_s_encode_fns, 0, 0 },
+  { "sub.s", ICLASS_SUB_S,
+    0,
+    Opcode_sub_s_encode_fns, 0, 0 },
+  { "mul.s", ICLASS_MUL_S,
+    0,
+    Opcode_mul_s_encode_fns, 0, 0 },
+  { "madd.s", ICLASS_MADD_S,
+    0,
+    Opcode_madd_s_encode_fns, 0, 0 },
+  { "msub.s", ICLASS_MSUB_S,
+    0,
+    Opcode_msub_s_encode_fns, 0, 0 },
+  { "sqrt0.s", ICLASS_SQRT0_S,
+    0,
+    Opcode_sqrt0_s_encode_fns, 0, 0 },
+  { "div0.s", ICLASS_DIV0_S,
+    0,
+    Opcode_div0_s_encode_fns, 0, 0 },
+  { "recip0.s", ICLASS_RECIP0_S,
+    0,
+    Opcode_recip0_s_encode_fns, 0, 0 },
+  { "rsqrt0.s", ICLASS_RSQRT0_S,
+    0,
+    Opcode_rsqrt0_s_encode_fns, 0, 0 },
+  { "maddn.s", ICLASS_MADDN_S,
+    0,
+    Opcode_maddn_s_encode_fns, 0, 0 },
+  { "divn.s", ICLASS_DIVN_S,
+    0,
+    Opcode_divn_s_encode_fns, 0, 0 },
+  { "const.s", ICLASS_CONST_S,
+    0,
+    Opcode_const_s_encode_fns, 0, 0 },
+  { "nexp01.s", ICLASS_NEXP01_S,
+    0,
+    Opcode_nexp01_s_encode_fns, 0, 0 },
+  { "addexp.s", ICLASS_ADDEXP_S,
+    0,
+    Opcode_addexp_s_encode_fns, 0, 0 },
+  { "addexpm.s", ICLASS_ADDEXPM_S,
+    0,
+    Opcode_addexpm_s_encode_fns, 0, 0 },
+  { "mkdadj.s", ICLASS_MKDADJ_S,
+    0,
+    Opcode_mkdadj_s_encode_fns, 0, 0 },
+  { "mksadj.s", ICLASS_MKSADJ_S,
+    0,
+    Opcode_mksadj_s_encode_fns, 0, 0 },
+  { "excw", ICLASS_xt_iclass_excw,
+    0,
+    Opcode_excw_encode_fns, 0, 0 },
+  { "rfe", ICLASS_xt_iclass_rfe,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_rfe_encode_fns, 0, 0 },
+  { "rfde", ICLASS_xt_iclass_rfde,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_rfde_encode_fns, 0, 0 },
+  { "syscall", ICLASS_xt_iclass_syscall,
+    0,
+    Opcode_syscall_encode_fns, 0, 0 },
+  { "call12", ICLASS_xt_iclass_call12,
+    XTENSA_OPCODE_IS_CALL,
+    Opcode_call12_encode_fns, 0, 0 },
+  { "call8", ICLASS_xt_iclass_call8,
+    XTENSA_OPCODE_IS_CALL,
+    Opcode_call8_encode_fns, 0, 0 },
+  { "call4", ICLASS_xt_iclass_call4,
+    XTENSA_OPCODE_IS_CALL,
+    Opcode_call4_encode_fns, 0, 0 },
+  { "callx12", ICLASS_xt_iclass_callx12,
+    XTENSA_OPCODE_IS_CALL,
+    Opcode_callx12_encode_fns, 0, 0 },
+  { "callx8", ICLASS_xt_iclass_callx8,
+    XTENSA_OPCODE_IS_CALL,
+    Opcode_callx8_encode_fns, 0, 0 },
+  { "callx4", ICLASS_xt_iclass_callx4,
+    XTENSA_OPCODE_IS_CALL,
+    Opcode_callx4_encode_fns, 0, 0 },
+  { "entry", ICLASS_xt_iclass_entry,
+    0,
+    Opcode_entry_encode_fns, 0, 0 },
+  { "movsp", ICLASS_xt_iclass_movsp,
+    0,
+    Opcode_movsp_encode_fns, 0, 0 },
+  { "rotw", ICLASS_xt_iclass_rotw,
+    0,
+    Opcode_rotw_encode_fns, 0, 0 },
+  { "retw", ICLASS_xt_iclass_retw,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_retw_encode_fns, 0, 0 },
+  { "retw.n", ICLASS_xt_iclass_retw,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_retw_n_encode_fns, 0, 0 },
+  { "rfwo", ICLASS_xt_iclass_rfwou,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_rfwo_encode_fns, 0, 0 },
+  { "rfwu", ICLASS_xt_iclass_rfwou,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_rfwu_encode_fns, 0, 0 },
+  { "l32e", ICLASS_xt_iclass_l32e,
+    0,
+    Opcode_l32e_encode_fns, 0, 0 },
+  { "s32e", ICLASS_xt_iclass_s32e,
+    0,
+    Opcode_s32e_encode_fns, 0, 0 },
+  { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase,
+    0,
+    Opcode_rsr_windowbase_encode_fns, 0, 0 },
+  { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase,
+    0,
+    Opcode_wsr_windowbase_encode_fns, 0, 0 },
+  { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase,
+    0,
+    Opcode_xsr_windowbase_encode_fns, 0, 0 },
+  { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart,
+    0,
+    Opcode_rsr_windowstart_encode_fns, 0, 0 },
+  { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart,
+    0,
+    Opcode_wsr_windowstart_encode_fns, 0, 0 },
+  { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart,
+    0,
+    Opcode_xsr_windowstart_encode_fns, 0, 0 },
+  { "add.n", ICLASS_xt_iclass_add_n,
+    0,
+    Opcode_add_n_encode_fns, 0, 0 },
+  { "addi.n", ICLASS_xt_iclass_addi_n,
+    0,
+    Opcode_addi_n_encode_fns, 0, 0 },
+  { "beqz.n", ICLASS_xt_iclass_bz6,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_beqz_n_encode_fns, 0, 0 },
+  { "bnez.n", ICLASS_xt_iclass_bz6,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bnez_n_encode_fns, 0, 0 },
+  { "ill.n", ICLASS_xt_iclass_ill_n,
+    0,
+    Opcode_ill_n_encode_fns, 0, 0 },
+  { "l32i.n", ICLASS_xt_iclass_loadi4,
+    0,
+    Opcode_l32i_n_encode_fns, 0, 0 },
+  { "mov.n", ICLASS_xt_iclass_mov_n,
+    0,
+    Opcode_mov_n_encode_fns, 0, 0 },
+  { "movi.n", ICLASS_xt_iclass_movi_n,
+    0,
+    Opcode_movi_n_encode_fns, 0, 0 },
+  { "nop.n", ICLASS_xt_iclass_nopn,
+    0,
+    Opcode_nop_n_encode_fns, 0, 0 },
+  { "ret.n", ICLASS_xt_iclass_retn,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_ret_n_encode_fns, 0, 0 },
+  { "s32i.n", ICLASS_xt_iclass_storei4,
+    0,
+    Opcode_s32i_n_encode_fns, 0, 0 },
+  { "rur.threadptr", ICLASS_rur_threadptr,
+    0,
+    Opcode_rur_threadptr_encode_fns, 0, 0 },
+  { "wur.threadptr", ICLASS_wur_threadptr,
+    0,
+    Opcode_wur_threadptr_encode_fns, 0, 0 },
+  { "addi", ICLASS_xt_iclass_addi,
+    0,
+    Opcode_addi_encode_fns, 0, 0 },
+  { "addmi", ICLASS_xt_iclass_addmi,
+    0,
+    Opcode_addmi_encode_fns, 0, 0 },
+  { "add", ICLASS_xt_iclass_addsub,
+    0,
+    Opcode_add_encode_fns, 0, 0 },
+  { "sub", ICLASS_xt_iclass_addsub,
+    0,
+    Opcode_sub_encode_fns, 0, 0 },
+  { "addx2", ICLASS_xt_iclass_addsub,
+    0,
+    Opcode_addx2_encode_fns, 0, 0 },
+  { "addx4", ICLASS_xt_iclass_addsub,
+    0,
+    Opcode_addx4_encode_fns, 0, 0 },
+  { "addx8", ICLASS_xt_iclass_addsub,
+    0,
+    Opcode_addx8_encode_fns, 0, 0 },
+  { "subx2", ICLASS_xt_iclass_addsub,
+    0,
+    Opcode_subx2_encode_fns, 0, 0 },
+  { "subx4", ICLASS_xt_iclass_addsub,
+    0,
+    Opcode_subx4_encode_fns, 0, 0 },
+  { "subx8", ICLASS_xt_iclass_addsub,
+    0,
+    Opcode_subx8_encode_fns, 0, 0 },
+  { "and", ICLASS_xt_iclass_bit,
+    0,
+    Opcode_and_encode_fns, 0, 0 },
+  { "or", ICLASS_xt_iclass_bit,
+    0,
+    Opcode_or_encode_fns, 0, 0 },
+  { "xor", ICLASS_xt_iclass_bit,
+    0,
+    Opcode_xor_encode_fns, 0, 0 },
+  { "beqi", ICLASS_xt_iclass_bsi8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_beqi_encode_fns, 0, 0 },
+  { "bnei", ICLASS_xt_iclass_bsi8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bnei_encode_fns, 0, 0 },
+  { "bgei", ICLASS_xt_iclass_bsi8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bgei_encode_fns, 0, 0 },
+  { "blti", ICLASS_xt_iclass_bsi8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_blti_encode_fns, 0, 0 },
+  { "bbci", ICLASS_xt_iclass_bsi8b,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bbci_encode_fns, 0, 0 },
+  { "bbsi", ICLASS_xt_iclass_bsi8b,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bbsi_encode_fns, 0, 0 },
+  { "bgeui", ICLASS_xt_iclass_bsi8u,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bgeui_encode_fns, 0, 0 },
+  { "bltui", ICLASS_xt_iclass_bsi8u,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bltui_encode_fns, 0, 0 },
+  { "beq", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_beq_encode_fns, 0, 0 },
+  { "bne", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bne_encode_fns, 0, 0 },
+  { "bge", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bge_encode_fns, 0, 0 },
+  { "blt", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_blt_encode_fns, 0, 0 },
+  { "bgeu", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bgeu_encode_fns, 0, 0 },
+  { "bltu", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bltu_encode_fns, 0, 0 },
+  { "bany", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bany_encode_fns, 0, 0 },
+  { "bnone", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bnone_encode_fns, 0, 0 },
+  { "ball", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_ball_encode_fns, 0, 0 },
+  { "bnall", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bnall_encode_fns, 0, 0 },
+  { "bbc", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bbc_encode_fns, 0, 0 },
+  { "bbs", ICLASS_xt_iclass_bst8,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bbs_encode_fns, 0, 0 },
+  { "beqz", ICLASS_xt_iclass_bsz12,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_beqz_encode_fns, 0, 0 },
+  { "bnez", ICLASS_xt_iclass_bsz12,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bnez_encode_fns, 0, 0 },
+  { "bgez", ICLASS_xt_iclass_bsz12,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bgez_encode_fns, 0, 0 },
+  { "bltz", ICLASS_xt_iclass_bsz12,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bltz_encode_fns, 0, 0 },
+  { "call0", ICLASS_xt_iclass_call0,
+    XTENSA_OPCODE_IS_CALL,
+    Opcode_call0_encode_fns, 0, 0 },
+  { "callx0", ICLASS_xt_iclass_callx0,
+    XTENSA_OPCODE_IS_CALL,
+    Opcode_callx0_encode_fns, 0, 0 },
+  { "extui", ICLASS_xt_iclass_exti,
+    0,
+    Opcode_extui_encode_fns, 0, 0 },
+  { "ill", ICLASS_xt_iclass_ill,
+    0,
+    Opcode_ill_encode_fns, 0, 0 },
+  { "j", ICLASS_xt_iclass_jump,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_j_encode_fns, 0, 0 },
+  { "jx", ICLASS_xt_iclass_jumpx,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_jx_encode_fns, 0, 0 },
+  { "l16ui", ICLASS_xt_iclass_l16ui,
+    0,
+    Opcode_l16ui_encode_fns, 0, 0 },
+  { "l16si", ICLASS_xt_iclass_l16si,
+    0,
+    Opcode_l16si_encode_fns, 0, 0 },
+  { "l32i", ICLASS_xt_iclass_l32i,
+    0,
+    Opcode_l32i_encode_fns, 0, 0 },
+  { "l32r", ICLASS_xt_iclass_l32r,
+    0,
+    Opcode_l32r_encode_fns, 0, 0 },
+  { "l8ui", ICLASS_xt_iclass_l8i,
+    0,
+    Opcode_l8ui_encode_fns, 0, 0 },
+  { "loop", ICLASS_xt_iclass_loop,
+    XTENSA_OPCODE_IS_LOOP,
+    Opcode_loop_encode_fns, 0, 0 },
+  { "loopnez", ICLASS_xt_iclass_loopz,
+    XTENSA_OPCODE_IS_LOOP,
+    Opcode_loopnez_encode_fns, 0, 0 },
+  { "loopgtz", ICLASS_xt_iclass_loopz,
+    XTENSA_OPCODE_IS_LOOP,
+    Opcode_loopgtz_encode_fns, 0, 0 },
+  { "movi", ICLASS_xt_iclass_movi,
+    0,
+    Opcode_movi_encode_fns, 0, 0 },
+  { "moveqz", ICLASS_xt_iclass_movz,
+    0,
+    Opcode_moveqz_encode_fns, 0, 0 },
+  { "movnez", ICLASS_xt_iclass_movz,
+    0,
+    Opcode_movnez_encode_fns, 0, 0 },
+  { "movltz", ICLASS_xt_iclass_movz,
+    0,
+    Opcode_movltz_encode_fns, 0, 0 },
+  { "movgez", ICLASS_xt_iclass_movz,
+    0,
+    Opcode_movgez_encode_fns, 0, 0 },
+  { "neg", ICLASS_xt_iclass_neg,
+    0,
+    Opcode_neg_encode_fns, 0, 0 },
+  { "abs", ICLASS_xt_iclass_neg,
+    0,
+    Opcode_abs_encode_fns, 0, 0 },
+  { "nop", ICLASS_xt_iclass_nop,
+    0,
+    Opcode_nop_encode_fns, 0, 0 },
+  { "ret", ICLASS_xt_iclass_return,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_ret_encode_fns, 0, 0 },
+  { "simcall", ICLASS_xt_iclass_simcall,
+    0,
+    Opcode_simcall_encode_fns, 0, 0 },
+  { "s16i", ICLASS_xt_iclass_s16i,
+    0,
+    Opcode_s16i_encode_fns, 0, 0 },
+  { "s32i", ICLASS_xt_iclass_s32i,
+    0,
+    Opcode_s32i_encode_fns, 0, 0 },
+  { "s32nb", ICLASS_xt_iclass_s32nb,
+    0,
+    Opcode_s32nb_encode_fns, 0, 0 },
+  { "s8i", ICLASS_xt_iclass_s8i,
+    0,
+    Opcode_s8i_encode_fns, 0, 0 },
+  { "ssr", ICLASS_xt_iclass_sar,
+    0,
+    Opcode_ssr_encode_fns, 0, 0 },
+  { "ssl", ICLASS_xt_iclass_sar,
+    0,
+    Opcode_ssl_encode_fns, 0, 0 },
+  { "ssa8l", ICLASS_xt_iclass_sar,
+    0,
+    Opcode_ssa8l_encode_fns, 0, 0 },
+  { "ssa8b", ICLASS_xt_iclass_sar,
+    0,
+    Opcode_ssa8b_encode_fns, 0, 0 },
+  { "ssai", ICLASS_xt_iclass_sari,
+    0,
+    Opcode_ssai_encode_fns, 0, 0 },
+  { "sll", ICLASS_xt_iclass_shifts,
+    0,
+    Opcode_sll_encode_fns, 0, 0 },
+  { "src", ICLASS_xt_iclass_shiftst,
+    0,
+    Opcode_src_encode_fns, 0, 0 },
+  { "srl", ICLASS_xt_iclass_shiftt,
+    0,
+    Opcode_srl_encode_fns, 0, 0 },
+  { "sra", ICLASS_xt_iclass_shiftt,
+    0,
+    Opcode_sra_encode_fns, 0, 0 },
+  { "slli", ICLASS_xt_iclass_slli,
+    0,
+    Opcode_slli_encode_fns, 0, 0 },
+  { "srai", ICLASS_xt_iclass_srai,
+    0,
+    Opcode_srai_encode_fns, 0, 0 },
+  { "srli", ICLASS_xt_iclass_srli,
+    0,
+    Opcode_srli_encode_fns, 0, 0 },
+  { "memw", ICLASS_xt_iclass_memw,
+    0,
+    Opcode_memw_encode_fns, 0, 0 },
+  { "extw", ICLASS_xt_iclass_extw,
+    0,
+    Opcode_extw_encode_fns, 0, 0 },
+  { "isync", ICLASS_xt_iclass_isync,
+    0,
+    Opcode_isync_encode_fns, 0, 0 },
+  { "rsync", ICLASS_xt_iclass_sync,
+    0,
+    Opcode_rsync_encode_fns, 0, 0 },
+  { "esync", ICLASS_xt_iclass_sync,
+    0,
+    Opcode_esync_encode_fns, 0, 0 },
+  { "dsync", ICLASS_xt_iclass_sync,
+    0,
+    Opcode_dsync_encode_fns, 0, 0 },
+  { "rsil", ICLASS_xt_iclass_rsil,
+    0,
+    Opcode_rsil_encode_fns, 0, 0 },
+  { "rsr.lend", ICLASS_xt_iclass_rsr_lend,
+    0,
+    Opcode_rsr_lend_encode_fns, 0, 0 },
+  { "wsr.lend", ICLASS_xt_iclass_wsr_lend,
+    0,
+    Opcode_wsr_lend_encode_fns, 0, 0 },
+  { "xsr.lend", ICLASS_xt_iclass_xsr_lend,
+    0,
+    Opcode_xsr_lend_encode_fns, 0, 0 },
+  { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount,
+    0,
+    Opcode_rsr_lcount_encode_fns, 0, 0 },
+  { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount,
+    0,
+    Opcode_wsr_lcount_encode_fns, 0, 0 },
+  { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount,
+    0,
+    Opcode_xsr_lcount_encode_fns, 0, 0 },
+  { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg,
+    0,
+    Opcode_rsr_lbeg_encode_fns, 0, 0 },
+  { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg,
+    0,
+    Opcode_wsr_lbeg_encode_fns, 0, 0 },
+  { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg,
+    0,
+    Opcode_xsr_lbeg_encode_fns, 0, 0 },
+  { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
+    0,
+    Opcode_rsr_sar_encode_fns, 0, 0 },
+  { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
+    0,
+    Opcode_wsr_sar_encode_fns, 0, 0 },
+  { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
+    0,
+    Opcode_xsr_sar_encode_fns, 0, 0 },
+  { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl,
+    0,
+    Opcode_rsr_memctl_encode_fns, 0, 0 },
+  { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl,
+    0,
+    Opcode_wsr_memctl_encode_fns, 0, 0 },
+  { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl,
+    0,
+    Opcode_xsr_memctl_encode_fns, 0, 0 },
+  { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase,
+    0,
+    Opcode_rsr_litbase_encode_fns, 0, 0 },
+  { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase,
+    0,
+    Opcode_wsr_litbase_encode_fns, 0, 0 },
+  { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
+    0,
+    Opcode_xsr_litbase_encode_fns, 0, 0 },
+  { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0,
+    0,
+    Opcode_rsr_configid0_encode_fns, 0, 0 },
+  { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0,
+    0,
+    Opcode_wsr_configid0_encode_fns, 0, 0 },
+  { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1,
+    0,
+    Opcode_rsr_configid1_encode_fns, 0, 0 },
+  { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
+    0,
+    Opcode_rsr_ps_encode_fns, 0, 0 },
+  { "wsr.ps", ICLASS_xt_iclass_wsr_ps,
+    0,
+    Opcode_wsr_ps_encode_fns, 0, 0 },
+  { "xsr.ps", ICLASS_xt_iclass_xsr_ps,
+    0,
+    Opcode_xsr_ps_encode_fns, 0, 0 },
+  { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
+    0,
+    Opcode_rsr_epc1_encode_fns, 0, 0 },
+  { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
+    0,
+    Opcode_wsr_epc1_encode_fns, 0, 0 },
+  { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
+    0,
+    Opcode_xsr_epc1_encode_fns, 0, 0 },
+  { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
+    0,
+    Opcode_rsr_excsave1_encode_fns, 0, 0 },
+  { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
+    0,
+    Opcode_wsr_excsave1_encode_fns, 0, 0 },
+  { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
+    0,
+    Opcode_xsr_excsave1_encode_fns, 0, 0 },
+  { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
+    0,
+    Opcode_rsr_epc2_encode_fns, 0, 0 },
+  { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
+    0,
+    Opcode_wsr_epc2_encode_fns, 0, 0 },
+  { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
+    0,
+    Opcode_xsr_epc2_encode_fns, 0, 0 },
+  { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
+    0,
+    Opcode_rsr_excsave2_encode_fns, 0, 0 },
+  { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
+    0,
+    Opcode_wsr_excsave2_encode_fns, 0, 0 },
+  { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
+    0,
+    Opcode_xsr_excsave2_encode_fns, 0, 0 },
+  { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3,
+    0,
+    Opcode_rsr_epc3_encode_fns, 0, 0 },
+  { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3,
+    0,
+    Opcode_wsr_epc3_encode_fns, 0, 0 },
+  { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3,
+    0,
+    Opcode_xsr_epc3_encode_fns, 0, 0 },
+  { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3,
+    0,
+    Opcode_rsr_excsave3_encode_fns, 0, 0 },
+  { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3,
+    0,
+    Opcode_wsr_excsave3_encode_fns, 0, 0 },
+  { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3,
+    0,
+    Opcode_xsr_excsave3_encode_fns, 0, 0 },
+  { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4,
+    0,
+    Opcode_rsr_epc4_encode_fns, 0, 0 },
+  { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4,
+    0,
+    Opcode_wsr_epc4_encode_fns, 0, 0 },
+  { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4,
+    0,
+    Opcode_xsr_epc4_encode_fns, 0, 0 },
+  { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4,
+    0,
+    Opcode_rsr_excsave4_encode_fns, 0, 0 },
+  { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4,
+    0,
+    Opcode_wsr_excsave4_encode_fns, 0, 0 },
+  { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4,
+    0,
+    Opcode_xsr_excsave4_encode_fns, 0, 0 },
+  { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5,
+    0,
+    Opcode_rsr_epc5_encode_fns, 0, 0 },
+  { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5,
+    0,
+    Opcode_wsr_epc5_encode_fns, 0, 0 },
+  { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5,
+    0,
+    Opcode_xsr_epc5_encode_fns, 0, 0 },
+  { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5,
+    0,
+    Opcode_rsr_excsave5_encode_fns, 0, 0 },
+  { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5,
+    0,
+    Opcode_wsr_excsave5_encode_fns, 0, 0 },
+  { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5,
+    0,
+    Opcode_xsr_excsave5_encode_fns, 0, 0 },
+  { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6,
+    0,
+    Opcode_rsr_epc6_encode_fns, 0, 0 },
+  { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6,
+    0,
+    Opcode_wsr_epc6_encode_fns, 0, 0 },
+  { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6,
+    0,
+    Opcode_xsr_epc6_encode_fns, 0, 0 },
+  { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6,
+    0,
+    Opcode_rsr_excsave6_encode_fns, 0, 0 },
+  { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6,
+    0,
+    Opcode_wsr_excsave6_encode_fns, 0, 0 },
+  { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6,
+    0,
+    Opcode_xsr_excsave6_encode_fns, 0, 0 },
+  { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7,
+    0,
+    Opcode_rsr_epc7_encode_fns, 0, 0 },
+  { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7,
+    0,
+    Opcode_wsr_epc7_encode_fns, 0, 0 },
+  { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7,
+    0,
+    Opcode_xsr_epc7_encode_fns, 0, 0 },
+  { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7,
+    0,
+    Opcode_rsr_excsave7_encode_fns, 0, 0 },
+  { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7,
+    0,
+    Opcode_wsr_excsave7_encode_fns, 0, 0 },
+  { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7,
+    0,
+    Opcode_xsr_excsave7_encode_fns, 0, 0 },
+  { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
+    0,
+    Opcode_rsr_eps2_encode_fns, 0, 0 },
+  { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
+    0,
+    Opcode_wsr_eps2_encode_fns, 0, 0 },
+  { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
+    0,
+    Opcode_xsr_eps2_encode_fns, 0, 0 },
+  { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3,
+    0,
+    Opcode_rsr_eps3_encode_fns, 0, 0 },
+  { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3,
+    0,
+    Opcode_wsr_eps3_encode_fns, 0, 0 },
+  { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3,
+    0,
+    Opcode_xsr_eps3_encode_fns, 0, 0 },
+  { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4,
+    0,
+    Opcode_rsr_eps4_encode_fns, 0, 0 },
+  { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4,
+    0,
+    Opcode_wsr_eps4_encode_fns, 0, 0 },
+  { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4,
+    0,
+    Opcode_xsr_eps4_encode_fns, 0, 0 },
+  { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5,
+    0,
+    Opcode_rsr_eps5_encode_fns, 0, 0 },
+  { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5,
+    0,
+    Opcode_wsr_eps5_encode_fns, 0, 0 },
+  { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5,
+    0,
+    Opcode_xsr_eps5_encode_fns, 0, 0 },
+  { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6,
+    0,
+    Opcode_rsr_eps6_encode_fns, 0, 0 },
+  { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6,
+    0,
+    Opcode_wsr_eps6_encode_fns, 0, 0 },
+  { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6,
+    0,
+    Opcode_xsr_eps6_encode_fns, 0, 0 },
+  { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7,
+    0,
+    Opcode_rsr_eps7_encode_fns, 0, 0 },
+  { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7,
+    0,
+    Opcode_wsr_eps7_encode_fns, 0, 0 },
+  { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7,
+    0,
+    Opcode_xsr_eps7_encode_fns, 0, 0 },
+  { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
+    0,
+    Opcode_rsr_excvaddr_encode_fns, 0, 0 },
+  { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
+    0,
+    Opcode_wsr_excvaddr_encode_fns, 0, 0 },
+  { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
+    0,
+    Opcode_xsr_excvaddr_encode_fns, 0, 0 },
+  { "rsr.depc", ICLASS_xt_iclass_rsr_depc,
+    0,
+    Opcode_rsr_depc_encode_fns, 0, 0 },
+  { "wsr.depc", ICLASS_xt_iclass_wsr_depc,
+    0,
+    Opcode_wsr_depc_encode_fns, 0, 0 },
+  { "xsr.depc", ICLASS_xt_iclass_xsr_depc,
+    0,
+    Opcode_xsr_depc_encode_fns, 0, 0 },
+  { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
+    0,
+    Opcode_rsr_exccause_encode_fns, 0, 0 },
+  { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
+    0,
+    Opcode_wsr_exccause_encode_fns, 0, 0 },
+  { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
+    0,
+    Opcode_xsr_exccause_encode_fns, 0, 0 },
+  { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0,
+    0,
+    Opcode_rsr_misc0_encode_fns, 0, 0 },
+  { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0,
+    0,
+    Opcode_wsr_misc0_encode_fns, 0, 0 },
+  { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0,
+    0,
+    Opcode_xsr_misc0_encode_fns, 0, 0 },
+  { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
+    0,
+    Opcode_rsr_misc1_encode_fns, 0, 0 },
+  { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
+    0,
+    Opcode_wsr_misc1_encode_fns, 0, 0 },
+  { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
+    0,
+    Opcode_xsr_misc1_encode_fns, 0, 0 },
+  { "rsr.misc2", ICLASS_xt_iclass_rsr_misc2,
+    0,
+    Opcode_rsr_misc2_encode_fns, 0, 0 },
+  { "wsr.misc2", ICLASS_xt_iclass_wsr_misc2,
+    0,
+    Opcode_wsr_misc2_encode_fns, 0, 0 },
+  { "xsr.misc2", ICLASS_xt_iclass_xsr_misc2,
+    0,
+    Opcode_xsr_misc2_encode_fns, 0, 0 },
+  { "rsr.misc3", ICLASS_xt_iclass_rsr_misc3,
+    0,
+    Opcode_rsr_misc3_encode_fns, 0, 0 },
+  { "wsr.misc3", ICLASS_xt_iclass_wsr_misc3,
+    0,
+    Opcode_wsr_misc3_encode_fns, 0, 0 },
+  { "xsr.misc3", ICLASS_xt_iclass_xsr_misc3,
+    0,
+    Opcode_xsr_misc3_encode_fns, 0, 0 },
+  { "rsr.prid", ICLASS_xt_iclass_rsr_prid,
+    0,
+    Opcode_rsr_prid_encode_fns, 0, 0 },
+  { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
+    0,
+    Opcode_rsr_vecbase_encode_fns, 0, 0 },
+  { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
+    0,
+    Opcode_wsr_vecbase_encode_fns, 0, 0 },
+  { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
+    0,
+    Opcode_xsr_vecbase_encode_fns, 0, 0 },
+  { "salt", ICLASS_xt_iclass_salt,
+    0,
+    Opcode_salt_encode_fns, 0, 0 },
+  { "saltu", ICLASS_xt_iclass_salt,
+    0,
+    Opcode_saltu_encode_fns, 0, 0 },
+  { "mul16u", ICLASS_xt_mul16,
+    0,
+    Opcode_mul16u_encode_fns, 0, 0 },
+  { "mul16s", ICLASS_xt_mul16,
+    0,
+    Opcode_mul16s_encode_fns, 0, 0 },
+  { "mull", ICLASS_xt_mul32,
+    0,
+    Opcode_mull_encode_fns, 0, 0 },
+  { "muluh", ICLASS_xt_mul32h,
+    0,
+    Opcode_muluh_encode_fns, 0, 0 },
+  { "mulsh", ICLASS_xt_mul32h,
+    0,
+    Opcode_mulsh_encode_fns, 0, 0 },
+  { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa,
+    0,
+    Opcode_mul_aa_ll_encode_fns, 0, 0 },
+  { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa,
+    0,
+    Opcode_mul_aa_hl_encode_fns, 0, 0 },
+  { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa,
+    0,
+    Opcode_mul_aa_lh_encode_fns, 0, 0 },
+  { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa,
+    0,
+    Opcode_mul_aa_hh_encode_fns, 0, 0 },
+  { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa,
+    0,
+    Opcode_umul_aa_ll_encode_fns, 0, 0 },
+  { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa,
+    0,
+    Opcode_umul_aa_hl_encode_fns, 0, 0 },
+  { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa,
+    0,
+    Opcode_umul_aa_lh_encode_fns, 0, 0 },
+  { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa,
+    0,
+    Opcode_umul_aa_hh_encode_fns, 0, 0 },
+  { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad,
+    0,
+    Opcode_mul_ad_ll_encode_fns, 0, 0 },
+  { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad,
+    0,
+    Opcode_mul_ad_hl_encode_fns, 0, 0 },
+  { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad,
+    0,
+    Opcode_mul_ad_lh_encode_fns, 0, 0 },
+  { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad,
+    0,
+    Opcode_mul_ad_hh_encode_fns, 0, 0 },
+  { "mul.da.ll", ICLASS_xt_iclass_mac16_da,
+    0,
+    Opcode_mul_da_ll_encode_fns, 0, 0 },
+  { "mul.da.hl", ICLASS_xt_iclass_mac16_da,
+    0,
+    Opcode_mul_da_hl_encode_fns, 0, 0 },
+  { "mul.da.lh", ICLASS_xt_iclass_mac16_da,
+    0,
+    Opcode_mul_da_lh_encode_fns, 0, 0 },
+  { "mul.da.hh", ICLASS_xt_iclass_mac16_da,
+    0,
+    Opcode_mul_da_hh_encode_fns, 0, 0 },
+  { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd,
+    0,
+    Opcode_mul_dd_ll_encode_fns, 0, 0 },
+  { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd,
+    0,
+    Opcode_mul_dd_hl_encode_fns, 0, 0 },
+  { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd,
+    0,
+    Opcode_mul_dd_lh_encode_fns, 0, 0 },
+  { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd,
+    0,
+    Opcode_mul_dd_hh_encode_fns, 0, 0 },
+  { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa,
+    0,
+    Opcode_mula_aa_ll_encode_fns, 0, 0 },
+  { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa,
+    0,
+    Opcode_mula_aa_hl_encode_fns, 0, 0 },
+  { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa,
+    0,
+    Opcode_mula_aa_lh_encode_fns, 0, 0 },
+  { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa,
+    0,
+    Opcode_mula_aa_hh_encode_fns, 0, 0 },
+  { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa,
+    0,
+    Opcode_muls_aa_ll_encode_fns, 0, 0 },
+  { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa,
+    0,
+    Opcode_muls_aa_hl_encode_fns, 0, 0 },
+  { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa,
+    0,
+    Opcode_muls_aa_lh_encode_fns, 0, 0 },
+  { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa,
+    0,
+    Opcode_muls_aa_hh_encode_fns, 0, 0 },
+  { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad,
+    0,
+    Opcode_mula_ad_ll_encode_fns, 0, 0 },
+  { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad,
+    0,
+    Opcode_mula_ad_hl_encode_fns, 0, 0 },
+  { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad,
+    0,
+    Opcode_mula_ad_lh_encode_fns, 0, 0 },
+  { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad,
+    0,
+    Opcode_mula_ad_hh_encode_fns, 0, 0 },
+  { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad,
+    0,
+    Opcode_muls_ad_ll_encode_fns, 0, 0 },
+  { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad,
+    0,
+    Opcode_muls_ad_hl_encode_fns, 0, 0 },
+  { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad,
+    0,
+    Opcode_muls_ad_lh_encode_fns, 0, 0 },
+  { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad,
+    0,
+    Opcode_muls_ad_hh_encode_fns, 0, 0 },
+  { "mula.da.ll", ICLASS_xt_iclass_mac16a_da,
+    0,
+    Opcode_mula_da_ll_encode_fns, 0, 0 },
+  { "mula.da.hl", ICLASS_xt_iclass_mac16a_da,
+    0,
+    Opcode_mula_da_hl_encode_fns, 0, 0 },
+  { "mula.da.lh", ICLASS_xt_iclass_mac16a_da,
+    0,
+    Opcode_mula_da_lh_encode_fns, 0, 0 },
+  { "mula.da.hh", ICLASS_xt_iclass_mac16a_da,
+    0,
+    Opcode_mula_da_hh_encode_fns, 0, 0 },
+  { "muls.da.ll", ICLASS_xt_iclass_mac16a_da,
+    0,
+    Opcode_muls_da_ll_encode_fns, 0, 0 },
+  { "muls.da.hl", ICLASS_xt_iclass_mac16a_da,
+    0,
+    Opcode_muls_da_hl_encode_fns, 0, 0 },
+  { "muls.da.lh", ICLASS_xt_iclass_mac16a_da,
+    0,
+    Opcode_muls_da_lh_encode_fns, 0, 0 },
+  { "muls.da.hh", ICLASS_xt_iclass_mac16a_da,
+    0,
+    Opcode_muls_da_hh_encode_fns, 0, 0 },
+  { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd,
+    0,
+    Opcode_mula_dd_ll_encode_fns, 0, 0 },
+  { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd,
+    0,
+    Opcode_mula_dd_hl_encode_fns, 0, 0 },
+  { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd,
+    0,
+    Opcode_mula_dd_lh_encode_fns, 0, 0 },
+  { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd,
+    0,
+    Opcode_mula_dd_hh_encode_fns, 0, 0 },
+  { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd,
+    0,
+    Opcode_muls_dd_ll_encode_fns, 0, 0 },
+  { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd,
+    0,
+    Opcode_muls_dd_hl_encode_fns, 0, 0 },
+  { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd,
+    0,
+    Opcode_muls_dd_lh_encode_fns, 0, 0 },
+  { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd,
+    0,
+    Opcode_muls_dd_hh_encode_fns, 0, 0 },
+  { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da,
+    0,
+    Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
+  { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da,
+    0,
+    Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
+  { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da,
+    0,
+    Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
+  { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da,
+    0,
+    Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
+  { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da,
+    0,
+    Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
+  { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da,
+    0,
+    Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
+  { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da,
+    0,
+    Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
+  { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da,
+    0,
+    Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
+  { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd,
+    0,
+    Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
+  { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd,
+    0,
+    Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
+  { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd,
+    0,
+    Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
+  { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd,
+    0,
+    Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
+  { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd,
+    0,
+    Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
+  { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd,
+    0,
+    Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
+  { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd,
+    0,
+    Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
+  { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd,
+    0,
+    Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
+  { "lddec", ICLASS_xt_iclass_mac16_l,
+    0,
+    Opcode_lddec_encode_fns, 0, 0 },
+  { "ldinc", ICLASS_xt_iclass_mac16_l,
+    0,
+    Opcode_ldinc_encode_fns, 0, 0 },
+  { "rsr.m0", ICLASS_xt_iclass_rsr_m0,
+    0,
+    Opcode_rsr_m0_encode_fns, 0, 0 },
+  { "wsr.m0", ICLASS_xt_iclass_wsr_m0,
+    0,
+    Opcode_wsr_m0_encode_fns, 0, 0 },
+  { "xsr.m0", ICLASS_xt_iclass_xsr_m0,
+    0,
+    Opcode_xsr_m0_encode_fns, 0, 0 },
+  { "rsr.m1", ICLASS_xt_iclass_rsr_m1,
+    0,
+    Opcode_rsr_m1_encode_fns, 0, 0 },
+  { "wsr.m1", ICLASS_xt_iclass_wsr_m1,
+    0,
+    Opcode_wsr_m1_encode_fns, 0, 0 },
+  { "xsr.m1", ICLASS_xt_iclass_xsr_m1,
+    0,
+    Opcode_xsr_m1_encode_fns, 0, 0 },
+  { "rsr.m2", ICLASS_xt_iclass_rsr_m2,
+    0,
+    Opcode_rsr_m2_encode_fns, 0, 0 },
+  { "wsr.m2", ICLASS_xt_iclass_wsr_m2,
+    0,
+    Opcode_wsr_m2_encode_fns, 0, 0 },
+  { "xsr.m2", ICLASS_xt_iclass_xsr_m2,
+    0,
+    Opcode_xsr_m2_encode_fns, 0, 0 },
+  { "rsr.m3", ICLASS_xt_iclass_rsr_m3,
+    0,
+    Opcode_rsr_m3_encode_fns, 0, 0 },
+  { "wsr.m3", ICLASS_xt_iclass_wsr_m3,
+    0,
+    Opcode_wsr_m3_encode_fns, 0, 0 },
+  { "xsr.m3", ICLASS_xt_iclass_xsr_m3,
+    0,
+    Opcode_xsr_m3_encode_fns, 0, 0 },
+  { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo,
+    0,
+    Opcode_rsr_acclo_encode_fns, 0, 0 },
+  { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo,
+    0,
+    Opcode_wsr_acclo_encode_fns, 0, 0 },
+  { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo,
+    0,
+    Opcode_xsr_acclo_encode_fns, 0, 0 },
+  { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi,
+    0,
+    Opcode_rsr_acchi_encode_fns, 0, 0 },
+  { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi,
+    0,
+    Opcode_wsr_acchi_encode_fns, 0, 0 },
+  { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi,
+    0,
+    Opcode_xsr_acchi_encode_fns, 0, 0 },
+  { "rfi", ICLASS_xt_iclass_rfi,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_rfi_encode_fns, 0, 0 },
+  { "waiti", ICLASS_xt_iclass_wait,
+    0,
+    Opcode_waiti_encode_fns, 0, 0 },
+  { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
+    0,
+    Opcode_rsr_interrupt_encode_fns, 0, 0 },
+  { "wsr.intset", ICLASS_xt_iclass_wsr_intset,
+    0,
+    Opcode_wsr_intset_encode_fns, 0, 0 },
+  { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
+    0,
+    Opcode_wsr_intclear_encode_fns, 0, 0 },
+  { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
+    0,
+    Opcode_rsr_intenable_encode_fns, 0, 0 },
+  { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
+    0,
+    Opcode_wsr_intenable_encode_fns, 0, 0 },
+  { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
+    0,
+    Opcode_xsr_intenable_encode_fns, 0, 0 },
+  { "break", ICLASS_xt_iclass_break,
+    0,
+    Opcode_break_encode_fns, 0, 0 },
+  { "break.n", ICLASS_xt_iclass_break_n,
+    0,
+    Opcode_break_n_encode_fns, 0, 0 },
+  { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0,
+    0,
+    Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
+  { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0,
+    0,
+    Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
+  { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0,
+    0,
+    Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
+  { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0,
+    0,
+    Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
+  { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0,
+    0,
+    Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
+  { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0,
+    0,
+    Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
+  { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1,
+    0,
+    Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
+  { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1,
+    0,
+    Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
+  { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1,
+    0,
+    Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
+  { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1,
+    0,
+    Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
+  { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1,
+    0,
+    Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
+  { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1,
+    0,
+    Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
+  { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0,
+    0,
+    Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
+  { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0,
+    0,
+    Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
+  { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0,
+    0,
+    Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
+  { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1,
+    0,
+    Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
+  { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1,
+    0,
+    Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
+  { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1,
+    0,
+    Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
+  { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable,
+    0,
+    Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
+  { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable,
+    0,
+    Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
+  { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable,
+    0,
+    Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
+  { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
+    0,
+    Opcode_rsr_debugcause_encode_fns, 0, 0 },
+  { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
+    0,
+    Opcode_wsr_debugcause_encode_fns, 0, 0 },
+  { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
+    0,
+    Opcode_xsr_debugcause_encode_fns, 0, 0 },
+  { "rsr.icount", ICLASS_xt_iclass_rsr_icount,
+    0,
+    Opcode_rsr_icount_encode_fns, 0, 0 },
+  { "wsr.icount", ICLASS_xt_iclass_wsr_icount,
+    0,
+    Opcode_wsr_icount_encode_fns, 0, 0 },
+  { "xsr.icount", ICLASS_xt_iclass_xsr_icount,
+    0,
+    Opcode_xsr_icount_encode_fns, 0, 0 },
+  { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
+    0,
+    Opcode_rsr_icountlevel_encode_fns, 0, 0 },
+  { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
+    0,
+    Opcode_wsr_icountlevel_encode_fns, 0, 0 },
+  { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
+    0,
+    Opcode_xsr_icountlevel_encode_fns, 0, 0 },
+  { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
+    0,
+    Opcode_rsr_ddr_encode_fns, 0, 0 },
+  { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
+    0,
+    Opcode_wsr_ddr_encode_fns, 0, 0 },
+  { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
+    0,
+    Opcode_xsr_ddr_encode_fns, 0, 0 },
+  { "lddr32.p", ICLASS_xt_iclass_lddr32_p,
+    0,
+    Opcode_lddr32_p_encode_fns, 0, 0 },
+  { "sddr32.p", ICLASS_xt_iclass_sddr32_p,
+    0,
+    Opcode_sddr32_p_encode_fns, 0, 0 },
+  { "rfdo", ICLASS_xt_iclass_rfdo,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_rfdo_encode_fns, 0, 0 },
+  { "rfdd", ICLASS_xt_iclass_rfdd,
+    XTENSA_OPCODE_IS_JUMP,
+    Opcode_rfdd_encode_fns, 0, 0 },
+  { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid,
+    0,
+    Opcode_wsr_mmid_encode_fns, 0, 0 },
+  { "andb", ICLASS_xt_iclass_bbool1,
+    0,
+    Opcode_andb_encode_fns, 0, 0 },
+  { "andbc", ICLASS_xt_iclass_bbool1,
+    0,
+    Opcode_andbc_encode_fns, 0, 0 },
+  { "orb", ICLASS_xt_iclass_bbool1,
+    0,
+    Opcode_orb_encode_fns, 0, 0 },
+  { "orbc", ICLASS_xt_iclass_bbool1,
+    0,
+    Opcode_orbc_encode_fns, 0, 0 },
+  { "xorb", ICLASS_xt_iclass_bbool1,
+    0,
+    Opcode_xorb_encode_fns, 0, 0 },
+  { "any4", ICLASS_xt_iclass_bbool4,
+    0,
+    Opcode_any4_encode_fns, 0, 0 },
+  { "all4", ICLASS_xt_iclass_bbool4,
+    0,
+    Opcode_all4_encode_fns, 0, 0 },
+  { "any8", ICLASS_xt_iclass_bbool8,
+    0,
+    Opcode_any8_encode_fns, 0, 0 },
+  { "all8", ICLASS_xt_iclass_bbool8,
+    0,
+    Opcode_all8_encode_fns, 0, 0 },
+  { "bf", ICLASS_xt_iclass_bbranch,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bf_encode_fns, 0, 0 },
+  { "bt", ICLASS_xt_iclass_bbranch,
+    XTENSA_OPCODE_IS_BRANCH,
+    Opcode_bt_encode_fns, 0, 0 },
+  { "movf", ICLASS_xt_iclass_bmove,
+    0,
+    Opcode_movf_encode_fns, 0, 0 },
+  { "movt", ICLASS_xt_iclass_bmove,
+    0,
+    Opcode_movt_encode_fns, 0, 0 },
+  { "rsr.br", ICLASS_xt_iclass_RSR_BR,
+    0,
+    Opcode_rsr_br_encode_fns, 0, 0 },
+  { "wsr.br", ICLASS_xt_iclass_WSR_BR,
+    0,
+    Opcode_wsr_br_encode_fns, 0, 0 },
+  { "xsr.br", ICLASS_xt_iclass_XSR_BR,
+    0,
+    Opcode_xsr_br_encode_fns, 0, 0 },
+  { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
+    0,
+    Opcode_rsr_ccount_encode_fns, 0, 0 },
+  { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
+    0,
+    Opcode_wsr_ccount_encode_fns, 0, 0 },
+  { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
+    0,
+    Opcode_xsr_ccount_encode_fns, 0, 0 },
+  { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
+    0,
+    Opcode_rsr_ccompare0_encode_fns, 0, 0 },
+  { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
+    0,
+    Opcode_wsr_ccompare0_encode_fns, 0, 0 },
+  { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
+    0,
+    Opcode_xsr_ccompare0_encode_fns, 0, 0 },
+  { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1,
+    0,
+    Opcode_rsr_ccompare1_encode_fns, 0, 0 },
+  { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1,
+    0,
+    Opcode_wsr_ccompare1_encode_fns, 0, 0 },
+  { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1,
+    0,
+    Opcode_xsr_ccompare1_encode_fns, 0, 0 },
+  { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2,
+    0,
+    Opcode_rsr_ccompare2_encode_fns, 0, 0 },
+  { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2,
+    0,
+    Opcode_wsr_ccompare2_encode_fns, 0, 0 },
+  { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2,
+    0,
+    Opcode_xsr_ccompare2_encode_fns, 0, 0 },
+  { "idtlb", ICLASS_xt_iclass_idtlb,
+    0,
+    Opcode_idtlb_encode_fns, 0, 0 },
+  { "pdtlb", ICLASS_xt_iclass_rdtlb,
+    0,
+    Opcode_pdtlb_encode_fns, 0, 0 },
+  { "rdtlb0", ICLASS_xt_iclass_rdtlb,
+    0,
+    Opcode_rdtlb0_encode_fns, 0, 0 },
+  { "rdtlb1", ICLASS_xt_iclass_rdtlb,
+    0,
+    Opcode_rdtlb1_encode_fns, 0, 0 },
+  { "wdtlb", ICLASS_xt_iclass_wdtlb,
+    0,
+    Opcode_wdtlb_encode_fns, 0, 0 },
+  { "iitlb", ICLASS_xt_iclass_iitlb,
+    0,
+    Opcode_iitlb_encode_fns, 0, 0 },
+  { "pitlb", ICLASS_xt_iclass_ritlb,
+    0,
+    Opcode_pitlb_encode_fns, 0, 0 },
+  { "ritlb0", ICLASS_xt_iclass_ritlb,
+    0,
+    Opcode_ritlb0_encode_fns, 0, 0 },
+  { "ritlb1", ICLASS_xt_iclass_ritlb,
+    0,
+    Opcode_ritlb1_encode_fns, 0, 0 },
+  { "witlb", ICLASS_xt_iclass_witlb,
+    0,
+    Opcode_witlb_encode_fns, 0, 0 },
+  { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable,
+    0,
+    Opcode_rsr_cpenable_encode_fns, 0, 0 },
+  { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable,
+    0,
+    Opcode_wsr_cpenable_encode_fns, 0, 0 },
+  { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable,
+    0,
+    Opcode_xsr_cpenable_encode_fns, 0, 0 },
+  { "clamps", ICLASS_xt_iclass_clamp,
+    0,
+    Opcode_clamps_encode_fns, 0, 0 },
+  { "min", ICLASS_xt_iclass_minmax,
+    0,
+    Opcode_min_encode_fns, 0, 0 },
+  { "max", ICLASS_xt_iclass_minmax,
+    0,
+    Opcode_max_encode_fns, 0, 0 },
+  { "minu", ICLASS_xt_iclass_minmax,
+    0,
+    Opcode_minu_encode_fns, 0, 0 },
+  { "maxu", ICLASS_xt_iclass_minmax,
+    0,
+    Opcode_maxu_encode_fns, 0, 0 },
+  { "nsa", ICLASS_xt_iclass_nsa,
+    0,
+    Opcode_nsa_encode_fns, 0, 0 },
+  { "nsau", ICLASS_xt_iclass_nsa,
+    0,
+    Opcode_nsau_encode_fns, 0, 0 },
+  { "sext", ICLASS_xt_iclass_sx,
+    0,
+    Opcode_sext_encode_fns, 0, 0 },
+  { "l32ai", ICLASS_xt_iclass_l32ai,
+    0,
+    Opcode_l32ai_encode_fns, 0, 0 },
+  { "s32ri", ICLASS_xt_iclass_s32ri,
+    0,
+    Opcode_s32ri_encode_fns, 0, 0 },
+  { "s32c1i", ICLASS_xt_iclass_s32c1i,
+    0,
+    Opcode_s32c1i_encode_fns, 0, 0 },
+  { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1,
+    0,
+    Opcode_rsr_scompare1_encode_fns, 0, 0 },
+  { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1,
+    0,
+    Opcode_wsr_scompare1_encode_fns, 0, 0 },
+  { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1,
+    0,
+    Opcode_xsr_scompare1_encode_fns, 0, 0 },
+  { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl,
+    0,
+    Opcode_rsr_atomctl_encode_fns, 0, 0 },
+  { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl,
+    0,
+    Opcode_wsr_atomctl_encode_fns, 0, 0 },
+  { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl,
+    0,
+    Opcode_xsr_atomctl_encode_fns, 0, 0 },
+  { "quou", ICLASS_xt_iclass_div,
+    0,
+    Opcode_quou_encode_fns, 0, 0 },
+  { "quos", ICLASS_xt_iclass_div,
+    0,
+    Opcode_quos_encode_fns, 0, 0 },
+  { "remu", ICLASS_xt_iclass_div,
+    0,
+    Opcode_remu_encode_fns, 0, 0 },
+  { "rems", ICLASS_xt_iclass_div,
+    0,
+    Opcode_rems_encode_fns, 0, 0 },
+  { "rsr.eraccess", ICLASS_xt_iclass_rsr_eraccess,
+    0,
+    Opcode_rsr_eraccess_encode_fns, 0, 0 },
+  { "wsr.eraccess", ICLASS_xt_iclass_wsr_eraccess,
+    0,
+    Opcode_wsr_eraccess_encode_fns, 0, 0 },
+  { "xsr.eraccess", ICLASS_xt_iclass_xsr_eraccess,
+    0,
+    Opcode_xsr_eraccess_encode_fns, 0, 0 },
+  { "rer", ICLASS_xt_iclass_rer,
+    0,
+    Opcode_rer_encode_fns, 0, 0 },
+  { "wer", ICLASS_xt_iclass_wer,
+    0,
+    Opcode_wer_encode_fns, 0, 0 },
+  { "rur.fcr", ICLASS_rur_fcr,
+    0,
+    Opcode_rur_fcr_encode_fns, 0, 0 },
+  { "wur.fcr", ICLASS_wur_fcr,
+    0,
+    Opcode_wur_fcr_encode_fns, 0, 0 },
+  { "rur.fsr", ICLASS_rur_fsr,
+    0,
+    Opcode_rur_fsr_encode_fns, 0, 0 },
+  { "wur.fsr", ICLASS_wur_fsr,
+    0,
+    Opcode_wur_fsr_encode_fns, 0, 0 },
+  { "st.qr", ICLASS_st_QR,
+    0,
+    Opcode_st_qr_encode_fns, 0, 0 },
+  { "ld.qr", ICLASS_ld_QR,
+    0,
+    Opcode_ld_qr_encode_fns, 0, 0 },
+  { "mv.qr", ICLASS_mv_QR,
+    0,
+    Opcode_mv_qr_encode_fns, 0, 0 },
+  { "ee.wr_mask_gpio_out", ICLASS_EE_WR_MASK_GPIO_OUT,
+    0,
+    Opcode_ee_wr_mask_gpio_out_encode_fns, 0, 0 },
+  { "ee.set_bit_gpio_out", ICLASS_EE_SET_BIT_GPIO_OUT,
+    0,
+    Opcode_ee_set_bit_gpio_out_encode_fns, 0, 0 },
+  { "ee.clr_bit_gpio_out", ICLASS_EE_CLR_BIT_GPIO_OUT,
+    0,
+    Opcode_ee_clr_bit_gpio_out_encode_fns, 0, 0 },
+  { "ee.get_gpio_in", ICLASS_EE_GET_GPIO_IN,
+    0,
+    Opcode_ee_get_gpio_in_encode_fns, 0, 0 },
+  { "ee.vld.128.ip", ICLASS_EE_VLD_128_IP,
+    0,
+    Opcode_ee_vld_128_ip_encode_fns, 9, Opcode_ee_vld_128_ip_funcUnit_uses },
+  { "ee.vld.128.xp", ICLASS_EE_VLD_128_XP,
+    0,
+    Opcode_ee_vld_128_xp_encode_fns, 9, Opcode_ee_vld_128_xp_funcUnit_uses },
+  { "ee.vld.h.64.ip", ICLASS_EE_VLD_H_64_IP,
+    0,
+    Opcode_ee_vld_h_64_ip_encode_fns, 9, Opcode_ee_vld_h_64_ip_funcUnit_uses },
+  { "ee.vld.h.64.xp", ICLASS_EE_VLD_H_64_XP,
+    0,
+    Opcode_ee_vld_h_64_xp_encode_fns, 9, Opcode_ee_vld_h_64_xp_funcUnit_uses },
+  { "ee.vld.l.64.ip", ICLASS_EE_VLD_L_64_IP,
+    0,
+    Opcode_ee_vld_l_64_ip_encode_fns, 9, Opcode_ee_vld_l_64_ip_funcUnit_uses },
+  { "ee.vld.l.64.xp", ICLASS_EE_VLD_L_64_XP,
+    0,
+    Opcode_ee_vld_l_64_xp_encode_fns, 9, Opcode_ee_vld_l_64_xp_funcUnit_uses },
+  { "ee.vldbc.16.ip", ICLASS_EE_VLDBC_16_IP,
+    0,
+    Opcode_ee_vldbc_16_ip_encode_fns, 9, Opcode_ee_vldbc_16_ip_funcUnit_uses },
+  { "ee.vldbc.16", ICLASS_EE_VLDBC_16,
+    0,
+    Opcode_ee_vldbc_16_encode_fns, 9, Opcode_ee_vldbc_16_funcUnit_uses },
+  { "ee.vldbc.16.xp", ICLASS_EE_VLDBC_16_XP,
+    0,
+    Opcode_ee_vldbc_16_xp_encode_fns, 9, Opcode_ee_vldbc_16_xp_funcUnit_uses },
+  { "ee.vldbc.32.ip", ICLASS_EE_VLDBC_32_IP,
+    0,
+    Opcode_ee_vldbc_32_ip_encode_fns, 9, Opcode_ee_vldbc_32_ip_funcUnit_uses },
+  { "ee.vldbc.32", ICLASS_EE_VLDBC_32,
+    0,
+    Opcode_ee_vldbc_32_encode_fns, 9, Opcode_ee_vldbc_32_funcUnit_uses },
+  { "ee.vldbc.32.xp", ICLASS_EE_VLDBC_32_XP,
+    0,
+    Opcode_ee_vldbc_32_xp_encode_fns, 9, Opcode_ee_vldbc_32_xp_funcUnit_uses },
+  { "ee.vldbc.8.ip", ICLASS_EE_VLDBC_8_IP,
+    0,
+    Opcode_ee_vldbc_8_ip_encode_fns, 9, Opcode_ee_vldbc_8_ip_funcUnit_uses },
+  { "ee.vldbc.8", ICLASS_EE_VLDBC_8,
+    0,
+    Opcode_ee_vldbc_8_encode_fns, 9, Opcode_ee_vldbc_8_funcUnit_uses },
+  { "ee.vldbc.8.xp", ICLASS_EE_VLDBC_8_XP,
+    0,
+    Opcode_ee_vldbc_8_xp_encode_fns, 9, Opcode_ee_vldbc_8_xp_funcUnit_uses },
+  { "ee.vldhbc.16.incp", ICLASS_EE_VLDHBC_16_INCP,
+    0,
+    Opcode_ee_vldhbc_16_incp_encode_fns, 9, Opcode_ee_vldhbc_16_incp_funcUnit_uses },
+  { "ee.ldf.128.ip", ICLASS_EE_LDF_128_IP,
+    0,
+    Opcode_ee_ldf_128_ip_encode_fns, 9, Opcode_ee_ldf_128_ip_funcUnit_uses },
+  { "ee.ldf.128.xp", ICLASS_EE_LDF_128_XP,
+    0,
+    Opcode_ee_ldf_128_xp_encode_fns, 9, Opcode_ee_ldf_128_xp_funcUnit_uses },
+  { "ee.ldf.64.ip", ICLASS_EE_LDF_64_IP,
+    0,
+    Opcode_ee_ldf_64_ip_encode_fns, 9, Opcode_ee_ldf_64_ip_funcUnit_uses },
+  { "ee.ldf.64.xp", ICLASS_EE_LDF_64_XP,
+    0,
+    Opcode_ee_ldf_64_xp_encode_fns, 9, Opcode_ee_ldf_64_xp_funcUnit_uses },
+  { "ee.ld.128.usar.ip", ICLASS_EE_LD_128_USAR_IP,
+    0,
+    Opcode_ee_ld_128_usar_ip_encode_fns, 9, Opcode_ee_ld_128_usar_ip_funcUnit_uses },
+  { "ee.ld.128.usar.xp", ICLASS_EE_LD_128_USAR_XP,
+    0,
+    Opcode_ee_ld_128_usar_xp_encode_fns, 9, Opcode_ee_ld_128_usar_xp_funcUnit_uses },
+  { "ee.ldqa.s16.128.ip", ICLASS_EE_LDQA_S16_128_IP,
+    0,
+    Opcode_ee_ldqa_s16_128_ip_encode_fns, 9, Opcode_ee_ldqa_s16_128_ip_funcUnit_uses },
+  { "ee.ldqa.s16.128.xp", ICLASS_EE_LDQA_S16_128_XP,
+    0,
+    Opcode_ee_ldqa_s16_128_xp_encode_fns, 9, Opcode_ee_ldqa_s16_128_xp_funcUnit_uses },
+  { "ee.ldqa.s8.128.ip", ICLASS_EE_LDQA_S8_128_IP,
+    0,
+    Opcode_ee_ldqa_s8_128_ip_encode_fns, 9, Opcode_ee_ldqa_s8_128_ip_funcUnit_uses },
+  { "ee.ldqa.s8.128.xp", ICLASS_EE_LDQA_S8_128_XP,
+    0,
+    Opcode_ee_ldqa_s8_128_xp_encode_fns, 9, Opcode_ee_ldqa_s8_128_xp_funcUnit_uses },
+  { "ee.ldqa.u16.128.ip", ICLASS_EE_LDQA_U16_128_IP,
+    0,
+    Opcode_ee_ldqa_u16_128_ip_encode_fns, 9, Opcode_ee_ldqa_u16_128_ip_funcUnit_uses },
+  { "ee.ldqa.u16.128.xp", ICLASS_EE_LDQA_U16_128_XP,
+    0,
+    Opcode_ee_ldqa_u16_128_xp_encode_fns, 9, Opcode_ee_ldqa_u16_128_xp_funcUnit_uses },
+  { "ee.ldqa.u8.128.ip", ICLASS_EE_LDQA_U8_128_IP,
+    0,
+    Opcode_ee_ldqa_u8_128_ip_encode_fns, 9, Opcode_ee_ldqa_u8_128_ip_funcUnit_uses },
+  { "ee.ldqa.u8.128.xp", ICLASS_EE_LDQA_U8_128_XP,
+    0,
+    Opcode_ee_ldqa_u8_128_xp_encode_fns, 9, Opcode_ee_ldqa_u8_128_xp_funcUnit_uses },
+  { "ee.ld.qacc_h.h.32.ip", ICLASS_EE_LD_QACC_H_H_32_IP,
+    0,
+    Opcode_ee_ld_qacc_h_h_32_ip_encode_fns, 9, Opcode_ee_ld_qacc_h_h_32_ip_funcUnit_uses },
+  { "ee.ld.qacc_h.l.128.ip", ICLASS_EE_LD_QACC_H_L_128_IP,
+    0,
+    Opcode_ee_ld_qacc_h_l_128_ip_encode_fns, 9, Opcode_ee_ld_qacc_h_l_128_ip_funcUnit_uses },
+  { "ee.ld.qacc_l.h.32.ip", ICLASS_EE_LD_QACC_L_H_32_IP,
+    0,
+    Opcode_ee_ld_qacc_l_h_32_ip_encode_fns, 9, Opcode_ee_ld_qacc_l_h_32_ip_funcUnit_uses },
+  { "ee.ld.qacc_l.l.128.ip", ICLASS_EE_LD_QACC_L_L_128_IP,
+    0,
+    Opcode_ee_ld_qacc_l_l_128_ip_encode_fns, 9, Opcode_ee_ld_qacc_l_l_128_ip_funcUnit_uses },
+  { "ee.ld.accx.ip", ICLASS_EE_LD_ACCX_IP,
+    0,
+    Opcode_ee_ld_accx_ip_encode_fns, 9, Opcode_ee_ld_accx_ip_funcUnit_uses },
+  { "ee.ldxq.32", ICLASS_EE_LDXQ_32,
+    0,
+    Opcode_ee_ldxq_32_encode_fns, 9, Opcode_ee_ldxq_32_funcUnit_uses },
+  { "ee.ld.ua_state.ip", ICLASS_EE_LD_UA_STATE_IP,
+    0,
+    Opcode_ee_ld_ua_state_ip_encode_fns, 9, Opcode_ee_ld_ua_state_ip_funcUnit_uses },
+  { "ee.st.ua_state.ip", ICLASS_EE_ST_UA_STATE_IP,
+    0,
+    Opcode_ee_st_ua_state_ip_encode_fns, 9, Opcode_ee_st_ua_state_ip_funcUnit_uses },
+  { "ee.vst.128.ip", ICLASS_EE_VST_128_IP,
+    0,
+    Opcode_ee_vst_128_ip_encode_fns, 9, Opcode_ee_vst_128_ip_funcUnit_uses },
+  { "ee.vst.128.xp", ICLASS_EE_VST_128_XP,
+    0,
+    Opcode_ee_vst_128_xp_encode_fns, 9, Opcode_ee_vst_128_xp_funcUnit_uses },
+  { "ee.vst.h.64.ip", ICLASS_EE_VST_H_64_IP,
+    0,
+    Opcode_ee_vst_h_64_ip_encode_fns, 9, Opcode_ee_vst_h_64_ip_funcUnit_uses },
+  { "ee.vst.h.64.xp", ICLASS_EE_VST_H_64_XP,
+    0,
+    Opcode_ee_vst_h_64_xp_encode_fns, 9, Opcode_ee_vst_h_64_xp_funcUnit_uses },
+  { "ee.vst.l.64.ip", ICLASS_EE_VST_L_64_IP,
+    0,
+    Opcode_ee_vst_l_64_ip_encode_fns, 9, Opcode_ee_vst_l_64_ip_funcUnit_uses },
+  { "ee.vst.l.64.xp", ICLASS_EE_VST_L_64_XP,
+    0,
+    Opcode_ee_vst_l_64_xp_encode_fns, 9, Opcode_ee_vst_l_64_xp_funcUnit_uses },
+  { "ee.stf.128.ip", ICLASS_EE_STF_128_IP,
+    0,
+    Opcode_ee_stf_128_ip_encode_fns, 9, Opcode_ee_stf_128_ip_funcUnit_uses },
+  { "ee.stf.128.xp", ICLASS_EE_STF_128_XP,
+    0,
+    Opcode_ee_stf_128_xp_encode_fns, 9, Opcode_ee_stf_128_xp_funcUnit_uses },
+  { "ee.stf.64.ip", ICLASS_EE_STF_64_IP,
+    0,
+    Opcode_ee_stf_64_ip_encode_fns, 9, Opcode_ee_stf_64_ip_funcUnit_uses },
+  { "ee.stf.64.xp", ICLASS_EE_STF_64_XP,
+    0,
+    Opcode_ee_stf_64_xp_encode_fns, 9, Opcode_ee_stf_64_xp_funcUnit_uses },
+  { "ee.st.qacc_h.h.32.ip", ICLASS_EE_ST_QACC_H_H_32_IP,
+    0,
+    Opcode_ee_st_qacc_h_h_32_ip_encode_fns, 9, Opcode_ee_st_qacc_h_h_32_ip_funcUnit_uses },
+  { "ee.st.qacc_h.l.128.ip", ICLASS_EE_ST_QACC_H_L_128_IP,
+    0,
+    Opcode_ee_st_qacc_h_l_128_ip_encode_fns, 9, Opcode_ee_st_qacc_h_l_128_ip_funcUnit_uses },
+  { "ee.st.qacc_l.h.32.ip", ICLASS_EE_ST_QACC_L_H_32_IP,
+    0,
+    Opcode_ee_st_qacc_l_h_32_ip_encode_fns, 9, Opcode_ee_st_qacc_l_h_32_ip_funcUnit_uses },
+  { "ee.st.qacc_l.l.128.ip", ICLASS_EE_ST_QACC_L_L_128_IP,
+    0,
+    Opcode_ee_st_qacc_l_l_128_ip_encode_fns, 9, Opcode_ee_st_qacc_l_l_128_ip_funcUnit_uses },
+  { "ee.st.accx.ip", ICLASS_EE_ST_ACCX_IP,
+    0,
+    Opcode_ee_st_accx_ip_encode_fns, 9, Opcode_ee_st_accx_ip_funcUnit_uses },
+  { "ee.stxq.32", ICLASS_EE_STXQ_32,
+    0,
+    Opcode_ee_stxq_32_encode_fns, 9, Opcode_ee_stxq_32_funcUnit_uses },
+  { "ee.movi.32.a", ICLASS_EE_MOVI_32_A,
+    0,
+    Opcode_ee_movi_32_a_encode_fns, 0, 0 },
+  { "ee.movi.32.q", ICLASS_EE_MOVI_32_Q,
+    0,
+    Opcode_ee_movi_32_q_encode_fns, 0, 0 },
+  { "ee.vzip.16", ICLASS_EE_VZIP_16,
+    0,
+    Opcode_ee_vzip_16_encode_fns, 0, 0 },
+  { "ee.vzip.32", ICLASS_EE_VZIP_32,
+    0,
+    Opcode_ee_vzip_32_encode_fns, 0, 0 },
+  { "ee.vzip.8", ICLASS_EE_VZIP_8,
+    0,
+    Opcode_ee_vzip_8_encode_fns, 0, 0 },
+  { "ee.vunzip.16", ICLASS_EE_VUNZIP_16,
+    0,
+    Opcode_ee_vunzip_16_encode_fns, 0, 0 },
+  { "ee.vunzip.32", ICLASS_EE_VUNZIP_32,
+    0,
+    Opcode_ee_vunzip_32_encode_fns, 0, 0 },
+  { "ee.vunzip.8", ICLASS_EE_VUNZIP_8,
+    0,
+    Opcode_ee_vunzip_8_encode_fns, 0, 0 },
+  { "ee.zero.accx", ICLASS_EE_ZERO_ACCX,
+    0,
+    Opcode_ee_zero_accx_encode_fns, 0, 0 },
+  { "ee.zero.qacc", ICLASS_EE_ZERO_QACC,
+    0,
+    Opcode_ee_zero_qacc_encode_fns, 0, 0 },
+  { "ee.zero.q", ICLASS_EE_ZERO_Q,
+    0,
+    Opcode_ee_zero_q_encode_fns, 0, 0 },
+  { "ee.mov.s16.qacc", ICLASS_EE_MOV_S16_QACC,
+    0,
+    Opcode_ee_mov_s16_qacc_encode_fns, 0, 0 },
+  { "ee.mov.s8.qacc", ICLASS_EE_MOV_S8_QACC,
+    0,
+    Opcode_ee_mov_s8_qacc_encode_fns, 0, 0 },
+  { "ee.mov.u16.qacc", ICLASS_EE_MOV_U16_QACC,
+    0,
+    Opcode_ee_mov_u16_qacc_encode_fns, 0, 0 },
+  { "ee.mov.u8.qacc", ICLASS_EE_MOV_U8_QACC,
+    0,
+    Opcode_ee_mov_u8_qacc_encode_fns, 0, 0 },
+  { "ee.vadds.s16.ld.incp", ICLASS_EE_VADDS_S16_LD_INCP,
+    0,
+    Opcode_ee_vadds_s16_ld_incp_encode_fns, 77, Opcode_ee_vadds_s16_ld_incp_funcUnit_uses },
+  { "ee.vadds.s16.st.incp", ICLASS_EE_VADDS_S16_ST_INCP,
+    0,
+    Opcode_ee_vadds_s16_st_incp_encode_fns, 77, Opcode_ee_vadds_s16_st_incp_funcUnit_uses },
+  { "ee.vadds.s16", ICLASS_EE_VADDS_S16,
+    0,
+    Opcode_ee_vadds_s16_encode_fns, 77, Opcode_ee_vadds_s16_funcUnit_uses },
+  { "ee.vadds.s32.ld.incp", ICLASS_EE_VADDS_S32_LD_INCP,
+    0,
+    Opcode_ee_vadds_s32_ld_incp_encode_fns, 77, Opcode_ee_vadds_s32_ld_incp_funcUnit_uses },
+  { "ee.vadds.s32.st.incp", ICLASS_EE_VADDS_S32_ST_INCP,
+    0,
+    Opcode_ee_vadds_s32_st_incp_encode_fns, 77, Opcode_ee_vadds_s32_st_incp_funcUnit_uses },
+  { "ee.vadds.s32", ICLASS_EE_VADDS_S32,
+    0,
+    Opcode_ee_vadds_s32_encode_fns, 77, Opcode_ee_vadds_s32_funcUnit_uses },
+  { "ee.vadds.s8.ld.incp", ICLASS_EE_VADDS_S8_LD_INCP,
+    0,
+    Opcode_ee_vadds_s8_ld_incp_encode_fns, 77, Opcode_ee_vadds_s8_ld_incp_funcUnit_uses },
+  { "ee.vadds.s8.st.incp", ICLASS_EE_VADDS_S8_ST_INCP,
+    0,
+    Opcode_ee_vadds_s8_st_incp_encode_fns, 77, Opcode_ee_vadds_s8_st_incp_funcUnit_uses },
+  { "ee.vadds.s8", ICLASS_EE_VADDS_S8,
+    0,
+    Opcode_ee_vadds_s8_encode_fns, 77, Opcode_ee_vadds_s8_funcUnit_uses },
+  { "ee.vsubs.s16.ld.incp", ICLASS_EE_VSUBS_S16_LD_INCP,
+    0,
+    Opcode_ee_vsubs_s16_ld_incp_encode_fns, 77, Opcode_ee_vsubs_s16_ld_incp_funcUnit_uses },
+  { "ee.vsubs.s16.st.incp", ICLASS_EE_VSUBS_S16_ST_INCP,
+    0,
+    Opcode_ee_vsubs_s16_st_incp_encode_fns, 77, Opcode_ee_vsubs_s16_st_incp_funcUnit_uses },
+  { "ee.vsubs.s16", ICLASS_EE_VSUBS_S16,
+    0,
+    Opcode_ee_vsubs_s16_encode_fns, 77, Opcode_ee_vsubs_s16_funcUnit_uses },
+  { "ee.vsubs.s32.ld.incp", ICLASS_EE_VSUBS_S32_LD_INCP,
+    0,
+    Opcode_ee_vsubs_s32_ld_incp_encode_fns, 77, Opcode_ee_vsubs_s32_ld_incp_funcUnit_uses },
+  { "ee.vsubs.s32.st.incp", ICLASS_EE_VSUBS_S32_ST_INCP,
+    0,
+    Opcode_ee_vsubs_s32_st_incp_encode_fns, 77, Opcode_ee_vsubs_s32_st_incp_funcUnit_uses },
+  { "ee.vsubs.s32", ICLASS_EE_VSUBS_S32,
+    0,
+    Opcode_ee_vsubs_s32_encode_fns, 77, Opcode_ee_vsubs_s32_funcUnit_uses },
+  { "ee.vsubs.s8.ld.incp", ICLASS_EE_VSUBS_S8_LD_INCP,
+    0,
+    Opcode_ee_vsubs_s8_ld_incp_encode_fns, 77, Opcode_ee_vsubs_s8_ld_incp_funcUnit_uses },
+  { "ee.vsubs.s8.st.incp", ICLASS_EE_VSUBS_S8_ST_INCP,
+    0,
+    Opcode_ee_vsubs_s8_st_incp_encode_fns, 77, Opcode_ee_vsubs_s8_st_incp_funcUnit_uses },
+  { "ee.vsubs.s8", ICLASS_EE_VSUBS_S8,
+    0,
+    Opcode_ee_vsubs_s8_encode_fns, 77, Opcode_ee_vsubs_s8_funcUnit_uses },
+  { "ee.vmul.s16.ld.incp", ICLASS_EE_VMUL_S16_LD_INCP,
+    0,
+    Opcode_ee_vmul_s16_ld_incp_encode_fns, 77, Opcode_ee_vmul_s16_ld_incp_funcUnit_uses },
+  { "ee.vmul.s16.st.incp", ICLASS_EE_VMUL_S16_ST_INCP,
+    0,
+    Opcode_ee_vmul_s16_st_incp_encode_fns, 77, Opcode_ee_vmul_s16_st_incp_funcUnit_uses },
+  { "ee.vmul.s16", ICLASS_EE_VMUL_S16,
+    0,
+    Opcode_ee_vmul_s16_encode_fns, 77, Opcode_ee_vmul_s16_funcUnit_uses },
+  { "ee.vmul.s8.ld.incp", ICLASS_EE_VMUL_S8_LD_INCP,
+    0,
+    Opcode_ee_vmul_s8_ld_incp_encode_fns, 77, Opcode_ee_vmul_s8_ld_incp_funcUnit_uses },
+  { "ee.vmul.s8.st.incp", ICLASS_EE_VMUL_S8_ST_INCP,
+    0,
+    Opcode_ee_vmul_s8_st_incp_encode_fns, 77, Opcode_ee_vmul_s8_st_incp_funcUnit_uses },
+  { "ee.vmul.s8", ICLASS_EE_VMUL_S8,
+    0,
+    Opcode_ee_vmul_s8_encode_fns, 77, Opcode_ee_vmul_s8_funcUnit_uses },
+  { "ee.vmul.u16.ld.incp", ICLASS_EE_VMUL_U16_LD_INCP,
+    0,
+    Opcode_ee_vmul_u16_ld_incp_encode_fns, 77, Opcode_ee_vmul_u16_ld_incp_funcUnit_uses },
+  { "ee.vmul.u16.st.incp", ICLASS_EE_VMUL_U16_ST_INCP,
+    0,
+    Opcode_ee_vmul_u16_st_incp_encode_fns, 77, Opcode_ee_vmul_u16_st_incp_funcUnit_uses },
+  { "ee.vmul.u16", ICLASS_EE_VMUL_U16,
+    0,
+    Opcode_ee_vmul_u16_encode_fns, 77, Opcode_ee_vmul_u16_funcUnit_uses },
+  { "ee.vmul.u8.ld.incp", ICLASS_EE_VMUL_U8_LD_INCP,
+    0,
+    Opcode_ee_vmul_u8_ld_incp_encode_fns, 77, Opcode_ee_vmul_u8_ld_incp_funcUnit_uses },
+  { "ee.vmul.u8.st.incp", ICLASS_EE_VMUL_U8_ST_INCP,
+    0,
+    Opcode_ee_vmul_u8_st_incp_encode_fns, 77, Opcode_ee_vmul_u8_st_incp_funcUnit_uses },
+  { "ee.vmul.u8", ICLASS_EE_VMUL_U8,
+    0,
+    Opcode_ee_vmul_u8_encode_fns, 77, Opcode_ee_vmul_u8_funcUnit_uses },
+  { "ee.cmul.s16.ld.incp", ICLASS_EE_CMUL_S16_LD_INCP,
+    0,
+    Opcode_ee_cmul_s16_ld_incp_encode_fns, 77, Opcode_ee_cmul_s16_ld_incp_funcUnit_uses },
+  { "ee.cmul.s16.st.incp", ICLASS_EE_CMUL_S16_ST_INCP,
+    0,
+    Opcode_ee_cmul_s16_st_incp_encode_fns, 77, Opcode_ee_cmul_s16_st_incp_funcUnit_uses },
+  { "ee.cmul.s16", ICLASS_EE_CMUL_S16,
+    0,
+    Opcode_ee_cmul_s16_encode_fns, 77, Opcode_ee_cmul_s16_funcUnit_uses },
+  { "ee.vmulas.s16.accx.ld.ip.qup", ICLASS_EE_VMULAS_S16_ACCX_LD_IP_QUP,
+    0,
+    Opcode_ee_vmulas_s16_accx_ld_ip_qup_encode_fns, 77, Opcode_ee_vmulas_s16_accx_ld_ip_qup_funcUnit_uses },
+  { "ee.vmulas.s16.accx.ld.ip", ICLASS_EE_VMULAS_S16_ACCX_LD_IP,
+    0,
+    Opcode_ee_vmulas_s16_accx_ld_ip_encode_fns, 77, Opcode_ee_vmulas_s16_accx_ld_ip_funcUnit_uses },
+  { "ee.vmulas.s16.accx.ld.xp.qup", ICLASS_EE_VMULAS_S16_ACCX_LD_XP_QUP,
+    0,
+    Opcode_ee_vmulas_s16_accx_ld_xp_qup_encode_fns, 77, Opcode_ee_vmulas_s16_accx_ld_xp_qup_funcUnit_uses },
+  { "ee.vmulas.s16.accx.ld.xp", ICLASS_EE_VMULAS_S16_ACCX_LD_XP,
+    0,
+    Opcode_ee_vmulas_s16_accx_ld_xp_encode_fns, 77, Opcode_ee_vmulas_s16_accx_ld_xp_funcUnit_uses },
+  { "ee.vmulas.s16.accx", ICLASS_EE_VMULAS_S16_ACCX,
+    0,
+    Opcode_ee_vmulas_s16_accx_encode_fns, 77, Opcode_ee_vmulas_s16_accx_funcUnit_uses },
+  { "ee.vmulas.s8.accx.ld.ip.qup", ICLASS_EE_VMULAS_S8_ACCX_LD_IP_QUP,
+    0,
+    Opcode_ee_vmulas_s8_accx_ld_ip_qup_encode_fns, 77, Opcode_ee_vmulas_s8_accx_ld_ip_qup_funcUnit_uses },
+  { "ee.vmulas.s8.accx.ld.ip", ICLASS_EE_VMULAS_S8_ACCX_LD_IP,
+    0,
+    Opcode_ee_vmulas_s8_accx_ld_ip_encode_fns, 77, Opcode_ee_vmulas_s8_accx_ld_ip_funcUnit_uses },
+  { "ee.vmulas.s8.accx.ld.xp.qup", ICLASS_EE_VMULAS_S8_ACCX_LD_XP_QUP,
+    0,
+    Opcode_ee_vmulas_s8_accx_ld_xp_qup_encode_fns, 77, Opcode_ee_vmulas_s8_accx_ld_xp_qup_funcUnit_uses },
+  { "ee.vmulas.s8.accx.ld.xp", ICLASS_EE_VMULAS_S8_ACCX_LD_XP,
+    0,
+    Opcode_ee_vmulas_s8_accx_ld_xp_encode_fns, 77, Opcode_ee_vmulas_s8_accx_ld_xp_funcUnit_uses },
+  { "ee.vmulas.s8.accx", ICLASS_EE_VMULAS_S8_ACCX,
+    0,
+    Opcode_ee_vmulas_s8_accx_encode_fns, 77, Opcode_ee_vmulas_s8_accx_funcUnit_uses },
+  { "ee.vmulas.u16.accx.ld.ip.qup", ICLASS_EE_VMULAS_U16_ACCX_LD_IP_QUP,
+    0,
+    Opcode_ee_vmulas_u16_accx_ld_ip_qup_encode_fns, 77, Opcode_ee_vmulas_u16_accx_ld_ip_qup_funcUnit_uses },
+  { "ee.vmulas.u16.accx.ld.ip", ICLASS_EE_VMULAS_U16_ACCX_LD_IP,
+    0,
+    Opcode_ee_vmulas_u16_accx_ld_ip_encode_fns, 77, Opcode_ee_vmulas_u16_accx_ld_ip_funcUnit_uses },
+  { "ee.vmulas.u16.accx.ld.xp.qup", ICLASS_EE_VMULAS_U16_ACCX_LD_XP_QUP,
+    0,
+    Opcode_ee_vmulas_u16_accx_ld_xp_qup_encode_fns, 77, Opcode_ee_vmulas_u16_accx_ld_xp_qup_funcUnit_uses },
+  { "ee.vmulas.u16.accx.ld.xp", ICLASS_EE_VMULAS_U16_ACCX_LD_XP,
+    0,
+    Opcode_ee_vmulas_u16_accx_ld_xp_encode_fns, 77, Opcode_ee_vmulas_u16_accx_ld_xp_funcUnit_uses },
+  { "ee.vmulas.u16.accx", ICLASS_EE_VMULAS_U16_ACCX,
+    0,
+    Opcode_ee_vmulas_u16_accx_encode_fns, 77, Opcode_ee_vmulas_u16_accx_funcUnit_uses },
+  { "ee.vmulas.u8.accx.ld.ip.qup", ICLASS_EE_VMULAS_U8_ACCX_LD_IP_QUP,
+    0,
+    Opcode_ee_vmulas_u8_accx_ld_ip_qup_encode_fns, 77, Opcode_ee_vmulas_u8_accx_ld_ip_qup_funcUnit_uses },
+  { "ee.vmulas.u8.accx.ld.ip", ICLASS_EE_VMULAS_U8_ACCX_LD_IP,
+    0,
+    Opcode_ee_vmulas_u8_accx_ld_ip_encode_fns, 77, Opcode_ee_vmulas_u8_accx_ld_ip_funcUnit_uses },
+  { "ee.vmulas.u8.accx.ld.xp.qup", ICLASS_EE_VMULAS_U8_ACCX_LD_XP_QUP,
+    0,
+    Opcode_ee_vmulas_u8_accx_ld_xp_qup_encode_fns, 77, Opcode_ee_vmulas_u8_accx_ld_xp_qup_funcUnit_uses },
+  { "ee.vmulas.u8.accx.ld.xp", ICLASS_EE_VMULAS_U8_ACCX_LD_XP,
+    0,
+    Opcode_ee_vmulas_u8_accx_ld_xp_encode_fns, 77, Opcode_ee_vmulas_u8_accx_ld_xp_funcUnit_uses },
+  { "ee.vmulas.u8.accx", ICLASS_EE_VMULAS_U8_ACCX,
+    0,
+    Opcode_ee_vmulas_u8_accx_encode_fns, 77, Opcode_ee_vmulas_u8_accx_funcUnit_uses },
+  { "ee.vmulas.s16.qacc.ldbc.incp.qup", ICLASS_EE_VMULAS_S16_QACC_LDBC_INCP_QUP,
+    0,
+    Opcode_ee_vmulas_s16_qacc_ldbc_incp_qup_encode_fns, 77, Opcode_ee_vmulas_s16_qacc_ldbc_incp_qup_funcUnit_uses },
+  { "ee.vmulas.s16.qacc.ldbc.incp", ICLASS_EE_VMULAS_S16_QACC_LDBC_INCP,
+    0,
+    Opcode_ee_vmulas_s16_qacc_ldbc_incp_encode_fns, 77, Opcode_ee_vmulas_s16_qacc_ldbc_incp_funcUnit_uses },
+  { "ee.vmulas.s16.qacc.ld.ip.qup", ICLASS_EE_VMULAS_S16_QACC_LD_IP_QUP,
+    0,
+    Opcode_ee_vmulas_s16_qacc_ld_ip_qup_encode_fns, 77, Opcode_ee_vmulas_s16_qacc_ld_ip_qup_funcUnit_uses },
+  { "ee.vmulas.s16.qacc.ld.ip", ICLASS_EE_VMULAS_S16_QACC_LD_IP,
+    0,
+    Opcode_ee_vmulas_s16_qacc_ld_ip_encode_fns, 77, Opcode_ee_vmulas_s16_qacc_ld_ip_funcUnit_uses },
+  { "ee.vmulas.s16.qacc.ld.xp.qup", ICLASS_EE_VMULAS_S16_QACC_LD_XP_QUP,
+    0,
+    Opcode_ee_vmulas_s16_qacc_ld_xp_qup_encode_fns, 77, Opcode_ee_vmulas_s16_qacc_ld_xp_qup_funcUnit_uses },
+  { "ee.vmulas.s16.qacc.ld.xp", ICLASS_EE_VMULAS_S16_QACC_LD_XP,
+    0,
+    Opcode_ee_vmulas_s16_qacc_ld_xp_encode_fns, 77, Opcode_ee_vmulas_s16_qacc_ld_xp_funcUnit_uses },
+  { "ee.vmulas.s16.qacc", ICLASS_EE_VMULAS_S16_QACC,
+    0,
+    Opcode_ee_vmulas_s16_qacc_encode_fns, 77, Opcode_ee_vmulas_s16_qacc_funcUnit_uses },
+  { "ee.vmulas.s8.qacc.ldbc.incp.qup", ICLASS_EE_VMULAS_S8_QACC_LDBC_INCP_QUP,
+    0,
+    Opcode_ee_vmulas_s8_qacc_ldbc_incp_qup_encode_fns, 77, Opcode_ee_vmulas_s8_qacc_ldbc_incp_qup_funcUnit_uses },
+  { "ee.vmulas.s8.qacc.ldbc.incp", ICLASS_EE_VMULAS_S8_QACC_LDBC_INCP,
+    0,
+    Opcode_ee_vmulas_s8_qacc_ldbc_incp_encode_fns, 77, Opcode_ee_vmulas_s8_qacc_ldbc_incp_funcUnit_uses },
+  { "ee.vmulas.s8.qacc.ld.ip.qup", ICLASS_EE_VMULAS_S8_QACC_LD_IP_QUP,
+    0,
+    Opcode_ee_vmulas_s8_qacc_ld_ip_qup_encode_fns, 77, Opcode_ee_vmulas_s8_qacc_ld_ip_qup_funcUnit_uses },
+  { "ee.vmulas.s8.qacc.ld.ip", ICLASS_EE_VMULAS_S8_QACC_LD_IP,
+    0,
+    Opcode_ee_vmulas_s8_qacc_ld_ip_encode_fns, 77, Opcode_ee_vmulas_s8_qacc_ld_ip_funcUnit_uses },
+  { "ee.vmulas.s8.qacc.ld.xp.qup", ICLASS_EE_VMULAS_S8_QACC_LD_XP_QUP,
+    0,
+    Opcode_ee_vmulas_s8_qacc_ld_xp_qup_encode_fns, 77, Opcode_ee_vmulas_s8_qacc_ld_xp_qup_funcUnit_uses },
+  { "ee.vmulas.s8.qacc.ld.xp", ICLASS_EE_VMULAS_S8_QACC_LD_XP,
+    0,
+    Opcode_ee_vmulas_s8_qacc_ld_xp_encode_fns, 77, Opcode_ee_vmulas_s8_qacc_ld_xp_funcUnit_uses },
+  { "ee.vmulas.s8.qacc", ICLASS_EE_VMULAS_S8_QACC,
+    0,
+    Opcode_ee_vmulas_s8_qacc_encode_fns, 77, Opcode_ee_vmulas_s8_qacc_funcUnit_uses },
+  { "ee.vmulas.u16.qacc.ldbc.incp.qup", ICLASS_EE_VMULAS_U16_QACC_LDBC_INCP_QUP,
+    0,
+    Opcode_ee_vmulas_u16_qacc_ldbc_incp_qup_encode_fns, 77, Opcode_ee_vmulas_u16_qacc_ldbc_incp_qup_funcUnit_uses },
+  { "ee.vmulas.u16.qacc.ldbc.incp", ICLASS_EE_VMULAS_U16_QACC_LDBC_INCP,
+    0,
+    Opcode_ee_vmulas_u16_qacc_ldbc_incp_encode_fns, 77, Opcode_ee_vmulas_u16_qacc_ldbc_incp_funcUnit_uses },
+  { "ee.vmulas.u16.qacc.ld.ip.qup", ICLASS_EE_VMULAS_U16_QACC_LD_IP_QUP,
+    0,
+    Opcode_ee_vmulas_u16_qacc_ld_ip_qup_encode_fns, 77, Opcode_ee_vmulas_u16_qacc_ld_ip_qup_funcUnit_uses },
+  { "ee.vmulas.u16.qacc.ld.ip", ICLASS_EE_VMULAS_U16_QACC_LD_IP,
+    0,
+    Opcode_ee_vmulas_u16_qacc_ld_ip_encode_fns, 77, Opcode_ee_vmulas_u16_qacc_ld_ip_funcUnit_uses },
+  { "ee.vmulas.u16.qacc.ld.xp.qup", ICLASS_EE_VMULAS_U16_QACC_LD_XP_QUP,
+    0,
+    Opcode_ee_vmulas_u16_qacc_ld_xp_qup_encode_fns, 77, Opcode_ee_vmulas_u16_qacc_ld_xp_qup_funcUnit_uses },
+  { "ee.vmulas.u16.qacc.ld.xp", ICLASS_EE_VMULAS_U16_QACC_LD_XP,
+    0,
+    Opcode_ee_vmulas_u16_qacc_ld_xp_encode_fns, 77, Opcode_ee_vmulas_u16_qacc_ld_xp_funcUnit_uses },
+  { "ee.vmulas.u16.qacc", ICLASS_EE_VMULAS_U16_QACC,
+    0,
+    Opcode_ee_vmulas_u16_qacc_encode_fns, 77, Opcode_ee_vmulas_u16_qacc_funcUnit_uses },
+  { "ee.vmulas.u8.qacc.ldbc.incp.qup", ICLASS_EE_VMULAS_U8_QACC_LDBC_INCP_QUP,
+    0,
+    Opcode_ee_vmulas_u8_qacc_ldbc_incp_qup_encode_fns, 77, Opcode_ee_vmulas_u8_qacc_ldbc_incp_qup_funcUnit_uses },
+  { "ee.vmulas.u8.qacc.ldbc.incp", ICLASS_EE_VMULAS_U8_QACC_LDBC_INCP,
+    0,
+    Opcode_ee_vmulas_u8_qacc_ldbc_incp_encode_fns, 77, Opcode_ee_vmulas_u8_qacc_ldbc_incp_funcUnit_uses },
+  { "ee.vmulas.u8.qacc.ld.ip.qup", ICLASS_EE_VMULAS_U8_QACC_LD_IP_QUP,
+    0,
+    Opcode_ee_vmulas_u8_qacc_ld_ip_qup_encode_fns, 77, Opcode_ee_vmulas_u8_qacc_ld_ip_qup_funcUnit_uses },
+  { "ee.vmulas.u8.qacc.ld.ip", ICLASS_EE_VMULAS_U8_QACC_LD_IP,
+    0,
+    Opcode_ee_vmulas_u8_qacc_ld_ip_encode_fns, 77, Opcode_ee_vmulas_u8_qacc_ld_ip_funcUnit_uses },
+  { "ee.vmulas.u8.qacc.ld.xp.qup", ICLASS_EE_VMULAS_U8_QACC_LD_XP_QUP,
+    0,
+    Opcode_ee_vmulas_u8_qacc_ld_xp_qup_encode_fns, 77, Opcode_ee_vmulas_u8_qacc_ld_xp_qup_funcUnit_uses },
+  { "ee.vmulas.u8.qacc.ld.xp", ICLASS_EE_VMULAS_U8_QACC_LD_XP,
+    0,
+    Opcode_ee_vmulas_u8_qacc_ld_xp_encode_fns, 77, Opcode_ee_vmulas_u8_qacc_ld_xp_funcUnit_uses },
+  { "ee.vmulas.u8.qacc", ICLASS_EE_VMULAS_U8_QACC,
+    0,
+    Opcode_ee_vmulas_u8_qacc_encode_fns, 77, Opcode_ee_vmulas_u8_qacc_funcUnit_uses },
+  { "ee.vsmulas.s16.qacc.ld.incp", ICLASS_EE_VSMULAS_S16_QACC_LD_INCP,
+    0,
+    Opcode_ee_vsmulas_s16_qacc_ld_incp_encode_fns, 77, Opcode_ee_vsmulas_s16_qacc_ld_incp_funcUnit_uses },
+  { "ee.vsmulas.s16.qacc", ICLASS_EE_VSMULAS_S16_QACC,
+    0,
+    Opcode_ee_vsmulas_s16_qacc_encode_fns, 77, Opcode_ee_vsmulas_s16_qacc_funcUnit_uses },
+  { "ee.vsmulas.s8.qacc.ld.incp", ICLASS_EE_VSMULAS_S8_QACC_LD_INCP,
+    0,
+    Opcode_ee_vsmulas_s8_qacc_ld_incp_encode_fns, 77, Opcode_ee_vsmulas_s8_qacc_ld_incp_funcUnit_uses },
+  { "ee.vsmulas.s8.qacc", ICLASS_EE_VSMULAS_S8_QACC,
+    0,
+    Opcode_ee_vsmulas_s8_qacc_encode_fns, 77, Opcode_ee_vsmulas_s8_qacc_funcUnit_uses },
+  { "ee.srcmb.s16.qacc", ICLASS_EE_SRCMB_S16_QACC,
+    0,
+    Opcode_ee_srcmb_s16_qacc_encode_fns, 24, Opcode_ee_srcmb_s16_qacc_funcUnit_uses },
+  { "ee.srcmb.s8.qacc", ICLASS_EE_SRCMB_S8_QACC,
+    0,
+    Opcode_ee_srcmb_s8_qacc_encode_fns, 24, Opcode_ee_srcmb_s8_qacc_funcUnit_uses },
+  { "ee.srs.accx", ICLASS_EE_SRS_ACCX,
+    0,
+    Opcode_ee_srs_accx_encode_fns, 2, Opcode_ee_srs_accx_funcUnit_uses },
+  { "ee.vrelu.s16", ICLASS_EE_VRELU_S16,
+    0,
+    Opcode_ee_vrelu_s16_encode_fns, 77, Opcode_ee_vrelu_s16_funcUnit_uses },
+  { "ee.vrelu.s8", ICLASS_EE_VRELU_S8,
+    0,
+    Opcode_ee_vrelu_s8_encode_fns, 77, Opcode_ee_vrelu_s8_funcUnit_uses },
+  { "ee.vprelu.s16", ICLASS_EE_VPRELU_S16,
+    0,
+    Opcode_ee_vprelu_s16_encode_fns, 77, Opcode_ee_vprelu_s16_funcUnit_uses },
+  { "ee.vprelu.s8", ICLASS_EE_VPRELU_S8,
+    0,
+    Opcode_ee_vprelu_s8_encode_fns, 77, Opcode_ee_vprelu_s8_funcUnit_uses },
+  { "ee.vmax.s16.ld.incp", ICLASS_EE_VMAX_S16_LD_INCP,
+    0,
+    Opcode_ee_vmax_s16_ld_incp_encode_fns, 77, Opcode_ee_vmax_s16_ld_incp_funcUnit_uses },
+  { "ee.vmax.s16.st.incp", ICLASS_EE_VMAX_S16_ST_INCP,
+    0,
+    Opcode_ee_vmax_s16_st_incp_encode_fns, 77, Opcode_ee_vmax_s16_st_incp_funcUnit_uses },
+  { "ee.vmax.s16", ICLASS_EE_VMAX_S16,
+    0,
+    Opcode_ee_vmax_s16_encode_fns, 77, Opcode_ee_vmax_s16_funcUnit_uses },
+  { "ee.vmax.s32.ld.incp", ICLASS_EE_VMAX_S32_LD_INCP,
+    0,
+    Opcode_ee_vmax_s32_ld_incp_encode_fns, 77, Opcode_ee_vmax_s32_ld_incp_funcUnit_uses },
+  { "ee.vmax.s32.st.incp", ICLASS_EE_VMAX_S32_ST_INCP,
+    0,
+    Opcode_ee_vmax_s32_st_incp_encode_fns, 77, Opcode_ee_vmax_s32_st_incp_funcUnit_uses },
+  { "ee.vmax.s32", ICLASS_EE_VMAX_S32,
+    0,
+    Opcode_ee_vmax_s32_encode_fns, 77, Opcode_ee_vmax_s32_funcUnit_uses },
+  { "ee.vmax.s8.ld.incp", ICLASS_EE_VMAX_S8_LD_INCP,
+    0,
+    Opcode_ee_vmax_s8_ld_incp_encode_fns, 77, Opcode_ee_vmax_s8_ld_incp_funcUnit_uses },
+  { "ee.vmax.s8.st.incp", ICLASS_EE_VMAX_S8_ST_INCP,
+    0,
+    Opcode_ee_vmax_s8_st_incp_encode_fns, 77, Opcode_ee_vmax_s8_st_incp_funcUnit_uses },
+  { "ee.vmax.s8", ICLASS_EE_VMAX_S8,
+    0,
+    Opcode_ee_vmax_s8_encode_fns, 77, Opcode_ee_vmax_s8_funcUnit_uses },
+  { "ee.vmin.s16.ld.incp", ICLASS_EE_VMIN_S16_LD_INCP,
+    0,
+    Opcode_ee_vmin_s16_ld_incp_encode_fns, 77, Opcode_ee_vmin_s16_ld_incp_funcUnit_uses },
+  { "ee.vmin.s16.st.incp", ICLASS_EE_VMIN_S16_ST_INCP,
+    0,
+    Opcode_ee_vmin_s16_st_incp_encode_fns, 77, Opcode_ee_vmin_s16_st_incp_funcUnit_uses },
+  { "ee.vmin.s16", ICLASS_EE_VMIN_S16,
+    0,
+    Opcode_ee_vmin_s16_encode_fns, 77, Opcode_ee_vmin_s16_funcUnit_uses },
+  { "ee.vmin.s32.ld.incp", ICLASS_EE_VMIN_S32_LD_INCP,
+    0,
+    Opcode_ee_vmin_s32_ld_incp_encode_fns, 77, Opcode_ee_vmin_s32_ld_incp_funcUnit_uses },
+  { "ee.vmin.s32.st.incp", ICLASS_EE_VMIN_S32_ST_INCP,
+    0,
+    Opcode_ee_vmin_s32_st_incp_encode_fns, 77, Opcode_ee_vmin_s32_st_incp_funcUnit_uses },
+  { "ee.vmin.s32", ICLASS_EE_VMIN_S32,
+    0,
+    Opcode_ee_vmin_s32_encode_fns, 77, Opcode_ee_vmin_s32_funcUnit_uses },
+  { "ee.vmin.s8.ld.incp", ICLASS_EE_VMIN_S8_LD_INCP,
+    0,
+    Opcode_ee_vmin_s8_ld_incp_encode_fns, 77, Opcode_ee_vmin_s8_ld_incp_funcUnit_uses },
+  { "ee.vmin.s8.st.incp", ICLASS_EE_VMIN_S8_ST_INCP,
+    0,
+    Opcode_ee_vmin_s8_st_incp_encode_fns, 77, Opcode_ee_vmin_s8_st_incp_funcUnit_uses },
+  { "ee.vmin.s8", ICLASS_EE_VMIN_S8,
+    0,
+    Opcode_ee_vmin_s8_encode_fns, 77, Opcode_ee_vmin_s8_funcUnit_uses },
+  { "ee.vcmp.eq.s16", ICLASS_EE_VCMP_EQ_S16,
+    0,
+    Opcode_ee_vcmp_eq_s16_encode_fns, 77, Opcode_ee_vcmp_eq_s16_funcUnit_uses },
+  { "ee.vcmp.eq.s32", ICLASS_EE_VCMP_EQ_S32,
+    0,
+    Opcode_ee_vcmp_eq_s32_encode_fns, 77, Opcode_ee_vcmp_eq_s32_funcUnit_uses },
+  { "ee.vcmp.eq.s8", ICLASS_EE_VCMP_EQ_S8,
+    0,
+    Opcode_ee_vcmp_eq_s8_encode_fns, 77, Opcode_ee_vcmp_eq_s8_funcUnit_uses },
+  { "ee.vcmp.gt.s16", ICLASS_EE_VCMP_GT_S16,
+    0,
+    Opcode_ee_vcmp_gt_s16_encode_fns, 77, Opcode_ee_vcmp_gt_s16_funcUnit_uses },
+  { "ee.vcmp.gt.s32", ICLASS_EE_VCMP_GT_S32,
+    0,
+    Opcode_ee_vcmp_gt_s32_encode_fns, 77, Opcode_ee_vcmp_gt_s32_funcUnit_uses },
+  { "ee.vcmp.gt.s8", ICLASS_EE_VCMP_GT_S8,
+    0,
+    Opcode_ee_vcmp_gt_s8_encode_fns, 77, Opcode_ee_vcmp_gt_s8_funcUnit_uses },
+  { "ee.vcmp.lt.s16", ICLASS_EE_VCMP_LT_S16,
+    0,
+    Opcode_ee_vcmp_lt_s16_encode_fns, 77, Opcode_ee_vcmp_lt_s16_funcUnit_uses },
+  { "ee.vcmp.lt.s32", ICLASS_EE_VCMP_LT_S32,
+    0,
+    Opcode_ee_vcmp_lt_s32_encode_fns, 77, Opcode_ee_vcmp_lt_s32_funcUnit_uses },
+  { "ee.vcmp.lt.s8", ICLASS_EE_VCMP_LT_S8,
+    0,
+    Opcode_ee_vcmp_lt_s8_encode_fns, 77, Opcode_ee_vcmp_lt_s8_funcUnit_uses },
+  { "ee.andq", ICLASS_EE_ANDQ,
+    0,
+    Opcode_ee_andq_encode_fns, 0, 0 },
+  { "ee.notq", ICLASS_EE_NOTQ,
+    0,
+    Opcode_ee_notq_encode_fns, 0, 0 },
+  { "ee.orq", ICLASS_EE_ORQ,
+    0,
+    Opcode_ee_orq_encode_fns, 0, 0 },
+  { "ee.xorq", ICLASS_EE_XORQ,
+    0,
+    Opcode_ee_xorq_encode_fns, 0, 0 },
+  { "ee.slci.2q", ICLASS_EE_SLCI_2Q,
+    0,
+    Opcode_ee_slci_2q_encode_fns, 1, Opcode_ee_slci_2q_funcUnit_uses },
+  { "ee.slcxxp.2q", ICLASS_EE_SLCXXP_2Q,
+    0,
+    Opcode_ee_slcxxp_2q_encode_fns, 1, Opcode_ee_slcxxp_2q_funcUnit_uses },
+  { "ee.srci.2q", ICLASS_EE_SRCI_2Q,
+    0,
+    Opcode_ee_srci_2q_encode_fns, 1, Opcode_ee_srci_2q_funcUnit_uses },
+  { "ee.srcq.128.st.incp", ICLASS_EE_SRCQ_128_ST_INCP,
+    0,
+    Opcode_ee_srcq_128_st_incp_encode_fns, 1, Opcode_ee_srcq_128_st_incp_funcUnit_uses },
+  { "ee.src.q.ld.ip", ICLASS_EE_SRC_Q_LD_IP,
+    0,
+    Opcode_ee_src_q_ld_ip_encode_fns, 1, Opcode_ee_src_q_ld_ip_funcUnit_uses },
+  { "ee.src.q.ld.xp", ICLASS_EE_SRC_Q_LD_XP,
+    0,
+    Opcode_ee_src_q_ld_xp_encode_fns, 1, Opcode_ee_src_q_ld_xp_funcUnit_uses },
+  { "ee.src.q.qup", ICLASS_EE_SRC_Q_QUP,
+    0,
+    Opcode_ee_src_q_qup_encode_fns, 1, Opcode_ee_src_q_qup_funcUnit_uses },
+  { "ee.src.q", ICLASS_EE_SRC_Q,
+    0,
+    Opcode_ee_src_q_encode_fns, 1, Opcode_ee_src_q_funcUnit_uses },
+  { "ee.srcxxp.2q", ICLASS_EE_SRCXXP_2Q,
+    0,
+    Opcode_ee_srcxxp_2q_encode_fns, 1, Opcode_ee_srcxxp_2q_funcUnit_uses },
+  { "ee.vsl.32", ICLASS_EE_VSL_32,
+    0,
+    Opcode_ee_vsl_32_encode_fns, 1, Opcode_ee_vsl_32_funcUnit_uses },
+  { "ee.vsr.32", ICLASS_EE_VSR_32,
+    0,
+    Opcode_ee_vsr_32_encode_fns, 1, Opcode_ee_vsr_32_funcUnit_uses },
+  { "ee.fft.r2bf.s16.st.incp", ICLASS_EE_FFT_R2BF_S16_ST_INCP,
+    0,
+    Opcode_ee_fft_r2bf_s16_st_incp_encode_fns, 17, Opcode_ee_fft_r2bf_s16_st_incp_funcUnit_uses },
+  { "ee.fft.r2bf.s16", ICLASS_EE_FFT_R2BF_S16,
+    0,
+    Opcode_ee_fft_r2bf_s16_encode_fns, 17, Opcode_ee_fft_r2bf_s16_funcUnit_uses },
+  { "ee.fft.cmul.s16.ld.xp", ICLASS_EE_FFT_CMUL_S16_LD_XP,
+    0,
+    Opcode_ee_fft_cmul_s16_ld_xp_encode_fns, 9, Opcode_ee_fft_cmul_s16_ld_xp_funcUnit_uses },
+  { "ee.fft.cmul.s16.st.xp", ICLASS_EE_FFT_CMUL_S16_ST_XP,
+    0,
+    Opcode_ee_fft_cmul_s16_st_xp_encode_fns, 9, Opcode_ee_fft_cmul_s16_st_xp_funcUnit_uses },
+  { "ee.bitrev", ICLASS_EE_BITREV,
+    0,
+    Opcode_ee_bitrev_encode_fns, 9, Opcode_ee_bitrev_funcUnit_uses },
+  { "ee.fft.ams.s16.ld.incp", ICLASS_EE_FFT_AMS_S16_LD_INCP,
+    0,
+    Opcode_ee_fft_ams_s16_ld_incp_encode_fns, 17, Opcode_ee_fft_ams_s16_ld_incp_funcUnit_uses },
+  { "ee.fft.ams.s16.ld.incp.uaup", ICLASS_EE_FFT_AMS_S16_LD_INCP_UAUP,
+    0,
+    Opcode_ee_fft_ams_s16_ld_incp_uaup_encode_fns, 17, Opcode_ee_fft_ams_s16_ld_incp_uaup_funcUnit_uses },
+  { "ee.fft.ams.s16.ld.r32.decp", ICLASS_EE_FFT_AMS_S16_LD_R32_DECP,
+    0,
+    Opcode_ee_fft_ams_s16_ld_r32_decp_encode_fns, 17, Opcode_ee_fft_ams_s16_ld_r32_decp_funcUnit_uses },
+  { "ee.fft.ams.s16.st.incp", ICLASS_EE_FFT_AMS_S16_ST_INCP,
+    0,
+    Opcode_ee_fft_ams_s16_st_incp_encode_fns, 17, Opcode_ee_fft_ams_s16_st_incp_funcUnit_uses },
+  { "ee.fft.vst.r32.decp", ICLASS_EE_FFT_VST_R32_DECP,
+    0,
+    Opcode_ee_fft_vst_r32_decp_encode_fns, 1, Opcode_ee_fft_vst_r32_decp_funcUnit_uses },
+  { "rur.accx_0", ICLASS_rur_accx_0,
+    0,
+    Opcode_rur_accx_0_encode_fns, 0, 0 },
+  { "wur.accx_0", ICLASS_wur_accx_0,
+    0,
+    Opcode_wur_accx_0_encode_fns, 0, 0 },
+  { "rur.accx_1", ICLASS_rur_accx_1,
+    0,
+    Opcode_rur_accx_1_encode_fns, 0, 0 },
+  { "wur.accx_1", ICLASS_wur_accx_1,
+    0,
+    Opcode_wur_accx_1_encode_fns, 0, 0 },
+  { "rur.qacc_h_0", ICLASS_rur_qacc_h_0,
+    0,
+    Opcode_rur_qacc_h_0_encode_fns, 0, 0 },
+  { "wur.qacc_h_0", ICLASS_wur_qacc_h_0,
+    0,
+    Opcode_wur_qacc_h_0_encode_fns, 0, 0 },
+  { "rur.qacc_h_1", ICLASS_rur_qacc_h_1,
+    0,
+    Opcode_rur_qacc_h_1_encode_fns, 0, 0 },
+  { "wur.qacc_h_1", ICLASS_wur_qacc_h_1,
+    0,
+    Opcode_wur_qacc_h_1_encode_fns, 0, 0 },
+  { "rur.qacc_h_2", ICLASS_rur_qacc_h_2,
+    0,
+    Opcode_rur_qacc_h_2_encode_fns, 0, 0 },
+  { "wur.qacc_h_2", ICLASS_wur_qacc_h_2,
+    0,
+    Opcode_wur_qacc_h_2_encode_fns, 0, 0 },
+  { "rur.qacc_h_3", ICLASS_rur_qacc_h_3,
+    0,
+    Opcode_rur_qacc_h_3_encode_fns, 0, 0 },
+  { "wur.qacc_h_3", ICLASS_wur_qacc_h_3,
+    0,
+    Opcode_wur_qacc_h_3_encode_fns, 0, 0 },
+  { "rur.qacc_h_4", ICLASS_rur_qacc_h_4,
+    0,
+    Opcode_rur_qacc_h_4_encode_fns, 0, 0 },
+  { "wur.qacc_h_4", ICLASS_wur_qacc_h_4,
+    0,
+    Opcode_wur_qacc_h_4_encode_fns, 0, 0 },
+  { "rur.qacc_l_0", ICLASS_rur_qacc_l_0,
+    0,
+    Opcode_rur_qacc_l_0_encode_fns, 0, 0 },
+  { "wur.qacc_l_0", ICLASS_wur_qacc_l_0,
+    0,
+    Opcode_wur_qacc_l_0_encode_fns, 0, 0 },
+  { "rur.qacc_l_1", ICLASS_rur_qacc_l_1,
+    0,
+    Opcode_rur_qacc_l_1_encode_fns, 0, 0 },
+  { "wur.qacc_l_1", ICLASS_wur_qacc_l_1,
+    0,
+    Opcode_wur_qacc_l_1_encode_fns, 0, 0 },
+  { "rur.qacc_l_2", ICLASS_rur_qacc_l_2,
+    0,
+    Opcode_rur_qacc_l_2_encode_fns, 0, 0 },
+  { "wur.qacc_l_2", ICLASS_wur_qacc_l_2,
+    0,
+    Opcode_wur_qacc_l_2_encode_fns, 0, 0 },
+  { "rur.qacc_l_3", ICLASS_rur_qacc_l_3,
+    0,
+    Opcode_rur_qacc_l_3_encode_fns, 0, 0 },
+  { "wur.qacc_l_3", ICLASS_wur_qacc_l_3,
+    0,
+    Opcode_wur_qacc_l_3_encode_fns, 0, 0 },
+  { "rur.qacc_l_4", ICLASS_rur_qacc_l_4,
+    0,
+    Opcode_rur_qacc_l_4_encode_fns, 0, 0 },
+  { "wur.qacc_l_4", ICLASS_wur_qacc_l_4,
+    0,
+    Opcode_wur_qacc_l_4_encode_fns, 0, 0 },
+  { "rur.gpio_out", ICLASS_rur_gpio_out,
+    0,
+    Opcode_rur_gpio_out_encode_fns, 0, 0 },
+  { "wur.gpio_out", ICLASS_wur_gpio_out,
+    0,
+    Opcode_wur_gpio_out_encode_fns, 0, 0 },
+  { "rur.sar_byte", ICLASS_rur_sar_byte,
+    0,
+    Opcode_rur_sar_byte_encode_fns, 0, 0 },
+  { "wur.sar_byte", ICLASS_wur_sar_byte,
+    0,
+    Opcode_wur_sar_byte_encode_fns, 0, 0 },
+  { "rur.fft_bit_width", ICLASS_rur_fft_bit_width,
+    0,
+    Opcode_rur_fft_bit_width_encode_fns, 0, 0 },
+  { "wur.fft_bit_width", ICLASS_wur_fft_bit_width,
+    0,
+    Opcode_wur_fft_bit_width_encode_fns, 0, 0 },
+  { "rur.ua_state_0", ICLASS_rur_ua_state_0,
+    0,
+    Opcode_rur_ua_state_0_encode_fns, 0, 0 },
+  { "wur.ua_state_0", ICLASS_wur_ua_state_0,
+    0,
+    Opcode_wur_ua_state_0_encode_fns, 0, 0 },
+  { "rur.ua_state_1", ICLASS_rur_ua_state_1,
+    0,
+    Opcode_rur_ua_state_1_encode_fns, 0, 0 },
+  { "wur.ua_state_1", ICLASS_wur_ua_state_1,
+    0,
+    Opcode_wur_ua_state_1_encode_fns, 0, 0 },
+  { "rur.ua_state_2", ICLASS_rur_ua_state_2,
+    0,
+    Opcode_rur_ua_state_2_encode_fns, 0, 0 },
+  { "wur.ua_state_2", ICLASS_wur_ua_state_2,
+    0,
+    Opcode_wur_ua_state_2_encode_fns, 0, 0 },
+  { "rur.ua_state_3", ICLASS_rur_ua_state_3,
+    0,
+    Opcode_rur_ua_state_3_encode_fns, 0, 0 },
+  { "wur.ua_state_3", ICLASS_wur_ua_state_3,
+    0,
+    Opcode_wur_ua_state_3_encode_fns, 0, 0 }
+};
+
+enum xtensa_opcode_id {
+  OPCODE_LSI,
+  OPCODE_LSIP,
+  OPCODE_LSX,
+  OPCODE_LSXP,
+  OPCODE_SSI,
+  OPCODE_SSIP,
+  OPCODE_SSX,
+  OPCODE_SSXP,
+  OPCODE_ABS_S,
+  OPCODE_NEG_S,
+  OPCODE_MOV_S,
+  OPCODE_MOVEQZ_S,
+  OPCODE_MOVNEZ_S,
+  OPCODE_MOVLTZ_S,
+  OPCODE_MOVGEZ_S,
+  OPCODE_MOVF_S,
+  OPCODE_MOVT_S,
+  OPCODE_WFR,
+  OPCODE_RFR,
+  OPCODE_ROUND_S,
+  OPCODE_CEIL_S,
+  OPCODE_FLOOR_S,
+  OPCODE_TRUNC_S,
+  OPCODE_UTRUNC_S,
+  OPCODE_FLOAT_S,
+  OPCODE_UFLOAT_S,
+  OPCODE_UN_S,
+  OPCODE_ULT_S,
+  OPCODE_ULE_S,
+  OPCODE_UEQ_S,
+  OPCODE_OLT_S,
+  OPCODE_OLE_S,
+  OPCODE_OEQ_S,
+  OPCODE_ADD_S,
+  OPCODE_SUB_S,
+  OPCODE_MUL_S,
+  OPCODE_MADD_S,
+  OPCODE_MSUB_S,
+  OPCODE_SQRT0_S,
+  OPCODE_DIV0_S,
+  OPCODE_RECIP0_S,
+  OPCODE_RSQRT0_S,
+  OPCODE_MADDN_S,
+  OPCODE_DIVN_S,
+  OPCODE_CONST_S,
+  OPCODE_NEXP01_S,
+  OPCODE_ADDEXP_S,
+  OPCODE_ADDEXPM_S,
+  OPCODE_MKDADJ_S,
+  OPCODE_MKSADJ_S,
+  OPCODE_EXCW,
+  OPCODE_RFE,
+  OPCODE_RFDE,
+  OPCODE_SYSCALL,
+  OPCODE_CALL12,
+  OPCODE_CALL8,
+  OPCODE_CALL4,
+  OPCODE_CALLX12,
+  OPCODE_CALLX8,
+  OPCODE_CALLX4,
+  OPCODE_ENTRY,
+  OPCODE_MOVSP,
+  OPCODE_ROTW,
+  OPCODE_RETW,
+  OPCODE_RETW_N,
+  OPCODE_RFWO,
+  OPCODE_RFWU,
+  OPCODE_L32E,
+  OPCODE_S32E,
+  OPCODE_RSR_WINDOWBASE,
+  OPCODE_WSR_WINDOWBASE,
+  OPCODE_XSR_WINDOWBASE,
+  OPCODE_RSR_WINDOWSTART,
+  OPCODE_WSR_WINDOWSTART,
+  OPCODE_XSR_WINDOWSTART,
+  OPCODE_ADD_N,
+  OPCODE_ADDI_N,
+  OPCODE_BEQZ_N,
+  OPCODE_BNEZ_N,
+  OPCODE_ILL_N,
+  OPCODE_L32I_N,
+  OPCODE_MOV_N,
+  OPCODE_MOVI_N,
+  OPCODE_NOP_N,
+  OPCODE_RET_N,
+  OPCODE_S32I_N,
+  OPCODE_RUR_THREADPTR,
+  OPCODE_WUR_THREADPTR,
+  OPCODE_ADDI,
+  OPCODE_ADDMI,
+  OPCODE_ADD,
+  OPCODE_SUB,
+  OPCODE_ADDX2,
+  OPCODE_ADDX4,
+  OPCODE_ADDX8,
+  OPCODE_SUBX2,
+  OPCODE_SUBX4,
+  OPCODE_SUBX8,
+  OPCODE_AND,
+  OPCODE_OR,
+  OPCODE_XOR,
+  OPCODE_BEQI,
+  OPCODE_BNEI,
+  OPCODE_BGEI,
+  OPCODE_BLTI,
+  OPCODE_BBCI,
+  OPCODE_BBSI,
+  OPCODE_BGEUI,
+  OPCODE_BLTUI,
+  OPCODE_BEQ,
+  OPCODE_BNE,
+  OPCODE_BGE,
+  OPCODE_BLT,
+  OPCODE_BGEU,
+  OPCODE_BLTU,
+  OPCODE_BANY,
+  OPCODE_BNONE,
+  OPCODE_BALL,
+  OPCODE_BNALL,
+  OPCODE_BBC,
+  OPCODE_BBS,
+  OPCODE_BEQZ,
+  OPCODE_BNEZ,
+  OPCODE_BGEZ,
+  OPCODE_BLTZ,
+  OPCODE_CALL0,
+  OPCODE_CALLX0,
+  OPCODE_EXTUI,
+  OPCODE_ILL,
+  OPCODE_J,
+  OPCODE_JX,
+  OPCODE_L16UI,
+  OPCODE_L16SI,
+  OPCODE_L32I,
+  OPCODE_L32R,
+  OPCODE_L8UI,
+  OPCODE_LOOP,
+  OPCODE_LOOPNEZ,
+  OPCODE_LOOPGTZ,
+  OPCODE_MOVI,
+  OPCODE_MOVEQZ,
+  OPCODE_MOVNEZ,
+  OPCODE_MOVLTZ,
+  OPCODE_MOVGEZ,
+  OPCODE_NEG,
+  OPCODE_ABS,
+  OPCODE_NOP,
+  OPCODE_RET,
+  OPCODE_SIMCALL,
+  OPCODE_S16I,
+  OPCODE_S32I,
+  OPCODE_S32NB,
+  OPCODE_S8I,
+  OPCODE_SSR,
+  OPCODE_SSL,
+  OPCODE_SSA8L,
+  OPCODE_SSA8B,
+  OPCODE_SSAI,
+  OPCODE_SLL,
+  OPCODE_SRC,
+  OPCODE_SRL,
+  OPCODE_SRA,
+  OPCODE_SLLI,
+  OPCODE_SRAI,
+  OPCODE_SRLI,
+  OPCODE_MEMW,
+  OPCODE_EXTW,
+  OPCODE_ISYNC,
+  OPCODE_RSYNC,
+  OPCODE_ESYNC,
+  OPCODE_DSYNC,
+  OPCODE_RSIL,
+  OPCODE_RSR_LEND,
+  OPCODE_WSR_LEND,
+  OPCODE_XSR_LEND,
+  OPCODE_RSR_LCOUNT,
+  OPCODE_WSR_LCOUNT,
+  OPCODE_XSR_LCOUNT,
+  OPCODE_RSR_LBEG,
+  OPCODE_WSR_LBEG,
+  OPCODE_XSR_LBEG,
+  OPCODE_RSR_SAR,
+  OPCODE_WSR_SAR,
+  OPCODE_XSR_SAR,
+  OPCODE_RSR_MEMCTL,
+  OPCODE_WSR_MEMCTL,
+  OPCODE_XSR_MEMCTL,
+  OPCODE_RSR_LITBASE,
+  OPCODE_WSR_LITBASE,
+  OPCODE_XSR_LITBASE,
+  OPCODE_RSR_CONFIGID0,
+  OPCODE_WSR_CONFIGID0,
+  OPCODE_RSR_CONFIGID1,
+  OPCODE_RSR_PS,
+  OPCODE_WSR_PS,
+  OPCODE_XSR_PS,
+  OPCODE_RSR_EPC1,
+  OPCODE_WSR_EPC1,
+  OPCODE_XSR_EPC1,
+  OPCODE_RSR_EXCSAVE1,
+  OPCODE_WSR_EXCSAVE1,
+  OPCODE_XSR_EXCSAVE1,
+  OPCODE_RSR_EPC2,
+  OPCODE_WSR_EPC2,
+  OPCODE_XSR_EPC2,
+  OPCODE_RSR_EXCSAVE2,
+  OPCODE_WSR_EXCSAVE2,
+  OPCODE_XSR_EXCSAVE2,
+  OPCODE_RSR_EPC3,
+  OPCODE_WSR_EPC3,
+  OPCODE_XSR_EPC3,
+  OPCODE_RSR_EXCSAVE3,
+  OPCODE_WSR_EXCSAVE3,
+  OPCODE_XSR_EXCSAVE3,
+  OPCODE_RSR_EPC4,
+  OPCODE_WSR_EPC4,
+  OPCODE_XSR_EPC4,
+  OPCODE_RSR_EXCSAVE4,
+  OPCODE_WSR_EXCSAVE4,
+  OPCODE_XSR_EXCSAVE4,
+  OPCODE_RSR_EPC5,
+  OPCODE_WSR_EPC5,
+  OPCODE_XSR_EPC5,
+  OPCODE_RSR_EXCSAVE5,
+  OPCODE_WSR_EXCSAVE5,
+  OPCODE_XSR_EXCSAVE5,
+  OPCODE_RSR_EPC6,
+  OPCODE_WSR_EPC6,
+  OPCODE_XSR_EPC6,
+  OPCODE_RSR_EXCSAVE6,
+  OPCODE_WSR_EXCSAVE6,
+  OPCODE_XSR_EXCSAVE6,
+  OPCODE_RSR_EPC7,
+  OPCODE_WSR_EPC7,
+  OPCODE_XSR_EPC7,
+  OPCODE_RSR_EXCSAVE7,
+  OPCODE_WSR_EXCSAVE7,
+  OPCODE_XSR_EXCSAVE7,
+  OPCODE_RSR_EPS2,
+  OPCODE_WSR_EPS2,
+  OPCODE_XSR_EPS2,
+  OPCODE_RSR_EPS3,
+  OPCODE_WSR_EPS3,
+  OPCODE_XSR_EPS3,
+  OPCODE_RSR_EPS4,
+  OPCODE_WSR_EPS4,
+  OPCODE_XSR_EPS4,
+  OPCODE_RSR_EPS5,
+  OPCODE_WSR_EPS5,
+  OPCODE_XSR_EPS5,
+  OPCODE_RSR_EPS6,
+  OPCODE_WSR_EPS6,
+  OPCODE_XSR_EPS6,
+  OPCODE_RSR_EPS7,
+  OPCODE_WSR_EPS7,
+  OPCODE_XSR_EPS7,
+  OPCODE_RSR_EXCVADDR,
+  OPCODE_WSR_EXCVADDR,
+  OPCODE_XSR_EXCVADDR,
+  OPCODE_RSR_DEPC,
+  OPCODE_WSR_DEPC,
+  OPCODE_XSR_DEPC,
+  OPCODE_RSR_EXCCAUSE,
+  OPCODE_WSR_EXCCAUSE,
+  OPCODE_XSR_EXCCAUSE,
+  OPCODE_RSR_MISC0,
+  OPCODE_WSR_MISC0,
+  OPCODE_XSR_MISC0,
+  OPCODE_RSR_MISC1,
+  OPCODE_WSR_MISC1,
+  OPCODE_XSR_MISC1,
+  OPCODE_RSR_MISC2,
+  OPCODE_WSR_MISC2,
+  OPCODE_XSR_MISC2,
+  OPCODE_RSR_MISC3,
+  OPCODE_WSR_MISC3,
+  OPCODE_XSR_MISC3,
+  OPCODE_RSR_PRID,
+  OPCODE_RSR_VECBASE,
+  OPCODE_WSR_VECBASE,
+  OPCODE_XSR_VECBASE,
+  OPCODE_SALT,
+  OPCODE_SALTU,
+  OPCODE_MUL16U,
+  OPCODE_MUL16S,
+  OPCODE_MULL,
+  OPCODE_MULUH,
+  OPCODE_MULSH,
+  OPCODE_MUL_AA_LL,
+  OPCODE_MUL_AA_HL,
+  OPCODE_MUL_AA_LH,
+  OPCODE_MUL_AA_HH,
+  OPCODE_UMUL_AA_LL,
+  OPCODE_UMUL_AA_HL,
+  OPCODE_UMUL_AA_LH,
+  OPCODE_UMUL_AA_HH,
+  OPCODE_MUL_AD_LL,
+  OPCODE_MUL_AD_HL,
+  OPCODE_MUL_AD_LH,
+  OPCODE_MUL_AD_HH,
+  OPCODE_MUL_DA_LL,
+  OPCODE_MUL_DA_HL,
+  OPCODE_MUL_DA_LH,
+  OPCODE_MUL_DA_HH,
+  OPCODE_MUL_DD_LL,
+  OPCODE_MUL_DD_HL,
+  OPCODE_MUL_DD_LH,
+  OPCODE_MUL_DD_HH,
+  OPCODE_MULA_AA_LL,
+  OPCODE_MULA_AA_HL,
+  OPCODE_MULA_AA_LH,
+  OPCODE_MULA_AA_HH,
+  OPCODE_MULS_AA_LL,
+  OPCODE_MULS_AA_HL,
+  OPCODE_MULS_AA_LH,
+  OPCODE_MULS_AA_HH,
+  OPCODE_MULA_AD_LL,
+  OPCODE_MULA_AD_HL,
+  OPCODE_MULA_AD_LH,
+  OPCODE_MULA_AD_HH,
+  OPCODE_MULS_AD_LL,
+  OPCODE_MULS_AD_HL,
+  OPCODE_MULS_AD_LH,
+  OPCODE_MULS_AD_HH,
+  OPCODE_MULA_DA_LL,
+  OPCODE_MULA_DA_HL,
+  OPCODE_MULA_DA_LH,
+  OPCODE_MULA_DA_HH,
+  OPCODE_MULS_DA_LL,
+  OPCODE_MULS_DA_HL,
+  OPCODE_MULS_DA_LH,
+  OPCODE_MULS_DA_HH,
+  OPCODE_MULA_DD_LL,
+  OPCODE_MULA_DD_HL,
+  OPCODE_MULA_DD_LH,
+  OPCODE_MULA_DD_HH,
+  OPCODE_MULS_DD_LL,
+  OPCODE_MULS_DD_HL,
+  OPCODE_MULS_DD_LH,
+  OPCODE_MULS_DD_HH,
+  OPCODE_MULA_DA_LL_LDDEC,
+  OPCODE_MULA_DA_LL_LDINC,
+  OPCODE_MULA_DA_HL_LDDEC,
+  OPCODE_MULA_DA_HL_LDINC,
+  OPCODE_MULA_DA_LH_LDDEC,
+  OPCODE_MULA_DA_LH_LDINC,
+  OPCODE_MULA_DA_HH_LDDEC,
+  OPCODE_MULA_DA_HH_LDINC,
+  OPCODE_MULA_DD_LL_LDDEC,
+  OPCODE_MULA_DD_LL_LDINC,
+  OPCODE_MULA_DD_HL_LDDEC,
+  OPCODE_MULA_DD_HL_LDINC,
+  OPCODE_MULA_DD_LH_LDDEC,
+  OPCODE_MULA_DD_LH_LDINC,
+  OPCODE_MULA_DD_HH_LDDEC,
+  OPCODE_MULA_DD_HH_LDINC,
+  OPCODE_LDDEC,
+  OPCODE_LDINC,
+  OPCODE_RSR_M0,
+  OPCODE_WSR_M0,
+  OPCODE_XSR_M0,
+  OPCODE_RSR_M1,
+  OPCODE_WSR_M1,
+  OPCODE_XSR_M1,
+  OPCODE_RSR_M2,
+  OPCODE_WSR_M2,
+  OPCODE_XSR_M2,
+  OPCODE_RSR_M3,
+  OPCODE_WSR_M3,
+  OPCODE_XSR_M3,
+  OPCODE_RSR_ACCLO,
+  OPCODE_WSR_ACCLO,
+  OPCODE_XSR_ACCLO,
+  OPCODE_RSR_ACCHI,
+  OPCODE_WSR_ACCHI,
+  OPCODE_XSR_ACCHI,
+  OPCODE_RFI,
+  OPCODE_WAITI,
+  OPCODE_RSR_INTERRUPT,
+  OPCODE_WSR_INTSET,
+  OPCODE_WSR_INTCLEAR,
+  OPCODE_RSR_INTENABLE,
+  OPCODE_WSR_INTENABLE,
+  OPCODE_XSR_INTENABLE,
+  OPCODE_BREAK,
+  OPCODE_BREAK_N,
+  OPCODE_RSR_DBREAKA0,
+  OPCODE_WSR_DBREAKA0,
+  OPCODE_XSR_DBREAKA0,
+  OPCODE_RSR_DBREAKC0,
+  OPCODE_WSR_DBREAKC0,
+  OPCODE_XSR_DBREAKC0,
+  OPCODE_RSR_DBREAKA1,
+  OPCODE_WSR_DBREAKA1,
+  OPCODE_XSR_DBREAKA1,
+  OPCODE_RSR_DBREAKC1,
+  OPCODE_WSR_DBREAKC1,
+  OPCODE_XSR_DBREAKC1,
+  OPCODE_RSR_IBREAKA0,
+  OPCODE_WSR_IBREAKA0,
+  OPCODE_XSR_IBREAKA0,
+  OPCODE_RSR_IBREAKA1,
+  OPCODE_WSR_IBREAKA1,
+  OPCODE_XSR_IBREAKA1,
+  OPCODE_RSR_IBREAKENABLE,
+  OPCODE_WSR_IBREAKENABLE,
+  OPCODE_XSR_IBREAKENABLE,
+  OPCODE_RSR_DEBUGCAUSE,
+  OPCODE_WSR_DEBUGCAUSE,
+  OPCODE_XSR_DEBUGCAUSE,
+  OPCODE_RSR_ICOUNT,
+  OPCODE_WSR_ICOUNT,
+  OPCODE_XSR_ICOUNT,
+  OPCODE_RSR_ICOUNTLEVEL,
+  OPCODE_WSR_ICOUNTLEVEL,
+  OPCODE_XSR_ICOUNTLEVEL,
+  OPCODE_RSR_DDR,
+  OPCODE_WSR_DDR,
+  OPCODE_XSR_DDR,
+  OPCODE_LDDR32_P,
+  OPCODE_SDDR32_P,
+  OPCODE_RFDO,
+  OPCODE_RFDD,
+  OPCODE_WSR_MMID,
+  OPCODE_ANDB,
+  OPCODE_ANDBC,
+  OPCODE_ORB,
+  OPCODE_ORBC,
+  OPCODE_XORB,
+  OPCODE_ANY4,
+  OPCODE_ALL4,
+  OPCODE_ANY8,
+  OPCODE_ALL8,
+  OPCODE_BF,
+  OPCODE_BT,
+  OPCODE_MOVF,
+  OPCODE_MOVT,
+  OPCODE_RSR_BR,
+  OPCODE_WSR_BR,
+  OPCODE_XSR_BR,
+  OPCODE_RSR_CCOUNT,
+  OPCODE_WSR_CCOUNT,
+  OPCODE_XSR_CCOUNT,
+  OPCODE_RSR_CCOMPARE0,
+  OPCODE_WSR_CCOMPARE0,
+  OPCODE_XSR_CCOMPARE0,
+  OPCODE_RSR_CCOMPARE1,
+  OPCODE_WSR_CCOMPARE1,
+  OPCODE_XSR_CCOMPARE1,
+  OPCODE_RSR_CCOMPARE2,
+  OPCODE_WSR_CCOMPARE2,
+  OPCODE_XSR_CCOMPARE2,
+  OPCODE_IDTLB,
+  OPCODE_PDTLB,
+  OPCODE_RDTLB0,
+  OPCODE_RDTLB1,
+  OPCODE_WDTLB,
+  OPCODE_IITLB,
+  OPCODE_PITLB,
+  OPCODE_RITLB0,
+  OPCODE_RITLB1,
+  OPCODE_WITLB,
+  OPCODE_RSR_CPENABLE,
+  OPCODE_WSR_CPENABLE,
+  OPCODE_XSR_CPENABLE,
+  OPCODE_CLAMPS,
+  OPCODE_MIN,
+  OPCODE_MAX,
+  OPCODE_MINU,
+  OPCODE_MAXU,
+  OPCODE_NSA,
+  OPCODE_NSAU,
+  OPCODE_SEXT,
+  OPCODE_L32AI,
+  OPCODE_S32RI,
+  OPCODE_S32C1I,
+  OPCODE_RSR_SCOMPARE1,
+  OPCODE_WSR_SCOMPARE1,
+  OPCODE_XSR_SCOMPARE1,
+  OPCODE_RSR_ATOMCTL,
+  OPCODE_WSR_ATOMCTL,
+  OPCODE_XSR_ATOMCTL,
+  OPCODE_QUOU,
+  OPCODE_QUOS,
+  OPCODE_REMU,
+  OPCODE_REMS,
+  OPCODE_RSR_ERACCESS,
+  OPCODE_WSR_ERACCESS,
+  OPCODE_XSR_ERACCESS,
+  OPCODE_RER,
+  OPCODE_WER,
+  OPCODE_RUR_FCR,
+  OPCODE_WUR_FCR,
+  OPCODE_RUR_FSR,
+  OPCODE_WUR_FSR,
+  OPCODE_st_QR,
+  OPCODE_ld_QR,
+  OPCODE_mv_QR,
+  OPCODE_EE_WR_MASK_GPIO_OUT,
+  OPCODE_EE_SET_BIT_GPIO_OUT,
+  OPCODE_EE_CLR_BIT_GPIO_OUT,
+  OPCODE_EE_GET_GPIO_IN,
+  OPCODE_EE_VLD_128_IP,
+  OPCODE_EE_VLD_128_XP,
+  OPCODE_EE_VLD_H_64_IP,
+  OPCODE_EE_VLD_H_64_XP,
+  OPCODE_EE_VLD_L_64_IP,
+  OPCODE_EE_VLD_L_64_XP,
+  OPCODE_EE_VLDBC_16_IP,
+  OPCODE_EE_VLDBC_16,
+  OPCODE_EE_VLDBC_16_XP,
+  OPCODE_EE_VLDBC_32_IP,
+  OPCODE_EE_VLDBC_32,
+  OPCODE_EE_VLDBC_32_XP,
+  OPCODE_EE_VLDBC_8_IP,
+  OPCODE_EE_VLDBC_8,
+  OPCODE_EE_VLDBC_8_XP,
+  OPCODE_EE_VLDHBC_16_INCP,
+  OPCODE_EE_LDF_128_IP,
+  OPCODE_EE_LDF_128_XP,
+  OPCODE_EE_LDF_64_IP,
+  OPCODE_EE_LDF_64_XP,
+  OPCODE_EE_LD_128_USAR_IP,
+  OPCODE_EE_LD_128_USAR_XP,
+  OPCODE_EE_LDQA_S16_128_IP,
+  OPCODE_EE_LDQA_S16_128_XP,
+  OPCODE_EE_LDQA_S8_128_IP,
+  OPCODE_EE_LDQA_S8_128_XP,
+  OPCODE_EE_LDQA_U16_128_IP,
+  OPCODE_EE_LDQA_U16_128_XP,
+  OPCODE_EE_LDQA_U8_128_IP,
+  OPCODE_EE_LDQA_U8_128_XP,
+  OPCODE_EE_LD_QACC_H_H_32_IP,
+  OPCODE_EE_LD_QACC_H_L_128_IP,
+  OPCODE_EE_LD_QACC_L_H_32_IP,
+  OPCODE_EE_LD_QACC_L_L_128_IP,
+  OPCODE_EE_LD_ACCX_IP,
+  OPCODE_EE_LDXQ_32,
+  OPCODE_EE_LD_UA_STATE_IP,
+  OPCODE_EE_ST_UA_STATE_IP,
+  OPCODE_EE_VST_128_IP,
+  OPCODE_EE_VST_128_XP,
+  OPCODE_EE_VST_H_64_IP,
+  OPCODE_EE_VST_H_64_XP,
+  OPCODE_EE_VST_L_64_IP,
+  OPCODE_EE_VST_L_64_XP,
+  OPCODE_EE_STF_128_IP,
+  OPCODE_EE_STF_128_XP,
+  OPCODE_EE_STF_64_IP,
+  OPCODE_EE_STF_64_XP,
+  OPCODE_EE_ST_QACC_H_H_32_IP,
+  OPCODE_EE_ST_QACC_H_L_128_IP,
+  OPCODE_EE_ST_QACC_L_H_32_IP,
+  OPCODE_EE_ST_QACC_L_L_128_IP,
+  OPCODE_EE_ST_ACCX_IP,
+  OPCODE_EE_STXQ_32,
+  OPCODE_EE_MOVI_32_A,
+  OPCODE_EE_MOVI_32_Q,
+  OPCODE_EE_VZIP_16,
+  OPCODE_EE_VZIP_32,
+  OPCODE_EE_VZIP_8,
+  OPCODE_EE_VUNZIP_16,
+  OPCODE_EE_VUNZIP_32,
+  OPCODE_EE_VUNZIP_8,
+  OPCODE_EE_ZERO_ACCX,
+  OPCODE_EE_ZERO_QACC,
+  OPCODE_EE_ZERO_Q,
+  OPCODE_EE_MOV_S16_QACC,
+  OPCODE_EE_MOV_S8_QACC,
+  OPCODE_EE_MOV_U16_QACC,
+  OPCODE_EE_MOV_U8_QACC,
+  OPCODE_EE_VADDS_S16_LD_INCP,
+  OPCODE_EE_VADDS_S16_ST_INCP,
+  OPCODE_EE_VADDS_S16,
+  OPCODE_EE_VADDS_S32_LD_INCP,
+  OPCODE_EE_VADDS_S32_ST_INCP,
+  OPCODE_EE_VADDS_S32,
+  OPCODE_EE_VADDS_S8_LD_INCP,
+  OPCODE_EE_VADDS_S8_ST_INCP,
+  OPCODE_EE_VADDS_S8,
+  OPCODE_EE_VSUBS_S16_LD_INCP,
+  OPCODE_EE_VSUBS_S16_ST_INCP,
+  OPCODE_EE_VSUBS_S16,
+  OPCODE_EE_VSUBS_S32_LD_INCP,
+  OPCODE_EE_VSUBS_S32_ST_INCP,
+  OPCODE_EE_VSUBS_S32,
+  OPCODE_EE_VSUBS_S8_LD_INCP,
+  OPCODE_EE_VSUBS_S8_ST_INCP,
+  OPCODE_EE_VSUBS_S8,
+  OPCODE_EE_VMUL_S16_LD_INCP,
+  OPCODE_EE_VMUL_S16_ST_INCP,
+  OPCODE_EE_VMUL_S16,
+  OPCODE_EE_VMUL_S8_LD_INCP,
+  OPCODE_EE_VMUL_S8_ST_INCP,
+  OPCODE_EE_VMUL_S8,
+  OPCODE_EE_VMUL_U16_LD_INCP,
+  OPCODE_EE_VMUL_U16_ST_INCP,
+  OPCODE_EE_VMUL_U16,
+  OPCODE_EE_VMUL_U8_LD_INCP,
+  OPCODE_EE_VMUL_U8_ST_INCP,
+  OPCODE_EE_VMUL_U8,
+  OPCODE_EE_CMUL_S16_LD_INCP,
+  OPCODE_EE_CMUL_S16_ST_INCP,
+  OPCODE_EE_CMUL_S16,
+  OPCODE_EE_VMULAS_S16_ACCX_LD_IP_QUP,
+  OPCODE_EE_VMULAS_S16_ACCX_LD_IP,
+  OPCODE_EE_VMULAS_S16_ACCX_LD_XP_QUP,
+  OPCODE_EE_VMULAS_S16_ACCX_LD_XP,
+  OPCODE_EE_VMULAS_S16_ACCX,
+  OPCODE_EE_VMULAS_S8_ACCX_LD_IP_QUP,
+  OPCODE_EE_VMULAS_S8_ACCX_LD_IP,
+  OPCODE_EE_VMULAS_S8_ACCX_LD_XP_QUP,
+  OPCODE_EE_VMULAS_S8_ACCX_LD_XP,
+  OPCODE_EE_VMULAS_S8_ACCX,
+  OPCODE_EE_VMULAS_U16_ACCX_LD_IP_QUP,
+  OPCODE_EE_VMULAS_U16_ACCX_LD_IP,
+  OPCODE_EE_VMULAS_U16_ACCX_LD_XP_QUP,
+  OPCODE_EE_VMULAS_U16_ACCX_LD_XP,
+  OPCODE_EE_VMULAS_U16_ACCX,
+  OPCODE_EE_VMULAS_U8_ACCX_LD_IP_QUP,
+  OPCODE_EE_VMULAS_U8_ACCX_LD_IP,
+  OPCODE_EE_VMULAS_U8_ACCX_LD_XP_QUP,
+  OPCODE_EE_VMULAS_U8_ACCX_LD_XP,
+  OPCODE_EE_VMULAS_U8_ACCX,
+  OPCODE_EE_VMULAS_S16_QACC_LDBC_INCP_QUP,
+  OPCODE_EE_VMULAS_S16_QACC_LDBC_INCP,
+  OPCODE_EE_VMULAS_S16_QACC_LD_IP_QUP,
+  OPCODE_EE_VMULAS_S16_QACC_LD_IP,
+  OPCODE_EE_VMULAS_S16_QACC_LD_XP_QUP,
+  OPCODE_EE_VMULAS_S16_QACC_LD_XP,
+  OPCODE_EE_VMULAS_S16_QACC,
+  OPCODE_EE_VMULAS_S8_QACC_LDBC_INCP_QUP,
+  OPCODE_EE_VMULAS_S8_QACC_LDBC_INCP,
+  OPCODE_EE_VMULAS_S8_QACC_LD_IP_QUP,
+  OPCODE_EE_VMULAS_S8_QACC_LD_IP,
+  OPCODE_EE_VMULAS_S8_QACC_LD_XP_QUP,
+  OPCODE_EE_VMULAS_S8_QACC_LD_XP,
+  OPCODE_EE_VMULAS_S8_QACC,
+  OPCODE_EE_VMULAS_U16_QACC_LDBC_INCP_QUP,
+  OPCODE_EE_VMULAS_U16_QACC_LDBC_INCP,
+  OPCODE_EE_VMULAS_U16_QACC_LD_IP_QUP,
+  OPCODE_EE_VMULAS_U16_QACC_LD_IP,
+  OPCODE_EE_VMULAS_U16_QACC_LD_XP_QUP,
+  OPCODE_EE_VMULAS_U16_QACC_LD_XP,
+  OPCODE_EE_VMULAS_U16_QACC,
+  OPCODE_EE_VMULAS_U8_QACC_LDBC_INCP_QUP,
+  OPCODE_EE_VMULAS_U8_QACC_LDBC_INCP,
+  OPCODE_EE_VMULAS_U8_QACC_LD_IP_QUP,
+  OPCODE_EE_VMULAS_U8_QACC_LD_IP,
+  OPCODE_EE_VMULAS_U8_QACC_LD_XP_QUP,
+  OPCODE_EE_VMULAS_U8_QACC_LD_XP,
+  OPCODE_EE_VMULAS_U8_QACC,
+  OPCODE_EE_VSMULAS_S16_QACC_LD_INCP,
+  OPCODE_EE_VSMULAS_S16_QACC,
+  OPCODE_EE_VSMULAS_S8_QACC_LD_INCP,
+  OPCODE_EE_VSMULAS_S8_QACC,
+  OPCODE_EE_SRCMB_S16_QACC,
+  OPCODE_EE_SRCMB_S8_QACC,
+  OPCODE_EE_SRS_ACCX,
+  OPCODE_EE_VRELU_S16,
+  OPCODE_EE_VRELU_S8,
+  OPCODE_EE_VPRELU_S16,
+  OPCODE_EE_VPRELU_S8,
+  OPCODE_EE_VMAX_S16_LD_INCP,
+  OPCODE_EE_VMAX_S16_ST_INCP,
+  OPCODE_EE_VMAX_S16,
+  OPCODE_EE_VMAX_S32_LD_INCP,
+  OPCODE_EE_VMAX_S32_ST_INCP,
+  OPCODE_EE_VMAX_S32,
+  OPCODE_EE_VMAX_S8_LD_INCP,
+  OPCODE_EE_VMAX_S8_ST_INCP,
+  OPCODE_EE_VMAX_S8,
+  OPCODE_EE_VMIN_S16_LD_INCP,
+  OPCODE_EE_VMIN_S16_ST_INCP,
+  OPCODE_EE_VMIN_S16,
+  OPCODE_EE_VMIN_S32_LD_INCP,
+  OPCODE_EE_VMIN_S32_ST_INCP,
+  OPCODE_EE_VMIN_S32,
+  OPCODE_EE_VMIN_S8_LD_INCP,
+  OPCODE_EE_VMIN_S8_ST_INCP,
+  OPCODE_EE_VMIN_S8,
+  OPCODE_EE_VCMP_EQ_S16,
+  OPCODE_EE_VCMP_EQ_S32,
+  OPCODE_EE_VCMP_EQ_S8,
+  OPCODE_EE_VCMP_GT_S16,
+  OPCODE_EE_VCMP_GT_S32,
+  OPCODE_EE_VCMP_GT_S8,
+  OPCODE_EE_VCMP_LT_S16,
+  OPCODE_EE_VCMP_LT_S32,
+  OPCODE_EE_VCMP_LT_S8,
+  OPCODE_EE_ANDQ,
+  OPCODE_EE_NOTQ,
+  OPCODE_EE_ORQ,
+  OPCODE_EE_XORQ,
+  OPCODE_EE_SLCI_2Q,
+  OPCODE_EE_SLCXXP_2Q,
+  OPCODE_EE_SRCI_2Q,
+  OPCODE_EE_SRCQ_128_ST_INCP,
+  OPCODE_EE_SRC_Q_LD_IP,
+  OPCODE_EE_SRC_Q_LD_XP,
+  OPCODE_EE_SRC_Q_QUP,
+  OPCODE_EE_SRC_Q,
+  OPCODE_EE_SRCXXP_2Q,
+  OPCODE_EE_VSL_32,
+  OPCODE_EE_VSR_32,
+  OPCODE_EE_FFT_R2BF_S16_ST_INCP,
+  OPCODE_EE_FFT_R2BF_S16,
+  OPCODE_EE_FFT_CMUL_S16_LD_XP,
+  OPCODE_EE_FFT_CMUL_S16_ST_XP,
+  OPCODE_EE_BITREV,
+  OPCODE_EE_FFT_AMS_S16_LD_INCP,
+  OPCODE_EE_FFT_AMS_S16_LD_INCP_UAUP,
+  OPCODE_EE_FFT_AMS_S16_LD_R32_DECP,
+  OPCODE_EE_FFT_AMS_S16_ST_INCP,
+  OPCODE_EE_FFT_VST_R32_DECP,
+  OPCODE_RUR_ACCX_0,
+  OPCODE_WUR_ACCX_0,
+  OPCODE_RUR_ACCX_1,
+  OPCODE_WUR_ACCX_1,
+  OPCODE_RUR_QACC_H_0,
+  OPCODE_WUR_QACC_H_0,
+  OPCODE_RUR_QACC_H_1,
+  OPCODE_WUR_QACC_H_1,
+  OPCODE_RUR_QACC_H_2,
+  OPCODE_WUR_QACC_H_2,
+  OPCODE_RUR_QACC_H_3,
+  OPCODE_WUR_QACC_H_3,
+  OPCODE_RUR_QACC_H_4,
+  OPCODE_WUR_QACC_H_4,
+  OPCODE_RUR_QACC_L_0,
+  OPCODE_WUR_QACC_L_0,
+  OPCODE_RUR_QACC_L_1,
+  OPCODE_WUR_QACC_L_1,
+  OPCODE_RUR_QACC_L_2,
+  OPCODE_WUR_QACC_L_2,
+  OPCODE_RUR_QACC_L_3,
+  OPCODE_WUR_QACC_L_3,
+  OPCODE_RUR_QACC_L_4,
+  OPCODE_WUR_QACC_L_4,
+  OPCODE_RUR_GPIO_OUT,
+  OPCODE_WUR_GPIO_OUT,
+  OPCODE_RUR_SAR_BYTE,
+  OPCODE_WUR_SAR_BYTE,
+  OPCODE_RUR_FFT_BIT_WIDTH,
+  OPCODE_WUR_FFT_BIT_WIDTH,
+  OPCODE_RUR_UA_STATE_0,
+  OPCODE_WUR_UA_STATE_0,
+  OPCODE_RUR_UA_STATE_1,
+  OPCODE_WUR_UA_STATE_1,
+  OPCODE_RUR_UA_STATE_2,
+  OPCODE_WUR_UA_STATE_2,
+  OPCODE_RUR_UA_STATE_3,
+  OPCODE_WUR_UA_STATE_3
+};
+
+\f
+/* Slot-specific opcode decode functions.  */
+
+static int
+Slot_inst_decode (const xtensa_insnbuf insn)
+{
+  if (Field_fld_inst_19_16_Slot_inst_get (insn) == 6 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 0)
+    return OPCODE_EE_LDF_64_XP;
+  if (Field_fld_inst_19_16_Slot_inst_get (insn) == 7 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 0)
+    return OPCODE_EE_STF_64_XP;
+  if (Field_fld_inst_23_0_Slot_inst_get (insn) == 2426884)
+    return OPCODE_EE_ZERO_ACCX;
+  if (Field_fld_inst_23_0_Slot_inst_get (insn) == 2426948)
+    return OPCODE_EE_ZERO_QACC;
+  if (Field_fld_inst_23_12_Slot_inst_get (insn) == 1796 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_LDQA_U8_128_XP;
+  if (Field_fld_inst_23_12_Slot_inst_get (insn) == 1812 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_LDQA_S8_128_XP;
+  if (Field_fld_inst_23_12_Slot_inst_get (insn) == 1828 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_WR_MASK_GPIO_OUT;
+  if (Field_fld_inst_23_12_Slot_inst_get (insn) == 1876 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_SET_BIT_GPIO_OUT;
+  if (Field_fld_inst_23_12_Slot_inst_get (insn) == 1892 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_CLR_BIT_GPIO_OUT;
+  if (Field_fld_inst_23_12_Slot_inst_get (insn) == 1956 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_LDQA_U16_128_XP;
+  if (Field_fld_inst_23_12_Slot_inst_get (insn) == 2020 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_LDQA_S16_128_XP;
+  if (Field_fld_inst_23_15_Slot_inst_get (insn) == 20 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 132)
+    return OPCODE_EE_VMULAS_U16_ACCX;
+  if (Field_fld_inst_23_15_Slot_inst_get (insn) == 20 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 196)
+    return OPCODE_EE_VMULAS_U8_ACCX;
+  if (Field_fld_inst_23_15_Slot_inst_get (insn) == 20 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 132)
+    return OPCODE_EE_VMULAS_U16_QACC;
+  if (Field_fld_inst_23_15_Slot_inst_get (insn) == 20 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 196)
+    return OPCODE_EE_VMULAS_U8_QACC;
+  if (Field_fld_inst_23_15_Slot_inst_get (insn) == 52 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 132)
+    return OPCODE_EE_VMULAS_S16_ACCX;
+  if (Field_fld_inst_23_15_Slot_inst_get (insn) == 52 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 196)
+    return OPCODE_EE_VMULAS_S8_ACCX;
+  if (Field_fld_inst_23_15_Slot_inst_get (insn) == 52 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 132)
+    return OPCODE_EE_VMULAS_S16_QACC;
+  if (Field_fld_inst_23_15_Slot_inst_get (insn) == 52 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 196)
+    return OPCODE_EE_VMULAS_S8_QACC;
+  if (Field_fld_inst_23_15_Slot_inst_get (insn) == 252 &&
+      Field_fld_inst_13_12_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_SRS_ACCX;
+  if (Field_fld_inst_23_21_Slot_inst_get (insn) == 4 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 7 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VMULAS_S16_QACC_LDBC_INCP;
+  if (Field_fld_inst_23_21_Slot_inst_get (insn) == 5 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 7 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VMULAS_S8_QACC_LDBC_INCP;
+  if (Field_fld_inst_23_21_Slot_inst_get (insn) == 6 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 7 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VMULAS_U16_QACC_LDBC_INCP;
+  if (Field_fld_inst_23_21_Slot_inst_get (insn) == 7 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 7 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VMULAS_U8_QACC_LDBC_INCP;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 15 &&
+      Field_fld_inst_14_12_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_9_6_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_4_0_Slot_inst_get (insn) == 4)
+    return OPCODE_mv_QR;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_12_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VLD_128_XP;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_12_Slot_inst_get (insn) == 6 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VLD_H_64_XP;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_12_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VLD_L_64_XP;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 5 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VLDBC_16_IP;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_12_Slot_inst_get (insn) == 4 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VLDBC_16_XP;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_12_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VLDBC_32_XP;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_12_Slot_inst_get (insn) == 5 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VLDBC_8_XP;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_12_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_LD_128_USAR_XP;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_12_Slot_inst_get (insn) == 7 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VST_128_XP;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 100)
+    return OPCODE_EE_VADDS_S16;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 116)
+    return OPCODE_EE_VADDS_S32;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 132)
+    return OPCODE_EE_VADDS_S8;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 212)
+    return OPCODE_EE_VSUBS_S16;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 228)
+    return OPCODE_EE_VSUBS_S32;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 244)
+    return OPCODE_EE_VSUBS_S8;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 132)
+    return OPCODE_EE_VMUL_S16;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 148)
+    return OPCODE_EE_VMUL_S8;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 164)
+    return OPCODE_EE_VMUL_U16;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 180)
+    return OPCODE_EE_VMUL_U8;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_7_6_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_CMUL_S16;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 196)
+    return OPCODE_EE_VSMULAS_S16_QACC;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_7_5_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VSMULAS_S8_QACC;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 12 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VPRELU_S16;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 12 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VPRELU_S8;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 36)
+    return OPCODE_EE_VMAX_S16;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 52)
+    return OPCODE_EE_VMAX_S32;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 68)
+    return OPCODE_EE_VMAX_S8;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 84)
+    return OPCODE_EE_VMIN_S16;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 100)
+    return OPCODE_EE_VMIN_S32;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 116)
+    return OPCODE_EE_VMIN_S8;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 148)
+    return OPCODE_EE_VCMP_EQ_S16;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 164)
+    return OPCODE_EE_VCMP_EQ_S32;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 180)
+    return OPCODE_EE_VCMP_EQ_S8;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 196)
+    return OPCODE_EE_VCMP_GT_S16;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 212)
+    return OPCODE_EE_VCMP_GT_S32;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 228)
+    return OPCODE_EE_VCMP_GT_S8;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 244)
+    return OPCODE_EE_VCMP_LT_S16;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VCMP_LT_S32;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_13_13_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_7_0_Slot_inst_get (insn) == 20)
+    return OPCODE_EE_VCMP_LT_S8;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 6 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_SLCXXP_2Q;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_12_Slot_inst_get (insn) == 6 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_st_QR;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_12_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_ld_QR;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_8_Slot_inst_get (insn) == 115 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VLDBC_16;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_8_Slot_inst_get (insn) == 119 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VLDBC_32;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 5 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VLDBC_8_IP;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_8_Slot_inst_get (insn) == 59 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VLDBC_8;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 12 &&
+      Field_fld_inst_11_8_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VLDHBC_16_INCP;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_12_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VST_H_64_XP;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_12_Slot_inst_get (insn) == 4 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VST_L_64_XP;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_12_Slot_inst_get (insn) == 7 &&
+      Field_fld_inst_9_8_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_MOVI_32_A;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_12_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_9_8_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_MOVI_32_Q;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 12 &&
+      Field_fld_inst_11_0_Slot_inst_get (insn) == 948)
+    return OPCODE_EE_VZIP_16;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 12 &&
+      Field_fld_inst_11_0_Slot_inst_get (insn) == 964)
+    return OPCODE_EE_VZIP_32;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 12 &&
+      Field_fld_inst_11_0_Slot_inst_get (insn) == 980)
+    return OPCODE_EE_VZIP_8;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 12 &&
+      Field_fld_inst_11_0_Slot_inst_get (insn) == 900)
+    return OPCODE_EE_VUNZIP_16;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 12 &&
+      Field_fld_inst_11_0_Slot_inst_get (insn) == 916)
+    return OPCODE_EE_VUNZIP_32;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 12 &&
+      Field_fld_inst_11_0_Slot_inst_get (insn) == 932)
+    return OPCODE_EE_VUNZIP_8;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_0_Slot_inst_get (insn) == 32676)
+    return OPCODE_EE_ZERO_Q;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_0_Slot_inst_get (insn) == 32548)
+    return OPCODE_EE_MOV_S16_QACC;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_0_Slot_inst_get (insn) == 32564)
+    return OPCODE_EE_MOV_S8_QACC;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_0_Slot_inst_get (insn) == 32612)
+    return OPCODE_EE_MOV_U16_QACC;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_0_Slot_inst_get (insn) == 32628)
+    return OPCODE_EE_MOV_U8_QACC;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_11_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_9_8_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_SRCMB_S16_QACC;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_11_Slot_inst_get (insn) == 15 &&
+      Field_fld_inst_9_8_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_SRCMB_S8_QACC;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_12_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VRELU_S16;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_12_Slot_inst_get (insn) == 5 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VRELU_S8;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_12_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_9_8_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_ANDQ;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_8_Slot_inst_get (insn) == 127 &&
+      Field_fld_inst_5_5_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_NOTQ;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_12_Slot_inst_get (insn) == 7 &&
+      Field_fld_inst_9_8_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_ORQ;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_12_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_9_8_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_XORQ;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 12 &&
+      Field_fld_inst_11_8_Slot_inst_get (insn) == 6 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_SLCI_2Q;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 12 &&
+      Field_fld_inst_11_8_Slot_inst_get (insn) == 10 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_SRCI_2Q;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 12 &&
+      Field_fld_inst_11_8_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_SRCQ_128_ST_INCP;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 12 &&
+      Field_fld_inst_11_7_Slot_inst_get (insn) == 14 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_SRC_Q_QUP;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 12 &&
+      Field_fld_inst_11_7_Slot_inst_get (insn) == 6 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_SRC_Q;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 6 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_SRCXXP_2Q;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_7_Slot_inst_get (insn) == 126 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VSL_32;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_7_Slot_inst_get (insn) == 127 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VSR_32;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 12 &&
+      Field_fld_inst_9_9_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_FFT_R2BF_S16;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_8_Slot_inst_get (insn) == 123 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_BITREV;
+  if (Field_fld_inst_23_22_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 13 &&
+      Field_fld_inst_14_11_Slot_inst_get (insn) == 6 &&
+      Field_fld_inst_9_8_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_FFT_VST_R32_DECP;
+  if (Field_fld_inst_23_23_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_21_15_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_LDQA_S16_128_IP;
+  if (Field_fld_inst_23_23_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_21_15_Slot_inst_get (insn) == 34 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_LDQA_S8_128_IP;
+  if (Field_fld_inst_23_23_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_21_15_Slot_inst_get (insn) == 10 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_LDQA_U16_128_IP;
+  if (Field_fld_inst_23_23_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_21_15_Slot_inst_get (insn) == 42 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_LDQA_U8_128_IP;
+  if (Field_fld_inst_23_23_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_21_15_Slot_inst_get (insn) == 60 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_LD_QACC_H_H_32_IP;
+  if (Field_fld_inst_23_23_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_21_15_Slot_inst_get (insn) == 12 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_LD_QACC_H_L_128_IP;
+  if (Field_fld_inst_23_23_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_21_15_Slot_inst_get (insn) == 44 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_LD_QACC_L_H_32_IP;
+  if (Field_fld_inst_23_23_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_21_15_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_LD_QACC_L_L_128_IP;
+  if (Field_fld_inst_23_23_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_21_15_Slot_inst_get (insn) == 28 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_LD_ACCX_IP;
+  if (Field_fld_inst_23_23_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_21_15_Slot_inst_get (insn) == 32 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_LD_UA_STATE_IP;
+  if (Field_fld_inst_23_23_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_21_15_Slot_inst_get (insn) == 56 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_ST_UA_STATE_IP;
+  if (Field_fld_inst_23_23_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_21_15_Slot_inst_get (insn) == 36 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_ST_QACC_H_H_32_IP;
+  if (Field_fld_inst_23_23_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_21_15_Slot_inst_get (insn) == 26 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_ST_QACC_H_L_128_IP;
+  if (Field_fld_inst_23_23_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_21_15_Slot_inst_get (insn) == 58 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_ST_QACC_L_H_32_IP;
+  if (Field_fld_inst_23_23_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_21_15_Slot_inst_get (insn) == 24 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_ST_QACC_L_L_128_IP;
+  if (Field_fld_inst_23_23_Slot_inst_get (insn) == 0 &&
+      Field_fld_inst_21_15_Slot_inst_get (insn) == 4 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_ST_ACCX_IP;
+  if (Field_fld_inst_23_23_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 3 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VLD_128_IP;
+  if (Field_fld_inst_23_23_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 8 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VLD_H_64_IP;
+  if (Field_fld_inst_23_23_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 9 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VLD_L_64_IP;
+  if (Field_fld_inst_23_23_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 2 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VLDBC_32_IP;
+  if (Field_fld_inst_23_23_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_LD_128_USAR_IP;
+  if (Field_fld_inst_23_23_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 10 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VST_128_IP;
+  if (Field_fld_inst_23_23_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 11 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VST_H_64_IP;
+  if (Field_fld_inst_23_23_Slot_inst_get (insn) == 1 &&
+      Field_fld_inst_19_16_Slot_inst_get (insn) == 4 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_VST_L_64_IP;
+  if (Field_fld_inst_23_8_Slot_inst_get (insn) == 25864 &&
+      Field_fld_inst_3_0_Slot_inst_get (insn) == 4)
+    return OPCODE_EE_GET_GPIO_IN;
+  if (Field_op0_Slot_inst_get (insn) == 0)
+    {
+      if (Field_op1_Slot_inst_get (insn) == 0)
+	{
+	  if (Field_op2_Slot_inst_get (insn) == 0)
+	    {
+	      if (Field_r_Slot_inst_get (insn) == 0)
+		{
+		  if (Field_m_Slot_inst_get (insn) == 0 &&
+		      Field_s_Slot_inst_get (insn) == 0 &&
+		      Field_n_Slot_inst_get (insn) == 0)
+		    return OPCODE_ILL;
+		  if (Field_m_Slot_inst_get (insn) == 2)
+		    {
+		      if (Field_n_Slot_inst_get (insn) == 0)
+			return OPCODE_RET;
+		      if (Field_n_Slot_inst_get (insn) == 1)
+			return OPCODE_RETW;
+		      if (Field_n_Slot_inst_get (insn) == 2)
+			return OPCODE_JX;
+		    }
+		  if (Field_m_Slot_inst_get (insn) == 3)
+		    {
+		      if (Field_n_Slot_inst_get (insn) == 0)
+			return OPCODE_CALLX0;
+		      if (Field_n_Slot_inst_get (insn) == 1)
+			return OPCODE_CALLX4;
+		      if (Field_n_Slot_inst_get (insn) == 2)
+			return OPCODE_CALLX8;
+		      if (Field_n_Slot_inst_get (insn) == 3)
+			return OPCODE_CALLX12;
+		    }
+		}
+	      if (Field_r_Slot_inst_get (insn) == 1)
+		return OPCODE_MOVSP;
+	      if (Field_r_Slot_inst_get (insn) == 2)
+		{
+		  if (Field_s_Slot_inst_get (insn) == 0)
+		    {
+		      if (Field_t_Slot_inst_get (insn) == 0)
+			return OPCODE_ISYNC;
+		      if (Field_t_Slot_inst_get (insn) == 1)
+			return OPCODE_RSYNC;
+		      if (Field_t_Slot_inst_get (insn) == 2)
+			return OPCODE_ESYNC;
+		      if (Field_t_Slot_inst_get (insn) == 3)
+			return OPCODE_DSYNC;
+		      if (Field_t_Slot_inst_get (insn) == 8)
+			return OPCODE_EXCW;
+		      if (Field_t_Slot_inst_get (insn) == 12)
+			return OPCODE_MEMW;
+		      if (Field_t_Slot_inst_get (insn) == 13)
+			return OPCODE_EXTW;
+		      if (Field_t_Slot_inst_get (insn) == 15)
+			return OPCODE_NOP;
+		    }
+		}
+	      if (Field_r_Slot_inst_get (insn) == 3)
+		{
+		  if (Field_t_Slot_inst_get (insn) == 0)
+		    {
+		      if (Field_s_Slot_inst_get (insn) == 0)
+			return OPCODE_RFE;
+		      if (Field_s_Slot_inst_get (insn) == 2)
+			return OPCODE_RFDE;
+		      if (Field_s_Slot_inst_get (insn) == 4)
+			return OPCODE_RFWO;
+		      if (Field_s_Slot_inst_get (insn) == 5)
+			return OPCODE_RFWU;
+		    }
+		  if (Field_t_Slot_inst_get (insn) == 1)
+		    return OPCODE_RFI;
+		}
+	      if (Field_r_Slot_inst_get (insn) == 4)
+		return OPCODE_BREAK;
+	      if (Field_r_Slot_inst_get (insn) == 5)
+		{
+		  if (Field_s_Slot_inst_get (insn) == 0 &&
+		      Field_t_Slot_inst_get (insn) == 0)
+		    return OPCODE_SYSCALL;
+		  if (Field_s_Slot_inst_get (insn) == 1 &&
+		      Field_t_Slot_inst_get (insn) == 0)
+		    return OPCODE_SIMCALL;
+		}
+	      if (Field_r_Slot_inst_get (insn) == 6)
+		return OPCODE_RSIL;
+	      if (Field_r_Slot_inst_get (insn) == 7 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_WAITI;
+	      if (Field_r_Slot_inst_get (insn) == 7)
+		{
+		  if (Field_t_Slot_inst_get (insn) == 14)
+		    return OPCODE_LDDR32_P;
+		  if (Field_t_Slot_inst_get (insn) == 15)
+		    return OPCODE_SDDR32_P;
+		}
+	      if (Field_r_Slot_inst_get (insn) == 8)
+		return OPCODE_ANY4;
+	      if (Field_r_Slot_inst_get (insn) == 9)
+		return OPCODE_ALL4;
+	      if (Field_r_Slot_inst_get (insn) == 10)
+		return OPCODE_ANY8;
+	      if (Field_r_Slot_inst_get (insn) == 11)
+		return OPCODE_ALL8;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 1)
+	    return OPCODE_AND;
+	  if (Field_op2_Slot_inst_get (insn) == 2)
+	    return OPCODE_OR;
+	  if (Field_op2_Slot_inst_get (insn) == 3)
+	    return OPCODE_XOR;
+	  if (Field_op2_Slot_inst_get (insn) == 4)
+	    {
+	      if (Field_r_Slot_inst_get (insn) == 0 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_SSR;
+	      if (Field_r_Slot_inst_get (insn) == 1 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_SSL;
+	      if (Field_r_Slot_inst_get (insn) == 2 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_SSA8L;
+	      if (Field_r_Slot_inst_get (insn) == 3 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_SSA8B;
+	      if (Field_r_Slot_inst_get (insn) == 4 &&
+		  Field_thi3_Slot_inst_get (insn) == 0)
+		return OPCODE_SSAI;
+	      if (Field_r_Slot_inst_get (insn) == 6)
+		return OPCODE_RER;
+	      if (Field_r_Slot_inst_get (insn) == 7)
+		return OPCODE_WER;
+	      if (Field_r_Slot_inst_get (insn) == 8 &&
+		  Field_s_Slot_inst_get (insn) == 0)
+		return OPCODE_ROTW;
+	      if (Field_r_Slot_inst_get (insn) == 14)
+		return OPCODE_NSA;
+	      if (Field_r_Slot_inst_get (insn) == 15)
+		return OPCODE_NSAU;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 5)
+	    {
+	      if (Field_r_Slot_inst_get (insn) == 3)
+		return OPCODE_RITLB0;
+	      if (Field_r_Slot_inst_get (insn) == 4 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_IITLB;
+	      if (Field_r_Slot_inst_get (insn) == 5)
+		return OPCODE_PITLB;
+	      if (Field_r_Slot_inst_get (insn) == 6)
+		return OPCODE_WITLB;
+	      if (Field_r_Slot_inst_get (insn) == 7)
+		return OPCODE_RITLB1;
+	      if (Field_r_Slot_inst_get (insn) == 11)
+		return OPCODE_RDTLB0;
+	      if (Field_r_Slot_inst_get (insn) == 12 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_IDTLB;
+	      if (Field_r_Slot_inst_get (insn) == 13)
+		return OPCODE_PDTLB;
+	      if (Field_r_Slot_inst_get (insn) == 14)
+		return OPCODE_WDTLB;
+	      if (Field_r_Slot_inst_get (insn) == 15)
+		return OPCODE_RDTLB1;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 6)
+	    {
+	      if (Field_s_Slot_inst_get (insn) == 0)
+		return OPCODE_NEG;
+	      if (Field_s_Slot_inst_get (insn) == 1)
+		return OPCODE_ABS;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 8)
+	    return OPCODE_ADD;
+	  if (Field_op2_Slot_inst_get (insn) == 9)
+	    return OPCODE_ADDX2;
+	  if (Field_op2_Slot_inst_get (insn) == 10)
+	    return OPCODE_ADDX4;
+	  if (Field_op2_Slot_inst_get (insn) == 11)
+	    return OPCODE_ADDX8;
+	  if (Field_op2_Slot_inst_get (insn) == 12)
+	    return OPCODE_SUB;
+	  if (Field_op2_Slot_inst_get (insn) == 13)
+	    return OPCODE_SUBX2;
+	  if (Field_op2_Slot_inst_get (insn) == 14)
+	    return OPCODE_SUBX4;
+	  if (Field_op2_Slot_inst_get (insn) == 15)
+	    return OPCODE_SUBX8;
+	}
+      if (Field_op1_Slot_inst_get (insn) == 1)
+	{
+	  if ((Field_op2_Slot_inst_get (insn) == 0 ||
+	       Field_op2_Slot_inst_get (insn) == 1))
+	    return OPCODE_SLLI;
+	  if ((Field_op2_Slot_inst_get (insn) == 2 ||
+	       Field_op2_Slot_inst_get (insn) == 3))
+	    return OPCODE_SRAI;
+	  if (Field_op2_Slot_inst_get (insn) == 4)
+	    return OPCODE_SRLI;
+	  if (Field_op2_Slot_inst_get (insn) == 6)
+	    {
+	      if (Field_sr_Slot_inst_get (insn) == 0)
+		return OPCODE_XSR_LBEG;
+	      if (Field_sr_Slot_inst_get (insn) == 1)
+		return OPCODE_XSR_LEND;
+	      if (Field_sr_Slot_inst_get (insn) == 2)
+		return OPCODE_XSR_LCOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 3)
+		return OPCODE_XSR_SAR;
+	      if (Field_sr_Slot_inst_get (insn) == 4)
+		return OPCODE_XSR_BR;
+	      if (Field_sr_Slot_inst_get (insn) == 5)
+		return OPCODE_XSR_LITBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 12)
+		return OPCODE_XSR_SCOMPARE1;
+	      if (Field_sr_Slot_inst_get (insn) == 16)
+		return OPCODE_XSR_ACCLO;
+	      if (Field_sr_Slot_inst_get (insn) == 17)
+		return OPCODE_XSR_ACCHI;
+	      if (Field_sr_Slot_inst_get (insn) == 32)
+		return OPCODE_XSR_M0;
+	      if (Field_sr_Slot_inst_get (insn) == 33)
+		return OPCODE_XSR_M1;
+	      if (Field_sr_Slot_inst_get (insn) == 34)
+		return OPCODE_XSR_M2;
+	      if (Field_sr_Slot_inst_get (insn) == 35)
+		return OPCODE_XSR_M3;
+	      if (Field_sr_Slot_inst_get (insn) == 72)
+		return OPCODE_XSR_WINDOWBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 73)
+		return OPCODE_XSR_WINDOWSTART;
+	      if (Field_sr_Slot_inst_get (insn) == 95)
+		return OPCODE_XSR_ERACCESS;
+	      if (Field_sr_Slot_inst_get (insn) == 96)
+		return OPCODE_XSR_IBREAKENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 97)
+		return OPCODE_XSR_MEMCTL;
+	      if (Field_sr_Slot_inst_get (insn) == 99)
+		return OPCODE_XSR_ATOMCTL;
+	      if (Field_sr_Slot_inst_get (insn) == 104)
+		return OPCODE_XSR_DDR;
+	      if (Field_sr_Slot_inst_get (insn) == 128)
+		return OPCODE_XSR_IBREAKA0;
+	      if (Field_sr_Slot_inst_get (insn) == 129)
+		return OPCODE_XSR_IBREAKA1;
+	      if (Field_sr_Slot_inst_get (insn) == 144)
+		return OPCODE_XSR_DBREAKA0;
+	      if (Field_sr_Slot_inst_get (insn) == 145)
+		return OPCODE_XSR_DBREAKA1;
+	      if (Field_sr_Slot_inst_get (insn) == 160)
+		return OPCODE_XSR_DBREAKC0;
+	      if (Field_sr_Slot_inst_get (insn) == 161)
+		return OPCODE_XSR_DBREAKC1;
+	      if (Field_sr_Slot_inst_get (insn) == 177)
+		return OPCODE_XSR_EPC1;
+	      if (Field_sr_Slot_inst_get (insn) == 178)
+		return OPCODE_XSR_EPC2;
+	      if (Field_sr_Slot_inst_get (insn) == 179)
+		return OPCODE_XSR_EPC3;
+	      if (Field_sr_Slot_inst_get (insn) == 180)
+		return OPCODE_XSR_EPC4;
+	      if (Field_sr_Slot_inst_get (insn) == 181)
+		return OPCODE_XSR_EPC5;
+	      if (Field_sr_Slot_inst_get (insn) == 182)
+		return OPCODE_XSR_EPC6;
+	      if (Field_sr_Slot_inst_get (insn) == 183)
+		return OPCODE_XSR_EPC7;
+	      if (Field_sr_Slot_inst_get (insn) == 192)
+		return OPCODE_XSR_DEPC;
+	      if (Field_sr_Slot_inst_get (insn) == 194)
+		return OPCODE_XSR_EPS2;
+	      if (Field_sr_Slot_inst_get (insn) == 195)
+		return OPCODE_XSR_EPS3;
+	      if (Field_sr_Slot_inst_get (insn) == 196)
+		return OPCODE_XSR_EPS4;
+	      if (Field_sr_Slot_inst_get (insn) == 197)
+		return OPCODE_XSR_EPS5;
+	      if (Field_sr_Slot_inst_get (insn) == 198)
+		return OPCODE_XSR_EPS6;
+	      if (Field_sr_Slot_inst_get (insn) == 199)
+		return OPCODE_XSR_EPS7;
+	      if (Field_sr_Slot_inst_get (insn) == 209)
+		return OPCODE_XSR_EXCSAVE1;
+	      if (Field_sr_Slot_inst_get (insn) == 210)
+		return OPCODE_XSR_EXCSAVE2;
+	      if (Field_sr_Slot_inst_get (insn) == 211)
+		return OPCODE_XSR_EXCSAVE3;
+	      if (Field_sr_Slot_inst_get (insn) == 212)
+		return OPCODE_XSR_EXCSAVE4;
+	      if (Field_sr_Slot_inst_get (insn) == 213)
+		return OPCODE_XSR_EXCSAVE5;
+	      if (Field_sr_Slot_inst_get (insn) == 214)
+		return OPCODE_XSR_EXCSAVE6;
+	      if (Field_sr_Slot_inst_get (insn) == 215)
+		return OPCODE_XSR_EXCSAVE7;
+	      if (Field_sr_Slot_inst_get (insn) == 224)
+		return OPCODE_XSR_CPENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 228)
+		return OPCODE_XSR_INTENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 230)
+		return OPCODE_XSR_PS;
+	      if (Field_sr_Slot_inst_get (insn) == 231)
+		return OPCODE_XSR_VECBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 232)
+		return OPCODE_XSR_EXCCAUSE;
+	      if (Field_sr_Slot_inst_get (insn) == 233)
+		return OPCODE_XSR_DEBUGCAUSE;
+	      if (Field_sr_Slot_inst_get (insn) == 234)
+		return OPCODE_XSR_CCOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 236)
+		return OPCODE_XSR_ICOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 237)
+		return OPCODE_XSR_ICOUNTLEVEL;
+	      if (Field_sr_Slot_inst_get (insn) == 238)
+		return OPCODE_XSR_EXCVADDR;
+	      if (Field_sr_Slot_inst_get (insn) == 240)
+		return OPCODE_XSR_CCOMPARE0;
+	      if (Field_sr_Slot_inst_get (insn) == 241)
+		return OPCODE_XSR_CCOMPARE1;
+	      if (Field_sr_Slot_inst_get (insn) == 242)
+		return OPCODE_XSR_CCOMPARE2;
+	      if (Field_sr_Slot_inst_get (insn) == 244)
+		return OPCODE_XSR_MISC0;
+	      if (Field_sr_Slot_inst_get (insn) == 245)
+		return OPCODE_XSR_MISC1;
+	      if (Field_sr_Slot_inst_get (insn) == 246)
+		return OPCODE_XSR_MISC2;
+	      if (Field_sr_Slot_inst_get (insn) == 247)
+		return OPCODE_XSR_MISC3;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 8)
+	    return OPCODE_SRC;
+	  if (Field_op2_Slot_inst_get (insn) == 9 &&
+	      Field_s_Slot_inst_get (insn) == 0)
+	    return OPCODE_SRL;
+	  if (Field_op2_Slot_inst_get (insn) == 10 &&
+	      Field_t_Slot_inst_get (insn) == 0)
+	    return OPCODE_SLL;
+	  if (Field_op2_Slot_inst_get (insn) == 11 &&
+	      Field_s_Slot_inst_get (insn) == 0)
+	    return OPCODE_SRA;
+	  if (Field_op2_Slot_inst_get (insn) == 12)
+	    return OPCODE_MUL16U;
+	  if (Field_op2_Slot_inst_get (insn) == 13)
+	    return OPCODE_MUL16S;
+	  if (Field_op2_Slot_inst_get (insn) == 15)
+	    {
+	      if (Field_r_Slot_inst_get (insn) == 14 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_RFDO;
+	      if (Field_r_Slot_inst_get (insn) == 14 &&
+		  Field_t_Slot_inst_get (insn) == 1)
+		return OPCODE_RFDD;
+	    }
+	}
+      if (Field_op1_Slot_inst_get (insn) == 2)
+	{
+	  if (Field_op2_Slot_inst_get (insn) == 0)
+	    return OPCODE_ANDB;
+	  if (Field_op2_Slot_inst_get (insn) == 1)
+	    return OPCODE_ANDBC;
+	  if (Field_op2_Slot_inst_get (insn) == 2)
+	    return OPCODE_ORB;
+	  if (Field_op2_Slot_inst_get (insn) == 3)
+	    return OPCODE_ORBC;
+	  if (Field_op2_Slot_inst_get (insn) == 4)
+	    return OPCODE_XORB;
+	  if (Field_op2_Slot_inst_get (insn) == 6)
+	    return OPCODE_SALTU;
+	  if (Field_op2_Slot_inst_get (insn) == 7)
+	    return OPCODE_SALT;
+	  if (Field_op2_Slot_inst_get (insn) == 8)
+	    return OPCODE_MULL;
+	  if (Field_op2_Slot_inst_get (insn) == 10)
+	    return OPCODE_MULUH;
+	  if (Field_op2_Slot_inst_get (insn) == 11)
+	    return OPCODE_MULSH;
+	  if (Field_op2_Slot_inst_get (insn) == 12)
+	    return OPCODE_QUOU;
+	  if (Field_op2_Slot_inst_get (insn) == 13)
+	    return OPCODE_QUOS;
+	  if (Field_op2_Slot_inst_get (insn) == 14)
+	    return OPCODE_REMU;
+	  if (Field_op2_Slot_inst_get (insn) == 15)
+	    return OPCODE_REMS;
+	}
+      if (Field_op1_Slot_inst_get (insn) == 3)
+	{
+	  if (Field_op2_Slot_inst_get (insn) == 0)
+	    {
+	      if (Field_sr_Slot_inst_get (insn) == 0)
+		return OPCODE_RSR_LBEG;
+	      if (Field_sr_Slot_inst_get (insn) == 1)
+		return OPCODE_RSR_LEND;
+	      if (Field_sr_Slot_inst_get (insn) == 2)
+		return OPCODE_RSR_LCOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 3)
+		return OPCODE_RSR_SAR;
+	      if (Field_sr_Slot_inst_get (insn) == 4)
+		return OPCODE_RSR_BR;
+	      if (Field_sr_Slot_inst_get (insn) == 5)
+		return OPCODE_RSR_LITBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 12)
+		return OPCODE_RSR_SCOMPARE1;
+	      if (Field_sr_Slot_inst_get (insn) == 16)
+		return OPCODE_RSR_ACCLO;
+	      if (Field_sr_Slot_inst_get (insn) == 17)
+		return OPCODE_RSR_ACCHI;
+	      if (Field_sr_Slot_inst_get (insn) == 32)
+		return OPCODE_RSR_M0;
+	      if (Field_sr_Slot_inst_get (insn) == 33)
+		return OPCODE_RSR_M1;
+	      if (Field_sr_Slot_inst_get (insn) == 34)
+		return OPCODE_RSR_M2;
+	      if (Field_sr_Slot_inst_get (insn) == 35)
+		return OPCODE_RSR_M3;
+	      if (Field_sr_Slot_inst_get (insn) == 72)
+		return OPCODE_RSR_WINDOWBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 73)
+		return OPCODE_RSR_WINDOWSTART;
+	      if (Field_sr_Slot_inst_get (insn) == 95)
+		return OPCODE_RSR_ERACCESS;
+	      if (Field_sr_Slot_inst_get (insn) == 96)
+		return OPCODE_RSR_IBREAKENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 97)
+		return OPCODE_RSR_MEMCTL;
+	      if (Field_sr_Slot_inst_get (insn) == 99)
+		return OPCODE_RSR_ATOMCTL;
+	      if (Field_sr_Slot_inst_get (insn) == 104)
+		return OPCODE_RSR_DDR;
+	      if (Field_sr_Slot_inst_get (insn) == 128)
+		return OPCODE_RSR_IBREAKA0;
+	      if (Field_sr_Slot_inst_get (insn) == 129)
+		return OPCODE_RSR_IBREAKA1;
+	      if (Field_sr_Slot_inst_get (insn) == 144)
+		return OPCODE_RSR_DBREAKA0;
+	      if (Field_sr_Slot_inst_get (insn) == 145)
+		return OPCODE_RSR_DBREAKA1;
+	      if (Field_sr_Slot_inst_get (insn) == 160)
+		return OPCODE_RSR_DBREAKC0;
+	      if (Field_sr_Slot_inst_get (insn) == 161)
+		return OPCODE_RSR_DBREAKC1;
+	      if (Field_sr_Slot_inst_get (insn) == 176)
+		return OPCODE_RSR_CONFIGID0;
+	      if (Field_sr_Slot_inst_get (insn) == 177)
+		return OPCODE_RSR_EPC1;
+	      if (Field_sr_Slot_inst_get (insn) == 178)
+		return OPCODE_RSR_EPC2;
+	      if (Field_sr_Slot_inst_get (insn) == 179)
+		return OPCODE_RSR_EPC3;
+	      if (Field_sr_Slot_inst_get (insn) == 180)
+		return OPCODE_RSR_EPC4;
+	      if (Field_sr_Slot_inst_get (insn) == 181)
+		return OPCODE_RSR_EPC5;
+	      if (Field_sr_Slot_inst_get (insn) == 182)
+		return OPCODE_RSR_EPC6;
+	      if (Field_sr_Slot_inst_get (insn) == 183)
+		return OPCODE_RSR_EPC7;
+	      if (Field_sr_Slot_inst_get (insn) == 192)
+		return OPCODE_RSR_DEPC;
+	      if (Field_sr_Slot_inst_get (insn) == 194)
+		return OPCODE_RSR_EPS2;
+	      if (Field_sr_Slot_inst_get (insn) == 195)
+		return OPCODE_RSR_EPS3;
+	      if (Field_sr_Slot_inst_get (insn) == 196)
+		return OPCODE_RSR_EPS4;
+	      if (Field_sr_Slot_inst_get (insn) == 197)
+		return OPCODE_RSR_EPS5;
+	      if (Field_sr_Slot_inst_get (insn) == 198)
+		return OPCODE_RSR_EPS6;
+	      if (Field_sr_Slot_inst_get (insn) == 199)
+		return OPCODE_RSR_EPS7;
+	      if (Field_sr_Slot_inst_get (insn) == 208)
+		return OPCODE_RSR_CONFIGID1;
+	      if (Field_sr_Slot_inst_get (insn) == 209)
+		return OPCODE_RSR_EXCSAVE1;
+	      if (Field_sr_Slot_inst_get (insn) == 210)
+		return OPCODE_RSR_EXCSAVE2;
+	      if (Field_sr_Slot_inst_get (insn) == 211)
+		return OPCODE_RSR_EXCSAVE3;
+	      if (Field_sr_Slot_inst_get (insn) == 212)
+		return OPCODE_RSR_EXCSAVE4;
+	      if (Field_sr_Slot_inst_get (insn) == 213)
+		return OPCODE_RSR_EXCSAVE5;
+	      if (Field_sr_Slot_inst_get (insn) == 214)
+		return OPCODE_RSR_EXCSAVE6;
+	      if (Field_sr_Slot_inst_get (insn) == 215)
+		return OPCODE_RSR_EXCSAVE7;
+	      if (Field_sr_Slot_inst_get (insn) == 224)
+		return OPCODE_RSR_CPENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 226)
+		return OPCODE_RSR_INTERRUPT;
+	      if (Field_sr_Slot_inst_get (insn) == 228)
+		return OPCODE_RSR_INTENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 230)
+		return OPCODE_RSR_PS;
+	      if (Field_sr_Slot_inst_get (insn) == 231)
+		return OPCODE_RSR_VECBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 232)
+		return OPCODE_RSR_EXCCAUSE;
+	      if (Field_sr_Slot_inst_get (insn) == 233)
+		return OPCODE_RSR_DEBUGCAUSE;
+	      if (Field_sr_Slot_inst_get (insn) == 234)
+		return OPCODE_RSR_CCOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 235)
+		return OPCODE_RSR_PRID;
+	      if (Field_sr_Slot_inst_get (insn) == 236)
+		return OPCODE_RSR_ICOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 237)
+		return OPCODE_RSR_ICOUNTLEVEL;
+	      if (Field_sr_Slot_inst_get (insn) == 238)
+		return OPCODE_RSR_EXCVADDR;
+	      if (Field_sr_Slot_inst_get (insn) == 240)
+		return OPCODE_RSR_CCOMPARE0;
+	      if (Field_sr_Slot_inst_get (insn) == 241)
+		return OPCODE_RSR_CCOMPARE1;
+	      if (Field_sr_Slot_inst_get (insn) == 242)
+		return OPCODE_RSR_CCOMPARE2;
+	      if (Field_sr_Slot_inst_get (insn) == 244)
+		return OPCODE_RSR_MISC0;
+	      if (Field_sr_Slot_inst_get (insn) == 245)
+		return OPCODE_RSR_MISC1;
+	      if (Field_sr_Slot_inst_get (insn) == 246)
+		return OPCODE_RSR_MISC2;
+	      if (Field_sr_Slot_inst_get (insn) == 247)
+		return OPCODE_RSR_MISC3;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 1)
+	    {
+	      if (Field_sr_Slot_inst_get (insn) == 0)
+		return OPCODE_WSR_LBEG;
+	      if (Field_sr_Slot_inst_get (insn) == 1)
+		return OPCODE_WSR_LEND;
+	      if (Field_sr_Slot_inst_get (insn) == 2)
+		return OPCODE_WSR_LCOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 3)
+		return OPCODE_WSR_SAR;
+	      if (Field_sr_Slot_inst_get (insn) == 4)
+		return OPCODE_WSR_BR;
+	      if (Field_sr_Slot_inst_get (insn) == 5)
+		return OPCODE_WSR_LITBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 12)
+		return OPCODE_WSR_SCOMPARE1;
+	      if (Field_sr_Slot_inst_get (insn) == 16)
+		return OPCODE_WSR_ACCLO;
+	      if (Field_sr_Slot_inst_get (insn) == 17)
+		return OPCODE_WSR_ACCHI;
+	      if (Field_sr_Slot_inst_get (insn) == 32)
+		return OPCODE_WSR_M0;
+	      if (Field_sr_Slot_inst_get (insn) == 33)
+		return OPCODE_WSR_M1;
+	      if (Field_sr_Slot_inst_get (insn) == 34)
+		return OPCODE_WSR_M2;
+	      if (Field_sr_Slot_inst_get (insn) == 35)
+		return OPCODE_WSR_M3;
+	      if (Field_sr_Slot_inst_get (insn) == 72)
+		return OPCODE_WSR_WINDOWBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 73)
+		return OPCODE_WSR_WINDOWSTART;
+	      if (Field_sr_Slot_inst_get (insn) == 89)
+		return OPCODE_WSR_MMID;
+	      if (Field_sr_Slot_inst_get (insn) == 95)
+		return OPCODE_WSR_ERACCESS;
+	      if (Field_sr_Slot_inst_get (insn) == 96)
+		return OPCODE_WSR_IBREAKENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 97)
+		return OPCODE_WSR_MEMCTL;
+	      if (Field_sr_Slot_inst_get (insn) == 99)
+		return OPCODE_WSR_ATOMCTL;
+	      if (Field_sr_Slot_inst_get (insn) == 104)
+		return OPCODE_WSR_DDR;
+	      if (Field_sr_Slot_inst_get (insn) == 128)
+		return OPCODE_WSR_IBREAKA0;
+	      if (Field_sr_Slot_inst_get (insn) == 129)
+		return OPCODE_WSR_IBREAKA1;
+	      if (Field_sr_Slot_inst_get (insn) == 144)
+		return OPCODE_WSR_DBREAKA0;
+	      if (Field_sr_Slot_inst_get (insn) == 145)
+		return OPCODE_WSR_DBREAKA1;
+	      if (Field_sr_Slot_inst_get (insn) == 160)
+		return OPCODE_WSR_DBREAKC0;
+	      if (Field_sr_Slot_inst_get (insn) == 161)
+		return OPCODE_WSR_DBREAKC1;
+	      if (Field_sr_Slot_inst_get (insn) == 176)
+		return OPCODE_WSR_CONFIGID0;
+	      if (Field_sr_Slot_inst_get (insn) == 177)
+		return OPCODE_WSR_EPC1;
+	      if (Field_sr_Slot_inst_get (insn) == 178)
+		return OPCODE_WSR_EPC2;
+	      if (Field_sr_Slot_inst_get (insn) == 179)
+		return OPCODE_WSR_EPC3;
+	      if (Field_sr_Slot_inst_get (insn) == 180)
+		return OPCODE_WSR_EPC4;
+	      if (Field_sr_Slot_inst_get (insn) == 181)
+		return OPCODE_WSR_EPC5;
+	      if (Field_sr_Slot_inst_get (insn) == 182)
+		return OPCODE_WSR_EPC6;
+	      if (Field_sr_Slot_inst_get (insn) == 183)
+		return OPCODE_WSR_EPC7;
+	      if (Field_sr_Slot_inst_get (insn) == 192)
+		return OPCODE_WSR_DEPC;
+	      if (Field_sr_Slot_inst_get (insn) == 194)
+		return OPCODE_WSR_EPS2;
+	      if (Field_sr_Slot_inst_get (insn) == 195)
+		return OPCODE_WSR_EPS3;
+	      if (Field_sr_Slot_inst_get (insn) == 196)
+		return OPCODE_WSR_EPS4;
+	      if (Field_sr_Slot_inst_get (insn) == 197)
+		return OPCODE_WSR_EPS5;
+	      if (Field_sr_Slot_inst_get (insn) == 198)
+		return OPCODE_WSR_EPS6;
+	      if (Field_sr_Slot_inst_get (insn) == 199)
+		return OPCODE_WSR_EPS7;
+	      if (Field_sr_Slot_inst_get (insn) == 209)
+		return OPCODE_WSR_EXCSAVE1;
+	      if (Field_sr_Slot_inst_get (insn) == 210)
+		return OPCODE_WSR_EXCSAVE2;
+	      if (Field_sr_Slot_inst_get (insn) == 211)
+		return OPCODE_WSR_EXCSAVE3;
+	      if (Field_sr_Slot_inst_get (insn) == 212)
+		return OPCODE_WSR_EXCSAVE4;
+	      if (Field_sr_Slot_inst_get (insn) == 213)
+		return OPCODE_WSR_EXCSAVE5;
+	      if (Field_sr_Slot_inst_get (insn) == 214)
+		return OPCODE_WSR_EXCSAVE6;
+	      if (Field_sr_Slot_inst_get (insn) == 215)
+		return OPCODE_WSR_EXCSAVE7;
+	      if (Field_sr_Slot_inst_get (insn) == 224)
+		return OPCODE_WSR_CPENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 226)
+		return OPCODE_WSR_INTSET;
+	      if (Field_sr_Slot_inst_get (insn) == 227)
+		return OPCODE_WSR_INTCLEAR;
+	      if (Field_sr_Slot_inst_get (insn) == 228)
+		return OPCODE_WSR_INTENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 230)
+		return OPCODE_WSR_PS;
+	      if (Field_sr_Slot_inst_get (insn) == 231)
+		return OPCODE_WSR_VECBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 232)
+		return OPCODE_WSR_EXCCAUSE;
+	      if (Field_sr_Slot_inst_get (insn) == 233)
+		return OPCODE_WSR_DEBUGCAUSE;
+	      if (Field_sr_Slot_inst_get (insn) == 234)
+		return OPCODE_WSR_CCOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 236)
+		return OPCODE_WSR_ICOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 237)
+		return OPCODE_WSR_ICOUNTLEVEL;
+	      if (Field_sr_Slot_inst_get (insn) == 238)
+		return OPCODE_WSR_EXCVADDR;
+	      if (Field_sr_Slot_inst_get (insn) == 240)
+		return OPCODE_WSR_CCOMPARE0;
+	      if (Field_sr_Slot_inst_get (insn) == 241)
+		return OPCODE_WSR_CCOMPARE1;
+	      if (Field_sr_Slot_inst_get (insn) == 242)
+		return OPCODE_WSR_CCOMPARE2;
+	      if (Field_sr_Slot_inst_get (insn) == 244)
+		return OPCODE_WSR_MISC0;
+	      if (Field_sr_Slot_inst_get (insn) == 245)
+		return OPCODE_WSR_MISC1;
+	      if (Field_sr_Slot_inst_get (insn) == 246)
+		return OPCODE_WSR_MISC2;
+	      if (Field_sr_Slot_inst_get (insn) == 247)
+		return OPCODE_WSR_MISC3;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 2)
+	    return OPCODE_SEXT;
+	  if (Field_op2_Slot_inst_get (insn) == 3)
+	    return OPCODE_CLAMPS;
+	  if (Field_op2_Slot_inst_get (insn) == 4)
+	    return OPCODE_MIN;
+	  if (Field_op2_Slot_inst_get (insn) == 5)
+	    return OPCODE_MAX;
+	  if (Field_op2_Slot_inst_get (insn) == 6)
+	    return OPCODE_MINU;
+	  if (Field_op2_Slot_inst_get (insn) == 7)
+	    return OPCODE_MAXU;
+	  if (Field_op2_Slot_inst_get (insn) == 8)
+	    return OPCODE_MOVEQZ;
+	  if (Field_op2_Slot_inst_get (insn) == 9)
+	    return OPCODE_MOVNEZ;
+	  if (Field_op2_Slot_inst_get (insn) == 10)
+	    return OPCODE_MOVLTZ;
+	  if (Field_op2_Slot_inst_get (insn) == 11)
+	    return OPCODE_MOVGEZ;
+	  if (Field_op2_Slot_inst_get (insn) == 12)
+	    return OPCODE_MOVF;
+	  if (Field_op2_Slot_inst_get (insn) == 13)
+	    return OPCODE_MOVT;
+	  if (Field_op2_Slot_inst_get (insn) == 14)
+	    {
+	      if (Field_st_Slot_inst_get (insn) == 0)
+		return OPCODE_RUR_ACCX_0;
+	      if (Field_st_Slot_inst_get (insn) == 1)
+		return OPCODE_RUR_ACCX_1;
+	      if (Field_st_Slot_inst_get (insn) == 2)
+		return OPCODE_RUR_QACC_H_0;
+	      if (Field_st_Slot_inst_get (insn) == 3)
+		return OPCODE_RUR_QACC_H_1;
+	      if (Field_st_Slot_inst_get (insn) == 4)
+		return OPCODE_RUR_QACC_H_2;
+	      if (Field_st_Slot_inst_get (insn) == 5)
+		return OPCODE_RUR_QACC_H_3;
+	      if (Field_st_Slot_inst_get (insn) == 6)
+		return OPCODE_RUR_QACC_H_4;
+	      if (Field_st_Slot_inst_get (insn) == 7)
+		return OPCODE_RUR_QACC_L_0;
+	      if (Field_st_Slot_inst_get (insn) == 8)
+		return OPCODE_RUR_QACC_L_1;
+	      if (Field_st_Slot_inst_get (insn) == 9)
+		return OPCODE_RUR_QACC_L_2;
+	      if (Field_st_Slot_inst_get (insn) == 10)
+		return OPCODE_RUR_QACC_L_3;
+	      if (Field_st_Slot_inst_get (insn) == 11)
+		return OPCODE_RUR_QACC_L_4;
+	      if (Field_st_Slot_inst_get (insn) == 12)
+		return OPCODE_RUR_GPIO_OUT;
+	      if (Field_st_Slot_inst_get (insn) == 13)
+		return OPCODE_RUR_SAR_BYTE;
+	      if (Field_st_Slot_inst_get (insn) == 14)
+		return OPCODE_RUR_FFT_BIT_WIDTH;
+	      if (Field_st_Slot_inst_get (insn) == 15)
+		return OPCODE_RUR_UA_STATE_0;
+	      if (Field_st_Slot_inst_get (insn) == 16)
+		return OPCODE_RUR_UA_STATE_1;
+	      if (Field_st_Slot_inst_get (insn) == 17)
+		return OPCODE_RUR_UA_STATE_2;
+	      if (Field_st_Slot_inst_get (insn) == 18)
+		return OPCODE_RUR_UA_STATE_3;
+	      if (Field_st_Slot_inst_get (insn) == 231)
+		return OPCODE_RUR_THREADPTR;
+	      if (Field_st_Slot_inst_get (insn) == 232)
+		return OPCODE_RUR_FCR;
+	      if (Field_st_Slot_inst_get (insn) == 233)
+		return OPCODE_RUR_FSR;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 15)
+	    {
+	      if (Field_sr_Slot_inst_get (insn) == 0)
+		return OPCODE_WUR_ACCX_0;
+	      if (Field_sr_Slot_inst_get (insn) == 1)
+		return OPCODE_WUR_ACCX_1;
+	      if (Field_sr_Slot_inst_get (insn) == 2)
+		return OPCODE_WUR_QACC_H_0;
+	      if (Field_sr_Slot_inst_get (insn) == 3)
+		return OPCODE_WUR_QACC_H_1;
+	      if (Field_sr_Slot_inst_get (insn) == 4)
+		return OPCODE_WUR_QACC_H_2;
+	      if (Field_sr_Slot_inst_get (insn) == 5)
+		return OPCODE_WUR_QACC_H_3;
+	      if (Field_sr_Slot_inst_get (insn) == 6)
+		return OPCODE_WUR_QACC_H_4;
+	      if (Field_sr_Slot_inst_get (insn) == 7)
+		return OPCODE_WUR_QACC_L_0;
+	      if (Field_sr_Slot_inst_get (insn) == 8)
+		return OPCODE_WUR_QACC_L_1;
+	      if (Field_sr_Slot_inst_get (insn) == 9)
+		return OPCODE_WUR_QACC_L_2;
+	      if (Field_sr_Slot_inst_get (insn) == 10)
+		return OPCODE_WUR_QACC_L_3;
+	      if (Field_sr_Slot_inst_get (insn) == 11)
+		return OPCODE_WUR_QACC_L_4;
+	      if (Field_sr_Slot_inst_get (insn) == 12)
+		return OPCODE_WUR_GPIO_OUT;
+	      if (Field_sr_Slot_inst_get (insn) == 13)
+		return OPCODE_WUR_SAR_BYTE;
+	      if (Field_sr_Slot_inst_get (insn) == 14)
+		return OPCODE_WUR_FFT_BIT_WIDTH;
+	      if (Field_sr_Slot_inst_get (insn) == 15)
+		return OPCODE_WUR_UA_STATE_0;
+	      if (Field_sr_Slot_inst_get (insn) == 16)
+		return OPCODE_WUR_UA_STATE_1;
+	      if (Field_sr_Slot_inst_get (insn) == 17)
+		return OPCODE_WUR_UA_STATE_2;
+	      if (Field_sr_Slot_inst_get (insn) == 18)
+		return OPCODE_WUR_UA_STATE_3;
+	      if (Field_sr_Slot_inst_get (insn) == 231)
+		return OPCODE_WUR_THREADPTR;
+	      if (Field_sr_Slot_inst_get (insn) == 232)
+		return OPCODE_WUR_FCR;
+	      if (Field_sr_Slot_inst_get (insn) == 233)
+		return OPCODE_WUR_FSR;
+	    }
+	}
+      if ((Field_op1_Slot_inst_get (insn) == 4 ||
+	   Field_op1_Slot_inst_get (insn) == 5))
+	return OPCODE_EXTUI;
+      if (Field_op1_Slot_inst_get (insn) == 8)
+	{
+	  if (Field_op2_Slot_inst_get (insn) == 0)
+	    return OPCODE_LSX;
+	  if (Field_op2_Slot_inst_get (insn) == 1)
+	    return OPCODE_LSXP;
+	  if (Field_op2_Slot_inst_get (insn) == 4)
+	    return OPCODE_SSX;
+	  if (Field_op2_Slot_inst_get (insn) == 5)
+	    return OPCODE_SSXP;
+	}
+      if (Field_op1_Slot_inst_get (insn) == 9)
+	{
+	  if (Field_op2_Slot_inst_get (insn) == 0)
+	    return OPCODE_L32E;
+	  if (Field_op2_Slot_inst_get (insn) == 4)
+	    return OPCODE_S32E;
+	  if (Field_op2_Slot_inst_get (insn) == 5)
+	    return OPCODE_S32NB;
+	}
+      if (Field_op1_Slot_inst_get (insn) == 10)
+	{
+	  if (Field_op2_Slot_inst_get (insn) == 0)
+	    return OPCODE_ADD_S;
+	  if (Field_op2_Slot_inst_get (insn) == 1)
+	    return OPCODE_SUB_S;
+	  if (Field_op2_Slot_inst_get (insn) == 2)
+	    return OPCODE_MUL_S;
+	  if (Field_op2_Slot_inst_get (insn) == 4)
+	    return OPCODE_MADD_S;
+	  if (Field_op2_Slot_inst_get (insn) == 5)
+	    return OPCODE_MSUB_S;
+	  if (Field_op2_Slot_inst_get (insn) == 6)
+	    return OPCODE_MADDN_S;
+	  if (Field_op2_Slot_inst_get (insn) == 7)
+	    return OPCODE_DIVN_S;
+	  if (Field_op2_Slot_inst_get (insn) == 8)
+	    return OPCODE_ROUND_S;
+	  if (Field_op2_Slot_inst_get (insn) == 9)
+	    return OPCODE_TRUNC_S;
+	  if (Field_op2_Slot_inst_get (insn) == 10)
+	    return OPCODE_FLOOR_S;
+	  if (Field_op2_Slot_inst_get (insn) == 11)
+	    return OPCODE_CEIL_S;
+	  if (Field_op2_Slot_inst_get (insn) == 12)
+	    return OPCODE_FLOAT_S;
+	  if (Field_op2_Slot_inst_get (insn) == 13)
+	    return OPCODE_UFLOAT_S;
+	  if (Field_op2_Slot_inst_get (insn) == 14)
+	    return OPCODE_UTRUNC_S;
+	  if (Field_op2_Slot_inst_get (insn) == 15)
+	    {
+	      if (Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_MOV_S;
+	      if (Field_t_Slot_inst_get (insn) == 1)
+		return OPCODE_ABS_S;
+	      if (Field_t_Slot_inst_get (insn) == 3)
+		return OPCODE_CONST_S;
+	      if (Field_t_Slot_inst_get (insn) == 4)
+		return OPCODE_RFR;
+	      if (Field_t_Slot_inst_get (insn) == 5)
+		return OPCODE_WFR;
+	      if (Field_t_Slot_inst_get (insn) == 6)
+		return OPCODE_NEG_S;
+	      if (Field_t_Slot_inst_get (insn) == 7)
+		return OPCODE_DIV0_S;
+	      if (Field_t_Slot_inst_get (insn) == 8)
+		return OPCODE_RECIP0_S;
+	      if (Field_t_Slot_inst_get (insn) == 9)
+		return OPCODE_SQRT0_S;
+	      if (Field_t_Slot_inst_get (insn) == 10)
+		return OPCODE_RSQRT0_S;
+	      if (Field_t_Slot_inst_get (insn) == 11)
+		return OPCODE_NEXP01_S;
+	      if (Field_t_Slot_inst_get (insn) == 12)
+		return OPCODE_MKSADJ_S;
+	      if (Field_t_Slot_inst_get (insn) == 13)
+		return OPCODE_MKDADJ_S;
+	      if (Field_t_Slot_inst_get (insn) == 14)
+		return OPCODE_ADDEXP_S;
+	      if (Field_t_Slot_inst_get (insn) == 15)
+		return OPCODE_ADDEXPM_S;
+	    }
+	}
+      if (Field_op1_Slot_inst_get (insn) == 11)
+	{
+	  if (Field_op2_Slot_inst_get (insn) == 1)
+	    return OPCODE_UN_S;
+	  if (Field_op2_Slot_inst_get (insn) == 2)
+	    return OPCODE_OEQ_S;
+	  if (Field_op2_Slot_inst_get (insn) == 3)
+	    return OPCODE_UEQ_S;
+	  if (Field_op2_Slot_inst_get (insn) == 4)
+	    return OPCODE_OLT_S;
+	  if (Field_op2_Slot_inst_get (insn) == 5)
+	    return OPCODE_ULT_S;
+	  if (Field_op2_Slot_inst_get (insn) == 6)
+	    return OPCODE_OLE_S;
+	  if (Field_op2_Slot_inst_get (insn) == 7)
+	    return OPCODE_ULE_S;
+	  if (Field_op2_Slot_inst_get (insn) == 8)
+	    return OPCODE_MOVEQZ_S;
+	  if (Field_op2_Slot_inst_get (insn) == 9)
+	    return OPCODE_MOVNEZ_S;
+	  if (Field_op2_Slot_inst_get (insn) == 10)
+	    return OPCODE_MOVLTZ_S;
+	  if (Field_op2_Slot_inst_get (insn) == 11)
+	    return OPCODE_MOVGEZ_S;
+	  if (Field_op2_Slot_inst_get (insn) == 12)
+	    return OPCODE_MOVF_S;
+	  if (Field_op2_Slot_inst_get (insn) == 13)
+	    return OPCODE_MOVT_S;
+	}
+    }
+  if (Field_op0_Slot_inst_get (insn) == 1)
+    return OPCODE_L32R;
+  if (Field_op0_Slot_inst_get (insn) == 2)
+    {
+      if (Field_r_Slot_inst_get (insn) == 0)
+	return OPCODE_L8UI;
+      if (Field_r_Slot_inst_get (insn) == 1)
+	return OPCODE_L16UI;
+      if (Field_r_Slot_inst_get (insn) == 2)
+	return OPCODE_L32I;
+      if (Field_r_Slot_inst_get (insn) == 4)
+	return OPCODE_S8I;
+      if (Field_r_Slot_inst_get (insn) == 5)
+	return OPCODE_S16I;
+      if (Field_r_Slot_inst_get (insn) == 6)
+	return OPCODE_S32I;
+      if (Field_r_Slot_inst_get (insn) == 9)
+	return OPCODE_L16SI;
+      if (Field_r_Slot_inst_get (insn) == 10)
+	return OPCODE_MOVI;
+      if (Field_r_Slot_inst_get (insn) == 11)
+	return OPCODE_L32AI;
+      if (Field_r_Slot_inst_get (insn) == 12)
+	return OPCODE_ADDI;
+      if (Field_r_Slot_inst_get (insn) == 13)
+	return OPCODE_ADDMI;
+      if (Field_r_Slot_inst_get (insn) == 14)
+	return OPCODE_S32C1I;
+      if (Field_r_Slot_inst_get (insn) == 15)
+	return OPCODE_S32RI;
+    }
+  if (Field_op0_Slot_inst_get (insn) == 3)
+    {
+      if (Field_r_Slot_inst_get (insn) == 0)
+	return OPCODE_LSI;
+      if (Field_r_Slot_inst_get (insn) == 4)
+	return OPCODE_SSI;
+      if (Field_r_Slot_inst_get (insn) == 8)
+	return OPCODE_LSIP;
+      if (Field_r_Slot_inst_get (insn) == 12)
+	return OPCODE_SSIP;
+    }
+  if (Field_op0_Slot_inst_get (insn) == 4)
+    {
+      if (Field_op2_Slot_inst_get (insn) == 0)
+	{
+	  if (Field_op1_Slot_inst_get (insn) == 8 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DD_LL_LDINC;
+	  if (Field_op1_Slot_inst_get (insn) == 9 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DD_HL_LDINC;
+	  if (Field_op1_Slot_inst_get (insn) == 10 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DD_LH_LDINC;
+	  if (Field_op1_Slot_inst_get (insn) == 11 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DD_HH_LDINC;
+	}
+      if (Field_op2_Slot_inst_get (insn) == 1)
+	{
+	  if (Field_op1_Slot_inst_get (insn) == 8 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DD_LL_LDDEC;
+	  if (Field_op1_Slot_inst_get (insn) == 9 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DD_HL_LDDEC;
+	  if (Field_op1_Slot_inst_get (insn) == 10 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DD_LH_LDDEC;
+	  if (Field_op1_Slot_inst_get (insn) == 11 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DD_HH_LDDEC;
+	}
+      if (Field_op2_Slot_inst_get (insn) == 2)
+	{
+	  if (Field_op1_Slot_inst_get (insn) == 4 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_DD_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 5 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_DD_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 6 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_DD_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 7 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_DD_HH;
+	  if (Field_op1_Slot_inst_get (insn) == 8 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DD_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 9 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DD_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 10 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DD_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 11 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DD_HH;
+	  if (Field_op1_Slot_inst_get (insn) == 12 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_DD_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 13 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_DD_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 14 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_DD_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 15 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_DD_HH;
+	}
+      if (Field_op2_Slot_inst_get (insn) == 3)
+	{
+	  if (Field_op1_Slot_inst_get (insn) == 4 &&
+	      Field_r_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_AD_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 5 &&
+	      Field_r_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_AD_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 6 &&
+	      Field_r_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_AD_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 7 &&
+	      Field_r_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_AD_HH;
+	  if (Field_op1_Slot_inst_get (insn) == 8 &&
+	      Field_r_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_AD_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 9 &&
+	      Field_r_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_AD_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 10 &&
+	      Field_r_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_AD_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 11 &&
+	      Field_r_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_AD_HH;
+	  if (Field_op1_Slot_inst_get (insn) == 12 &&
+	      Field_r_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_AD_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 13 &&
+	      Field_r_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_AD_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 14 &&
+	      Field_r_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_AD_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 15 &&
+	      Field_r_Slot_inst_get (insn) == 0 &&
+	      Field_t3_Slot_inst_get (insn) == 0 &&
+	      Field_tlo_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_AD_HH;
+	}
+      if (Field_op2_Slot_inst_get (insn) == 4)
+	{
+	  if (Field_op1_Slot_inst_get (insn) == 8 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DA_LL_LDINC;
+	  if (Field_op1_Slot_inst_get (insn) == 9 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DA_HL_LDINC;
+	  if (Field_op1_Slot_inst_get (insn) == 10 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DA_LH_LDINC;
+	  if (Field_op1_Slot_inst_get (insn) == 11 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DA_HH_LDINC;
+	}
+      if (Field_op2_Slot_inst_get (insn) == 5)
+	{
+	  if (Field_op1_Slot_inst_get (insn) == 8 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DA_LL_LDDEC;
+	  if (Field_op1_Slot_inst_get (insn) == 9 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DA_HL_LDDEC;
+	  if (Field_op1_Slot_inst_get (insn) == 10 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DA_LH_LDDEC;
+	  if (Field_op1_Slot_inst_get (insn) == 11 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DA_HH_LDDEC;
+	}
+      if (Field_op2_Slot_inst_get (insn) == 6)
+	{
+	  if (Field_op1_Slot_inst_get (insn) == 4 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_DA_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 5 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_DA_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 6 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_DA_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 7 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_DA_HH;
+	  if (Field_op1_Slot_inst_get (insn) == 8 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DA_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 9 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DA_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 10 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DA_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 11 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_DA_HH;
+	  if (Field_op1_Slot_inst_get (insn) == 12 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_DA_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 13 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_DA_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 14 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_DA_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 15 &&
+	      Field_s_Slot_inst_get (insn) == 0 &&
+	      Field_w_Slot_inst_get (insn) == 0 &&
+	      Field_r3_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_DA_HH;
+	}
+      if (Field_op2_Slot_inst_get (insn) == 7)
+	{
+	  if (Field_op1_Slot_inst_get (insn) == 0 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_UMUL_AA_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 1 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_UMUL_AA_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 2 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_UMUL_AA_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 3 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_UMUL_AA_HH;
+	  if (Field_op1_Slot_inst_get (insn) == 4 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_AA_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 5 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_AA_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 6 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_AA_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 7 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_MUL_AA_HH;
+	  if (Field_op1_Slot_inst_get (insn) == 8 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_AA_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 9 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_AA_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 10 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_AA_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 11 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULA_AA_HH;
+	  if (Field_op1_Slot_inst_get (insn) == 12 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_AA_LL;
+	  if (Field_op1_Slot_inst_get (insn) == 13 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_AA_HL;
+	  if (Field_op1_Slot_inst_get (insn) == 14 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_AA_LH;
+	  if (Field_op1_Slot_inst_get (insn) == 15 &&
+	      Field_r_Slot_inst_get (insn) == 0)
+	    return OPCODE_MULS_AA_HH;
+	}
+      if (Field_op2_Slot_inst_get (insn) == 8)
+	{
+	  if (Field_op1_Slot_inst_get (insn) == 0 &&
+	      Field_t_Slot_inst_get (insn) == 0 &&
+	      Field_rhi_Slot_inst_get (insn) == 0)
+	    return OPCODE_LDINC;
+	}
+      if (Field_op2_Slot_inst_get (insn) == 9)
+	{
+	  if (Field_op1_Slot_inst_get (insn) == 0 &&
+	      Field_t_Slot_inst_get (insn) == 0 &&
+	      Field_rhi_Slot_inst_get (insn) == 0)
+	    return OPCODE_LDDEC;
+	}
+    }
+  if (Field_op0_Slot_inst_get (insn) == 5)
+    {
+      if (Field_n_Slot_inst_get (insn) == 0)
+	return OPCODE_CALL0;
+      if (Field_n_Slot_inst_get (insn) == 1)
+	return OPCODE_CALL4;
+      if (Field_n_Slot_inst_get (insn) == 2)
+	return OPCODE_CALL8;
+      if (Field_n_Slot_inst_get (insn) == 3)
+	return OPCODE_CALL12;
+    }
+  if (Field_op0_Slot_inst_get (insn) == 6)
+    {
+      if (Field_n_Slot_inst_get (insn) == 0)
+	return OPCODE_J;
+      if (Field_n_Slot_inst_get (insn) == 1)
+	{
+	  if (Field_m_Slot_inst_get (insn) == 0)
+	    return OPCODE_BEQZ;
+	  if (Field_m_Slot_inst_get (insn) == 1)
+	    return OPCODE_BNEZ;
+	  if (Field_m_Slot_inst_get (insn) == 2)
+	    return OPCODE_BLTZ;
+	  if (Field_m_Slot_inst_get (insn) == 3)
+	    return OPCODE_BGEZ;
+	}
+      if (Field_n_Slot_inst_get (insn) == 2)
+	{
+	  if (Field_m_Slot_inst_get (insn) == 0)
+	    return OPCODE_BEQI;
+	  if (Field_m_Slot_inst_get (insn) == 1)
+	    return OPCODE_BNEI;
+	  if (Field_m_Slot_inst_get (insn) == 2)
+	    return OPCODE_BLTI;
+	  if (Field_m_Slot_inst_get (insn) == 3)
+	    return OPCODE_BGEI;
+	}
+      if (Field_n_Slot_inst_get (insn) == 3)
+	{
+	  if (Field_m_Slot_inst_get (insn) == 0)
+	    return OPCODE_ENTRY;
+	  if (Field_m_Slot_inst_get (insn) == 1)
+	    {
+	      if (Field_r_Slot_inst_get (insn) == 0)
+		return OPCODE_BF;
+	      if (Field_r_Slot_inst_get (insn) == 1)
+		return OPCODE_BT;
+	      if (Field_r_Slot_inst_get (insn) == 8)
+		return OPCODE_LOOP;
+	      if (Field_r_Slot_inst_get (insn) == 9)
+		return OPCODE_LOOPNEZ;
+	      if (Field_r_Slot_inst_get (insn) == 10)
+		return OPCODE_LOOPGTZ;
+	    }
+	  if (Field_m_Slot_inst_get (insn) == 2)
+	    return OPCODE_BLTUI;
+	  if (Field_m_Slot_inst_get (insn) == 3)
+	    return OPCODE_BGEUI;
+	}
+    }
+  if (Field_op0_Slot_inst_get (insn) == 7)
+    {
+      if (Field_r_Slot_inst_get (insn) == 0)
+	return OPCODE_BNONE;
+      if (Field_r_Slot_inst_get (insn) == 1)
+	return OPCODE_BEQ;
+      if (Field_r_Slot_inst_get (insn) == 2)
+	return OPCODE_BLT;
+      if (Field_r_Slot_inst_get (insn) == 3)
+	return OPCODE_BLTU;
+      if (Field_r_Slot_inst_get (insn) == 4)
+	return OPCODE_BALL;
+      if (Field_r_Slot_inst_get (insn) == 5)
+	return OPCODE_BBC;
+      if ((Field_r_Slot_inst_get (insn) == 6 ||
+	   Field_r_Slot_inst_get (insn) == 7))
+	return OPCODE_BBCI;
+      if (Field_r_Slot_inst_get (insn) == 8)
+	return OPCODE_BANY;
+      if (Field_r_Slot_inst_get (insn) == 9)
+	return OPCODE_BNE;
+      if (Field_r_Slot_inst_get (insn) == 10)
+	return OPCODE_BGE;
+      if (Field_r_Slot_inst_get (insn) == 11)
+	return OPCODE_BGEU;
+      if (Field_r_Slot_inst_get (insn) == 12)
+	return OPCODE_BNALL;
+      if (Field_r_Slot_inst_get (insn) == 13)
+	return OPCODE_BBS;
+      if ((Field_r_Slot_inst_get (insn) == 14 ||
+	   Field_r_Slot_inst_get (insn) == 15))
+	return OPCODE_BBSI;
+    }
+  return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_inst16b_decode (const xtensa_insnbuf insn)
+{
+  if (Field_op0_Slot_inst16b_get (insn) == 12)
+    {
+      if (Field_i_Slot_inst16b_get (insn) == 0)
+	return OPCODE_MOVI_N;
+      if (Field_i_Slot_inst16b_get (insn) == 1)
+	{
+	  if (Field_z_Slot_inst16b_get (insn) == 0)
+	    return OPCODE_BEQZ_N;
+	  if (Field_z_Slot_inst16b_get (insn) == 1)
+	    return OPCODE_BNEZ_N;
+	}
+    }
+  if (Field_op0_Slot_inst16b_get (insn) == 13)
+    {
+      if (Field_r_Slot_inst16b_get (insn) == 0)
+	return OPCODE_MOV_N;
+      if (Field_r_Slot_inst16b_get (insn) == 15)
+	{
+	  if (Field_t_Slot_inst16b_get (insn) == 0)
+	    return OPCODE_RET_N;
+	  if (Field_t_Slot_inst16b_get (insn) == 1)
+	    return OPCODE_RETW_N;
+	  if (Field_t_Slot_inst16b_get (insn) == 2)
+	    return OPCODE_BREAK_N;
+	  if (Field_t_Slot_inst16b_get (insn) == 3 &&
+	      Field_s_Slot_inst16b_get (insn) == 0)
+	    return OPCODE_NOP_N;
+	  if (Field_t_Slot_inst16b_get (insn) == 6 &&
+	      Field_s_Slot_inst16b_get (insn) == 0)
+	    return OPCODE_ILL_N;
+	}
+    }
+  return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_inst16a_decode (const xtensa_insnbuf insn)
+{
+  if (Field_op0_Slot_inst16a_get (insn) == 8)
+    return OPCODE_L32I_N;
+  if (Field_op0_Slot_inst16a_get (insn) == 9)
+    return OPCODE_S32I_N;
+  if (Field_op0_Slot_inst16a_get (insn) == 10)
+    return OPCODE_ADD_N;
+  if (Field_op0_Slot_inst16a_get (insn) == 11)
+    return OPCODE_ADDI_N;
+  return XTENSA_UNDEFINED;
+}
+
+static int
+Slot_slot_format_32_0_decode (const xtensa_insnbuf insn)
+{
+  if (Field_fld_slot_format_32_0_28_20_Slot_slot_format_32_0_get (insn) == 456 &&
+      Field_fld_slot_format_32_0_7_6_Slot_slot_format_32_0_get (insn) == 0)
+    return OPCODE_EE_CMUL_S16_ST_INCP;
+  if (Field_fld_slot_format_32_0_28_20_Slot_slot_format_32_0_get (insn) == 457 &&
+      Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_get (insn) == 0)
+    return OPCODE_EE_VADDS_S16_ST_INCP;
+  if (Field_fld_slot_format_32_0_28_20_Slot_slot_format_32_0_get (insn) == 457 &&
+      Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_get (insn) == 1)
+    return OPCODE_EE_VADDS_S32_ST_INCP;
+  if (Field_fld_slot_format_32_0_28_20_Slot_slot_format_32_0_get (insn) == 457 &&
+      Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_get (insn) == 2)
+    return OPCODE_EE_VADDS_S8_ST_INCP;
+  if (Field_fld_slot_format_32_0_28_20_Slot_slot_format_32_0_get (insn) == 457 &&
+      Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_get (insn) == 3)
+    return OPCODE_EE_VMAX_S16_ST_INCP;
+  if (Field_fld_slot_format_32_0_28_20_Slot_slot_format_32_0_get (insn) == 458 &&
+      Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_get (insn) == 3)
+    return OPCODE_EE_VMUL_S8_ST_INCP;
+  if (Field_fld_slot_format_32_0_28_20_Slot_slot_format_32_0_get (insn) == 458 &&
+      Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_get (insn) == 0)
+    return OPCODE_EE_VMAX_S32_ST_INCP;
+  if (Field_fld_slot_format_32_0_28_20_Slot_slot_format_32_0_get (insn) == 458 &&
+      Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_get (insn) == 1)
+    return OPCODE_EE_VMIN_S16_ST_INCP;
+  if (Field_fld_slot_format_32_0_28_20_Slot_slot_format_32_0_get (insn) == 458 &&
+      Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_get (insn) == 2)
+    return OPCODE_EE_VMIN_S8_ST_INCP;
+  if (Field_fld_slot_format_32_0_28_20_Slot_slot_format_32_0_get (insn) == 459 &&
+      Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_get (insn) == 2)
+    return OPCODE_EE_VMUL_S16_ST_INCP;
+  if (Field_fld_slot_format_32_0_28_20_Slot_slot_format_32_0_get (insn) == 459 &&
+      Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_get (insn) == 3)
+    return OPCODE_EE_VMUL_U16_ST_INCP;
+  if (Field_fld_slot_format_32_0_28_20_Slot_slot_format_32_0_get (insn) == 459 &&
+      Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_get (insn) == 0)
+    return OPCODE_EE_VMAX_S8_ST_INCP;
+  if (Field_fld_slot_format_32_0_28_20_Slot_slot_format_32_0_get (insn) == 459 &&
+      Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_get (insn) == 1)
+    return OPCODE_EE_VMIN_S32_ST_INCP;
+  if (Field_fld_slot_format_32_0_28_20_Slot_slot_format_32_0_get (insn) == 464 &&
+      Field_fld_slot_format_32_0_13_11_Slot_slot_format_32_0_get (insn) == 0)
+    return OPCODE_EE_SRC_Q_LD_XP;
+  if (Field_fld_slot_format_32_0_28_20_Slot_slot_format_32_0_get (insn) == 465 &&
+      Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_get (insn) == 1)
+    return OPCODE_EE_VSUBS_S16_ST_INCP;
+  if (Field_fld_slot_format_32_0_28_20_Slot_slot_format_32_0_get (insn) == 465 &&
+      Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_get (insn) == 2)
+    return OPCODE_EE_VSUBS_S32_ST_INCP;
+  if (Field_fld_slot_format_32_0_28_20_Slot_slot_format_32_0_get (insn) == 465 &&
+      Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_get (insn) == 3)
+    return OPCODE_EE_VSUBS_S8_ST_INCP;
+  if (Field_fld_slot_format_32_0_28_20_Slot_slot_format_32_0_get (insn) == 465 &&
+      Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_get (insn) == 0)
+    return OPCODE_EE_VMUL_U8_ST_INCP;
+  if (Field_fld_slot_format_32_0_28_20_Slot_slot_format_32_0_get (insn) == 465 &&
+      Field_fld_slot_format_32_0_13_13_Slot_slot_format_32_0_get (insn) == 0 &&
+      Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_get (insn) == 4)
+    return OPCODE_EE_FFT_R2BF_S16_ST_INCP;
+  if (Field_fld_slot_format_32_0_28_22_Slot_slot_format_32_0_get (insn) == 112 &&
+      Field_fld_slot_format_32_0_10_4_Slot_slot_format_32_0_get (insn) == 125)
+    return OPCODE_EE_LDXQ_32;
+  if (Field_fld_slot_format_32_0_28_22_Slot_slot_format_32_0_get (insn) == 115 &&
+      Field_fld_slot_format_32_0_19_17_Slot_slot_format_32_0_get (insn) == 0 &&
+      Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_get (insn) == 0)
+    return OPCODE_EE_STXQ_32;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 44)
+    return OPCODE_EE_VMULAS_S16_ACCX_LD_XP_QUP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 45)
+    return OPCODE_EE_VMULAS_S16_QACC_LD_XP_QUP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 46)
+    return OPCODE_EE_VMULAS_S8_ACCX_LD_XP_QUP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 47)
+    return OPCODE_EE_VMULAS_S8_QACC_LD_XP_QUP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 48)
+    return OPCODE_EE_VMULAS_U16_ACCX_LD_XP_QUP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 49)
+    return OPCODE_EE_VMULAS_U16_QACC_LD_XP_QUP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 50)
+    return OPCODE_EE_VMULAS_U8_ACCX_LD_XP_QUP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 51)
+    return OPCODE_EE_VMULAS_U8_QACC_LD_XP_QUP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 52)
+    return OPCODE_EE_FFT_AMS_S16_LD_INCP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 53)
+    return OPCODE_EE_FFT_AMS_S16_LD_INCP_UAUP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 54)
+    return OPCODE_EE_FFT_AMS_S16_LD_R32_DECP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 55)
+    return OPCODE_EE_FFT_CMUL_S16_LD_XP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_7_5_Slot_slot_format_32_0_get (insn) == 2)
+    return OPCODE_EE_LDF_64_IP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_7_5_Slot_slot_format_32_0_get (insn) == 3)
+    return OPCODE_EE_STF_64_IP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_10_4_Slot_slot_format_32_0_get (insn) == 45)
+    return OPCODE_EE_VADDS_S16_LD_INCP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_10_4_Slot_slot_format_32_0_get (insn) == 61)
+    return OPCODE_EE_VADDS_S32_LD_INCP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_10_4_Slot_slot_format_32_0_get (insn) == 28)
+    return OPCODE_EE_VADDS_S8_LD_INCP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_10_4_Slot_slot_format_32_0_get (insn) == 77)
+    return OPCODE_EE_VSUBS_S16_LD_INCP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_10_4_Slot_slot_format_32_0_get (insn) == 93)
+    return OPCODE_EE_VSUBS_S32_LD_INCP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_10_4_Slot_slot_format_32_0_get (insn) == 109)
+    return OPCODE_EE_VSUBS_S8_LD_INCP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_10_4_Slot_slot_format_32_0_get (insn) == 63)
+    return OPCODE_EE_VMUL_S16_LD_INCP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_10_4_Slot_slot_format_32_0_get (insn) == 76)
+    return OPCODE_EE_VMUL_S8_LD_INCP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_10_4_Slot_slot_format_32_0_get (insn) == 92)
+    return OPCODE_EE_VMUL_U16_LD_INCP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_10_4_Slot_slot_format_32_0_get (insn) == 108)
+    return OPCODE_EE_VMUL_U8_LD_INCP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_10_6_Slot_slot_format_32_0_get (insn) == 3)
+    return OPCODE_EE_CMUL_S16_LD_INCP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_get (insn) == 8)
+    return OPCODE_EE_VMULAS_S16_QACC_LDBC_INCP_QUP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_get (insn) == 9)
+    return OPCODE_EE_VMULAS_S8_QACC_LDBC_INCP_QUP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_get (insn) == 10)
+    return OPCODE_EE_VMULAS_U16_QACC_LDBC_INCP_QUP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_get (insn) == 11)
+    return OPCODE_EE_VMULAS_U8_QACC_LDBC_INCP_QUP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_10_4_Slot_slot_format_32_0_get (insn) == 124)
+    return OPCODE_EE_VSMULAS_S16_QACC_LD_INCP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_10_9_Slot_slot_format_32_0_get (insn) == 1 &&
+      Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_get (insn) == 12)
+    return OPCODE_EE_VSMULAS_S8_QACC_LD_INCP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_10_4_Slot_slot_format_32_0_get (insn) == 29)
+    return OPCODE_EE_VMAX_S16_LD_INCP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_10_4_Slot_slot_format_32_0_get (insn) == 30)
+    return OPCODE_EE_VMAX_S32_LD_INCP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_10_4_Slot_slot_format_32_0_get (insn) == 31)
+    return OPCODE_EE_VMAX_S8_LD_INCP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_10_4_Slot_slot_format_32_0_get (insn) == 46)
+    return OPCODE_EE_VMIN_S16_LD_INCP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_10_4_Slot_slot_format_32_0_get (insn) == 62)
+    return OPCODE_EE_VMIN_S32_LD_INCP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_10_4_Slot_slot_format_32_0_get (insn) == 47)
+    return OPCODE_EE_VMIN_S8_LD_INCP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 56 &&
+      Field_fld_slot_format_32_0_7_6_Slot_slot_format_32_0_get (insn) == 0)
+    return OPCODE_EE_SRC_Q_LD_IP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 60 &&
+      Field_fld_slot_format_32_0_19_17_Slot_slot_format_32_0_get (insn) == 0 &&
+      Field_fld_slot_format_32_0_10_8_Slot_slot_format_32_0_get (insn) == 1)
+    return OPCODE_EE_VMULAS_S16_ACCX_LD_XP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 60 &&
+      Field_fld_slot_format_32_0_19_17_Slot_slot_format_32_0_get (insn) == 2 &&
+      Field_fld_slot_format_32_0_10_8_Slot_slot_format_32_0_get (insn) == 1)
+    return OPCODE_EE_VMULAS_S8_ACCX_LD_XP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 60 &&
+      Field_fld_slot_format_32_0_19_17_Slot_slot_format_32_0_get (insn) == 4 &&
+      Field_fld_slot_format_32_0_10_8_Slot_slot_format_32_0_get (insn) == 1)
+    return OPCODE_EE_VMULAS_U16_ACCX_LD_XP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 60 &&
+      Field_fld_slot_format_32_0_19_17_Slot_slot_format_32_0_get (insn) == 6 &&
+      Field_fld_slot_format_32_0_10_8_Slot_slot_format_32_0_get (insn) == 1)
+    return OPCODE_EE_VMULAS_U8_ACCX_LD_XP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 60 &&
+      Field_fld_slot_format_32_0_19_17_Slot_slot_format_32_0_get (insn) == 1 &&
+      Field_fld_slot_format_32_0_10_8_Slot_slot_format_32_0_get (insn) == 1)
+    return OPCODE_EE_VMULAS_S16_QACC_LD_XP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 60 &&
+      Field_fld_slot_format_32_0_19_17_Slot_slot_format_32_0_get (insn) == 3 &&
+      Field_fld_slot_format_32_0_10_8_Slot_slot_format_32_0_get (insn) == 1)
+    return OPCODE_EE_VMULAS_S8_QACC_LD_XP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 60 &&
+      Field_fld_slot_format_32_0_19_17_Slot_slot_format_32_0_get (insn) == 5 &&
+      Field_fld_slot_format_32_0_10_8_Slot_slot_format_32_0_get (insn) == 1)
+    return OPCODE_EE_VMULAS_U16_QACC_LD_XP;
+  if (Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get (insn) == 60 &&
+      Field_fld_slot_format_32_0_19_17_Slot_slot_format_32_0_get (insn) == 7 &&
+      Field_fld_slot_format_32_0_10_8_Slot_slot_format_32_0_get (insn) == 1)
+    return OPCODE_EE_VMULAS_U8_QACC_LD_XP;
+  if (Field_fld_slot_format_32_0_28_24_Slot_slot_format_32_0_get (insn) == 16)
+    return OPCODE_EE_LDF_128_IP;
+  if (Field_fld_slot_format_32_0_28_24_Slot_slot_format_32_0_get (insn) == 17)
+    return OPCODE_EE_LDF_128_XP;
+  if (Field_fld_slot_format_32_0_28_24_Slot_slot_format_32_0_get (insn) == 18)
+    return OPCODE_EE_STF_128_IP;
+  if (Field_fld_slot_format_32_0_28_24_Slot_slot_format_32_0_get (insn) == 19)
+    return OPCODE_EE_STF_128_XP;
+  if (Field_fld_slot_format_32_0_28_24_Slot_slot_format_32_0_get (insn) == 20)
+    return OPCODE_EE_FFT_AMS_S16_ST_INCP;
+  if (Field_fld_slot_format_32_0_28_24_Slot_slot_format_32_0_get (insn) == 21)
+    return OPCODE_EE_FFT_CMUL_S16_ST_XP;
+  if (Field_fld_slot_format_32_0_28_25_Slot_slot_format_32_0_get (insn) == 0)
+    return OPCODE_EE_VMULAS_S16_ACCX_LD_IP_QUP;
+  if (Field_fld_slot_format_32_0_28_25_Slot_slot_format_32_0_get (insn) == 1)
+    return OPCODE_EE_VMULAS_S16_QACC_LD_IP_QUP;
+  if (Field_fld_slot_format_32_0_28_25_Slot_slot_format_32_0_get (insn) == 2)
+    return OPCODE_EE_VMULAS_S8_ACCX_LD_IP_QUP;
+  if (Field_fld_slot_format_32_0_28_25_Slot_slot_format_32_0_get (insn) == 3)
+    return OPCODE_EE_VMULAS_S8_QACC_LD_IP_QUP;
+  if (Field_fld_slot_format_32_0_28_25_Slot_slot_format_32_0_get (insn) == 4)
+    return OPCODE_EE_VMULAS_U16_ACCX_LD_IP_QUP;
+  if (Field_fld_slot_format_32_0_28_25_Slot_slot_format_32_0_get (insn) == 5)
+    return OPCODE_EE_VMULAS_U16_QACC_LD_IP_QUP;
+  if (Field_fld_slot_format_32_0_28_25_Slot_slot_format_32_0_get (insn) == 6)
+    return OPCODE_EE_VMULAS_U8_ACCX_LD_IP_QUP;
+  if (Field_fld_slot_format_32_0_28_25_Slot_slot_format_32_0_get (insn) == 7)
+    return OPCODE_EE_VMULAS_U8_QACC_LD_IP_QUP;
+  if (Field_fld_slot_format_32_0_28_25_Slot_slot_format_32_0_get (insn) == 15 &&
+      Field_fld_slot_format_32_0_19_17_Slot_slot_format_32_0_get (insn) == 0 &&
+      Field_fld_slot_format_32_0_10_8_Slot_slot_format_32_0_get (insn) == 0)
+    return OPCODE_EE_VMULAS_S16_ACCX_LD_IP;
+  if (Field_fld_slot_format_32_0_28_25_Slot_slot_format_32_0_get (insn) == 15 &&
+      Field_fld_slot_format_32_0_19_17_Slot_slot_format_32_0_get (insn) == 2 &&
+      Field_fld_slot_format_32_0_10_8_Slot_slot_format_32_0_get (insn) == 0)
+    return OPCODE_EE_VMULAS_S8_ACCX_LD_IP;
+  if (Field_fld_slot_format_32_0_28_25_Slot_slot_format_32_0_get (insn) == 15 &&
+      Field_fld_slot_format_32_0_19_17_Slot_slot_format_32_0_get (insn) == 4 &&
+      Field_fld_slot_format_32_0_10_8_Slot_slot_format_32_0_get (insn) == 0)
+    return OPCODE_EE_VMULAS_U16_ACCX_LD_IP;
+  if (Field_fld_slot_format_32_0_28_25_Slot_slot_format_32_0_get (insn) == 15 &&
+      Field_fld_slot_format_32_0_19_17_Slot_slot_format_32_0_get (insn) == 6 &&
+      Field_fld_slot_format_32_0_10_8_Slot_slot_format_32_0_get (insn) == 0)
+    return OPCODE_EE_VMULAS_U8_ACCX_LD_IP;
+  if (Field_fld_slot_format_32_0_28_25_Slot_slot_format_32_0_get (insn) == 15 &&
+      Field_fld_slot_format_32_0_19_17_Slot_slot_format_32_0_get (insn) == 1 &&
+      Field_fld_slot_format_32_0_10_8_Slot_slot_format_32_0_get (insn) == 0)
+    return OPCODE_EE_VMULAS_S16_QACC_LD_IP;
+  if (Field_fld_slot_format_32_0_28_25_Slot_slot_format_32_0_get (insn) == 15 &&
+      Field_fld_slot_format_32_0_19_17_Slot_slot_format_32_0_get (insn) == 3 &&
+      Field_fld_slot_format_32_0_10_8_Slot_slot_format_32_0_get (insn) == 0)
+    return OPCODE_EE_VMULAS_S8_QACC_LD_IP;
+  if (Field_fld_slot_format_32_0_28_25_Slot_slot_format_32_0_get (insn) == 15 &&
+      Field_fld_slot_format_32_0_19_17_Slot_slot_format_32_0_get (insn) == 5 &&
+      Field_fld_slot_format_32_0_10_8_Slot_slot_format_32_0_get (insn) == 0)
+    return OPCODE_EE_VMULAS_U16_QACC_LD_IP;
+  if (Field_fld_slot_format_32_0_28_25_Slot_slot_format_32_0_get (insn) == 15 &&
+      Field_fld_slot_format_32_0_19_17_Slot_slot_format_32_0_get (insn) == 7 &&
+      Field_fld_slot_format_32_0_10_8_Slot_slot_format_32_0_get (insn) == 0)
+    return OPCODE_EE_VMULAS_U8_QACC_LD_IP;
+  if (Field_fld_slot_format_32_0_28_4_Slot_slot_format_32_0_get (insn) == 30154752 &&
+      Field_fld_slot_format_32_0_3_0_Slot_slot_format_32_0_get (insn) == 0)
+    return OPCODE_NOP;
+  return XTENSA_UNDEFINED;
+}
+
+\f
+/* Instruction slots.  */
+
+static void
+Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
+			    xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = (insn[0] & 0xffffff);
+}
+
+static void
+Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
+			    const xtensa_insnbuf slotbuf)
+{
+  insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
+}
+
+static void
+Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
+				xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = (insn[0] & 0xffff);
+}
+
+static void
+Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
+				const xtensa_insnbuf slotbuf)
+{
+  insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
+}
+
+static void
+Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
+				xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = (insn[0] & 0xffff);
+}
+
+static void
+Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
+				const xtensa_insnbuf slotbuf)
+{
+  insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
+}
+
+static void
+Slot_format_32_Format_slot_format_32_0_0_get (const xtensa_insnbuf insn,
+					      xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = ((insn[0] & 0xff0) >> 4);
+  slotbuf[0] = (slotbuf[0] & ~0xf00) | (((insn[0] & 0xf00000) >> 20) << 8);
+  slotbuf[0] = (slotbuf[0] & ~0xf000) | (((insn[0] & 0xf000) >> 12) << 12);
+  slotbuf[0] = (slotbuf[0] & ~0x10000) | ((insn[0] & 0x1) << 16);
+  slotbuf[0] = (slotbuf[0] & ~0x1e0000) | (((insn[0] & 0xf0000) >> 16) << 17);
+  slotbuf[0] = (slotbuf[0] & ~0x1fe00000) | (((insn[0] & 0xff000000) >> 24) << 21);
+}
+
+static void
+Slot_format_32_Format_slot_format_32_0_0_set (xtensa_insnbuf insn,
+					      const xtensa_insnbuf slotbuf)
+{
+  insn[0] = (insn[0] & ~0xff0) | ((slotbuf[0] & 0xff) << 4);
+  insn[0] = (insn[0] & ~0xf00000) | (((slotbuf[0] & 0xf00) >> 8) << 20);
+  insn[0] = (insn[0] & ~0xf000) | (((slotbuf[0] & 0xf000) >> 12) << 12);
+  insn[0] = (insn[0] & ~0x1) | ((slotbuf[0] & 0x10000) >> 16);
+  insn[0] = (insn[0] & ~0xf0000) | (((slotbuf[0] & 0x1e0000) >> 17) << 16);
+  insn[0] = (insn[0] & ~0xff000000) | (((slotbuf[0] & 0x1fe00000) >> 21) << 24);
+}
+
+static xtensa_get_field_fn
+Slot_inst_get_field_fns[] = {
+  Field_t_Slot_inst_get,
+  Field_bbi4_Slot_inst_get,
+  Field_bbi_Slot_inst_get,
+  Field_imm12_Slot_inst_get,
+  Field_imm8_Slot_inst_get,
+  Field_s_Slot_inst_get,
+  Field_imm12b_Slot_inst_get,
+  Field_imm16_Slot_inst_get,
+  Field_m_Slot_inst_get,
+  Field_n_Slot_inst_get,
+  Field_offset_Slot_inst_get,
+  Field_op0_Slot_inst_get,
+  Field_op1_Slot_inst_get,
+  Field_op2_Slot_inst_get,
+  Field_r_Slot_inst_get,
+  Field_sa4_Slot_inst_get,
+  Field_sae4_Slot_inst_get,
+  Field_sae_Slot_inst_get,
+  Field_sal_Slot_inst_get,
+  Field_sargt_Slot_inst_get,
+  Field_sas4_Slot_inst_get,
+  Field_sas_Slot_inst_get,
+  Field_sr_Slot_inst_get,
+  Field_st_Slot_inst_get,
+  Field_thi3_Slot_inst_get,
+  Field_imm4_Slot_inst_get,
+  Field_mn_Slot_inst_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_r3_Slot_inst_get,
+  Field_rbit2_Slot_inst_get,
+  Field_rhi_Slot_inst_get,
+  Field_t3_Slot_inst_get,
+  Field_tbit2_Slot_inst_get,
+  Field_tlo_Slot_inst_get,
+  Field_w_Slot_inst_get,
+  Field_y_Slot_inst_get,
+  Field_x_Slot_inst_get,
+  Field_t2_Slot_inst_get,
+  Field_s2_Slot_inst_get,
+  Field_r2_Slot_inst_get,
+  Field_t4_Slot_inst_get,
+  Field_s4_Slot_inst_get,
+  Field_r4_Slot_inst_get,
+  Field_t8_Slot_inst_get,
+  Field_s8_Slot_inst_get,
+  Field_r8_Slot_inst_get,
+  Field_xt_wbr15_imm_Slot_inst_get,
+  Field_xt_wbr18_imm_Slot_inst_get,
+  0,
+  0,
+  Field_fld_st_qr_b_Slot_inst_get,
+  Field_fld_st_qr_a_Slot_inst_get,
+  Field_fld_ld_qr_b_Slot_inst_get,
+  Field_fld_ld_qr_a_Slot_inst_get,
+  Field_fld_qr_Slot_inst_get,
+  Field_fld_inst_4_0_Slot_inst_get,
+  Field_fld_inst_9_6_Slot_inst_get,
+  Field_fld_mv_qr_b_Slot_inst_get,
+  Field_fld_mv_qr_a_Slot_inst_get,
+  Field_fld_ee_wr_mask_gpio_out_mask_Slot_inst_get,
+  Field_fld_ee_wr_mask_gpio_out_value_Slot_inst_get,
+  Field_fld_ee_set_bit_gpio_out_mask_Slot_inst_get,
+  Field_fld_ee_clr_bit_gpio_out_clear_Slot_inst_get,
+  Field_fld_inst_23_8_Slot_inst_get,
+  Field_fld_ee_get_gpio_in_au_Slot_inst_get,
+  Field_fld_inst_23_22_Slot_inst_get,
+  Field_fld_semantic_ld_st_imm2_Slot_inst_get,
+  Field_fld_inst_14_8_Slot_inst_get,
+  Field_fld_semantic_ld_st_imm1_Slot_inst_get,
+  Field_fld_inst_11_8_Slot_inst_get,
+  Field_fld_semantic_ld_st_qu1_Slot_inst_get,
+  0,
+  Field_fld_semantic_ld_st_as_Slot_inst_get,
+  Field_fld_semantic_ld_st_fu0_Slot_inst_get,
+  Field_fld_semantic_ld_st_fu1_Slot_inst_get,
+  0,
+  0,
+  0,
+  Field_fld_semantic_ld_st_ad_Slot_inst_get,
+  Field_fld_semantic_ld_st_imm8_Slot_inst_get,
+  0,
+  Field_fld_inst_3_0_Slot_inst_get,
+  Field_fld_inst_19_16_Slot_inst_get,
+  Field_fld_inst_23_23_Slot_inst_get,
+  Field_fld_inst_14_12_Slot_inst_get,
+  Field_fld_inst_21_15_Slot_inst_get,
+  Field_fld_semantic_ld_st_imm16_Slot_inst_get,
+  Field_fld_inst_23_12_Slot_inst_get,
+  Field_fld_semantic_ld_st_imm4_Slot_inst_get,
+  0,
+  0,
+  0,
+  Field_fld_semantic_ld_st_qu_Slot_inst_get,
+  0,
+  Field_fld_semantic_ld_st_fv0_Slot_inst_get,
+  Field_fld_semantic_ld_st_fv1_Slot_inst_get,
+  0,
+  0,
+  Field_fld_semantic_ld_st_qv_Slot_inst_get,
+  Field_fld_ee_movi_32_a_sel4_Slot_inst_get,
+  Field_fld_ee_movi_32_a_au_Slot_inst_get,
+  Field_fld_ee_movi_32_a_qs_Slot_inst_get,
+  Field_fld_ee_movi_32_q_sel4_Slot_inst_get,
+  Field_fld_ee_movi_32_q_as_Slot_inst_get,
+  Field_fld_ee_movi_32_q_qu_Slot_inst_get,
+  Field_fld_ee_vzip_16_qs1_Slot_inst_get,
+  Field_fld_ee_vzip_16_qs0_Slot_inst_get,
+  Field_fld_ee_vzip_32_qs1_Slot_inst_get,
+  Field_fld_ee_vzip_32_qs0_Slot_inst_get,
+  Field_fld_ee_vzip_8_qs1_Slot_inst_get,
+  Field_fld_ee_vzip_8_qs0_Slot_inst_get,
+  Field_fld_inst_11_0_Slot_inst_get,
+  Field_fld_ee_vunzip_16_qs1_Slot_inst_get,
+  Field_fld_ee_vunzip_16_qs0_Slot_inst_get,
+  Field_fld_ee_vunzip_32_qs1_Slot_inst_get,
+  Field_fld_ee_vunzip_32_qs0_Slot_inst_get,
+  Field_fld_ee_vunzip_8_qs1_Slot_inst_get,
+  Field_fld_ee_vunzip_8_qs0_Slot_inst_get,
+  Field_fld_inst_23_0_Slot_inst_get,
+  Field_fld_ee_zero_q_qa_Slot_inst_get,
+  Field_fld_inst_14_0_Slot_inst_get,
+  Field_fld_ee_mov_s16_qacc_qs_Slot_inst_get,
+  Field_fld_ee_mov_s8_qacc_qs_Slot_inst_get,
+  Field_fld_ee_mov_u16_qacc_qs_Slot_inst_get,
+  Field_fld_ee_mov_u8_qacc_qs_Slot_inst_get,
+  0,
+  Field_fld_inst_7_0_Slot_inst_get,
+  Field_fld_semantic_cal_double_q_qa_Slot_inst_get,
+  Field_fld_semantic_cal_double_q_as_Slot_inst_get,
+  Field_fld_semantic_cal_double_q_qu_Slot_inst_get,
+  0,
+  0,
+  0,
+  Field_fld_inst_7_6_Slot_inst_get,
+  Field_fld_semantic_cal_double_q_sel4_Slot_inst_get,
+  Field_fld_semantic_cal_double_q_qy_Slot_inst_get,
+  Field_fld_semantic_cal_double_q_qx_Slot_inst_get,
+  Field_fld_semantic_cal_double_q_qz_Slot_inst_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_fld_inst_23_21_Slot_inst_get,
+  Field_fld_semantic_cal_double_q_sel8_Slot_inst_get,
+  0,
+  Field_fld_inst_7_5_Slot_inst_get,
+  Field_fld_semantic_cal_double_q_sel16_Slot_inst_get,
+  Field_fld_inst_14_11_Slot_inst_get,
+  Field_fld_semantic_srcmb_qacc_sel2_Slot_inst_get,
+  Field_fld_semantic_srcmb_qacc_as_Slot_inst_get,
+  Field_fld_semantic_srcmb_qacc_qu_Slot_inst_get,
+  Field_fld_inst_13_12_Slot_inst_get,
+  Field_fld_inst_23_15_Slot_inst_get,
+  Field_fld_ee_srs_accx_sel2_Slot_inst_get,
+  Field_fld_ee_srs_accx_as_Slot_inst_get,
+  Field_fld_ee_srs_accx_au_Slot_inst_get,
+  Field_fld_semantic_cal_double_q_ax_Slot_inst_get,
+  Field_fld_semantic_cal_double_q_qs_Slot_inst_get,
+  Field_fld_inst_13_13_Slot_inst_get,
+  Field_fld_semantic_cal_double_q_ay_Slot_inst_get,
+  Field_fld_inst_9_8_Slot_inst_get,
+  Field_fld_semantic_vlogic_qy_Slot_inst_get,
+  Field_fld_semantic_vlogic_qx_Slot_inst_get,
+  Field_fld_semantic_vlogic_qa_Slot_inst_get,
+  Field_fld_inst_5_5_Slot_inst_get,
+  Field_fld_semantic_shfq_sar16_Slot_inst_get,
+  Field_fld_semantic_shfq_qs0_Slot_inst_get,
+  Field_fld_semantic_shfq_qs1_Slot_inst_get,
+  Field_fld_semantic_shfq_ad_Slot_inst_get,
+  Field_fld_semantic_shfq_as_Slot_inst_get,
+  0,
+  0,
+  0,
+  0,
+  Field_fld_inst_11_7_Slot_inst_get,
+  Field_fld_semantic_shfq_qa_Slot_inst_get,
+  Field_fld_inst_14_7_Slot_inst_get,
+  Field_fld_semantic_shfq_qs_Slot_inst_get,
+  0,
+  0,
+  0,
+  Field_fld_inst_9_9_Slot_inst_get,
+  Field_fld_semantic_fft_rxbf_sel2_Slot_inst_get,
+  Field_fld_semantic_fft_rxbf_qy_Slot_inst_get,
+  Field_fld_semantic_fft_rxbf_qx_Slot_inst_get,
+  Field_fld_semantic_fft_rxbf_qa1_Slot_inst_get,
+  Field_fld_semantic_fft_rxbf_qa0_Slot_inst_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_fld_ee_bitrev_ax_Slot_inst_get,
+  Field_fld_ee_bitrev_qa_Slot_inst_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_fld_ee_fft_vst_r32_decp_sar2_Slot_inst_get,
+  Field_fld_ee_fft_vst_r32_decp_as_Slot_inst_get,
+  Field_fld_ee_fft_vst_r32_decp_qv_Slot_inst_get,
+  Implicit_Field_ar0_get,
+  Implicit_Field_ar4_get,
+  Implicit_Field_ar8_get,
+  Implicit_Field_ar12_get,
+  Implicit_Field_mr0_get,
+  Implicit_Field_mr1_get,
+  Implicit_Field_mr2_get,
+  Implicit_Field_mr3_get,
+  Implicit_Field_bt16_get,
+  Implicit_Field_bs16_get,
+  Implicit_Field_br16_get,
+  Implicit_Field_brall_get
+};
+
+static xtensa_set_field_fn
+Slot_inst_set_field_fns[] = {
+  Field_t_Slot_inst_set,
+  Field_bbi4_Slot_inst_set,
+  Field_bbi_Slot_inst_set,
+  Field_imm12_Slot_inst_set,
+  Field_imm8_Slot_inst_set,
+  Field_s_Slot_inst_set,
+  Field_imm12b_Slot_inst_set,
+  Field_imm16_Slot_inst_set,
+  Field_m_Slot_inst_set,
+  Field_n_Slot_inst_set,
+  Field_offset_Slot_inst_set,
+  Field_op0_Slot_inst_set,
+  Field_op1_Slot_inst_set,
+  Field_op2_Slot_inst_set,
+  Field_r_Slot_inst_set,
+  Field_sa4_Slot_inst_set,
+  Field_sae4_Slot_inst_set,
+  Field_sae_Slot_inst_set,
+  Field_sal_Slot_inst_set,
+  Field_sargt_Slot_inst_set,
+  Field_sas4_Slot_inst_set,
+  Field_sas_Slot_inst_set,
+  Field_sr_Slot_inst_set,
+  Field_st_Slot_inst_set,
+  Field_thi3_Slot_inst_set,
+  Field_imm4_Slot_inst_set,
+  Field_mn_Slot_inst_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_r3_Slot_inst_set,
+  Field_rbit2_Slot_inst_set,
+  Field_rhi_Slot_inst_set,
+  Field_t3_Slot_inst_set,
+  Field_tbit2_Slot_inst_set,
+  Field_tlo_Slot_inst_set,
+  Field_w_Slot_inst_set,
+  Field_y_Slot_inst_set,
+  Field_x_Slot_inst_set,
+  Field_t2_Slot_inst_set,
+  Field_s2_Slot_inst_set,
+  Field_r2_Slot_inst_set,
+  Field_t4_Slot_inst_set,
+  Field_s4_Slot_inst_set,
+  Field_r4_Slot_inst_set,
+  Field_t8_Slot_inst_set,
+  Field_s8_Slot_inst_set,
+  Field_r8_Slot_inst_set,
+  Field_xt_wbr15_imm_Slot_inst_set,
+  Field_xt_wbr18_imm_Slot_inst_set,
+  0,
+  0,
+  Field_fld_st_qr_b_Slot_inst_set,
+  Field_fld_st_qr_a_Slot_inst_set,
+  Field_fld_ld_qr_b_Slot_inst_set,
+  Field_fld_ld_qr_a_Slot_inst_set,
+  Field_fld_qr_Slot_inst_set,
+  Field_fld_inst_4_0_Slot_inst_set,
+  Field_fld_inst_9_6_Slot_inst_set,
+  Field_fld_mv_qr_b_Slot_inst_set,
+  Field_fld_mv_qr_a_Slot_inst_set,
+  Field_fld_ee_wr_mask_gpio_out_mask_Slot_inst_set,
+  Field_fld_ee_wr_mask_gpio_out_value_Slot_inst_set,
+  Field_fld_ee_set_bit_gpio_out_mask_Slot_inst_set,
+  Field_fld_ee_clr_bit_gpio_out_clear_Slot_inst_set,
+  Field_fld_inst_23_8_Slot_inst_set,
+  Field_fld_ee_get_gpio_in_au_Slot_inst_set,
+  Field_fld_inst_23_22_Slot_inst_set,
+  Field_fld_semantic_ld_st_imm2_Slot_inst_set,
+  Field_fld_inst_14_8_Slot_inst_set,
+  Field_fld_semantic_ld_st_imm1_Slot_inst_set,
+  Field_fld_inst_11_8_Slot_inst_set,
+  Field_fld_semantic_ld_st_qu1_Slot_inst_set,
+  0,
+  Field_fld_semantic_ld_st_as_Slot_inst_set,
+  Field_fld_semantic_ld_st_fu0_Slot_inst_set,
+  Field_fld_semantic_ld_st_fu1_Slot_inst_set,
+  0,
+  0,
+  0,
+  Field_fld_semantic_ld_st_ad_Slot_inst_set,
+  Field_fld_semantic_ld_st_imm8_Slot_inst_set,
+  0,
+  Field_fld_inst_3_0_Slot_inst_set,
+  Field_fld_inst_19_16_Slot_inst_set,
+  Field_fld_inst_23_23_Slot_inst_set,
+  Field_fld_inst_14_12_Slot_inst_set,
+  Field_fld_inst_21_15_Slot_inst_set,
+  Field_fld_semantic_ld_st_imm16_Slot_inst_set,
+  Field_fld_inst_23_12_Slot_inst_set,
+  Field_fld_semantic_ld_st_imm4_Slot_inst_set,
+  0,
+  0,
+  0,
+  Field_fld_semantic_ld_st_qu_Slot_inst_set,
+  0,
+  Field_fld_semantic_ld_st_fv0_Slot_inst_set,
+  Field_fld_semantic_ld_st_fv1_Slot_inst_set,
+  0,
+  0,
+  Field_fld_semantic_ld_st_qv_Slot_inst_set,
+  Field_fld_ee_movi_32_a_sel4_Slot_inst_set,
+  Field_fld_ee_movi_32_a_au_Slot_inst_set,
+  Field_fld_ee_movi_32_a_qs_Slot_inst_set,
+  Field_fld_ee_movi_32_q_sel4_Slot_inst_set,
+  Field_fld_ee_movi_32_q_as_Slot_inst_set,
+  Field_fld_ee_movi_32_q_qu_Slot_inst_set,
+  Field_fld_ee_vzip_16_qs1_Slot_inst_set,
+  Field_fld_ee_vzip_16_qs0_Slot_inst_set,
+  Field_fld_ee_vzip_32_qs1_Slot_inst_set,
+  Field_fld_ee_vzip_32_qs0_Slot_inst_set,
+  Field_fld_ee_vzip_8_qs1_Slot_inst_set,
+  Field_fld_ee_vzip_8_qs0_Slot_inst_set,
+  Field_fld_inst_11_0_Slot_inst_set,
+  Field_fld_ee_vunzip_16_qs1_Slot_inst_set,
+  Field_fld_ee_vunzip_16_qs0_Slot_inst_set,
+  Field_fld_ee_vunzip_32_qs1_Slot_inst_set,
+  Field_fld_ee_vunzip_32_qs0_Slot_inst_set,
+  Field_fld_ee_vunzip_8_qs1_Slot_inst_set,
+  Field_fld_ee_vunzip_8_qs0_Slot_inst_set,
+  Field_fld_inst_23_0_Slot_inst_set,
+  Field_fld_ee_zero_q_qa_Slot_inst_set,
+  Field_fld_inst_14_0_Slot_inst_set,
+  Field_fld_ee_mov_s16_qacc_qs_Slot_inst_set,
+  Field_fld_ee_mov_s8_qacc_qs_Slot_inst_set,
+  Field_fld_ee_mov_u16_qacc_qs_Slot_inst_set,
+  Field_fld_ee_mov_u8_qacc_qs_Slot_inst_set,
+  0,
+  Field_fld_inst_7_0_Slot_inst_set,
+  Field_fld_semantic_cal_double_q_qa_Slot_inst_set,
+  Field_fld_semantic_cal_double_q_as_Slot_inst_set,
+  Field_fld_semantic_cal_double_q_qu_Slot_inst_set,
+  0,
+  0,
+  0,
+  Field_fld_inst_7_6_Slot_inst_set,
+  Field_fld_semantic_cal_double_q_sel4_Slot_inst_set,
+  Field_fld_semantic_cal_double_q_qy_Slot_inst_set,
+  Field_fld_semantic_cal_double_q_qx_Slot_inst_set,
+  Field_fld_semantic_cal_double_q_qz_Slot_inst_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_fld_inst_23_21_Slot_inst_set,
+  Field_fld_semantic_cal_double_q_sel8_Slot_inst_set,
+  0,
+  Field_fld_inst_7_5_Slot_inst_set,
+  Field_fld_semantic_cal_double_q_sel16_Slot_inst_set,
+  Field_fld_inst_14_11_Slot_inst_set,
+  Field_fld_semantic_srcmb_qacc_sel2_Slot_inst_set,
+  Field_fld_semantic_srcmb_qacc_as_Slot_inst_set,
+  Field_fld_semantic_srcmb_qacc_qu_Slot_inst_set,
+  Field_fld_inst_13_12_Slot_inst_set,
+  Field_fld_inst_23_15_Slot_inst_set,
+  Field_fld_ee_srs_accx_sel2_Slot_inst_set,
+  Field_fld_ee_srs_accx_as_Slot_inst_set,
+  Field_fld_ee_srs_accx_au_Slot_inst_set,
+  Field_fld_semantic_cal_double_q_ax_Slot_inst_set,
+  Field_fld_semantic_cal_double_q_qs_Slot_inst_set,
+  Field_fld_inst_13_13_Slot_inst_set,
+  Field_fld_semantic_cal_double_q_ay_Slot_inst_set,
+  Field_fld_inst_9_8_Slot_inst_set,
+  Field_fld_semantic_vlogic_qy_Slot_inst_set,
+  Field_fld_semantic_vlogic_qx_Slot_inst_set,
+  Field_fld_semantic_vlogic_qa_Slot_inst_set,
+  Field_fld_inst_5_5_Slot_inst_set,
+  Field_fld_semantic_shfq_sar16_Slot_inst_set,
+  Field_fld_semantic_shfq_qs0_Slot_inst_set,
+  Field_fld_semantic_shfq_qs1_Slot_inst_set,
+  Field_fld_semantic_shfq_ad_Slot_inst_set,
+  Field_fld_semantic_shfq_as_Slot_inst_set,
+  0,
+  0,
+  0,
+  0,
+  Field_fld_inst_11_7_Slot_inst_set,
+  Field_fld_semantic_shfq_qa_Slot_inst_set,
+  Field_fld_inst_14_7_Slot_inst_set,
+  Field_fld_semantic_shfq_qs_Slot_inst_set,
+  0,
+  0,
+  0,
+  Field_fld_inst_9_9_Slot_inst_set,
+  Field_fld_semantic_fft_rxbf_sel2_Slot_inst_set,
+  Field_fld_semantic_fft_rxbf_qy_Slot_inst_set,
+  Field_fld_semantic_fft_rxbf_qx_Slot_inst_set,
+  Field_fld_semantic_fft_rxbf_qa1_Slot_inst_set,
+  Field_fld_semantic_fft_rxbf_qa0_Slot_inst_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_fld_ee_bitrev_ax_Slot_inst_set,
+  Field_fld_ee_bitrev_qa_Slot_inst_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_fld_ee_fft_vst_r32_decp_sar2_Slot_inst_set,
+  Field_fld_ee_fft_vst_r32_decp_as_Slot_inst_set,
+  Field_fld_ee_fft_vst_r32_decp_qv_Slot_inst_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_inst16a_get_field_fns[] = {
+  Field_t_Slot_inst16a_get,
+  0,
+  0,
+  0,
+  0,
+  Field_s_Slot_inst16a_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_op0_Slot_inst16a_get,
+  0,
+  0,
+  Field_r_Slot_inst16a_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_sr_Slot_inst16a_get,
+  Field_st_Slot_inst16a_get,
+  0,
+  Field_imm4_Slot_inst16a_get,
+  0,
+  Field_i_Slot_inst16a_get,
+  Field_imm6lo_Slot_inst16a_get,
+  Field_imm6hi_Slot_inst16a_get,
+  Field_imm7lo_Slot_inst16a_get,
+  Field_imm7hi_Slot_inst16a_get,
+  Field_z_Slot_inst16a_get,
+  Field_imm6_Slot_inst16a_get,
+  Field_imm7_Slot_inst16a_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_t2_Slot_inst16a_get,
+  Field_s2_Slot_inst16a_get,
+  Field_r2_Slot_inst16a_get,
+  Field_t4_Slot_inst16a_get,
+  Field_s4_Slot_inst16a_get,
+  Field_r4_Slot_inst16a_get,
+  Field_t8_Slot_inst16a_get,
+  Field_s8_Slot_inst16a_get,
+  Field_r8_Slot_inst16a_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Implicit_Field_ar0_get,
+  Implicit_Field_ar4_get,
+  Implicit_Field_ar8_get,
+  Implicit_Field_ar12_get,
+  Implicit_Field_mr0_get,
+  Implicit_Field_mr1_get,
+  Implicit_Field_mr2_get,
+  Implicit_Field_mr3_get,
+  Implicit_Field_bt16_get,
+  Implicit_Field_bs16_get,
+  Implicit_Field_br16_get,
+  Implicit_Field_brall_get
+};
+
+static xtensa_set_field_fn
+Slot_inst16a_set_field_fns[] = {
+  Field_t_Slot_inst16a_set,
+  0,
+  0,
+  0,
+  0,
+  Field_s_Slot_inst16a_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_op0_Slot_inst16a_set,
+  0,
+  0,
+  Field_r_Slot_inst16a_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_sr_Slot_inst16a_set,
+  Field_st_Slot_inst16a_set,
+  0,
+  Field_imm4_Slot_inst16a_set,
+  0,
+  Field_i_Slot_inst16a_set,
+  Field_imm6lo_Slot_inst16a_set,
+  Field_imm6hi_Slot_inst16a_set,
+  Field_imm7lo_Slot_inst16a_set,
+  Field_imm7hi_Slot_inst16a_set,
+  Field_z_Slot_inst16a_set,
+  Field_imm6_Slot_inst16a_set,
+  Field_imm7_Slot_inst16a_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_t2_Slot_inst16a_set,
+  Field_s2_Slot_inst16a_set,
+  Field_r2_Slot_inst16a_set,
+  Field_t4_Slot_inst16a_set,
+  Field_s4_Slot_inst16a_set,
+  Field_r4_Slot_inst16a_set,
+  Field_t8_Slot_inst16a_set,
+  Field_s8_Slot_inst16a_set,
+  Field_r8_Slot_inst16a_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_inst16b_get_field_fns[] = {
+  Field_t_Slot_inst16b_get,
+  0,
+  0,
+  0,
+  0,
+  Field_s_Slot_inst16b_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_op0_Slot_inst16b_get,
+  0,
+  0,
+  Field_r_Slot_inst16b_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_sr_Slot_inst16b_get,
+  Field_st_Slot_inst16b_get,
+  0,
+  Field_imm4_Slot_inst16b_get,
+  0,
+  Field_i_Slot_inst16b_get,
+  Field_imm6lo_Slot_inst16b_get,
+  Field_imm6hi_Slot_inst16b_get,
+  Field_imm7lo_Slot_inst16b_get,
+  Field_imm7hi_Slot_inst16b_get,
+  Field_z_Slot_inst16b_get,
+  Field_imm6_Slot_inst16b_get,
+  Field_imm7_Slot_inst16b_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_t2_Slot_inst16b_get,
+  Field_s2_Slot_inst16b_get,
+  Field_r2_Slot_inst16b_get,
+  Field_t4_Slot_inst16b_get,
+  Field_s4_Slot_inst16b_get,
+  Field_r4_Slot_inst16b_get,
+  Field_t8_Slot_inst16b_get,
+  Field_s8_Slot_inst16b_get,
+  Field_r8_Slot_inst16b_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Implicit_Field_ar0_get,
+  Implicit_Field_ar4_get,
+  Implicit_Field_ar8_get,
+  Implicit_Field_ar12_get,
+  Implicit_Field_mr0_get,
+  Implicit_Field_mr1_get,
+  Implicit_Field_mr2_get,
+  Implicit_Field_mr3_get,
+  Implicit_Field_bt16_get,
+  Implicit_Field_bs16_get,
+  Implicit_Field_br16_get,
+  Implicit_Field_brall_get
+};
+
+static xtensa_set_field_fn
+Slot_inst16b_set_field_fns[] = {
+  Field_t_Slot_inst16b_set,
+  0,
+  0,
+  0,
+  0,
+  Field_s_Slot_inst16b_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_op0_Slot_inst16b_set,
+  0,
+  0,
+  Field_r_Slot_inst16b_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_sr_Slot_inst16b_set,
+  Field_st_Slot_inst16b_set,
+  0,
+  Field_imm4_Slot_inst16b_set,
+  0,
+  Field_i_Slot_inst16b_set,
+  Field_imm6lo_Slot_inst16b_set,
+  Field_imm6hi_Slot_inst16b_set,
+  Field_imm7lo_Slot_inst16b_set,
+  Field_imm7hi_Slot_inst16b_set,
+  Field_z_Slot_inst16b_set,
+  Field_imm6_Slot_inst16b_set,
+  Field_imm7_Slot_inst16b_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_t2_Slot_inst16b_set,
+  Field_s2_Slot_inst16b_set,
+  Field_r2_Slot_inst16b_set,
+  Field_t4_Slot_inst16b_set,
+  Field_s4_Slot_inst16b_set,
+  Field_r4_Slot_inst16b_set,
+  Field_t8_Slot_inst16b_set,
+  Field_s8_Slot_inst16b_set,
+  Field_r8_Slot_inst16b_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set
+};
+
+static xtensa_get_field_fn
+Slot_slot_format_32_0_get_field_fns[] = {
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_fld_slot_format_32_0_3_0_Slot_slot_format_32_0_get,
+  Field_fld_slot_format_32_0_28_4_Slot_slot_format_32_0_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_fld_semantic_ld_st_imm16f_Slot_slot_format_32_0_get,
+  Field_fld_semantic_ld_st_as_Slot_slot_format_32_0_get,
+  Field_fld_semantic_ld_st_fu0_Slot_slot_format_32_0_get,
+  Field_fld_semantic_ld_st_fu1_Slot_slot_format_32_0_get,
+  Field_fld_semantic_ld_st_fu2_Slot_slot_format_32_0_get,
+  Field_fld_semantic_ld_st_fu3_Slot_slot_format_32_0_get,
+  Field_fld_slot_format_32_0_28_24_Slot_slot_format_32_0_get,
+  Field_fld_semantic_ld_st_ad_Slot_slot_format_32_0_get,
+  Field_fld_semantic_ld_st_imm8_Slot_slot_format_32_0_get,
+  Field_fld_slot_format_32_0_7_5_Slot_slot_format_32_0_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_fld_semantic_ld_st_sel8_Slot_slot_format_32_0_get,
+  Field_fld_semantic_ld_st_sel4_Slot_slot_format_32_0_get,
+  Field_fld_semantic_ld_st_qs_Slot_slot_format_32_0_get,
+  Field_fld_semantic_ld_st_qu_Slot_slot_format_32_0_get,
+  Field_fld_slot_format_32_0_28_22_Slot_slot_format_32_0_get,
+  Field_fld_semantic_ld_st_fv0_Slot_slot_format_32_0_get,
+  Field_fld_semantic_ld_st_fv1_Slot_slot_format_32_0_get,
+  Field_fld_semantic_ld_st_fv2_Slot_slot_format_32_0_get,
+  Field_fld_semantic_ld_st_fv3_Slot_slot_format_32_0_get,
+  Field_fld_semantic_ld_st_qv_Slot_slot_format_32_0_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_fld_slot_format_32_0_10_4_Slot_slot_format_32_0_get,
+  0,
+  Field_fld_semantic_cal_double_q_qa_Slot_slot_format_32_0_get,
+  Field_fld_semantic_cal_double_q_as_Slot_slot_format_32_0_get,
+  Field_fld_semantic_cal_double_q_qu_Slot_slot_format_32_0_get,
+  Field_fld_slot_format_32_0_10_6_Slot_slot_format_32_0_get,
+  Field_fld_semantic_cal_double_q_qv_Slot_slot_format_32_0_get,
+  Field_fld_slot_format_32_0_28_20_Slot_slot_format_32_0_get,
+  0,
+  Field_fld_semantic_cal_double_q_sel4_Slot_slot_format_32_0_get,
+  Field_fld_semantic_cal_double_q_qy_Slot_slot_format_32_0_get,
+  Field_fld_semantic_cal_double_q_qx_Slot_slot_format_32_0_get,
+  Field_fld_semantic_cal_double_q_qz_Slot_slot_format_32_0_get,
+  Field_fld_semantic_cal_double_q_qs1_Slot_slot_format_32_0_get,
+  Field_fld_semantic_cal_double_q_qs0_Slot_slot_format_32_0_get,
+  Field_fld_slot_format_32_0_28_25_Slot_slot_format_32_0_get,
+  Field_fld_semantic_cal_double_q_imm16_Slot_slot_format_32_0_get,
+  Field_fld_slot_format_32_0_10_8_Slot_slot_format_32_0_get,
+  Field_fld_slot_format_32_0_19_17_Slot_slot_format_32_0_get,
+  Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_get,
+  Field_fld_semantic_cal_double_q_ad_Slot_slot_format_32_0_get,
+  Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_get,
+  0,
+  Field_fld_semantic_cal_double_q_sel8_Slot_slot_format_32_0_get,
+  Field_fld_slot_format_32_0_10_9_Slot_slot_format_32_0_get,
+  0,
+  Field_fld_semantic_cal_double_q_sel16_Slot_slot_format_32_0_get,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_fld_semantic_shfq_qs0_Slot_slot_format_32_0_get,
+  Field_fld_semantic_shfq_qs1_Slot_slot_format_32_0_get,
+  Field_fld_semantic_shfq_ad_Slot_slot_format_32_0_get,
+  Field_fld_semantic_shfq_as_Slot_slot_format_32_0_get,
+  Field_fld_semantic_shfq_imm16_Slot_slot_format_32_0_get,
+  Field_fld_semantic_shfq_qu_Slot_slot_format_32_0_get,
+  Field_fld_slot_format_32_0_7_6_Slot_slot_format_32_0_get,
+  Field_fld_slot_format_32_0_13_11_Slot_slot_format_32_0_get,
+  0,
+  0,
+  0,
+  0,
+  Field_fld_semantic_fft_rxbf_sar4_Slot_slot_format_32_0_get,
+  Field_fld_semantic_fft_rxbf_as_Slot_slot_format_32_0_get,
+  Field_fld_slot_format_32_0_13_13_Slot_slot_format_32_0_get,
+  0,
+  0,
+  Field_fld_semantic_fft_rxbf_qy_Slot_slot_format_32_0_get,
+  Field_fld_semantic_fft_rxbf_qx_Slot_slot_format_32_0_get,
+  0,
+  Field_fld_semantic_fft_rxbf_qa0_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_cmul_s16_ld_xp_sel8_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_cmul_s16_ld_xp_qy_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_cmul_s16_ld_xp_qx_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_cmul_s16_ld_xp_qz_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_cmul_s16_ld_xp_ad_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_cmul_s16_ld_xp_as_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_cmul_s16_ld_xp_qu_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_cmul_s16_st_xp_sar4_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_cmul_s16_st_xp_upd4_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_cmul_s16_st_xp_sel8_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_cmul_s16_st_xp_ad_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_cmul_s16_st_xp_as_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_cmul_s16_st_xp_qv_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_cmul_s16_st_xp_qy_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_cmul_s16_st_xp_qx_Slot_slot_format_32_0_get,
+  0,
+  0,
+  Field_fld_ee_fft_ams_s16_ld_incp_sel2_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_ld_incp_qm_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_ld_incp_qy_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_ld_incp_qx_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_ld_incp_qz1_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_ld_incp_qz_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_ld_incp_as_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_ld_incp_qu_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_ld_incp_uaup_sel2_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_ld_incp_uaup_qm_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_ld_incp_uaup_qy_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_ld_incp_uaup_qx_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_ld_incp_uaup_qz1_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_ld_incp_uaup_qz_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_ld_incp_uaup_as_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_ld_incp_uaup_qu_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_ld_r32_decp_sel2_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_ld_r32_decp_qm_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_ld_r32_decp_qy_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_ld_r32_decp_qx_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_ld_r32_decp_qz1_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_ld_r32_decp_qz_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_ld_r32_decp_as_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_ld_r32_decp_qu_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_st_incp_sel2_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_st_incp_qm_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_st_incp_qy_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_st_incp_qx_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_st_incp_as_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_st_incp_as0_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_st_incp_qz1_Slot_slot_format_32_0_get,
+  Field_fld_ee_fft_ams_s16_st_incp_qv_Slot_slot_format_32_0_get,
+  0,
+  0,
+  0,
+  Implicit_Field_ar0_get,
+  Implicit_Field_ar4_get,
+  Implicit_Field_ar8_get,
+  Implicit_Field_ar12_get,
+  Implicit_Field_mr0_get,
+  Implicit_Field_mr1_get,
+  Implicit_Field_mr2_get,
+  Implicit_Field_mr3_get,
+  Implicit_Field_bt16_get,
+  Implicit_Field_bs16_get,
+  Implicit_Field_br16_get,
+  Implicit_Field_brall_get
+};
+
+static xtensa_set_field_fn
+Slot_slot_format_32_0_set_field_fns[] = {
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_fld_slot_format_32_0_3_0_Slot_slot_format_32_0_set,
+  Field_fld_slot_format_32_0_28_4_Slot_slot_format_32_0_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_fld_semantic_ld_st_imm16f_Slot_slot_format_32_0_set,
+  Field_fld_semantic_ld_st_as_Slot_slot_format_32_0_set,
+  Field_fld_semantic_ld_st_fu0_Slot_slot_format_32_0_set,
+  Field_fld_semantic_ld_st_fu1_Slot_slot_format_32_0_set,
+  Field_fld_semantic_ld_st_fu2_Slot_slot_format_32_0_set,
+  Field_fld_semantic_ld_st_fu3_Slot_slot_format_32_0_set,
+  Field_fld_slot_format_32_0_28_24_Slot_slot_format_32_0_set,
+  Field_fld_semantic_ld_st_ad_Slot_slot_format_32_0_set,
+  Field_fld_semantic_ld_st_imm8_Slot_slot_format_32_0_set,
+  Field_fld_slot_format_32_0_7_5_Slot_slot_format_32_0_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_fld_semantic_ld_st_sel8_Slot_slot_format_32_0_set,
+  Field_fld_semantic_ld_st_sel4_Slot_slot_format_32_0_set,
+  Field_fld_semantic_ld_st_qs_Slot_slot_format_32_0_set,
+  Field_fld_semantic_ld_st_qu_Slot_slot_format_32_0_set,
+  Field_fld_slot_format_32_0_28_22_Slot_slot_format_32_0_set,
+  Field_fld_semantic_ld_st_fv0_Slot_slot_format_32_0_set,
+  Field_fld_semantic_ld_st_fv1_Slot_slot_format_32_0_set,
+  Field_fld_semantic_ld_st_fv2_Slot_slot_format_32_0_set,
+  Field_fld_semantic_ld_st_fv3_Slot_slot_format_32_0_set,
+  Field_fld_semantic_ld_st_qv_Slot_slot_format_32_0_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_fld_slot_format_32_0_10_4_Slot_slot_format_32_0_set,
+  0,
+  Field_fld_semantic_cal_double_q_qa_Slot_slot_format_32_0_set,
+  Field_fld_semantic_cal_double_q_as_Slot_slot_format_32_0_set,
+  Field_fld_semantic_cal_double_q_qu_Slot_slot_format_32_0_set,
+  Field_fld_slot_format_32_0_10_6_Slot_slot_format_32_0_set,
+  Field_fld_semantic_cal_double_q_qv_Slot_slot_format_32_0_set,
+  Field_fld_slot_format_32_0_28_20_Slot_slot_format_32_0_set,
+  0,
+  Field_fld_semantic_cal_double_q_sel4_Slot_slot_format_32_0_set,
+  Field_fld_semantic_cal_double_q_qy_Slot_slot_format_32_0_set,
+  Field_fld_semantic_cal_double_q_qx_Slot_slot_format_32_0_set,
+  Field_fld_semantic_cal_double_q_qz_Slot_slot_format_32_0_set,
+  Field_fld_semantic_cal_double_q_qs1_Slot_slot_format_32_0_set,
+  Field_fld_semantic_cal_double_q_qs0_Slot_slot_format_32_0_set,
+  Field_fld_slot_format_32_0_28_25_Slot_slot_format_32_0_set,
+  Field_fld_semantic_cal_double_q_imm16_Slot_slot_format_32_0_set,
+  Field_fld_slot_format_32_0_10_8_Slot_slot_format_32_0_set,
+  Field_fld_slot_format_32_0_19_17_Slot_slot_format_32_0_set,
+  Field_fld_slot_format_32_0_28_23_Slot_slot_format_32_0_set,
+  Field_fld_semantic_cal_double_q_ad_Slot_slot_format_32_0_set,
+  Field_fld_slot_format_32_0_7_4_Slot_slot_format_32_0_set,
+  0,
+  Field_fld_semantic_cal_double_q_sel8_Slot_slot_format_32_0_set,
+  Field_fld_slot_format_32_0_10_9_Slot_slot_format_32_0_set,
+  0,
+  Field_fld_semantic_cal_double_q_sel16_Slot_slot_format_32_0_set,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  Field_fld_semantic_shfq_qs0_Slot_slot_format_32_0_set,
+  Field_fld_semantic_shfq_qs1_Slot_slot_format_32_0_set,
+  Field_fld_semantic_shfq_ad_Slot_slot_format_32_0_set,
+  Field_fld_semantic_shfq_as_Slot_slot_format_32_0_set,
+  Field_fld_semantic_shfq_imm16_Slot_slot_format_32_0_set,
+  Field_fld_semantic_shfq_qu_Slot_slot_format_32_0_set,
+  Field_fld_slot_format_32_0_7_6_Slot_slot_format_32_0_set,
+  Field_fld_slot_format_32_0_13_11_Slot_slot_format_32_0_set,
+  0,
+  0,
+  0,
+  0,
+  Field_fld_semantic_fft_rxbf_sar4_Slot_slot_format_32_0_set,
+  Field_fld_semantic_fft_rxbf_as_Slot_slot_format_32_0_set,
+  Field_fld_slot_format_32_0_13_13_Slot_slot_format_32_0_set,
+  0,
+  0,
+  Field_fld_semantic_fft_rxbf_qy_Slot_slot_format_32_0_set,
+  Field_fld_semantic_fft_rxbf_qx_Slot_slot_format_32_0_set,
+  0,
+  Field_fld_semantic_fft_rxbf_qa0_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_cmul_s16_ld_xp_sel8_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_cmul_s16_ld_xp_qy_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_cmul_s16_ld_xp_qx_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_cmul_s16_ld_xp_qz_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_cmul_s16_ld_xp_ad_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_cmul_s16_ld_xp_as_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_cmul_s16_ld_xp_qu_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_cmul_s16_st_xp_sar4_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_cmul_s16_st_xp_upd4_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_cmul_s16_st_xp_sel8_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_cmul_s16_st_xp_ad_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_cmul_s16_st_xp_as_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_cmul_s16_st_xp_qv_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_cmul_s16_st_xp_qy_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_cmul_s16_st_xp_qx_Slot_slot_format_32_0_set,
+  0,
+  0,
+  Field_fld_ee_fft_ams_s16_ld_incp_sel2_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_ld_incp_qm_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_ld_incp_qy_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_ld_incp_qx_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_ld_incp_qz1_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_ld_incp_qz_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_ld_incp_as_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_ld_incp_qu_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_ld_incp_uaup_sel2_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_ld_incp_uaup_qm_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_ld_incp_uaup_qy_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_ld_incp_uaup_qx_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_ld_incp_uaup_qz1_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_ld_incp_uaup_qz_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_ld_incp_uaup_as_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_ld_incp_uaup_qu_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_ld_r32_decp_sel2_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_ld_r32_decp_qm_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_ld_r32_decp_qy_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_ld_r32_decp_qx_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_ld_r32_decp_qz1_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_ld_r32_decp_qz_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_ld_r32_decp_as_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_ld_r32_decp_qu_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_st_incp_sel2_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_st_incp_qm_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_st_incp_qy_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_st_incp_qx_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_st_incp_as_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_st_incp_as0_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_st_incp_qz1_Slot_slot_format_32_0_set,
+  Field_fld_ee_fft_ams_s16_st_incp_qv_Slot_slot_format_32_0_set,
+  0,
+  0,
+  0,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set,
+  Implicit_Field_set
+};
+
+static xtensa_slot_internal slots[] = {
+  { "Inst", "x24", 0,
+    Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
+    Slot_inst_get_field_fns, Slot_inst_set_field_fns,
+    Slot_inst_decode, "nop" },
+  { "Inst16a", "x16a", 0,
+    Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
+    Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
+    Slot_inst16a_decode, "" },
+  { "Inst16b", "x16b", 0,
+    Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
+    Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
+    Slot_inst16b_decode, "nop.n" },
+  { "slot_format_32_0", "format_32", 0,
+    Slot_format_32_Format_slot_format_32_0_0_get, Slot_format_32_Format_slot_format_32_0_0_set,
+    Slot_slot_format_32_0_get_field_fns, Slot_slot_format_32_0_set_field_fns,
+    Slot_slot_format_32_0_decode, "nop" }
+};
+
+\f
+/* Instruction formats.  */
+
+static void
+Format_x24_encode (xtensa_insnbuf insn)
+{
+  insn[0] = 0;
+}
+
+static void
+Format_x16a_encode (xtensa_insnbuf insn)
+{
+  insn[0] = 0x8;
+}
+
+static void
+Format_x16b_encode (xtensa_insnbuf insn)
+{
+  insn[0] = 0xc;
+}
+
+static void
+Format_format_32_encode (xtensa_insnbuf insn)
+{
+  insn[0] = 0xe;
+}
+
+static int Format_x24_slots[] = { 0 };
+
+static int Format_x16a_slots[] = { 1 };
+
+static int Format_x16b_slots[] = { 2 };
+
+static int Format_format_32_slots[] = { 3 };
+
+static xtensa_format_internal formats[] = {
+  { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
+  { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
+  { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots },
+  { "format_32", 4, Format_format_32_encode, 1, Format_format_32_slots }
+};
+
+
+static int
+format_decoder (const xtensa_insnbuf insn)
+{
+  if ((insn[0] & 0x8) == 0)
+    return 0; /* x24 */
+  if ((insn[0] & 0xc) == 0x8)
+    return 1; /* x16a */
+  if ((insn[0] & 0xe) == 0xc)
+    return 2; /* x16b */
+  if ((insn[0] & 0xe) == 0xe)
+    return 3; /* format_32 */
+  return -1;
+}
+
+static int length_table[256] = {
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  4,
+  4,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  4,
+  4,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  4,
+  4,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  4,
+  4,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  4,
+  4,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  4,
+  4,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  4,
+  4,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  4,
+  4,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  4,
+  4,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  4,
+  4,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  4,
+  4,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  4,
+  4,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  4,
+  4,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  4,
+  4,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  4,
+  4,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  4,
+  4
+};
+
+static int
+length_decoder (const unsigned char *insn)
+{
+  int l = insn[0];
+  return length_table[l];
+}
+
+\f
+/* Top-level ISA structure.  */
+
+xtensa_isa_internal xtensa_esp32s3_modules = {
+  0 /* little-endian */,
+  4 /* insn_size */, 0,
+  4, formats, format_decoder, length_decoder,
+  4, slots,
+  263 /* num_fields */,
+  471, operands,
+  630, iclasses,
+  753, opcodes, 0,
+  9, regfiles,
+  NUM_STATES, states, 0,
+  NUM_SYSREGS, sysregs, 0,
+  { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
+  6, interfaces, 0,
+  94, funcUnits, 0
+};
diff --git a/bfd/xtensa-isa.c b/bfd/xtensa-isa.c
index 63efbd49948..9bd975b3337 100644
--- a/bfd/xtensa-isa.c
+++ b/bfd/xtensa-isa.c
@@ -24,6 +24,23 @@
 #include "xtensa-isa.h"
 #include "xtensa-isa-internal.h"
 
+extern xtensa_isa_internal xtensa_default_modules;
+extern xtensa_isa_internal xtensa_esp32_modules;
+extern xtensa_isa_internal xtensa_esp32s2_modules;
+extern xtensa_isa_internal xtensa_esp32s3_modules;
+
+const xtensa_isa_modules_t xtensa_isa_modules[] =
+{
+  { "default", (xtensa_isa) &xtensa_default_modules },
+  { "esp32",   (xtensa_isa) &xtensa_esp32_modules },
+  { "esp32s2", (xtensa_isa) &xtensa_esp32s2_modules },
+  { "esp32s3", (xtensa_isa) &xtensa_esp32s3_modules },
+  { NULL, NULL }
+};
+
+const int xtensa_isa_modules_count =
+  sizeof(xtensa_isa_modules)/sizeof(xtensa_isa_modules[0]);
+
 static xtensa_isa_status xtisa_errno;
 static char xtisa_error_msg[1024];
 
@@ -230,14 +247,18 @@ xtensa_insnbuf_from_chars (xtensa_isa isa,
 \f
 /* ISA information.  */
 
-extern xtensa_isa_internal xtensa_modules;
+xtensa_isa_internal *xtensa_modules = NULL;
 
 xtensa_isa
 xtensa_isa_init (xtensa_isa_status *errno_p, char **error_msg_p)
 {
-  xtensa_isa_internal *isa = &xtensa_modules;
+  xtensa_isa_internal *isa;
   int n, is_user;
 
+  if (xtensa_modules == NULL)
+    xtensa_modules = &xtensa_default_modules;
+
+  isa = xtensa_modules;
   /* Set up the opcode name lookup table.  */
   isa->opname_lookup_table =
     bfd_malloc (isa->num_opcodes * sizeof (xtensa_lookup_entry));
diff --git a/gas/config/tc-xtensa.c b/gas/config/tc-xtensa.c
index 630d147bf63..12730b5315a 100644
--- a/gas/config/tc-xtensa.c
+++ b/gas/config/tc-xtensa.c
@@ -30,6 +30,8 @@
 #include "xtensa-config.h"
 #include "elf/xtensa.h"
 
+#define streq(a, b)	      (strcmp (a, b) == 0)
+
 /* Provide default values for new configuration settings.  */
 #ifndef XTHAL_ABI_WINDOWED
 #define XTHAL_ABI_WINDOWED 0
@@ -590,6 +592,7 @@ static void build_section_rename (const char *);
 
 /* ISA imported from bfd.  */
 extern xtensa_isa xtensa_default_isa;
+extern void *xtensa_modules;
 
 extern int target_big_endian;
 
@@ -758,6 +761,8 @@ enum
 
   option_booleans,
   option_no_booleans,
+
+  option_isa_module,
 };
 
 const char *md_shortopts = "";
@@ -851,6 +856,8 @@ struct option md_longopts[] =
   { "booleans", no_argument, NULL, option_booleans },
   { "no-booleans", no_argument, NULL, option_no_booleans },
 
+  { "isa-module", required_argument, NULL, option_isa_module },
+
   { NULL, no_argument, NULL, 0 }
 };
 
@@ -860,6 +867,7 @@ size_t md_longopts_size = sizeof md_longopts;
 int
 md_parse_option (int c, const char *arg)
 {
+  const xtensa_isa_modules_t *module;
   switch (c)
     {
     case option_density:
@@ -1111,6 +1119,16 @@ md_parse_option (int c, const char *arg)
       target_have_booleans = 0;
       return 1;
 
+    case option_isa_module:
+      for (module = &xtensa_isa_modules[0]; module->name != NULL; module++)
+	  {
+	    if (streq (arg, module->name))
+	    {
+          xtensa_modules = module->isa_module;
+          return 1;
+        }
+      }
+
     default:
       return 0;
     }
@@ -1149,7 +1167,8 @@ Xtensa options:\n\
   --EB                    Generate code for a big endian machine.\n\
   --EL                    Generate code for a little endian machine.\n\
   --[no-]booleans         [Do not] use boolean registers.\n\
-  --[no-]loops            [Do not] zero-overhead loops.\n", stream);
+  --[no-]loops            [Do not] zero-overhead loops.\n\
+  --isa-module=<value>    Use chip specific ISA (default|esp32|esp32s2|esp32s3).\n", stream);
 }
 
 \f
diff --git a/include/elf/xtensa.h b/include/elf/xtensa.h
index 6d916f8fd64..bef3cd90705 100644
--- a/include/elf/xtensa.h
+++ b/include/elf/xtensa.h
@@ -148,6 +148,7 @@ typedef struct xtensa_info_entries_t
 {
   int abi;
   int use_absolute_literals;
+  int isa_module;
 } xtensa_info_entries;
 
 /* Flags in the property tables to specify whether blocks of memory are
@@ -240,6 +241,9 @@ xtensa_compute_fill_extra_space (property_table_entry *entry);
 extern int
 xtensa_abi_choice (void);
 
+extern int
+xtensa_isa_module_choice (void);
+
 extern void
 fill_xtensa_info (char **data);
 
diff --git a/include/xtensa-isa.h b/include/xtensa-isa.h
index c9ec9db8244..eefd2502c52 100644
--- a/include/xtensa-isa.h
+++ b/include/xtensa-isa.h
@@ -806,6 +806,14 @@ xtensa_funcUnit_name (xtensa_isa isa, xtensa_funcUnit fun);
 extern int
 xtensa_funcUnit_num_copies (xtensa_isa isa, xtensa_funcUnit fun);
 
+typedef struct xtensa_isa_modules
+{
+  const char *name;
+  xtensa_isa isa_module;
+} xtensa_isa_modules_t;
+
+extern const xtensa_isa_modules_t xtensa_isa_modules[];
+extern const int xtensa_isa_modules_count;
 
 #ifdef __cplusplus
 }
diff --git a/ld/emultempl/xtensaelf.em b/ld/emultempl/xtensaelf.em
index f06bcb97daa..eaa731d0e27 100644
--- a/ld/emultempl/xtensaelf.em
+++ b/ld/emultempl/xtensaelf.em
@@ -24,6 +24,7 @@
 #
 fragment <<EOF
 
+#include <xtensa-isa.h>
 #include <xtensa-config.h>
 #include "../bfd/elf-bfd.h"
 #include "elf/xtensa.h"
@@ -57,6 +58,8 @@ static bool xtensa_use_literal_pages = false;
 
 #define EXTRA_VALIDATION 0
 
+extern xtensa_isa xtensa_modules;
+
 /* Xtensa ABI.
    This option is defined in BDF library.  */
 extern int elf32xtensa_abi;
@@ -332,6 +335,33 @@ check_xtensa_info (bfd *abfd, xtensa_info_entries *entries)
       einfo (_("%P: %pB: warning: Xtensa incompatible use of the Extended L32R option (%d != %d)\n"),
              abfd, entries->use_absolute_literals, XSHAL_USE_ABSOLUTE_LITERALS);
     }
+
+  /* Check ISA_MODULE */
+  if (entries->isa_module >= xtensa_isa_modules_count)
+    {
+      einfo (_("%P: %pB: warning: unknown Xtensa isa module\n"),
+             abfd);
+    }
+  if (entries->isa_module < 0)
+    {
+      /* Do not check module if not present in .xtensa.info.
+         It provides backward compatibility.  */
+    }
+  else if (xtensa_modules == NULL)
+    {
+      xtensa_modules = xtensa_isa_modules[entries->isa_module].isa_module;
+    }
+  else if (entries->isa_module != xtensa_isa_module_choice ())
+    {
+      einfo (_("%P: %pB: warning: Xtensa incompatible use of different isa modules\n"),
+             abfd);
+    }
+
+  if (xtensa_modules == NULL)
+    {
+      einfo (_("%P: %pB: warning: Xtensa isa-module info not found. Using the default Xtensa module\n"),
+             abfd);
+    }
 }
 
 
-- 
2.34.1


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH 5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules
  2022-10-22 12:51 [PATCH 0/5] Add Xtensa ESP chips support Alexey Lapshin
                   ` (3 preceding siblings ...)
  2022-10-22 13:54 ` [PATCH 4/5] gas: xtensa: add esp32, esp32s2, esp32s3 isa-modules options Alexey Lapshin
@ 2022-10-22 13:56 ` Alexey Lapshin
  2022-10-25 19:13 ` [PATCH 0/5] Add Xtensa ESP chips support Max Filippov
  5 siblings, 0 replies; 14+ messages in thread
From: Alexey Lapshin @ 2022-10-22 13:56 UTC (permalink / raw)
  To: binutils; +Cc: Alexey Gerenkov, Ivan Grokhotkov, Anton Maklakov

Added Xtensa ESP chips support for gdb.
A chip isa-module gets from .xtensa.info section.

---
 gdb/Makefile.in                               |  10 +-
 gdb/configure.tgt                             |   2 +-
 ...tensa-config.c => xtensa-config-default.c} |  66 +--
 gdb/xtensa-config-esp32.c                     | 389 ++++++++++++++
 gdb/xtensa-config-esp32s2.c                   | 271 ++++++++++
 gdb/xtensa-config-esp32s3.c                   | 496 ++++++++++++++++++
 gdb/xtensa-tdep.c                             |  70 ++-
 gdb/xtensa-tdep.h                             |   2 +-
 8 files changed, 1263 insertions(+), 43 deletions(-)
 rename gdb/{xtensa-config.c => xtensa-config-default.c} (84%)
 create mode 100644 gdb/xtensa-config-esp32.c
 create mode 100644 gdb/xtensa-config-esp32s2.c
 create mode 100644 gdb/xtensa-config-esp32s3.c

diff --git a/gdb/Makefile.in b/gdb/Makefile.in
index 911daa2607b..6a60b53ae5a 100644
--- a/gdb/Makefile.in
+++ b/gdb/Makefile.in
@@ -867,7 +867,10 @@ ALL_TARGET_OBS = \
 	x86-tdep.o \
 	xcoffread.o \
 	xstormy16-tdep.o \
-	xtensa-config.o \
+	xtensa-config-default.o \
+	xtensa-config-esp32.o \
+	xtensa-config-esp32s2.o \
+	xtensa-config-esp32s3.o \
 	xtensa-linux-tdep.o \
 	xtensa-tdep.o \
 	z80-tdep.o
@@ -1822,7 +1825,10 @@ ALLDEPFILES = \
 	x86-tdep.c \
 	xcoffread.c \
 	xstormy16-tdep.c \
-	xtensa-config.c \
+	xtensa-config-default.c \
+	xtensa-config-esp32.c \
+	xtensa-config-esp32s2.c \
+	xtensa-config-esp32s3.c \
 	xtensa-linux-nat.c \
 	xtensa-linux-tdep.c \
 	xtensa-tdep.c \
diff --git a/gdb/configure.tgt b/gdb/configure.tgt
index 0705ccf32b8..2e547f586f8 100644
--- a/gdb/configure.tgt
+++ b/gdb/configure.tgt
@@ -105,7 +105,7 @@ x86_64-*-*)
 
 xtensa*)
 	# Target: Tensilica Xtensa processors
-	cpu_obs="xtensa-tdep.o xtensa-config.o solib-svr4.o"
+	cpu_obs="xtensa-tdep.o xtensa-config-default.o xtensa-config-
esp32.o xtensa-config-esp32s2.o xtensa-config-esp32s3.o solib-svr4.o"
 	;;
 
 esac
diff --git a/gdb/xtensa-config.c b/gdb/xtensa-config-default.c
similarity index 84%
rename from gdb/xtensa-config.c
rename to gdb/xtensa-config-default.c
index a28ffd58c96..e654325c460 100644
--- a/gdb/xtensa-config.c
+++ b/gdb/xtensa-config-default.c
@@ -27,38 +27,38 @@
 
 
 /* Masked registers.  */
-xtensa_reg_mask_t xtensa_submask0[] = { { 42, 0, 4 } };
-const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 };
-xtensa_reg_mask_t xtensa_submask1[] = { { 42, 5, 1 } };
-const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 };
-xtensa_reg_mask_t xtensa_submask2[] = { { 42, 18, 1 } };
-const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 };
-xtensa_reg_mask_t xtensa_submask3[] = { { 42, 6, 2 } };
-const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 };
-xtensa_reg_mask_t xtensa_submask4[] = { { 42, 4, 1 } };
-const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 };
-xtensa_reg_mask_t xtensa_submask5[] = { { 42, 16, 2 } };
-const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 };
-xtensa_reg_mask_t xtensa_submask6[] = { { 42, 8, 4 } };
-const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 };
-xtensa_reg_mask_t xtensa_submask7[] = { { 37, 12, 20 } };
-const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 };
-xtensa_reg_mask_t xtensa_submask8[] = { { 37, 0, 1 } };
-const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 };
-xtensa_reg_mask_t xtensa_submask9[] = { { 86, 8, 4 } };
-const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 };
-xtensa_reg_mask_t xtensa_submask10[] = { { 47, 24, 8 } };
-const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 };
-xtensa_reg_mask_t xtensa_submask11[] = { { 47, 16, 8 } };
-const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 };
-xtensa_reg_mask_t xtensa_submask12[] = { { 47, 8, 8 } };
-const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 };
-xtensa_reg_mask_t xtensa_submask13[] = { { 48, 16, 2 } };
-const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 };
-xtensa_reg_mask_t xtensa_submask14[] = { { 49, 16, 2 } };
-const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 };
-xtensa_reg_mask_t xtensa_submask15[] = { { 45, 22, 10 } };
-const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 };
+static xtensa_reg_mask_t xtensa_submask0[] = { { 42, 0, 4 } };
+static const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 };
+static xtensa_reg_mask_t xtensa_submask1[] = { { 42, 5, 1 } };
+static const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 };
+static xtensa_reg_mask_t xtensa_submask2[] = { { 42, 18, 1 } };
+static const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 };
+static xtensa_reg_mask_t xtensa_submask3[] = { { 42, 6, 2 } };
+static const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 };
+static xtensa_reg_mask_t xtensa_submask4[] = { { 42, 4, 1 } };
+static const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 };
+static xtensa_reg_mask_t xtensa_submask5[] = { { 42, 16, 2 } };
+static const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 };
+static xtensa_reg_mask_t xtensa_submask6[] = { { 42, 8, 4 } };
+static const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 };
+static xtensa_reg_mask_t xtensa_submask7[] = { { 37, 12, 20 } };
+static const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 };
+static xtensa_reg_mask_t xtensa_submask8[] = { { 37, 0, 1 } };
+static const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 };
+static xtensa_reg_mask_t xtensa_submask9[] = { { 86, 8, 4 } };
+static const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 };
+static xtensa_reg_mask_t xtensa_submask10[] = { { 47, 24, 8 } };
+static const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 };
+static xtensa_reg_mask_t xtensa_submask11[] = { { 47, 16, 8 } };
+static const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 };
+static xtensa_reg_mask_t xtensa_submask12[] = { { 47, 8, 8 } };
+static const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 };
+static xtensa_reg_mask_t xtensa_submask13[] = { { 48, 16, 2 } };
+static const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 };
+static xtensa_reg_mask_t xtensa_submask14[] = { { 49, 16, 2 } };
+static const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 };
+static xtensa_reg_mask_t xtensa_submask15[] = { { 45, 22, 10 } };
+static const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 };
 
 
 /* Register map.  */
@@ -213,4 +213,4 @@ static xtensa_register_t rmap[] =
   XTREG_END
 };
 
-xtensa_gdbarch_tdep xtensa_tdep (rmap);
+xtensa_gdbarch_tdep xtensa_tdep_default (rmap);
diff --git a/gdb/xtensa-config-esp32.c b/gdb/xtensa-config-esp32.c
new file mode 100644
index 00000000000..923bee640d3
--- /dev/null
+++ b/gdb/xtensa-config-esp32.c
@@ -0,0 +1,389 @@
+/* Configuration for the Xtensa architecture for GDB, the GNU
debugger.
+
+   Copyright (c) 2003-2016 Tensilica Inc.
+
+   Permission is hereby granted, free of charge, to any person
obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject
to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be
included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR
ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+#define XTENSA_CONFIG_VERSION 0x60
+
+#include "defs.h"
+#include "xtensa-config.h"
+#include "xtensa-tdep.h"
+
+
+
+/* Masked registers.  */
+static xtensa_reg_mask_t xtensa_submask0[] = { { 75, 0, 1 } };
+static const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 };
+static xtensa_reg_mask_t xtensa_submask1[] = { { 75, 1, 1 } };
+static const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 };
+static xtensa_reg_mask_t xtensa_submask2[] = { { 75, 2, 1 } };
+static const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 };
+static xtensa_reg_mask_t xtensa_submask3[] = { { 75, 3, 1 } };
+static const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 };
+static xtensa_reg_mask_t xtensa_submask4[] = { { 75, 4, 1 } };
+static const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 };
+static xtensa_reg_mask_t xtensa_submask5[] = { { 75, 5, 1 } };
+static const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 };
+static xtensa_reg_mask_t xtensa_submask6[] = { { 75, 6, 1 } };
+static const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 };
+static xtensa_reg_mask_t xtensa_submask7[] = { { 75, 7, 1 } };
+static const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 };
+static xtensa_reg_mask_t xtensa_submask8[] = { { 75, 8, 1 } };
+static const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 };
+static xtensa_reg_mask_t xtensa_submask9[] = { { 75, 9, 1 } };
+static const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 };
+static xtensa_reg_mask_t xtensa_submask10[] = { { 75, 10, 1 } };
+static const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 };
+static xtensa_reg_mask_t xtensa_submask11[] = { { 75, 11, 1 } };
+static const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 };
+static xtensa_reg_mask_t xtensa_submask12[] = { { 75, 12, 1 } };
+static const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 };
+static xtensa_reg_mask_t xtensa_submask13[] = { { 75, 13, 1 } };
+static const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 };
+static xtensa_reg_mask_t xtensa_submask14[] = { { 75, 14, 1 } };
+static const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 };
+static xtensa_reg_mask_t xtensa_submask15[] = { { 75, 15, 1 } };
+static const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 };
+static xtensa_reg_mask_t xtensa_submask16[] = { { 73, 0, 4 } };
+static const xtensa_mask_t xtensa_mask16 = { 1, xtensa_submask16 };
+static xtensa_reg_mask_t xtensa_submask17[] = { { 73, 5, 1 } };
+static const xtensa_mask_t xtensa_mask17 = { 1, xtensa_submask17 };
+static xtensa_reg_mask_t xtensa_submask18[] = { { 73, 18, 1 } };
+static const xtensa_mask_t xtensa_mask18 = { 1, xtensa_submask18 };
+static xtensa_reg_mask_t xtensa_submask19[] = { { 73, 4, 1 } };
+static const xtensa_mask_t xtensa_mask19 = { 1, xtensa_submask19 };
+static xtensa_reg_mask_t xtensa_submask20[] = { { 73, 16, 2 } };
+static const xtensa_mask_t xtensa_mask20 = { 1, xtensa_submask20 };
+static xtensa_reg_mask_t xtensa_submask21[] = { { 73, 8, 4 } };
+static const xtensa_mask_t xtensa_mask21 = { 1, xtensa_submask21 };
+static xtensa_reg_mask_t xtensa_submask22[] = { { 77, 0, 32 }, { 78,
0, 8 } };
+static const xtensa_mask_t xtensa_mask22 = { 2, xtensa_submask22 };
+static xtensa_reg_mask_t xtensa_submask23[] = { { 144, 8, 4 } };
+static const xtensa_mask_t xtensa_mask23 = { 1, xtensa_submask23 };
+static xtensa_reg_mask_t xtensa_submask24[] = { { 84, 0, 32 }, { 85,
0, 32 } };
+static const xtensa_mask_t xtensa_mask24 = { 2, xtensa_submask24 };
+static xtensa_reg_mask_t xtensa_submask25[] = { { 103, 0, 2 } };
+static const xtensa_mask_t xtensa_mask25 = { 1, xtensa_submask25 };
+static xtensa_reg_mask_t xtensa_submask26[] = { { 103, 6, 1 } };
+static const xtensa_mask_t xtensa_mask26 = { 1, xtensa_submask26 };
+static xtensa_reg_mask_t xtensa_submask27[] = { { 103, 5, 1 } };
+static const xtensa_mask_t xtensa_mask27 = { 1, xtensa_submask27 };
+static xtensa_reg_mask_t xtensa_submask28[] = { { 103, 4, 1 } };
+static const xtensa_mask_t xtensa_mask28 = { 1, xtensa_submask28 };
+static xtensa_reg_mask_t xtensa_submask29[] = { { 103, 3, 1 } };
+static const xtensa_mask_t xtensa_mask29 = { 1, xtensa_submask29 };
+static xtensa_reg_mask_t xtensa_submask30[] = { { 103, 2, 1 } };
+static const xtensa_mask_t xtensa_mask30 = { 1, xtensa_submask30 };
+static xtensa_reg_mask_t xtensa_submask31[] = { { 104, 11, 1 } };
+static const xtensa_mask_t xtensa_mask31 = { 1, xtensa_submask31 };
+static xtensa_reg_mask_t xtensa_submask32[] = { { 104, 10, 1 } };
+static const xtensa_mask_t xtensa_mask32 = { 1, xtensa_submask32 };
+static xtensa_reg_mask_t xtensa_submask33[] = { { 104, 9, 1 } };
+static const xtensa_mask_t xtensa_mask33 = { 1, xtensa_submask33 };
+static xtensa_reg_mask_t xtensa_submask34[] = { { 104, 8, 1 } };
+static const xtensa_mask_t xtensa_mask34 = { 1, xtensa_submask34 };
+static xtensa_reg_mask_t xtensa_submask35[] = { { 104, 7, 1 } };
+static const xtensa_mask_t xtensa_mask35 = { 1, xtensa_submask35 };
+static xtensa_reg_mask_t xtensa_submask36[] = { { 103, 12, 20 } };
+static const xtensa_mask_t xtensa_mask36 = { 1, xtensa_submask36 };
+static xtensa_reg_mask_t xtensa_submask37[] = { { 104, 12, 20 } };
+static const xtensa_mask_t xtensa_mask37 = { 1, xtensa_submask37 };
+static xtensa_reg_mask_t xtensa_submask38[] = { { 103, 7, 5 } };
+static const xtensa_mask_t xtensa_mask38 = { 1, xtensa_submask38 };
+static xtensa_reg_mask_t xtensa_submask39[] = { { 104, 0, 7 } };
+static const xtensa_mask_t xtensa_mask39 = { 1, xtensa_submask39 };
+
+
+/* Register map.  */
+static xtensa_register_t rmap[] = 
+{
+  /*    idx ofs bi sz al targno  flags cp typ group name  */
+  XTREG(  0,  0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc,         
0,0,0,0,0,0)
+  XTREG(  1,  4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0,        
0,0,0,0,0,0)
+  XTREG(  2,  8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1,        
0,0,0,0,0,0)
+  XTREG(  3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2,        
0,0,0,0,0,0)
+  XTREG(  4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3,        
0,0,0,0,0,0)
+  XTREG(  5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4,        
0,0,0,0,0,0)
+  XTREG(  6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5,        
0,0,0,0,0,0)
+  XTREG(  7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6,        
0,0,0,0,0,0)
+  XTREG(  8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7,        
0,0,0,0,0,0)
+  XTREG(  9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8,        
0,0,0,0,0,0)
+  XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9,        
0,0,0,0,0,0)
+  XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10,       
0,0,0,0,0,0)
+  XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11,       
0,0,0,0,0,0)
+  XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12,       
0,0,0,0,0,0)
+  XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13,       
0,0,0,0,0,0)
+  XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14,       
0,0,0,0,0,0)
+  XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15,       
0,0,0,0,0,0)
+  XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16,       
0,0,0,0,0,0)
+  XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17,       
0,0,0,0,0,0)
+  XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18,       
0,0,0,0,0,0)
+  XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19,       
0,0,0,0,0,0)
+  XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20,       
0,0,0,0,0,0)
+  XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21,       
0,0,0,0,0,0)
+  XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22,       
0,0,0,0,0,0)
+  XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23,       
0,0,0,0,0,0)
+  XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24,       
0,0,0,0,0,0)
+  XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25,       
0,0,0,0,0,0)
+  XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26,       
0,0,0,0,0,0)
+  XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27,       
0,0,0,0,0,0)
+  XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28,       
0,0,0,0,0,0)
+  XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29,       
0,0,0,0,0,0)
+  XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30,       
0,0,0,0,0,0)
+  XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31,       
0,0,0,0,0,0)
+  XTREG( 33,132,32, 4, 4,0x0120,0x0006,-2, 1,0x0002,ar32,       
0,0,0,0,0,0)
+  XTREG( 34,136,32, 4, 4,0x0121,0x0006,-2, 1,0x0002,ar33,       
0,0,0,0,0,0)
+  XTREG( 35,140,32, 4, 4,0x0122,0x0006,-2, 1,0x0002,ar34,       
0,0,0,0,0,0)
+  XTREG( 36,144,32, 4, 4,0x0123,0x0006,-2, 1,0x0002,ar35,       
0,0,0,0,0,0)
+  XTREG( 37,148,32, 4, 4,0x0124,0x0006,-2, 1,0x0002,ar36,       
0,0,0,0,0,0)
+  XTREG( 38,152,32, 4, 4,0x0125,0x0006,-2, 1,0x0002,ar37,       
0,0,0,0,0,0)
+  XTREG( 39,156,32, 4, 4,0x0126,0x0006,-2, 1,0x0002,ar38,       
0,0,0,0,0,0)
+  XTREG( 40,160,32, 4, 4,0x0127,0x0006,-2, 1,0x0002,ar39,       
0,0,0,0,0,0)
+  XTREG( 41,164,32, 4, 4,0x0128,0x0006,-2, 1,0x0002,ar40,       
0,0,0,0,0,0)
+  XTREG( 42,168,32, 4, 4,0x0129,0x0006,-2, 1,0x0002,ar41,       
0,0,0,0,0,0)
+  XTREG( 43,172,32, 4, 4,0x012a,0x0006,-2, 1,0x0002,ar42,       
0,0,0,0,0,0)
+  XTREG( 44,176,32, 4, 4,0x012b,0x0006,-2, 1,0x0002,ar43,       
0,0,0,0,0,0)
+  XTREG( 45,180,32, 4, 4,0x012c,0x0006,-2, 1,0x0002,ar44,       
0,0,0,0,0,0)
+  XTREG( 46,184,32, 4, 4,0x012d,0x0006,-2, 1,0x0002,ar45,       
0,0,0,0,0,0)
+  XTREG( 47,188,32, 4, 4,0x012e,0x0006,-2, 1,0x0002,ar46,       
0,0,0,0,0,0)
+  XTREG( 48,192,32, 4, 4,0x012f,0x0006,-2, 1,0x0002,ar47,       
0,0,0,0,0,0)
+  XTREG( 49,196,32, 4, 4,0x0130,0x0006,-2, 1,0x0002,ar48,       
0,0,0,0,0,0)
+  XTREG( 50,200,32, 4, 4,0x0131,0x0006,-2, 1,0x0002,ar49,       
0,0,0,0,0,0)
+  XTREG( 51,204,32, 4, 4,0x0132,0x0006,-2, 1,0x0002,ar50,       
0,0,0,0,0,0)
+  XTREG( 52,208,32, 4, 4,0x0133,0x0006,-2, 1,0x0002,ar51,       
0,0,0,0,0,0)
+  XTREG( 53,212,32, 4, 4,0x0134,0x0006,-2, 1,0x0002,ar52,       
0,0,0,0,0,0)
+  XTREG( 54,216,32, 4, 4,0x0135,0x0006,-2, 1,0x0002,ar53,       
0,0,0,0,0,0)
+  XTREG( 55,220,32, 4, 4,0x0136,0x0006,-2, 1,0x0002,ar54,       
0,0,0,0,0,0)
+  XTREG( 56,224,32, 4, 4,0x0137,0x0006,-2, 1,0x0002,ar55,       
0,0,0,0,0,0)
+  XTREG( 57,228,32, 4, 4,0x0138,0x0006,-2, 1,0x0002,ar56,       
0,0,0,0,0,0)
+  XTREG( 58,232,32, 4, 4,0x0139,0x0006,-2, 1,0x0002,ar57,       
0,0,0,0,0,0)
+  XTREG( 59,236,32, 4, 4,0x013a,0x0006,-2, 1,0x0002,ar58,       
0,0,0,0,0,0)
+  XTREG( 60,240,32, 4, 4,0x013b,0x0006,-2, 1,0x0002,ar59,       
0,0,0,0,0,0)
+  XTREG( 61,244,32, 4, 4,0x013c,0x0006,-2, 1,0x0002,ar60,       
0,0,0,0,0,0)
+  XTREG( 62,248,32, 4, 4,0x013d,0x0006,-2, 1,0x0002,ar61,       
0,0,0,0,0,0)
+  XTREG( 63,252,32, 4, 4,0x013e,0x0006,-2, 1,0x0002,ar62,       
0,0,0,0,0,0)
+  XTREG( 64,256,32, 4, 4,0x013f,0x0006,-2, 1,0x0002,ar63,       
0,0,0,0,0,0)
+  XTREG( 65,260,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg,       
0,0,0,0,0,0)
+  XTREG( 66,264,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend,       
0,0,0,0,0,0)
+  XTREG( 67,268,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount,     
0,0,0,0,0,0)
+  XTREG( 68,272, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar,        
0,0,0,0,0,0)
+  XTREG( 69,276, 4, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 
0,0,0,0,0,0)
+  XTREG( 70,280,16, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart,
0,0,0,0,0,0)
+  XTREG( 71,284,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0,  
0,0,0,0,0,0)
+  XTREG( 72,288,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1,  
0,0,0,0,0,0)
+  XTREG( 73,292,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps,         
0,0,0,0,0,0)
+  XTREG( 74,296,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr,  
0,0,0,0,0,0)
+  XTREG( 75,300,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br,         
0,0,0,0,0,0)
+  XTREG( 76,304,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1,  
0,0,0,0,0,0)
+  XTREG( 77,308,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo,      
0,0,0,0,0,0)
+  XTREG( 78,312, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi,      
0,0,0,0,0,0)
+  XTREG( 79,316,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0,         
0,0,0,0,0,0)
+  XTREG( 80,320,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1,         
0,0,0,0,0,0)
+  XTREG( 81,324,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2,         
0,0,0,0,0,0)
+  XTREG( 82,328,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3,         
0,0,0,0,0,0)
+  XTREG( 83,332,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate,   
0,0,0,0,0,0)
+  XTREG( 84,336,32, 4, 4,0x03ea,0x0006,-1, 3,0x0100,f64r_lo,    
0,0,0,0,0,0)
+  XTREG( 85,340,32, 4, 4,0x03eb,0x0006,-1, 3,0x0100,f64r_hi,    
0,0,0,0,0,0)
+  XTREG( 86,344,32, 4, 4,0x03ec,0x0006,-1, 3,0x0110,f64s,       
0,0,0,0,0,0)
+  XTREG( 87,348,32, 4, 4,0x0030,0x0006, 0, 4,0x0401,f0,
+            "03:03:44:00","03:03:04:00",0,0,0,0)
+  XTREG( 88,352,32, 4, 4,0x0031,0x0006, 0, 4,0x0401,f1,
+            "03:13:44:00","03:13:04:00",0,0,0,0)
+  XTREG( 89,356,32, 4, 4,0x0032,0x0006, 0, 4,0x0401,f2,
+            "03:23:44:00","03:23:04:00",0,0,0,0)
+  XTREG( 90,360,32, 4, 4,0x0033,0x0006, 0, 4,0x0401,f3,
+            "03:33:44:00","03:33:04:00",0,0,0,0)
+  XTREG( 91,364,32, 4, 4,0x0034,0x0006, 0, 4,0x0401,f4,
+            "03:43:44:00","03:43:04:00",0,0,0,0)
+  XTREG( 92,368,32, 4, 4,0x0035,0x0006, 0, 4,0x0401,f5,
+            "03:53:44:00","03:53:04:00",0,0,0,0)
+  XTREG( 93,372,32, 4, 4,0x0036,0x0006, 0, 4,0x0401,f6,
+            "03:63:44:00","03:63:04:00",0,0,0,0)
+  XTREG( 94,376,32, 4, 4,0x0037,0x0006, 0, 4,0x0401,f7,
+            "03:73:44:00","03:73:04:00",0,0,0,0)
+  XTREG( 95,380,32, 4, 4,0x0038,0x0006, 0, 4,0x0401,f8,
+            "03:83:44:00","03:83:04:00",0,0,0,0)
+  XTREG( 96,384,32, 4, 4,0x0039,0x0006, 0, 4,0x0401,f9,
+            "03:93:44:00","03:93:04:00",0,0,0,0)
+  XTREG( 97,388,32, 4, 4,0x003a,0x0006, 0, 4,0x0401,f10,
+            "03:a3:44:00","03:a3:04:00",0,0,0,0)
+  XTREG( 98,392,32, 4, 4,0x003b,0x0006, 0, 4,0x0401,f11,
+            "03:b3:44:00","03:b3:04:00",0,0,0,0)
+  XTREG( 99,396,32, 4, 4,0x003c,0x0006, 0, 4,0x0401,f12,
+            "03:c3:44:00","03:c3:04:00",0,0,0,0)
+  XTREG(100,400,32, 4, 4,0x003d,0x0006, 0, 4,0x0401,f13,
+            "03:d3:44:00","03:d3:04:00",0,0,0,0)
+  XTREG(101,404,32, 4, 4,0x003e,0x0006, 0, 4,0x0401,f14,
+            "03:e3:44:00","03:e3:04:00",0,0,0,0)
+  XTREG(102,408,32, 4, 4,0x003f,0x0006, 0, 4,0x0401,f15,
+            "03:f3:44:00","03:f3:04:00",0,0,0,0)
+  XTREG(103,412,32, 4, 4,0x03e8,0x0006, 0, 3,0x0100,fcr,        
0,0,0,0,0,0)
+  XTREG(104,416,32, 4, 4,0x03e9,0x0006, 0, 3,0x0100,fsr,        
0,0,0,0,0,0)
+  XTREG(105,420,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid,       
0,0,0,0,0,0)
+  XTREG(106,424, 2, 4, 4,0x0260,0x0007,-2,
2,0x1000,ibreakenable,0,0,0,0,0,0)
+  XTREG(107,428, 1, 4, 4,0x0261,0x0007,-2, 2,0x1000,memctl,     
0,0,0,0,0,0)
+  XTREG(108,432, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl,    
0,0,0,0,0,0)
+  XTREG(109,436,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr,        
0,0,0,0,0,0)
+  XTREG(110,440,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0,   
0,0,0,0,0,0)
+  XTREG(111,444,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1,   
0,0,0,0,0,0)
+  XTREG(112,448,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0,   
0,0,0,0,0,0)
+  XTREG(113,452,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1,   
0,0,0,0,0,0)
+  XTREG(114,456,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0,   
0,0,0,0,0,0)
+  XTREG(115,460,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1,   
0,0,0,0,0,0)
+  XTREG(116,464,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1,       
0,0,0,0,0,0)
+  XTREG(117,468,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2,       
0,0,0,0,0,0)
+  XTREG(118,472,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3,       
0,0,0,0,0,0)
+  XTREG(119,476,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4,       
0,0,0,0,0,0)
+  XTREG(120,480,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5,       
0,0,0,0,0,0)
+  XTREG(121,484,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6,       
0,0,0,0,0,0)
+  XTREG(122,488,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7,       
0,0,0,0,0,0)
+  XTREG(123,492,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc,       
0,0,0,0,0,0)
+  XTREG(124,496,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2,       
0,0,0,0,0,0)
+  XTREG(125,500,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3,       
0,0,0,0,0,0)
+  XTREG(126,504,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4,       
0,0,0,0,0,0)
+  XTREG(127,508,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5,       
0,0,0,0,0,0)
+  XTREG(128,512,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6,       
0,0,0,0,0,0)
+  XTREG(129,516,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7,       
0,0,0,0,0,0)
+  XTREG(130,520,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1,   
0,0,0,0,0,0)
+  XTREG(131,524,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2,   
0,0,0,0,0,0)
+  XTREG(132,528,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3,   
0,0,0,0,0,0)
+  XTREG(133,532,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4,   
0,0,0,0,0,0)
+  XTREG(134,536,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5,   
0,0,0,0,0,0)
+  XTREG(135,540,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6,   
0,0,0,0,0,0)
+  XTREG(136,544,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7,   
0,0,0,0,0,0)
+  XTREG(137,548, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable,   
0,0,0,0,0,0)
+  XTREG(138,552,32, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt,  
0,0,0,0,0,0)
+  XTREG(139,556,32, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset,     
0,0,0,0,0,0)
+  XTREG(140,560,32, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear,   
0,0,0,0,0,0)
+  XTREG(141,564,32, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable,  
0,0,0,0,0,0)
+  XTREG(142,568,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase,    
0,0,0,0,0,0)
+  XTREG(143,572, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause,   
0,0,0,0,0,0)
+  XTREG(144,576,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 
0,0,0,0,0,0)
+  XTREG(145,580,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount,     
0,0,0,0,0,0)
+  XTREG(146,584,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid,       
0,0,0,0,0,0)
+  XTREG(147,588,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount,     
0,0,0,0,0,0)
+  XTREG(148,592, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel,
0,0,0,0,0,0)
+  XTREG(149,596,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr,   
0,0,0,0,0,0)
+  XTREG(150,600,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0,  
0,0,0,0,0,0)
+  XTREG(151,604,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1,  
0,0,0,0,0,0)
+  XTREG(152,608,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2,  
0,0,0,0,0,0)
+  XTREG(153,612,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0,      
0,0,0,0,0,0)
+  XTREG(154,616,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1,      
0,0,0,0,0,0)
+  XTREG(155,620,32, 4, 4,0x02f6,0x0007,-2, 2,0x1000,misc2,      
0,0,0,0,0,0)
+  XTREG(156,624,32, 4, 4,0x02f7,0x0007,-2, 2,0x1000,misc3,      
0,0,0,0,0,0)
+  XTREG(157,628,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0,         
0,0,0,0,0,0)
+  XTREG(158,632,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1,         
0,0,0,0,0,0)
+  XTREG(159,636,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2,         
0,0,0,0,0,0)
+  XTREG(160,640,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3,         
0,0,0,0,0,0)
+  XTREG(161,644,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4,         
0,0,0,0,0,0)
+  XTREG(162,648,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5,         
0,0,0,0,0,0)
+  XTREG(163,652,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6,         
0,0,0,0,0,0)
+  XTREG(164,656,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7,         
0,0,0,0,0,0)
+  XTREG(165,660,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8,         
0,0,0,0,0,0)
+  XTREG(166,664,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9,         
0,0,0,0,0,0)
+  XTREG(167,668,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10,        
0,0,0,0,0,0)
+  XTREG(168,672,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11,        
0,0,0,0,0,0)
+  XTREG(169,676,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12,        
0,0,0,0,0,0)
+  XTREG(170,680,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13,        
0,0,0,0,0,0)
+  XTREG(171,684,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14,        
0,0,0,0,0,0)
+  XTREG(172,688,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15,        
0,0,0,0,0,0)
+  XTREG(173,692, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
+            0,0,&xtensa_mask0,0,0,0)
+  XTREG(174,693, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
+            0,0,&xtensa_mask1,0,0,0)
+  XTREG(175,694, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
+            0,0,&xtensa_mask2,0,0,0)
+  XTREG(176,695, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
+            0,0,&xtensa_mask3,0,0,0)
+  XTREG(177,696, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
+            0,0,&xtensa_mask4,0,0,0)
+  XTREG(178,697, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
+            0,0,&xtensa_mask5,0,0,0)
+  XTREG(179,698, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
+            0,0,&xtensa_mask6,0,0,0)
+  XTREG(180,699, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
+            0,0,&xtensa_mask7,0,0,0)
+  XTREG(181,700, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
+            0,0,&xtensa_mask8,0,0,0)
+  XTREG(182,701, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
+            0,0,&xtensa_mask9,0,0,0)
+  XTREG(183,702, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
+            0,0,&xtensa_mask10,0,0,0)
+  XTREG(184,703, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
+            0,0,&xtensa_mask11,0,0,0)
+  XTREG(185,704, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
+            0,0,&xtensa_mask12,0,0,0)
+  XTREG(186,705, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
+            0,0,&xtensa_mask13,0,0,0)
+  XTREG(187,706, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
+            0,0,&xtensa_mask14,0,0,0)
+  XTREG(188,707, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
+            0,0,&xtensa_mask15,0,0,0)
+  XTREG(189,708, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
+            0,0,&xtensa_mask16,0,0,0)
+  XTREG(190,712, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
+            0,0,&xtensa_mask17,0,0,0)
+  XTREG(191,716, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
+            0,0,&xtensa_mask18,0,0,0)
+  XTREG(192,720, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm,
+            0,0,&xtensa_mask19,0,0,0)
+  XTREG(193,724, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc,
+            0,0,&xtensa_mask20,0,0,0)
+  XTREG(194,728, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb,
+            0,0,&xtensa_mask21,0,0,0)
+  XTREG(195,732,40, 8, 4,0x200e,0x0006,-2, 6,0x1010,acc,
+            0,0,&xtensa_mask22,0,0,0)
+  XTREG(196,740, 4, 4, 4,0x2013,0x0006,-2, 6,0x1010,dbnum,
+            0,0,&xtensa_mask23,0,0,0)
+  XTREG(197,744,64, 8, 4,0x2015,0x0006,-2, 5,0x1010,f64r,
+            0,0,&xtensa_mask24,0,0,0)
+  XTREG(198,752, 2, 4, 4,0x2016,0x0006, 0, 5,0x1010,roundmode,
+            0,0,&xtensa_mask25,0,0,0)
+  XTREG(199,756, 1, 4, 4,0x2017,0x0006, 0, 5,0x1010,invalidenable,
+            0,0,&xtensa_mask26,0,0,0)
+  XTREG(200,760, 1, 4, 4,0x2018,0x0006, 0, 5,0x1010,divzeroenable,
+            0,0,&xtensa_mask27,0,0,0)
+  XTREG(201,764, 1, 4, 4,0x2019,0x0006, 0, 5,0x1010,overflowenable,
+            0,0,&xtensa_mask28,0,0,0)
+  XTREG(202,768, 1, 4, 4,0x201a,0x0006, 0, 5,0x1010,underflowenable,
+            0,0,&xtensa_mask29,0,0,0)
+  XTREG(203,772, 1, 4, 4,0x201b,0x0006, 0, 5,0x1010,inexactenable,
+            0,0,&xtensa_mask30,0,0,0)
+  XTREG(204,776, 1, 4, 4,0x201c,0x0006, 0, 5,0x1010,invalidflag,
+            0,0,&xtensa_mask31,0,0,0)
+  XTREG(205,780, 1, 4, 4,0x201d,0x0006, 0, 5,0x1010,divzeroflag,
+            0,0,&xtensa_mask32,0,0,0)
+  XTREG(206,784, 1, 4, 4,0x201e,0x0006, 0, 5,0x1010,overflowflag,
+            0,0,&xtensa_mask33,0,0,0)
+  XTREG(207,788, 1, 4, 4,0x201f,0x0006, 0, 5,0x1010,underflowflag,
+            0,0,&xtensa_mask34,0,0,0)
+  XTREG(208,792, 1, 4, 4,0x2020,0x0006, 0, 5,0x1010,inexactflag,
+            0,0,&xtensa_mask35,0,0,0)
+  XTREG(209,796,20, 4, 4,0x2021,0x0006, 0, 5,0x1010,fpreserved20,
+            0,0,&xtensa_mask36,0,0,0)
+  XTREG(210,800,20, 4, 4,0x2022,0x0006, 0, 5,0x1010,fpreserved20a,
+            0,0,&xtensa_mask37,0,0,0)
+  XTREG(211,804, 5, 4, 4,0x2023,0x0006, 0, 5,0x1010,fpreserved5,
+            0,0,&xtensa_mask38,0,0,0)
+  XTREG_END
+};
+
+xtensa_gdbarch_tdep xtensa_tdep_esp32 (rmap);
diff --git a/gdb/xtensa-config-esp32s2.c b/gdb/xtensa-config-esp32s2.c
new file mode 100644
index 00000000000..a12f129f4d9
--- /dev/null
+++ b/gdb/xtensa-config-esp32s2.c
@@ -0,0 +1,271 @@
+/* Configuration for the Xtensa architecture for GDB, the GNU
debugger.
+
+   Customer ID=14525; Build=0x787b1; Copyright (c) 2003-2018 Tensilica
Inc.
+
+   Permission is hereby granted, free of charge, to any person
obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject
to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be
included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR
ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+#define XTENSA_CONFIG_VERSION 0x60
+
+#include "defs.h"
+#include "xtensa-config.h"
+#include "xtensa-tdep.h"
+
+
+
+/* Masked registers.  */
+static xtensa_reg_mask_t xtensa_submask0[] = { { 70, 0, 4 } };
+static const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 };
+static xtensa_reg_mask_t xtensa_submask1[] = { { 70, 5, 1 } };
+static const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 };
+static xtensa_reg_mask_t xtensa_submask2[] = { { 70, 18, 1 } };
+static const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 };
+static xtensa_reg_mask_t xtensa_submask3[] = { { 70, 4, 1 } };
+static const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 };
+static xtensa_reg_mask_t xtensa_submask4[] = { { 70, 16, 2 } };
+static const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 };
+static xtensa_reg_mask_t xtensa_submask5[] = { { 70, 8, 4 } };
+static const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 };
+static xtensa_reg_mask_t xtensa_submask6[] = { { 110, 8, 4 } };
+static const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 };
+
+
+/* Register map.  */
+static xtensa_register_t rmap[] = 
+{
+  /*    idx ofs bi sz al targno  flags cp typ group name  */
+  XTREG(  0,  0,32, 4, 4,0x0020,0x0006,-2, 9,0x2100,pc,         
0,0,0,0,0,0)
+  XTREG(  1,  4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0,        
0,0,0,0,0,0)
+  XTREG(  2,  8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1,        
0,0,0,0,0,0)
+  XTREG(  3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2,        
0,0,0,0,0,0)
+  XTREG(  4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3,        
0,0,0,0,0,0)
+  XTREG(  5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4,        
0,0,0,0,0,0)
+  XTREG(  6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5,        
0,0,0,0,0,0)
+  XTREG(  7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6,        
0,0,0,0,0,0)
+  XTREG(  8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7,        
0,0,0,0,0,0)
+  XTREG(  9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8,        
0,0,0,0,0,0)
+  XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9,        
0,0,0,0,0,0)
+  XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10,       
0,0,0,0,0,0)
+  XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11,       
0,0,0,0,0,0)
+  XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12,       
0,0,0,0,0,0)
+  XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13,       
0,0,0,0,0,0)
+  XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14,       
0,0,0,0,0,0)
+  XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15,       
0,0,0,0,0,0)
+  XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16,       
0,0,0,0,0,0)
+  XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17,       
0,0,0,0,0,0)
+  XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18,       
0,0,0,0,0,0)
+  XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19,       
0,0,0,0,0,0)
+  XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20,       
0,0,0,0,0,0)
+  XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21,       
0,0,0,0,0,0)
+  XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22,       
0,0,0,0,0,0)
+  XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23,       
0,0,0,0,0,0)
+  XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24,       
0,0,0,0,0,0)
+  XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25,       
0,0,0,0,0,0)
+  XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26,       
0,0,0,0,0,0)
+  XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27,       
0,0,0,0,0,0)
+  XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28,       
0,0,0,0,0,0)
+  XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29,       
0,0,0,0,0,0)
+  XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30,       
0,0,0,0,0,0)
+  XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31,       
0,0,0,0,0,0)
+  XTREG( 33,132,32, 4, 4,0x0120,0x0006,-2, 1,0x0002,ar32,       
0,0,0,0,0,0)
+  XTREG( 34,136,32, 4, 4,0x0121,0x0006,-2, 1,0x0002,ar33,       
0,0,0,0,0,0)
+  XTREG( 35,140,32, 4, 4,0x0122,0x0006,-2, 1,0x0002,ar34,       
0,0,0,0,0,0)
+  XTREG( 36,144,32, 4, 4,0x0123,0x0006,-2, 1,0x0002,ar35,       
0,0,0,0,0,0)
+  XTREG( 37,148,32, 4, 4,0x0124,0x0006,-2, 1,0x0002,ar36,       
0,0,0,0,0,0)
+  XTREG( 38,152,32, 4, 4,0x0125,0x0006,-2, 1,0x0002,ar37,       
0,0,0,0,0,0)
+  XTREG( 39,156,32, 4, 4,0x0126,0x0006,-2, 1,0x0002,ar38,       
0,0,0,0,0,0)
+  XTREG( 40,160,32, 4, 4,0x0127,0x0006,-2, 1,0x0002,ar39,       
0,0,0,0,0,0)
+  XTREG( 41,164,32, 4, 4,0x0128,0x0006,-2, 1,0x0002,ar40,       
0,0,0,0,0,0)
+  XTREG( 42,168,32, 4, 4,0x0129,0x0006,-2, 1,0x0002,ar41,       
0,0,0,0,0,0)
+  XTREG( 43,172,32, 4, 4,0x012a,0x0006,-2, 1,0x0002,ar42,       
0,0,0,0,0,0)
+  XTREG( 44,176,32, 4, 4,0x012b,0x0006,-2, 1,0x0002,ar43,       
0,0,0,0,0,0)
+  XTREG( 45,180,32, 4, 4,0x012c,0x0006,-2, 1,0x0002,ar44,       
0,0,0,0,0,0)
+  XTREG( 46,184,32, 4, 4,0x012d,0x0006,-2, 1,0x0002,ar45,       
0,0,0,0,0,0)
+  XTREG( 47,188,32, 4, 4,0x012e,0x0006,-2, 1,0x0002,ar46,       
0,0,0,0,0,0)
+  XTREG( 48,192,32, 4, 4,0x012f,0x0006,-2, 1,0x0002,ar47,       
0,0,0,0,0,0)
+  XTREG( 49,196,32, 4, 4,0x0130,0x0006,-2, 1,0x0002,ar48,       
0,0,0,0,0,0)
+  XTREG( 50,200,32, 4, 4,0x0131,0x0006,-2, 1,0x0002,ar49,       
0,0,0,0,0,0)
+  XTREG( 51,204,32, 4, 4,0x0132,0x0006,-2, 1,0x0002,ar50,       
0,0,0,0,0,0)
+  XTREG( 52,208,32, 4, 4,0x0133,0x0006,-2, 1,0x0002,ar51,       
0,0,0,0,0,0)
+  XTREG( 53,212,32, 4, 4,0x0134,0x0006,-2, 1,0x0002,ar52,       
0,0,0,0,0,0)
+  XTREG( 54,216,32, 4, 4,0x0135,0x0006,-2, 1,0x0002,ar53,       
0,0,0,0,0,0)
+  XTREG( 55,220,32, 4, 4,0x0136,0x0006,-2, 1,0x0002,ar54,       
0,0,0,0,0,0)
+  XTREG( 56,224,32, 4, 4,0x0137,0x0006,-2, 1,0x0002,ar55,       
0,0,0,0,0,0)
+  XTREG( 57,228,32, 4, 4,0x0138,0x0006,-2, 1,0x0002,ar56,       
0,0,0,0,0,0)
+  XTREG( 58,232,32, 4, 4,0x0139,0x0006,-2, 1,0x0002,ar57,       
0,0,0,0,0,0)
+  XTREG( 59,236,32, 4, 4,0x013a,0x0006,-2, 1,0x0002,ar58,       
0,0,0,0,0,0)
+  XTREG( 60,240,32, 4, 4,0x013b,0x0006,-2, 1,0x0002,ar59,       
0,0,0,0,0,0)
+  XTREG( 61,244,32, 4, 4,0x013c,0x0006,-2, 1,0x0002,ar60,       
0,0,0,0,0,0)
+  XTREG( 62,248,32, 4, 4,0x013d,0x0006,-2, 1,0x0002,ar61,       
0,0,0,0,0,0)
+  XTREG( 63,252,32, 4, 4,0x013e,0x0006,-2, 1,0x0002,ar62,       
0,0,0,0,0,0)
+  XTREG( 64,256,32, 4, 4,0x013f,0x0006,-2, 1,0x0002,ar63,       
0,0,0,0,0,0)
+  XTREG( 65,260, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar,        
0,0,0,0,0,0)
+  XTREG( 66,264, 4, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 
0,0,0,0,0,0)
+  XTREG( 67,268,16, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart,
0,0,0,0,0,0)
+  XTREG( 68,272,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0,  
0,0,0,0,0,0)
+  XTREG( 69,276,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1,  
0,0,0,0,0,0)
+  XTREG( 70,280,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps,         
0,0,0,0,0,0)
+  XTREG( 71,284,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr,  
0,0,0,0,0,0)
+  XTREG( 72,288, 8, 4, 4,0x0300,0x000e,-1, 3,0x0210,gpio_out,   
0,0,0,0,0,0)
+  XTREG( 73,292,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid,       
0,0,0,0,0,0)
+  XTREG( 74,296, 2, 4, 4,0x0260,0x0007,-2,
2,0x1000,ibreakenable,0,0,0,0,0,0)
+  XTREG( 75,300,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr,        
0,0,0,0,0,0)
+  XTREG( 76,304,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0,   
0,0,0,0,0,0)
+  XTREG( 77,308,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1,   
0,0,0,0,0,0)
+  XTREG( 78,312,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0,   
0,0,0,0,0,0)
+  XTREG( 79,316,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1,   
0,0,0,0,0,0)
+  XTREG( 80,320,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0,   
0,0,0,0,0,0)
+  XTREG( 81,324,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1,   
0,0,0,0,0,0)
+  XTREG( 82,328,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1,       
0,0,0,0,0,0)
+  XTREG( 83,332,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2,       
0,0,0,0,0,0)
+  XTREG( 84,336,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3,       
0,0,0,0,0,0)
+  XTREG( 85,340,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4,       
0,0,0,0,0,0)
+  XTREG( 86,344,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5,       
0,0,0,0,0,0)
+  XTREG( 87,348,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6,       
0,0,0,0,0,0)
+  XTREG( 88,352,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7,       
0,0,0,0,0,0)
+  XTREG( 89,356,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc,       
0,0,0,0,0,0)
+  XTREG( 90,360,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2,       
0,0,0,0,0,0)
+  XTREG( 91,364,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3,       
0,0,0,0,0,0)
+  XTREG( 92,368,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4,       
0,0,0,0,0,0)
+  XTREG( 93,372,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5,       
0,0,0,0,0,0)
+  XTREG( 94,376,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6,       
0,0,0,0,0,0)
+  XTREG( 95,380,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7,       
0,0,0,0,0,0)
+  XTREG( 96,384,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1,   
0,0,0,0,0,0)
+  XTREG( 97,388,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2,   
0,0,0,0,0,0)
+  XTREG( 98,392,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3,   
0,0,0,0,0,0)
+  XTREG( 99,396,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4,   
0,0,0,0,0,0)
+  XTREG(100,400,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5,   
0,0,0,0,0,0)
+  XTREG(101,404,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6,   
0,0,0,0,0,0)
+  XTREG(102,408,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7,   
0,0,0,0,0,0)
+  XTREG(103,412, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable,   
0,0,0,0,0,0)
+  XTREG(104,416,32, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt,  
0,0,0,0,0,0)
+  XTREG(105,420,32, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset,     
0,0,0,0,0,0)
+  XTREG(106,424,32, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear,   
0,0,0,0,0,0)
+  XTREG(107,428,32, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable,  
0,0,0,0,0,0)
+  XTREG(108,432,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase,    
0,0,0,0,0,0)
+  XTREG(109,436, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause,   
0,0,0,0,0,0)
+  XTREG(110,440,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 
0,0,0,0,0,0)
+  XTREG(111,444,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount,     
0,0,0,0,0,0)
+  XTREG(112,448,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid,       
0,0,0,0,0,0)
+  XTREG(113,452,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount,     
0,0,0,0,0,0)
+  XTREG(114,456, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel,
0,0,0,0,0,0)
+  XTREG(115,460,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr,   
0,0,0,0,0,0)
+  XTREG(116,464,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0,  
0,0,0,0,0,0)
+  XTREG(117,468,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1,  
0,0,0,0,0,0)
+  XTREG(118,472,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2,  
0,0,0,0,0,0)
+  XTREG(119,476,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0,      
0,0,0,0,0,0)
+  XTREG(120,480,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1,      
0,0,0,0,0,0)
+  XTREG(121,484,32, 4, 4,0x02f6,0x0007,-2, 2,0x1000,misc2,      
0,0,0,0,0,0)
+  XTREG(122,488,32, 4, 4,0x02f7,0x0007,-2, 2,0x1000,misc3,      
0,0,0,0,0,0)
+  XTREG(123,492,32, 4, 4,0x2014,0x000f,-2, 4,0x0101,pwrctl,
+           
"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:0c:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(124,496,32, 4, 4,0x2015,0x000f,-2, 4,0x0101,pwrstat,
+           
"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:0c:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(125,500, 1, 4, 4,0x2016,0x000f,-2, 4,0x0101,eristat,
+           
"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:0c:03:60:55:11:03:52:c5:28:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(126,504,32, 4, 4,0x2017,0x000f,-2, 4,0x0101,cs_itctrl,
+           
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:0f:03:60:55:11:03:52:d5:03:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(127,508,16, 4, 4,0x2018,0x000f,-2, 4,0x0101,cs_claimset,
+           
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:0
4:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:6
4:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:62:24:00:03:60:
75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+  XTREG(128,512,16, 4, 4,0x2019,0x000f,-2, 4,0x0101,cs_claimclr,
+           
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:0
4:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:6
4:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:62:24:00:03:60:
75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+  XTREG(129,516,32, 4, 4,0x201a,0x000d,-2, 4,0x0101,cs_lockaccess,
+           
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:0
4:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:6
4:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:62:24:00:03:60:
75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+  XTREG(130,520,32, 4, 4,0x201b,0x000b,-2, 4,0x0101,cs_lockstatus,
+           
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:0
4:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:6
4:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:62:24:00:03:60:
75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+  XTREG(131,524, 1, 4, 4,0x201c,0x000b,-2, 4,0x0101,cs_authstatus,
+           
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:0
4:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:6
4:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:62:24:00:03:60:
75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+  XTREG(132,528,32, 4, 4,0x202b,0x000f,-2, 4,0x0101,fault_info,
+           
"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:30:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:0c:03:60:55:11:03:52:c5:30:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(133,532,32, 4, 4,0x202c,0x0003,-2, 4,0x0101,trax_id,
+           
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:60:65:40:03:62:64:0
0:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:5
5:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+  XTREG(134,536,32, 4, 4,0x202d,0x000f,-2, 4,0x0101,trax_control,
+           
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:00:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(135,540,32, 4, 4,0x202e,0x000b,-2, 4,0x0101,trax_status,
+           
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:00:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(136,544,32, 4, 4,0x202f,0x000f,-2, 4,0x0101,trax_data,
+           
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:00:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(137,548,32, 4, 4,0x2030,0x000f,-2, 4,0x0101,trax_address,
+           
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:00:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(138,552,32, 4, 4,0x2031,0x000f,-2, 4,0x0101,trax_pctrigger,
+           
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:00:03:60:55:11:03:52:c5:14:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(139,556,32, 4, 4,0x2032,0x000f,-2, 4,0x0101,trax_pcmatch,
+           
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:00:03:60:55:11:03:52:c5:18:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(140,560,32, 4, 4,0x2033,0x000f,-2, 4,0x0101,trax_delay,
+           
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:00:03:60:55:11:03:52:c5:1c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(141,564,32, 4, 4,0x2034,0x000f,-2, 4,0x0101,trax_memstart,
+           
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:00:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(142,568,32, 4, 4,0x2035,0x000f,-2, 4,0x0101,trax_memend,
+           
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:00:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(143,572,32, 4, 4,0x2043,0x000f,-2, 4,0x0101,pmg,
+           
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:60:65:40:03:62:64:0
0:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:5
5:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+  XTREG(144,576,32, 4, 4,0x2044,0x000f,-2, 4,0x0101,pmpc,
+           
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:04:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:04:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(145,580,32, 4, 4,0x2045,0x000f,-2, 4,0x0101,pm0,
+           
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:0
1:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:6
4:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:
75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+  XTREG(146,584,32, 4, 4,0x2046,0x000f,-2, 4,0x0101,pm1,
+           
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:0
1:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:6
4:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:
75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+  XTREG(147,588,32, 4, 4,0x2047,0x000f,-2, 4,0x0101,pmctrl0,
+           
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(148,592,32, 4, 4,0x2048,0x000f,-2, 4,0x0101,pmctrl1,
+           
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(149,596,32, 4, 4,0x2049,0x000f,-2, 4,0x0101,pmstat0,
+           
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:0
2:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:6
4:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:
75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+  XTREG(150,600,32, 4, 4,0x204a,0x000f,-2, 4,0x0101,pmstat1,
+           
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:0
2:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:6
4:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:
75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+  XTREG(151,604,32, 4, 4,0x204b,0x0003,-2, 4,0x0101,ocdid,
+           
"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:60:65:40:03:62:64:0
0:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:5
5:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+  XTREG(152,608,32, 4, 4,0x204c,0x000f,-2, 4,0x0101,ocd_dcrclr,
+           
"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:08:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(153,612,32, 4, 4,0x204d,0x000f,-2, 4,0x0101,ocd_dcrset,
+           
"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:08:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(154,616,32, 4, 4,0x204e,0x000f,-2, 4,0x0101,ocd_dsr,
+           
"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:08:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(155,620,32, 4, 4,0x0000,0x0006,-2, 8,0x2100,a0,         
0,0,0,0,0,0)
+  XTREG(156,624,32, 4, 4,0x0001,0x0006,-2, 8,0x2100,a1,         
0,0,0,0,0,0)
+  XTREG(157,628,32, 4, 4,0x0002,0x0006,-2, 8,0x2100,a2,         
0,0,0,0,0,0)
+  XTREG(158,632,32, 4, 4,0x0003,0x0006,-2, 8,0x2100,a3,         
0,0,0,0,0,0)
+  XTREG(159,636,32, 4, 4,0x0004,0x0006,-2, 8,0x2100,a4,         
0,0,0,0,0,0)
+  XTREG(160,640,32, 4, 4,0x0005,0x0006,-2, 8,0x2100,a5,         
0,0,0,0,0,0)
+  XTREG(161,644,32, 4, 4,0x0006,0x0006,-2, 8,0x2100,a6,         
0,0,0,0,0,0)
+  XTREG(162,648,32, 4, 4,0x0007,0x0006,-2, 8,0x2100,a7,         
0,0,0,0,0,0)
+  XTREG(163,652,32, 4, 4,0x0008,0x0006,-2, 8,0x2100,a8,         
0,0,0,0,0,0)
+  XTREG(164,656,32, 4, 4,0x0009,0x0006,-2, 8,0x2100,a9,         
0,0,0,0,0,0)
+  XTREG(165,660,32, 4, 4,0x000a,0x0006,-2, 8,0x2100,a10,        
0,0,0,0,0,0)
+  XTREG(166,664,32, 4, 4,0x000b,0x0006,-2, 8,0x2100,a11,        
0,0,0,0,0,0)
+  XTREG(167,668,32, 4, 4,0x000c,0x0006,-2, 8,0x2100,a12,        
0,0,0,0,0,0)
+  XTREG(168,672,32, 4, 4,0x000d,0x0006,-2, 8,0x2100,a13,        
0,0,0,0,0,0)
+  XTREG(169,676,32, 4, 4,0x000e,0x0006,-2, 8,0x2100,a14,        
0,0,0,0,0,0)
+  XTREG(170,680,32, 4, 4,0x000f,0x0006,-2, 8,0x2100,a15,        
0,0,0,0,0,0)
+  XTREG(171,684, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
+            0,0,&xtensa_mask0,0,0,0)
+  XTREG(172,688, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
+            0,0,&xtensa_mask1,0,0,0)
+  XTREG(173,692, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
+            0,0,&xtensa_mask2,0,0,0)
+  XTREG(174,696, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm,
+            0,0,&xtensa_mask3,0,0,0)
+  XTREG(175,700, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc,
+            0,0,&xtensa_mask4,0,0,0)
+  XTREG(176,704, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb,
+            0,0,&xtensa_mask5,0,0,0)
+  XTREG_END
+};
+
+xtensa_gdbarch_tdep xtensa_tdep_esp32s2 (rmap);
diff --git a/gdb/xtensa-config-esp32s3.c b/gdb/xtensa-config-esp32s3.c
new file mode 100644
index 00000000000..658b12b8903
--- /dev/null
+++ b/gdb/xtensa-config-esp32s3.c
@@ -0,0 +1,496 @@
+/* Configuration for the Xtensa architecture for GDB, the GNU
debugger.
+
+   Customer ID=15128; Build=0x90f1f; Copyright (c) 2003-2021 Tensilica
Inc.
+
+   Permission is hereby granted, free of charge, to any person
obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject
to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be
included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR
ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+#define XTENSA_CONFIG_VERSION 0x60
+
+#include "defs.h"
+#include "xtensa-config.h"
+#include "xtensa-tdep.h"
+
+
+
+/* Masked registers.  */
+static xtensa_reg_mask_t xtensa_submask0[] = { { 75, 0, 1 } };
+static const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 };
+static xtensa_reg_mask_t xtensa_submask1[] = { { 75, 1, 1 } };
+static const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 };
+static xtensa_reg_mask_t xtensa_submask2[] = { { 75, 2, 1 } };
+static const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 };
+static xtensa_reg_mask_t xtensa_submask3[] = { { 75, 3, 1 } };
+static const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 };
+static xtensa_reg_mask_t xtensa_submask4[] = { { 75, 4, 1 } };
+static const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 };
+static xtensa_reg_mask_t xtensa_submask5[] = { { 75, 5, 1 } };
+static const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 };
+static xtensa_reg_mask_t xtensa_submask6[] = { { 75, 6, 1 } };
+static const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 };
+static xtensa_reg_mask_t xtensa_submask7[] = { { 75, 7, 1 } };
+static const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 };
+static xtensa_reg_mask_t xtensa_submask8[] = { { 75, 8, 1 } };
+static const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 };
+static xtensa_reg_mask_t xtensa_submask9[] = { { 75, 9, 1 } };
+static const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 };
+static xtensa_reg_mask_t xtensa_submask10[] = { { 75, 10, 1 } };
+static const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 };
+static xtensa_reg_mask_t xtensa_submask11[] = { { 75, 11, 1 } };
+static const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 };
+static xtensa_reg_mask_t xtensa_submask12[] = { { 75, 12, 1 } };
+static const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 };
+static xtensa_reg_mask_t xtensa_submask13[] = { { 75, 13, 1 } };
+static const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 };
+static xtensa_reg_mask_t xtensa_submask14[] = { { 75, 14, 1 } };
+static const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 };
+static xtensa_reg_mask_t xtensa_submask15[] = { { 75, 15, 1 } };
+static const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 };
+static xtensa_reg_mask_t xtensa_submask16[] = { { 73, 0, 4 } };
+static const xtensa_mask_t xtensa_mask16 = { 1, xtensa_submask16 };
+static xtensa_reg_mask_t xtensa_submask17[] = { { 73, 5, 1 } };
+static const xtensa_mask_t xtensa_mask17 = { 1, xtensa_submask17 };
+static xtensa_reg_mask_t xtensa_submask18[] = { { 73, 18, 1 } };
+static const xtensa_mask_t xtensa_mask18 = { 1, xtensa_submask18 };
+static xtensa_reg_mask_t xtensa_submask19[] = { { 73, 4, 1 } };
+static const xtensa_mask_t xtensa_mask19 = { 1, xtensa_submask19 };
+static xtensa_reg_mask_t xtensa_submask20[] = { { 73, 16, 2 } };
+static const xtensa_mask_t xtensa_mask20 = { 1, xtensa_submask20 };
+static xtensa_reg_mask_t xtensa_submask21[] = { { 73, 8, 4 } };
+static const xtensa_mask_t xtensa_mask21 = { 1, xtensa_submask21 };
+static xtensa_reg_mask_t xtensa_submask22[] = { { 77, 0, 32 }, { 78,
0, 8 } };
+static const xtensa_mask_t xtensa_mask22 = { 2, xtensa_submask22 };
+static xtensa_reg_mask_t xtensa_submask23[] = { { 167, 8, 4 } };
+static const xtensa_mask_t xtensa_mask23 = { 1, xtensa_submask23 };
+static xtensa_reg_mask_t xtensa_submask24[] = { { 100, 0, 2 } };
+static const xtensa_mask_t xtensa_mask24 = { 1, xtensa_submask24 };
+static xtensa_reg_mask_t xtensa_submask25[] = { { 100, 6, 1 } };
+static const xtensa_mask_t xtensa_mask25 = { 1, xtensa_submask25 };
+static xtensa_reg_mask_t xtensa_submask26[] = { { 100, 5, 1 } };
+static const xtensa_mask_t xtensa_mask26 = { 1, xtensa_submask26 };
+static xtensa_reg_mask_t xtensa_submask27[] = { { 100, 4, 1 } };
+static const xtensa_mask_t xtensa_mask27 = { 1, xtensa_submask27 };
+static xtensa_reg_mask_t xtensa_submask28[] = { { 100, 3, 1 } };
+static const xtensa_mask_t xtensa_mask28 = { 1, xtensa_submask28 };
+static xtensa_reg_mask_t xtensa_submask29[] = { { 100, 2, 1 } };
+static const xtensa_mask_t xtensa_mask29 = { 1, xtensa_submask29 };
+static xtensa_reg_mask_t xtensa_submask30[] = { { 101, 11, 1 } };
+static const xtensa_mask_t xtensa_mask30 = { 1, xtensa_submask30 };
+static xtensa_reg_mask_t xtensa_submask31[] = { { 101, 10, 1 } };
+static const xtensa_mask_t xtensa_mask31 = { 1, xtensa_submask31 };
+static xtensa_reg_mask_t xtensa_submask32[] = { { 101, 9, 1 } };
+static const xtensa_mask_t xtensa_mask32 = { 1, xtensa_submask32 };
+static xtensa_reg_mask_t xtensa_submask33[] = { { 101, 8, 1 } };
+static const xtensa_mask_t xtensa_mask33 = { 1, xtensa_submask33 };
+static xtensa_reg_mask_t xtensa_submask34[] = { { 101, 7, 1 } };
+static const xtensa_mask_t xtensa_mask34 = { 1, xtensa_submask34 };
+static xtensa_reg_mask_t xtensa_submask35[] = { { 100, 12, 20 } };
+static const xtensa_mask_t xtensa_mask35 = { 1, xtensa_submask35 };
+static xtensa_reg_mask_t xtensa_submask36[] = { { 101, 12, 20 } };
+static const xtensa_mask_t xtensa_mask36 = { 1, xtensa_submask36 };
+static xtensa_reg_mask_t xtensa_submask37[] = { { 100, 7, 5 } };
+static const xtensa_mask_t xtensa_mask37 = { 1, xtensa_submask37 };
+static xtensa_reg_mask_t xtensa_submask38[] = { { 101, 0, 7 } };
+static const xtensa_mask_t xtensa_mask38 = { 1, xtensa_submask38 };
+static xtensa_reg_mask_t xtensa_submask39[] = { { 102, 0, 32 }, { 103,
0, 8 } };
+static const xtensa_mask_t xtensa_mask39 = { 2, xtensa_submask39 };
+static xtensa_reg_mask_t xtensa_submask40[] = { { 104, 0, 32 }, { 105,
0, 32 }, { 106, 0, 32 }, { 107, 0, 32 }, { 108, 0, 32 } };
+static const xtensa_mask_t xtensa_mask40 = { 5, xtensa_submask40 };
+static xtensa_reg_mask_t xtensa_submask41[] = { { 109, 0, 32 }, { 110,
0, 32 }, { 111, 0, 32 }, { 112, 0, 32 }, { 113, 0, 32 } };
+static const xtensa_mask_t xtensa_mask41 = { 5, xtensa_submask41 };
+static xtensa_reg_mask_t xtensa_submask42[] = { { 116, 0, 32 }, { 117,
0, 32 }, { 118, 0, 32 }, { 119, 0, 32 } };
+static const xtensa_mask_t xtensa_mask42 = { 4, xtensa_submask42 };
+
+
+/* Register map.  */
+static xtensa_register_t rmap[] = 
+{
+  /*    idx ofs bi sz al targno  flags cp typ group name  */
+  XTREG(  0,  0,32, 4, 4,0x0020,0x0006,-2, 9,0x2100,pc,         
0,0,0,0,0,0)
+  XTREG(  1,  4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0,        
0,0,0,0,0,0)
+  XTREG(  2,  8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1,        
0,0,0,0,0,0)
+  XTREG(  3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2,        
0,0,0,0,0,0)
+  XTREG(  4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3,        
0,0,0,0,0,0)
+  XTREG(  5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4,        
0,0,0,0,0,0)
+  XTREG(  6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5,        
0,0,0,0,0,0)
+  XTREG(  7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6,        
0,0,0,0,0,0)
+  XTREG(  8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7,        
0,0,0,0,0,0)
+  XTREG(  9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8,        
0,0,0,0,0,0)
+  XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9,        
0,0,0,0,0,0)
+  XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10,       
0,0,0,0,0,0)
+  XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11,       
0,0,0,0,0,0)
+  XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12,       
0,0,0,0,0,0)
+  XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13,       
0,0,0,0,0,0)
+  XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14,       
0,0,0,0,0,0)
+  XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15,       
0,0,0,0,0,0)
+  XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16,       
0,0,0,0,0,0)
+  XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17,       
0,0,0,0,0,0)
+  XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18,       
0,0,0,0,0,0)
+  XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19,       
0,0,0,0,0,0)
+  XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20,       
0,0,0,0,0,0)
+  XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21,       
0,0,0,0,0,0)
+  XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22,       
0,0,0,0,0,0)
+  XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23,       
0,0,0,0,0,0)
+  XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24,       
0,0,0,0,0,0)
+  XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25,       
0,0,0,0,0,0)
+  XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26,       
0,0,0,0,0,0)
+  XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27,       
0,0,0,0,0,0)
+  XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28,       
0,0,0,0,0,0)
+  XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29,       
0,0,0,0,0,0)
+  XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30,       
0,0,0,0,0,0)
+  XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31,       
0,0,0,0,0,0)
+  XTREG( 33,132,32, 4, 4,0x0120,0x0006,-2, 1,0x0002,ar32,       
0,0,0,0,0,0)
+  XTREG( 34,136,32, 4, 4,0x0121,0x0006,-2, 1,0x0002,ar33,       
0,0,0,0,0,0)
+  XTREG( 35,140,32, 4, 4,0x0122,0x0006,-2, 1,0x0002,ar34,       
0,0,0,0,0,0)
+  XTREG( 36,144,32, 4, 4,0x0123,0x0006,-2, 1,0x0002,ar35,       
0,0,0,0,0,0)
+  XTREG( 37,148,32, 4, 4,0x0124,0x0006,-2, 1,0x0002,ar36,       
0,0,0,0,0,0)
+  XTREG( 38,152,32, 4, 4,0x0125,0x0006,-2, 1,0x0002,ar37,       
0,0,0,0,0,0)
+  XTREG( 39,156,32, 4, 4,0x0126,0x0006,-2, 1,0x0002,ar38,       
0,0,0,0,0,0)
+  XTREG( 40,160,32, 4, 4,0x0127,0x0006,-2, 1,0x0002,ar39,       
0,0,0,0,0,0)
+  XTREG( 41,164,32, 4, 4,0x0128,0x0006,-2, 1,0x0002,ar40,       
0,0,0,0,0,0)
+  XTREG( 42,168,32, 4, 4,0x0129,0x0006,-2, 1,0x0002,ar41,       
0,0,0,0,0,0)
+  XTREG( 43,172,32, 4, 4,0x012a,0x0006,-2, 1,0x0002,ar42,       
0,0,0,0,0,0)
+  XTREG( 44,176,32, 4, 4,0x012b,0x0006,-2, 1,0x0002,ar43,       
0,0,0,0,0,0)
+  XTREG( 45,180,32, 4, 4,0x012c,0x0006,-2, 1,0x0002,ar44,       
0,0,0,0,0,0)
+  XTREG( 46,184,32, 4, 4,0x012d,0x0006,-2, 1,0x0002,ar45,       
0,0,0,0,0,0)
+  XTREG( 47,188,32, 4, 4,0x012e,0x0006,-2, 1,0x0002,ar46,       
0,0,0,0,0,0)
+  XTREG( 48,192,32, 4, 4,0x012f,0x0006,-2, 1,0x0002,ar47,       
0,0,0,0,0,0)
+  XTREG( 49,196,32, 4, 4,0x0130,0x0006,-2, 1,0x0002,ar48,       
0,0,0,0,0,0)
+  XTREG( 50,200,32, 4, 4,0x0131,0x0006,-2, 1,0x0002,ar49,       
0,0,0,0,0,0)
+  XTREG( 51,204,32, 4, 4,0x0132,0x0006,-2, 1,0x0002,ar50,       
0,0,0,0,0,0)
+  XTREG( 52,208,32, 4, 4,0x0133,0x0006,-2, 1,0x0002,ar51,       
0,0,0,0,0,0)
+  XTREG( 53,212,32, 4, 4,0x0134,0x0006,-2, 1,0x0002,ar52,       
0,0,0,0,0,0)
+  XTREG( 54,216,32, 4, 4,0x0135,0x0006,-2, 1,0x0002,ar53,       
0,0,0,0,0,0)
+  XTREG( 55,220,32, 4, 4,0x0136,0x0006,-2, 1,0x0002,ar54,       
0,0,0,0,0,0)
+  XTREG( 56,224,32, 4, 4,0x0137,0x0006,-2, 1,0x0002,ar55,       
0,0,0,0,0,0)
+  XTREG( 57,228,32, 4, 4,0x0138,0x0006,-2, 1,0x0002,ar56,       
0,0,0,0,0,0)
+  XTREG( 58,232,32, 4, 4,0x0139,0x0006,-2, 1,0x0002,ar57,       
0,0,0,0,0,0)
+  XTREG( 59,236,32, 4, 4,0x013a,0x0006,-2, 1,0x0002,ar58,       
0,0,0,0,0,0)
+  XTREG( 60,240,32, 4, 4,0x013b,0x0006,-2, 1,0x0002,ar59,       
0,0,0,0,0,0)
+  XTREG( 61,244,32, 4, 4,0x013c,0x0006,-2, 1,0x0002,ar60,       
0,0,0,0,0,0)
+  XTREG( 62,248,32, 4, 4,0x013d,0x0006,-2, 1,0x0002,ar61,       
0,0,0,0,0,0)
+  XTREG( 63,252,32, 4, 4,0x013e,0x0006,-2, 1,0x0002,ar62,       
0,0,0,0,0,0)
+  XTREG( 64,256,32, 4, 4,0x013f,0x0006,-2, 1,0x0002,ar63,       
0,0,0,0,0,0)
+  XTREG( 65,260,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg,       
0,0,0,0,0,0)
+  XTREG( 66,264,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend,       
0,0,0,0,0,0)
+  XTREG( 67,268,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount,     
0,0,0,0,0,0)
+  XTREG( 68,272, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar,        
0,0,0,0,0,0)
+  XTREG( 69,276, 4, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 
0,0,0,0,0,0)
+  XTREG( 70,280,16, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart,
0,0,0,0,0,0)
+  XTREG( 71,284,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0,  
0,0,0,0,0,0)
+  XTREG( 72,288,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1,  
0,0,0,0,0,0)
+  XTREG( 73,292,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps,         
0,0,0,0,0,0)
+  XTREG( 74,296,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr,  
0,0,0,0,0,0)
+  XTREG( 75,300,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br,         
0,0,0,0,0,0)
+  XTREG( 76,304,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1,  
0,0,0,0,0,0)
+  XTREG( 77,308,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo,      
0,0,0,0,0,0)
+  XTREG( 78,312, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi,      
0,0,0,0,0,0)
+  XTREG( 79,316,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0,         
0,0,0,0,0,0)
+  XTREG( 80,320,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1,         
0,0,0,0,0,0)
+  XTREG( 81,324,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2,         
0,0,0,0,0,0)
+  XTREG( 82,328,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3,         
0,0,0,0,0,0)
+  XTREG( 83,332, 8, 4, 4,0x030c,0x000e,-1, 3,0x0210,gpio_out,   
0,0,0,0,0,0)
+  XTREG( 84,336,32, 4, 4,0x0030,0x0006, 0, 4,0x0401,f0,
+            "03:03:44:00","03:03:04:00",0,0,0,0)
+  XTREG( 85,340,32, 4, 4,0x0031,0x0006, 0, 4,0x0401,f1,
+            "03:13:44:00","03:13:04:00",0,0,0,0)
+  XTREG( 86,344,32, 4, 4,0x0032,0x0006, 0, 4,0x0401,f2,
+            "03:23:44:00","03:23:04:00",0,0,0,0)
+  XTREG( 87,348,32, 4, 4,0x0033,0x0006, 0, 4,0x0401,f3,
+            "03:33:44:00","03:33:04:00",0,0,0,0)
+  XTREG( 88,352,32, 4, 4,0x0034,0x0006, 0, 4,0x0401,f4,
+            "03:43:44:00","03:43:04:00",0,0,0,0)
+  XTREG( 89,356,32, 4, 4,0x0035,0x0006, 0, 4,0x0401,f5,
+            "03:53:44:00","03:53:04:00",0,0,0,0)
+  XTREG( 90,360,32, 4, 4,0x0036,0x0006, 0, 4,0x0401,f6,
+            "03:63:44:00","03:63:04:00",0,0,0,0)
+  XTREG( 91,364,32, 4, 4,0x0037,0x0006, 0, 4,0x0401,f7,
+            "03:73:44:00","03:73:04:00",0,0,0,0)
+  XTREG( 92,368,32, 4, 4,0x0038,0x0006, 0, 4,0x0401,f8,
+            "03:83:44:00","03:83:04:00",0,0,0,0)
+  XTREG( 93,372,32, 4, 4,0x0039,0x0006, 0, 4,0x0401,f9,
+            "03:93:44:00","03:93:04:00",0,0,0,0)
+  XTREG( 94,376,32, 4, 4,0x003a,0x0006, 0, 4,0x0401,f10,
+            "03:a3:44:00","03:a3:04:00",0,0,0,0)
+  XTREG( 95,380,32, 4, 4,0x003b,0x0006, 0, 4,0x0401,f11,
+            "03:b3:44:00","03:b3:04:00",0,0,0,0)
+  XTREG( 96,384,32, 4, 4,0x003c,0x0006, 0, 4,0x0401,f12,
+            "03:c3:44:00","03:c3:04:00",0,0,0,0)
+  XTREG( 97,388,32, 4, 4,0x003d,0x0006, 0, 4,0x0401,f13,
+            "03:d3:44:00","03:d3:04:00",0,0,0,0)
+  XTREG( 98,392,32, 4, 4,0x003e,0x0006, 0, 4,0x0401,f14,
+            "03:e3:44:00","03:e3:04:00",0,0,0,0)
+  XTREG( 99,396,32, 4, 4,0x003f,0x0006, 0, 4,0x0401,f15,
+            "03:f3:44:00","03:f3:04:00",0,0,0,0)
+  XTREG(100,400,32, 4, 4,0x03e8,0x0006, 0, 3,0x0100,fcr,        
0,0,0,0,0,0)
+  XTREG(101,404,32, 4, 4,0x03e9,0x0006, 0, 3,0x0100,fsr,        
0,0,0,0,0,0)
+  XTREG(102,408,32, 4, 4,0x0300,0x0006, 3, 3,0x0200,accx_0,     
0,0,0,0,0,0)
+  XTREG(103,412, 8, 4, 4,0x0301,0x0006, 3, 3,0x0200,accx_1,     
0,0,0,0,0,0)
+  XTREG(104,416,32, 4, 4,0x0302,0x0006, 3, 3,0x0200,qacc_h_0,   
0,0,0,0,0,0)
+  XTREG(105,420,32, 4, 4,0x0303,0x0006, 3, 3,0x0200,qacc_h_1,   
0,0,0,0,0,0)
+  XTREG(106,424,32, 4, 4,0x0304,0x0006, 3, 3,0x0200,qacc_h_2,   
0,0,0,0,0,0)
+  XTREG(107,428,32, 4, 4,0x0305,0x0006, 3, 3,0x0200,qacc_h_3,   
0,0,0,0,0,0)
+  XTREG(108,432,32, 4, 4,0x0306,0x0006, 3, 3,0x0200,qacc_h_4,   
0,0,0,0,0,0)
+  XTREG(109,436,32, 4, 4,0x0307,0x0006, 3, 3,0x0200,qacc_l_0,   
0,0,0,0,0,0)
+  XTREG(110,440,32, 4, 4,0x0308,0x0006, 3, 3,0x0200,qacc_l_1,   
0,0,0,0,0,0)
+  XTREG(111,444,32, 4, 4,0x0309,0x0006, 3, 3,0x0200,qacc_l_2,   
0,0,0,0,0,0)
+  XTREG(112,448,32, 4, 4,0x030a,0x0006, 3, 3,0x0200,qacc_l_3,   
0,0,0,0,0,0)
+  XTREG(113,452,32, 4, 4,0x030b,0x0006, 3, 3,0x0200,qacc_l_4,   
0,0,0,0,0,0)
+  XTREG(114,456, 4, 4, 4,0x030d,0x0006, 3, 3,0x0210,sar_byte,   
0,0,0,0,0,0)
+  XTREG(115,460, 4, 4, 4,0x030e,0x0006, 3,
3,0x0210,fft_bit_width,0,0,0,0,0,0)
+  XTREG(116,464,32, 4, 4,0x030f,0x0006, 3, 3,0x0200,ua_state_0, 
0,0,0,0,0,0)
+  XTREG(117,468,32, 4, 4,0x0310,0x0006, 3, 3,0x0200,ua_state_1, 
0,0,0,0,0,0)
+  XTREG(118,472,32, 4, 4,0x0311,0x0006, 3, 3,0x0200,ua_state_2, 
0,0,0,0,0,0)
+  XTREG(119,476,32, 4, 4,0x0312,0x0006, 3, 3,0x0200,ua_state_3, 
0,0,0,0,0,0)
+  XTREG(120,480,128,16,16,0x1008,0x0006, 3, 4,0x0201,q0,
+            "03:44:60:cd","03:44:20:cd",0,0,0,0)
+  XTREG(121,496,128,16,16,0x1009,0x0006, 3, 4,0x0201,q1,
+            "03:44:e0:cd","03:44:a0:cd",0,0,0,0)
+  XTREG(122,512,128,16,16,0x100a,0x0006, 3, 4,0x0201,q2,
+            "03:44:60:dd","03:44:20:dd",0,0,0,0)
+  XTREG(123,528,128,16,16,0x100b,0x0006, 3, 4,0x0201,q3,
+            "03:44:e0:dd","03:44:a0:dd",0,0,0,0)
+  XTREG(124,544,128,16,16,0x100c,0x0006, 3, 4,0x0201,q4,
+            "03:44:60:ed","03:44:20:ed",0,0,0,0)
+  XTREG(125,560,128,16,16,0x100d,0x0006, 3, 4,0x0201,q5,
+            "03:44:e0:ed","03:44:a0:ed",0,0,0,0)
+  XTREG(126,576,128,16,16,0x100e,0x0006, 3, 4,0x0201,q6,
+            "03:44:60:fd","03:44:20:fd",0,0,0,0)
+  XTREG(127,592,128,16,16,0x100f,0x0006, 3, 4,0x0201,q7,
+            "03:44:e0:fd","03:44:a0:fd",0,0,0,0)
+  XTREG(128,608,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid,       
0,0,0,0,0,0)
+  XTREG(129,612, 2, 4, 4,0x0260,0x0007,-2,
2,0x1000,ibreakenable,0,0,0,0,0,0)
+  XTREG(130,616, 1, 4, 4,0x0261,0x0007,-2, 2,0x1000,memctl,     
0,0,0,0,0,0)
+  XTREG(131,620, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl,    
0,0,0,0,0,0)
+  XTREG(132,624,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr,        
0,0,0,0,0,0)
+  XTREG(133,628,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0,   
0,0,0,0,0,0)
+  XTREG(134,632,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1,   
0,0,0,0,0,0)
+  XTREG(135,636,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0,   
0,0,0,0,0,0)
+  XTREG(136,640,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1,   
0,0,0,0,0,0)
+  XTREG(137,644,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0,   
0,0,0,0,0,0)
+  XTREG(138,648,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1,   
0,0,0,0,0,0)
+  XTREG(139,652,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1,       
0,0,0,0,0,0)
+  XTREG(140,656,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2,       
0,0,0,0,0,0)
+  XTREG(141,660,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3,       
0,0,0,0,0,0)
+  XTREG(142,664,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4,       
0,0,0,0,0,0)
+  XTREG(143,668,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5,       
0,0,0,0,0,0)
+  XTREG(144,672,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6,       
0,0,0,0,0,0)
+  XTREG(145,676,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7,       
0,0,0,0,0,0)
+  XTREG(146,680,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc,       
0,0,0,0,0,0)
+  XTREG(147,684,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2,       
0,0,0,0,0,0)
+  XTREG(148,688,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3,       
0,0,0,0,0,0)
+  XTREG(149,692,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4,       
0,0,0,0,0,0)
+  XTREG(150,696,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5,       
0,0,0,0,0,0)
+  XTREG(151,700,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6,       
0,0,0,0,0,0)
+  XTREG(152,704,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7,       
0,0,0,0,0,0)
+  XTREG(153,708,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1,   
0,0,0,0,0,0)
+  XTREG(154,712,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2,   
0,0,0,0,0,0)
+  XTREG(155,716,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3,   
0,0,0,0,0,0)
+  XTREG(156,720,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4,   
0,0,0,0,0,0)
+  XTREG(157,724,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5,   
0,0,0,0,0,0)
+  XTREG(158,728,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6,   
0,0,0,0,0,0)
+  XTREG(159,732,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7,   
0,0,0,0,0,0)
+  XTREG(160,736, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable,   
0,0,0,0,0,0)
+  XTREG(161,740,32, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt,  
0,0,0,0,0,0)
+  XTREG(162,744,32, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset,     
0,0,0,0,0,0)
+  XTREG(163,748,32, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear,   
0,0,0,0,0,0)
+  XTREG(164,752,32, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable,  
0,0,0,0,0,0)
+  XTREG(165,756,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase,    
0,0,0,0,0,0)
+  XTREG(166,760, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause,   
0,0,0,0,0,0)
+  XTREG(167,764,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 
0,0,0,0,0,0)
+  XTREG(168,768,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount,     
0,0,0,0,0,0)
+  XTREG(169,772,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid,       
0,0,0,0,0,0)
+  XTREG(170,776,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount,     
0,0,0,0,0,0)
+  XTREG(171,780, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel,
0,0,0,0,0,0)
+  XTREG(172,784,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr,   
0,0,0,0,0,0)
+  XTREG(173,788,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0,  
0,0,0,0,0,0)
+  XTREG(174,792,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1,  
0,0,0,0,0,0)
+  XTREG(175,796,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2,  
0,0,0,0,0,0)
+  XTREG(176,800,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0,      
0,0,0,0,0,0)
+  XTREG(177,804,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1,      
0,0,0,0,0,0)
+  XTREG(178,808,32, 4, 4,0x02f6,0x0007,-2, 2,0x1000,misc2,      
0,0,0,0,0,0)
+  XTREG(179,812,32, 4, 4,0x02f7,0x0007,-2, 2,0x1000,misc3,      
0,0,0,0,0,0)
+  XTREG(180,816,32, 4, 4,0x2028,0x000f,-2, 4,0x0101,pwrctl,
+           
"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:20:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:0c:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(181,820,32, 4, 4,0x2029,0x000f,-2, 4,0x0101,pwrstat,
+           
"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:24:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:0c:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(182,824, 1, 4, 4,0x202a,0x000f,-2, 4,0x0101,eristat,
+           
"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:28:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:0c:03:60:55:11:03:52:c5:28:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(183,828,32, 4, 4,0x202b,0x000f,-2, 4,0x0101,cs_itctrl,
+           
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:d5:03:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:0f:03:60:55:11:03:52:d5:03:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(184,832,16, 4, 4,0x202c,0x000f,-2, 4,0x0101,cs_claimset,
+           
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:0
4:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:6
4:02:03:52:a4:0f:03:60:55:11:03:52:c5:a0:03:52:d5:04:03:62:24:00:03:60:
75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+  XTREG(185,836,16, 4, 4,0x202d,0x000f,-2, 4,0x0101,cs_claimclr,
+           
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:0
4:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:6
4:02:03:52:a4:0f:03:60:55:11:03:52:c5:a4:03:52:d5:04:03:62:24:00:03:60:
75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+  XTREG(186,840,32, 4, 4,0x202e,0x000d,-2, 4,0x0101,cs_lockaccess,
+           
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:0
4:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:6
4:02:03:52:a4:0f:03:60:55:11:03:52:c5:b0:03:52:d5:04:03:62:24:00:03:60:
75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+  XTREG(187,844,32, 4, 4,0x202f,0x000b,-2, 4,0x0101,cs_lockstatus,
+           
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:0
4:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:6
4:02:03:52:a4:0f:03:60:55:11:03:52:c5:b4:03:52:d5:04:03:62:24:00:03:60:
75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+  XTREG(188,848, 1, 4, 4,0x2030,0x000b,-2, 4,0x0101,cs_authstatus,
+           
"03:52:64:01:03:62:64:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:0
4:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:6
4:02:03:52:a4:0f:03:60:55:11:03:52:c5:b8:03:52:d5:04:03:62:24:00:03:60:
75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+  XTREG(189,852,32, 4, 4,0x203f,0x000f,-2, 4,0x0101,fault_info,
+           
"03:52:64:01:03:62:64:02:03:52:a4:0c:03:60:55:11:03:52:c5:30:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:0c:03:60:55:11:03:52:c5:30:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(190,856,32, 4, 4,0x2040,0x0003,-2, 4,0x0101,trax_id,
+           
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:60:65:40:03:62:64:0
0:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:00:03:60:5
5:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+  XTREG(191,860,32, 4, 4,0x2041,0x000f,-2, 4,0x0101,trax_control,
+           
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:04:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:00:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(192,864,32, 4, 4,0x2042,0x000b,-2, 4,0x0101,trax_status,
+           
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:08:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:00:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(193,868,32, 4, 4,0x2043,0x000f,-2, 4,0x0101,trax_data,
+           
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:0c:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:00:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(194,872,32, 4, 4,0x2044,0x000f,-2, 4,0x0101,trax_address,
+           
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:10:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:00:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(195,876,32, 4, 4,0x2045,0x000f,-2, 4,0x0101,trax_pctrigger,
+           
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:14:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:00:03:60:55:11:03:52:c5:14:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(196,880,32, 4, 4,0x2046,0x000f,-2, 4,0x0101,trax_pcmatch,
+           
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:18:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:00:03:60:55:11:03:52:c5:18:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(197,884,32, 4, 4,0x2047,0x000f,-2, 4,0x0101,trax_delay,
+           
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:1c:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:00:03:60:55:11:03:52:c5:1c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(198,888,32, 4, 4,0x2048,0x000f,-2, 4,0x0101,trax_memstart,
+           
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:20:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:00:03:60:55:11:03:52:c5:20:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(199,892,32, 4, 4,0x2049,0x000f,-2, 4,0x0101,trax_memend,
+           
"03:52:64:01:03:62:64:02:03:52:a4:00:03:60:55:11:03:52:c5:24:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:00:03:60:55:11:03:52:c5:24:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(200,896,32, 4, 4,0x2057,0x000f,-2, 4,0x0101,pmg,
+           
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:60:65:40:03:62:64:0
0:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:04:03:60:5
5:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+  XTREG(201,900,32, 4, 4,0x2058,0x000f,-2, 4,0x0101,pmpc,
+           
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:04:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:04:03:60:55:11:03:52:c5:04:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(202,904,32, 4, 4,0x2059,0x000f,-2, 4,0x0101,pm0,
+           
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:0
1:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:6
4:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:
75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+  XTREG(203,908,32, 4, 4,0x205a,0x000f,-2, 4,0x0101,pm1,
+           
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:0
1:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:6
4:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:01:03:62:24:00:03:60:
75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+  XTREG(204,912,32, 4, 4,0x205b,0x000f,-2, 4,0x0101,pmctrl0,
+           
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(205,916,32, 4, 4,0x205c,0x000f,-2, 4,0x0101,pmctrl1,
+           
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:d5:01:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:04:03:60:55:11:03:52:d5:01:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(206,920,32, 4, 4,0x205d,0x000f,-2, 4,0x0101,pmstat0,
+           
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:0
2:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:6
4:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:
75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+  XTREG(207,924,32, 4, 4,0x205e,0x000f,-2, 4,0x0101,pmstat1,
+           
"03:52:64:01:03:62:64:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:0
2:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:6
4:02:03:52:a4:04:03:60:55:11:03:52:c5:80:03:52:d5:02:03:62:24:00:03:60:
75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+  XTREG(208,928,32, 4, 4,0x205f,0x0003,-2, 4,0x0101,ocdid,
+           
"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:60:65:40:03:62:64:0
0:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a4:08:03:60:5
5:11:03:62:24:00:03:60:75:40:03:52:24:01:03:62:24:02",0,0,0,0)
+  XTREG(209,932,32, 4, 4,0x2060,0x000f,-2, 4,0x0101,ocd_dcrclr,
+           
"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:08:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:08:03:60:55:11:03:52:c5:08:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(210,936,32, 4, 4,0x2061,0x000f,-2, 4,0x0101,ocd_dcrset,
+           
"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:0c:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:08:03:60:55:11:03:52:c5:0c:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(211,940,32, 4, 4,0x2062,0x000f,-2, 4,0x0101,ocd_dsr,
+           
"03:52:64:01:03:62:64:02:03:52:a4:08:03:60:55:11:03:52:c5:10:03:60:65:4
0:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:02:03:52:a
4:08:03:60:55:11:03:52:c5:10:03:62:24:00:03:60:75:40:03:52:24:01:03:62:
24:02",0,0,0,0)
+  XTREG(212,944,32, 4, 4,0x0000,0x0006,-2, 8,0x2100,a0,         
0,0,0,0,0,0)
+  XTREG(213,948,32, 4, 4,0x0001,0x0006,-2, 8,0x2100,a1,         
0,0,0,0,0,0)
+  XTREG(214,952,32, 4, 4,0x0002,0x0006,-2, 8,0x2100,a2,         
0,0,0,0,0,0)
+  XTREG(215,956,32, 4, 4,0x0003,0x0006,-2, 8,0x2100,a3,         
0,0,0,0,0,0)
+  XTREG(216,960,32, 4, 4,0x0004,0x0006,-2, 8,0x2100,a4,         
0,0,0,0,0,0)
+  XTREG(217,964,32, 4, 4,0x0005,0x0006,-2, 8,0x2100,a5,         
0,0,0,0,0,0)
+  XTREG(218,968,32, 4, 4,0x0006,0x0006,-2, 8,0x2100,a6,         
0,0,0,0,0,0)
+  XTREG(219,972,32, 4, 4,0x0007,0x0006,-2, 8,0x2100,a7,         
0,0,0,0,0,0)
+  XTREG(220,976,32, 4, 4,0x0008,0x0006,-2, 8,0x2100,a8,         
0,0,0,0,0,0)
+  XTREG(221,980,32, 4, 4,0x0009,0x0006,-2, 8,0x2100,a9,         
0,0,0,0,0,0)
+  XTREG(222,984,32, 4, 4,0x000a,0x0006,-2, 8,0x2100,a10,        
0,0,0,0,0,0)
+  XTREG(223,988,32, 4, 4,0x000b,0x0006,-2, 8,0x2100,a11,        
0,0,0,0,0,0)
+  XTREG(224,992,32, 4, 4,0x000c,0x0006,-2, 8,0x2100,a12,        
0,0,0,0,0,0)
+  XTREG(225,996,32, 4, 4,0x000d,0x0006,-2, 8,0x2100,a13,        
0,0,0,0,0,0)
+  XTREG(226,1000,32, 4, 4,0x000e,0x0006,-2, 8,0x2100,a14,        
0,0,0,0,0,0)
+  XTREG(227,1004,32, 4, 4,0x000f,0x0006,-2, 8,0x2100,a15,        
0,0,0,0,0,0)
+  XTREG(228,1008, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
+            0,0,&xtensa_mask0,0,0,0)
+  XTREG(229,1009, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
+            0,0,&xtensa_mask1,0,0,0)
+  XTREG(230,1010, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
+            0,0,&xtensa_mask2,0,0,0)
+  XTREG(231,1011, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
+            0,0,&xtensa_mask3,0,0,0)
+  XTREG(232,1012, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
+            0,0,&xtensa_mask4,0,0,0)
+  XTREG(233,1013, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
+            0,0,&xtensa_mask5,0,0,0)
+  XTREG(234,1014, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
+            0,0,&xtensa_mask6,0,0,0)
+  XTREG(235,1015, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
+            0,0,&xtensa_mask7,0,0,0)
+  XTREG(236,1016, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
+            0,0,&xtensa_mask8,0,0,0)
+  XTREG(237,1017, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
+            0,0,&xtensa_mask9,0,0,0)
+  XTREG(238,1018, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
+            0,0,&xtensa_mask10,0,0,0)
+  XTREG(239,1019, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
+            0,0,&xtensa_mask11,0,0,0)
+  XTREG(240,1020, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
+            0,0,&xtensa_mask12,0,0,0)
+  XTREG(241,1021, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
+            0,0,&xtensa_mask13,0,0,0)
+  XTREG(242,1022, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
+            0,0,&xtensa_mask14,0,0,0)
+  XTREG(243,1023, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
+            0,0,&xtensa_mask15,0,0,0)
+  XTREG(244,1024, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
+            0,0,&xtensa_mask16,0,0,0)
+  XTREG(245,1028, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
+            0,0,&xtensa_mask17,0,0,0)
+  XTREG(246,1032, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
+            0,0,&xtensa_mask18,0,0,0)
+  XTREG(247,1036, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm,
+            0,0,&xtensa_mask19,0,0,0)
+  XTREG(248,1040, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc,
+            0,0,&xtensa_mask20,0,0,0)
+  XTREG(249,1044, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb,
+            0,0,&xtensa_mask21,0,0,0)
+  XTREG(250,1048,40, 8, 4,0x200e,0x0006,-2, 6,0x1010,acc,
+            0,0,&xtensa_mask22,0,0,0)
+  XTREG(251,1056, 4, 4, 4,0x2013,0x0006,-2, 6,0x1010,dbnum,
+            0,0,&xtensa_mask23,0,0,0)
+  XTREG(252,1060, 2, 4, 4,0x2015,0x0006, 0, 5,0x1010,roundmode,
+            0,0,&xtensa_mask24,0,0,0)
+  XTREG(253,1064, 1, 4, 4,0x2016,0x0006, 0, 5,0x1010,invalidenable,
+            0,0,&xtensa_mask25,0,0,0)
+  XTREG(254,1068, 1, 4, 4,0x2017,0x0006, 0, 5,0x1010,divzeroenable,
+            0,0,&xtensa_mask26,0,0,0)
+  XTREG(255,1072, 1, 4, 4,0x2018,0x0006, 0, 5,0x1010,overflowenable,
+            0,0,&xtensa_mask27,0,0,0)
+  XTREG(256,1076, 1, 4, 4,0x2019,0x0006, 0, 5,0x1010,underflowenable,
+            0,0,&xtensa_mask28,0,0,0)
+  XTREG(257,1080, 1, 4, 4,0x201a,0x0006, 0, 5,0x1010,inexactenable,
+            0,0,&xtensa_mask29,0,0,0)
+  XTREG(258,1084, 1, 4, 4,0x201b,0x0006, 0, 5,0x1010,invalidflag,
+            0,0,&xtensa_mask30,0,0,0)
+  XTREG(259,1088, 1, 4, 4,0x201c,0x0006, 0, 5,0x1010,divzeroflag,
+            0,0,&xtensa_mask31,0,0,0)
+  XTREG(260,1092, 1, 4, 4,0x201d,0x0006, 0, 5,0x1010,overflowflag,
+            0,0,&xtensa_mask32,0,0,0)
+  XTREG(261,1096, 1, 4, 4,0x201e,0x0006, 0, 5,0x1010,underflowflag,
+            0,0,&xtensa_mask33,0,0,0)
+  XTREG(262,1100, 1, 4, 4,0x201f,0x0006, 0, 5,0x1010,inexactflag,
+            0,0,&xtensa_mask34,0,0,0)
+  XTREG(263,1104,20, 4, 4,0x2020,0x0006, 0, 5,0x1010,fpreserved20,
+            0,0,&xtensa_mask35,0,0,0)
+  XTREG(264,1108,20, 4, 4,0x2021,0x0006, 0, 5,0x1010,fpreserved20a,
+            0,0,&xtensa_mask36,0,0,0)
+  XTREG(265,1112, 5, 4, 4,0x2022,0x0006, 0, 5,0x1010,fpreserved5,
+            0,0,&xtensa_mask37,0,0,0)
+  XTREG(266,1116, 7, 4, 4,0x2023,0x0006, 0, 5,0x1010,fpreserved7,
+            0,0,&xtensa_mask38,0,0,0)
+  XTREG(267,1120,40, 8, 4,0x2024,0x0006, 3, 5,0x0210,accx,
+            0,0,&xtensa_mask39,0,0,0)
+  XTREG(268,1128,160,20, 4,0x2025,0x0006, 3, 5,0x0210,qacc_h,
+            0,0,&xtensa_mask40,0,0,0)
+  XTREG(269,1148,160,20, 4,0x2026,0x0006, 3, 5,0x0210,qacc_l,
+            0,0,&xtensa_mask41,0,0,0)
+  XTREG_END
+};
+
+xtensa_gdbarch_tdep xtensa_tdep_esp32s3 (rmap);
diff --git a/gdb/xtensa-tdep.c b/gdb/xtensa-tdep.c
index b6558838e44..5a884cc1175 100644
--- a/gdb/xtensa-tdep.c
+++ b/gdb/xtensa-tdep.c
@@ -42,6 +42,7 @@
 #include "xtensa-isa.h"
 #include "xtensa-tdep.h"
 #include "xtensa-config.h"
+#include "elf/xtensa.h"
 #include <algorithm>
 
 
@@ -930,6 +931,7 @@ typedef struct xtensa_windowed_frame_cache
 #define C0_NOSTK   -1	/* to_stk value if register has not been
stored.  */
 
 extern xtensa_isa xtensa_default_isa;
+extern xtensa_isa xtensa_modules;
 
 typedef struct xtensa_c0reg
 {
@@ -3152,9 +3154,66 @@ xtensa_derive_tdep (xtensa_gdbarch_tdep *tdep)
   tdep->max_register_virtual_size = max_size;
 }
 
-/* Module "constructor" function.  */
+extern xtensa_gdbarch_tdep xtensa_tdep_default;
+extern xtensa_gdbarch_tdep xtensa_tdep_esp32;
+extern xtensa_gdbarch_tdep xtensa_tdep_esp32s2;
+extern xtensa_gdbarch_tdep xtensa_tdep_esp32s3;
+
+xtensa_gdbarch_tdep *current_tdep = &xtensa_tdep_default;
+/* Keep it synced with xtensa_isa_modules.  */
+xtensa_gdbarch_tdep *xtensa_tdeps[] =
+{
+  &xtensa_tdep_default,
+  &xtensa_tdep_esp32,
+  &xtensa_tdep_esp32s2,
+  &xtensa_tdep_esp32s2
+};
+
+static void
+apply_xtensa_info_config (bfd *abfd)
+{
+  asection *info_sec;
+  xtensa_info_entries xtensa_info;
 
-extern xtensa_gdbarch_tdep xtensa_tdep;
+  if (! abfd)
+    return;
+
+  info_sec = bfd_get_section_by_name (abfd, ".xtensa.info");
+
+  if (! info_sec)
+    return;
+
+  if (! read_xtensa_info (abfd, info_sec, &xtensa_info))
+    return;
+
+  /* Process ISA_MODULE  */
+  if (xtensa_info.isa_module < 0
+      || xtensa_info.isa_module >= xtensa_isa_modules_count)
+    {
+      warning (_("Unknown xtensa isa-module, use the default."));
+      xtensa_info.isa_module = 0;
+    }
+
+  xtensa_default_isa = NULL;
+  xtensa_modules =
xtensa_isa_modules[xtensa_info.isa_module].isa_module;
+  current_tdep = xtensa_tdeps[xtensa_info.isa_module];
+
+  if (xtensa_info.isa_module > 0)
+    {
+      current_tdep->num_aregs =
xtensa_regfile_num_entries(xtensa_modules, 0);
+    }
+
+  /* Process ABI  */
+  current_tdep->call_abi = (xtensa_info.abi == XTHAL_ABI_CALL0
+                          ? CallAbiCall0Only : CallAbiDefault);
+  current_tdep->isa_use_windowed_registers = xtensa_info.abi !=
+      XTHAL_ABI_CALL0;
+
+  /* Process USE_ABSOLUTE_LITERALS  */
+  current_tdep->isa_use_ext_l32r = xtensa_info.use_absolute_literals;
+}
+
+/* Module "constructor" function.  */
 
 static struct gdbarch *
 xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list
*arches)
@@ -3163,13 +3222,12 @@ xtensa_gdbarch_init (struct gdbarch_info info,
struct gdbarch_list *arches)
 
   DEBUGTRACE ("gdbarch_init()\n");
 
+  apply_xtensa_info_config(info.abfd);
+
   if (!xtensa_default_isa)
     xtensa_default_isa = xtensa_isa_init (0, 0);
 
-  /* We have to set the byte order before we call gdbarch_alloc.  */
-  info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG :
BFD_ENDIAN_LITTLE;
-
-  xtensa_gdbarch_tdep *tdep = &xtensa_tdep;
+  xtensa_gdbarch_tdep *tdep = current_tdep;
   gdbarch = gdbarch_alloc (&info, tdep);
   xtensa_derive_tdep (tdep);
 
diff --git a/gdb/xtensa-tdep.h b/gdb/xtensa-tdep.h
index 1840ef98b49..bdd06bc28fc 100644
--- a/gdb/xtensa-tdep.h
+++ b/gdb/xtensa-tdep.h
@@ -126,7 +126,7 @@ typedef struct
   const char *store;		/* Instruction sequence to store
register.  */
 } xtensa_register_t;
 
-/*  For xtensa-config.c to expand to the structure above.  */
+/*  For xtensa-config-*.c to expand to the structure above.  */
 #define
XTREG(index,ofs,bsz,sz,al,tnum,flg,cp,ty,gr,name,fet,sto,mas,ct,x,y) \
        {#name, ofs, (xtensa_register_type_t) (ty), \
 	((xtensa_register_group_t) \
-- 
2.34.1


^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH 0/5] Add Xtensa ESP chips support
  2022-10-22 12:51 [PATCH 0/5] Add Xtensa ESP chips support Alexey Lapshin
                   ` (4 preceding siblings ...)
  2022-10-22 13:56 ` [PATCH 5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules Alexey Lapshin
@ 2022-10-25 19:13 ` Max Filippov
  2022-10-25 20:17   ` Alexey Lapshin
  5 siblings, 1 reply; 14+ messages in thread
From: Max Filippov @ 2022-10-25 19:13 UTC (permalink / raw)
  To: Alexey Lapshin; +Cc: binutils, Anton Maklakov, Alexey Gerenkov, Ivan Grokhotkov

Hi Alexey,

On Sat, Oct 22, 2022 at 5:51 AM Alexey Lapshin via Binutils
<binutils@sourceware.org> wrote:
>
> Since ESP chips are getting more and more popular for developers I
> would like to suggest these patches to consider to include Xtensa ESP
> chips support for binutils and gdb.
>
> The chips support was done in a not common binutils way. There are a
> few reasons for that:
> As I know, the Xtensa specific code for binutils and gdb is generated
> with tools from Tensilica Inc.
> To build binutils and gdb with other chip presets we need to override
> some related files (https://github.com/espressif/xtensa-overlays).
> To make it easy to integrate new chips I did refactor the code a bit to
> make a possibility to just copy and paste Tensilica-generated files and
> modify a few lines in a code to make it supported in binutils and gdb.
>
> Please consider these changes to merge, I believe this could be a
> pretty improvement to extend supported CPUs without using third-party
> sources patches.
>
> Alexey Lapshin (5):
>   bfd: xtensa: move common code from ld and gas
>   gas: xtensa: add endianness, loops, booleans options
>   ld: xtensa: use default LD command line options to specify endianness
>   gas: xtensa: add esp32, esp32s2, esp32s3 isa-modules options
>   gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules

I'd like to review this series but it has two technical issues:
- the patches are not in plain text format and so git am is unable to apply them
- the 4th patch of the series didn't make it through the list, I guess
it's too big

I guess the easiest way for me to review this series is if you could point
me to a public git repository with these patches. Alternatively you could
use git send-email to send the patches, split patch 4 into pieces (e.g.
one core per patch) and add me to the cc: list.

-- 
Thanks.
-- Max

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH 0/5] Add Xtensa ESP chips support
  2022-10-25 19:13 ` [PATCH 0/5] Add Xtensa ESP chips support Max Filippov
@ 2022-10-25 20:17   ` Alexey Lapshin
  2022-10-27 15:39     ` Max Filippov
  0 siblings, 1 reply; 14+ messages in thread
From: Alexey Lapshin @ 2022-10-25 20:17 UTC (permalink / raw)
  To: jcmvbkbc; +Cc: Alexey Gerenkov, Anton Maklakov, binutils, Ivan Grokhotkov

Hi Max,

Thank you for reaching out. Yes, patch 4/5 is too big and should be
split into at least 6 parts to upload here.

I uploaded changes to the github:
https://github.com/espressif/binutils-gdb/commits/feature/binutils-2_39-port-esp-chips
Regards,
Alexey


On Tue, 2022-10-25 at 12:13 -0700, Max Filippov wrote:
> [External: This email originated outside Espressif]
> 
> Hi Alexey,
> 
> On Sat, Oct 22, 2022 at 5:51 AM Alexey Lapshin via Binutils
> <binutils@sourceware.org> wrote:
> > 
> > Since ESP chips are getting more and more popular for developers I
> > would like to suggest these patches to consider to include Xtensa
> > ESP
> > chips support for binutils and gdb.
> > 
> > The chips support was done in a not common binutils way. There are
> > a
> > few reasons for that:
> > As I know, the Xtensa specific code for binutils and gdb is
> > generated
> > with tools from Tensilica Inc.
> > To build binutils and gdb with other chip presets we need to
> > override
> > some related files (https://github.com/espressif/xtensa-overlays).
> > To make it easy to integrate new chips I did refactor the code a
> > bit to
> > make a possibility to just copy and paste Tensilica-generated files
> > and
> > modify a few lines in a code to make it supported in binutils and
> > gdb.
> > 
> > Please consider these changes to merge, I believe this could be a
> > pretty improvement to extend supported CPUs without using third-
> > party
> > sources patches.
> > 
> > Alexey Lapshin (5):
> >   bfd: xtensa: move common code from ld and gas
> >   gas: xtensa: add endianness, loops, booleans options
> >   ld: xtensa: use default LD command line options to specify
> > endianness
> >   gas: xtensa: add esp32, esp32s2, esp32s3 isa-modules options
> >   gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules
> 
> I'd like to review this series but it has two technical issues:
> - the patches are not in plain text format and so git am is unable to
> apply them
> - the 4th patch of the series didn't make it through the list, I
> guess
> it's too big
> 
> I guess the easiest way for me to review this series is if you could
> point
> me to a public git repository with these patches. Alternatively you
> could
> use git send-email to send the patches, split patch 4 into pieces
> (e.g.
> one core per patch) and add me to the cc: list.
> 
> --
> Thanks.
> -- Max


^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH 0/5] Add Xtensa ESP chips support
  2022-10-25 20:17   ` Alexey Lapshin
@ 2022-10-27 15:39     ` Max Filippov
  2022-10-27 19:39       ` Alexey Lapshin
  0 siblings, 1 reply; 14+ messages in thread
From: Max Filippov @ 2022-10-27 15:39 UTC (permalink / raw)
  To: Alexey Lapshin; +Cc: Alexey Gerenkov, Anton Maklakov, binutils, Ivan Grokhotkov

Hi Alexey,

On Tue, Oct 25, 2022 at 1:17 PM Alexey Lapshin
<alexey.lapshin@espressif.com> wrote:
> I uploaded changes to the github:
> https://github.com/espressif/binutils-gdb/commits/feature/binutils-2_39-port-esp-chips

Thank you. I have taken a look and have run a couple tests.
It is nice to see an effort to improve the current state of the xtensa
toolchain, however this series has a number of issues that I consider
important and think that they must be addressed.

First issue is that these changes break existing workflows for the
xtensa toolchain customization. I believe that it is possible to add
support for multiple xtensa cores without breaking the current
configuration mechanism.

Second issue is that these changes are not internally coherent.
For example I would expect that choosing a core that we're
assembling for would result in production of an object file with
correct endianness for the chosen core, but this is not the case:
xtensa-elf-as --isa-module=esp32 will produce an object file
marked as elf32-xtensa-be. New switches that control endianness
only do partial job, affecting literals and data, but not instructions
(which they cannot do by design).
There's an --isa-module switch for the assembler, but nothing
matching it for the objdump. To experience the issue try to
assemble the 'salt' instruction (available in esp32s3) and get it
back from the disassembler. Recording core ID in the .xtensa.info
section is a clever idea that could potentially help in this situation,
but 1) AFAICT it is not used for that purpose now and 2) what's
the option for disassembling code that lacks the .xtensa.info?
Also, recording the sequential number in this section doesn't look
like the right choice to me.
The switches --[no-]booleans and --[no-]loops are not really
documented and AFAICT they do nothing at this point. They don't
control which code is accepted or generated, they only affect
available relaxation transformations, but I don't see any
transformations that depend on the presence of the boolean
option or zero overhead loops.
There are remaining core-specific macros, like XCHAL_HAVE_BE
in the code that is only compiled once, which means that this code
gets definitions for these macros from the default configuration,
leaving the reader of this code with the question "how is it
supposed to work for cores that define these macros differently"?

Third issue is related to the second, this series adds support for
the new cores meaning that other interested parties could follow
suit, but since it's done incoherently it does not set the right
example that could actually be followed.

I still think that the series that I posted back in 2017 here
  https://sourceware.org/pipermail/binutils/2017-May/098159.html
was a step in the right direction, providing basis for dynamic
configuration, yet not excluding the opportunity to have core
support built into the toolchain. It's a shame that I couldn't
complete it back then, I guess I should try to do it this time.

-- 
Thanks.
-- Max

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH 0/5] Add Xtensa ESP chips support
  2022-10-27 15:39     ` Max Filippov
@ 2022-10-27 19:39       ` Alexey Lapshin
  2022-10-28 15:48         ` Max Filippov
  0 siblings, 1 reply; 14+ messages in thread
From: Alexey Lapshin @ 2022-10-27 19:39 UTC (permalink / raw)
  To: jcmvbkbc; +Cc: Alexey Gerenkov, Anton Maklakov, binutils, Ivan Grokhotkov

Thank you for the review 

> I still think that the series that I posted back in 2017 here
>   https://sourceware.org/pipermail/binutils/2017-May/098159.html

FYI we already use your approach in GDB (with some improvements and
modifications).
Only the difference is that we pass chip name over command-line option,
not through ENV variable.
https://github.com/espressif/esp-xtensaconfig-lib
Line in GDB to use it:
https://github.com/espressif/binutils-gdb/commit/add3053905e646af67692ae1a67fd5ee76e84723#diff-a4fc3be128b23679672d7d28616e553d81c0631f38e9205774721678bbabfcb7R102
The main disadvantage of this is that we need to have duplicated source
files from binutils inside this library. And be careful when upgrading
to another binutils version because some structure declarations could
change.


> First issue is that these changes break existing workflows for the
> xtensa toolchain customization. I believe that it is possible to add
> support for multiple xtensa cores without breaking the current
> configuration mechanism.

Could you elaborate on this? I'm very new here and do not fully
understand the existing workflow and what was broken.


> xtensa-elf-as --isa-module=esp32 will produce an object file
> marked as elf32-xtensa-be. New switches that control endianness
> only do partial job, affecting literals and data, but not
> instructions
> (which they cannot do by design).

I was disappointed here too because in the default binutils
configuration we have:
#define XCHAL_HAVE_BE 1

But in xtensa-module.c:
xtensa_isa_internal xtensa_modules = {
  0 /* little-endian */, 


> what's the option for disassembling code that lacks the .xtensa.info?

Another option could be to write cpu to the elf's e_flags. The initial
code exists. Needs just to add another machines:
https://github.com/bminor/binutils-gdb/blob/1eeb0316304f2d4e2c48aa8887e28c936bfe4f4d/include/elf/xtensa.h#L104
But yes, the problem still exists with any approach for files generated
before these changes (I suppose also for yours from 2017 ). As a
workaround, it could be added command-line options for tools to force
use specified chip configuration..


What if I redo this patch with removing the most definitions from
xtensa-config.h? XCHAL_HAVE_BE, XCHAL_HAVE_ABS, XCHAL_HAVE_ADDX, ..., 
and most all other hardcoded definitions could be gotten from xtensa-
modules.c


On Thu, 2022-10-27 at 08:39 -0700, Max Filippov wrote:
> [External: This email originated outside Espressif]
> 
> Hi Alexey,
> 
> On Tue, Oct 25, 2022 at 1:17 PM Alexey Lapshin
> <alexey.lapshin@espressif.com> wrote:
> > I uploaded changes to the github:
> > https://github.com/espressif/binutils-gdb/commits/feature/binutils-2_39-port-esp-chips
> 
> Thank you. I have taken a look and have run a couple tests.
> It is nice to see an effort to improve the current state of the
> xtensa
> toolchain, however this series has a number of issues that I consider
> important and think that they must be addressed.
> 
> First issue is that these changes break existing workflows for the
> xtensa toolchain customization. I believe that it is possible to add
> support for multiple xtensa cores without breaking the current
> configuration mechanism.
> 
> Second issue is that these changes are not internally coherent.
> For example I would expect that choosing a core that we're
> assembling for would result in production of an object file with
> correct endianness for the chosen core, but this is not the case:
> xtensa-elf-as --isa-module=esp32 will produce an object file
> marked as elf32-xtensa-be. New switches that control endianness
> only do partial job, affecting literals and data, but not
> instructions
> (which they cannot do by design).
> There's an --isa-module switch for the assembler, but nothing
> matching it for the objdump. To experience the issue try to
> assemble the 'salt' instruction (available in esp32s3) and get it
> back from the disassembler. Recording core ID in the .xtensa.info
> section is a clever idea that could potentially help in this
> situation,
> but 1) AFAICT it is not used for that purpose now and 2) what's
> the option for disassembling code that lacks the .xtensa.info?
> Also, recording the sequential number in this section doesn't look
> like the right choice to me.
> The switches --[no-]booleans and --[no-]loops are not really
> documented and AFAICT they do nothing at this point. They don't
> control which code is accepted or generated, they only affect
> available relaxation transformations, but I don't see any
> transformations that depend on the presence of the boolean
> option or zero overhead loops.
> There are remaining core-specific macros, like XCHAL_HAVE_BE
> in the code that is only compiled once, which means that this code
> gets definitions for these macros from the default configuration,
> leaving the reader of this code with the question "how is it
> supposed to work for cores that define these macros differently"?
> 
> Third issue is related to the second, this series adds support for
> the new cores meaning that other interested parties could follow
> suit, but since it's done incoherently it does not set the right
> example that could actually be followed.
> 
> I still think that the series that I posted back in 2017 here
>   https://sourceware.org/pipermail/binutils/2017-May/098159.html
> was a step in the right direction, providing basis for dynamic
> configuration, yet not excluding the opportunity to have core
> support built into the toolchain. It's a shame that I couldn't
> complete it back then, I guess I should try to do it this time.
> 
> --
> Thanks.
> -- Max


^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH 0/5] Add Xtensa ESP chips support
  2022-10-27 19:39       ` Alexey Lapshin
@ 2022-10-28 15:48         ` Max Filippov
  2022-10-28 16:05           ` Max Filippov
  0 siblings, 1 reply; 14+ messages in thread
From: Max Filippov @ 2022-10-28 15:48 UTC (permalink / raw)
  To: Alexey Lapshin; +Cc: Alexey Gerenkov, Anton Maklakov, binutils, Ivan Grokhotkov

On Thu, Oct 27, 2022 at 12:39 PM Alexey Lapshin
<alexey.lapshin@espressif.com> wrote:
> > I still think that the series that I posted back in 2017 here
> >   https://sourceware.org/pipermail/binutils/2017-May/098159.html
>
> FYI we already use your approach in GDB (with some improvements and
> modifications).

Wow, cool. I didn't know about that.

> Only the difference is that we pass chip name over command-line option,
> not through ENV variable.

Is there any advantage to it? I know that IDF requires some environment setup
and choosing the target core anyway.

> https://github.com/espressif/esp-xtensaconfig-lib
> Line in GDB to use it:
> https://github.com/espressif/binutils-gdb/commit/add3053905e646af67692ae1a67fd5ee76e84723#diff-a4fc3be128b23679672d7d28616e553d81c0631f38e9205774721678bbabfcb7R102
> The main disadvantage of this is that we need to have duplicated source
> files from binutils inside this library.

I'm curious why? IIRC I got rid of all such dependencies in my version,
but then I could have missed something as I haven't been using it a lot.
Certainly I paid very little attention to the gdb.

> > First issue is that these changes break existing workflows for the
> > xtensa toolchain customization. I believe that it is possible to add
> > support for multiple xtensa cores without breaking the current
> > configuration mechanism.
>
> Could you elaborate on this? I'm very new here and do not fully
> understand the existing workflow and what was broken.

Sure, it's the replacement of the binutils overlay files that wouldn't
work with this change. Description is available here:
 http://wiki.linux-xtensa.org/index.php/Toolchain_Overlay_File
and overlay application is a part of toolchain build systems like
crosstool-NG:
  https://github.com/crosstool-ng/crosstool-ng/blob/crosstool-ng-1.25.0/scripts/functions#L2413
and buildroot:
  https://github.com/buildroot/buildroot/blob/2022.08/package/binutils/binutils.mk#L115

> > what's the option for disassembling code that lacks the .xtensa.info?
>
> Another option could be to write cpu to the elf's e_flags. The initial
> code exists. Needs just to add another machines:
> https://github.com/bminor/binutils-gdb/blob/1eeb0316304f2d4e2c48aa8887e28c936bfe4f4d/include/elf/xtensa.h#L104

Any kind of numbering means that there must be an authority that
will at least make sure that the numbers are unique.
I think we're much better off recording core name in the .xtensa.info
while also providing a fallback mechanism for the case this information
is missing or there's a need to override it.

I think that I need to research why Tensilica hasn't done anything
like that, neither here nor in its internal toolchain.

> What if I redo this patch with removing the most definitions from
> xtensa-config.h? XCHAL_HAVE_BE, XCHAL_HAVE_ABS, XCHAL_HAVE_ADDX, ...,
> and most all other hardcoded definitions could be gotten from xtensa-
> modules.c

That will not remove these definitions from the existing overlays. And also
there's a copy of this header in the gcc tree, which I'd like to keep in sync.
xtensa-dynconfig series was able to deal with these names by redefining
the X?HAL_* macros. I think that we first need to complete getting rid of
the macro use in preprocessor conditionals inside the toolchain source
code. And then provide these macros as compiler built-ins for the target
libraries.

-- 
Thanks.
-- Max

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH 0/5] Add Xtensa ESP chips support
  2022-10-28 15:48         ` Max Filippov
@ 2022-10-28 16:05           ` Max Filippov
  2022-10-31  6:38             ` Alexey Lapshin
  0 siblings, 1 reply; 14+ messages in thread
From: Max Filippov @ 2022-10-28 16:05 UTC (permalink / raw)
  To: Alexey Lapshin; +Cc: Alexey Gerenkov, Anton Maklakov, binutils, Ivan Grokhotkov

On Fri, Oct 28, 2022 at 8:48 AM Max Filippov <jcmvbkbc@gmail.com> wrote:
> I think that we first need to complete getting rid of
> the macro use in preprocessor conditionals inside the toolchain source

...and in other static contexts of course, like static initializers,
array sizes, etc.

-- 
Thanks.
-- Max

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH 0/5] Add Xtensa ESP chips support
  2022-10-28 16:05           ` Max Filippov
@ 2022-10-31  6:38             ` Alexey Lapshin
  2022-10-31 16:10               ` Max Filippov
  0 siblings, 1 reply; 14+ messages in thread
From: Alexey Lapshin @ 2022-10-31  6:38 UTC (permalink / raw)
  To: jcmvbkbc; +Cc: Alexey Gerenkov, Anton Maklakov, binutils, Ivan Grokhotkov

Thank you for clarification. Now I see that my approach is not really
fit to the current workflow.

I could port your patch from 2017 (with espressif's changes and
comments resolves) to the latest binutils and send it to mailing list.
If you don't mind.

Regards,
Alexey

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH 0/5] Add Xtensa ESP chips support
  2022-10-31  6:38             ` Alexey Lapshin
@ 2022-10-31 16:10               ` Max Filippov
  0 siblings, 0 replies; 14+ messages in thread
From: Max Filippov @ 2022-10-31 16:10 UTC (permalink / raw)
  To: Alexey Lapshin; +Cc: Alexey Gerenkov, Anton Maklakov, binutils, Ivan Grokhotkov

On Sun, Oct 30, 2022 at 11:38 PM Alexey Lapshin
<alexey.lapshin@espressif.com> wrote:
> I could port your patch from 2017 (with espressif's changes and
> comments resolves) to the latest binutils and send it to mailing list.
> If you don't mind.

Sure, I guess we can start with that. I also have a couple improvements in mind,
let's see if we can make something solid this time.

-- 
Thanks.
-- Max

^ permalink raw reply	[flat|nested] 14+ messages in thread

end of thread, other threads:[~2022-10-31 16:10 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-22 12:51 [PATCH 0/5] Add Xtensa ESP chips support Alexey Lapshin
2022-10-22 12:53 ` [PATCH 1/5] bfd: xtensa: move common code from ld and gas Alexey Lapshin
2022-10-22 12:55 ` [PATCH 2/5] gas: xtensa: add endianness, loops, booleans options Alexey Lapshin
2022-10-22 12:56 ` [PATCH 3/5] ld: xtensa: use default LD command line options for endianness Alexey Lapshin
2022-10-22 13:54 ` [PATCH 4/5] gas: xtensa: add esp32, esp32s2, esp32s3 isa-modules options Alexey Lapshin
2022-10-22 13:56 ` [PATCH 5/5] gdb: xtensa: add support for esp32, esp32s2, esp32s3 isa-modules Alexey Lapshin
2022-10-25 19:13 ` [PATCH 0/5] Add Xtensa ESP chips support Max Filippov
2022-10-25 20:17   ` Alexey Lapshin
2022-10-27 15:39     ` Max Filippov
2022-10-27 19:39       ` Alexey Lapshin
2022-10-28 15:48         ` Max Filippov
2022-10-28 16:05           ` Max Filippov
2022-10-31  6:38             ` Alexey Lapshin
2022-10-31 16:10               ` Max Filippov

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