* [PATCH v2 0/3] RISC-V: Prepare Privileged Architecture 1.12
@ 2021-12-24 3:22 Tsukasa OI
2021-12-24 3:22 ` [PATCH v2 1/3] RISC-V: Make testcase indentation consistent Tsukasa OI
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Tsukasa OI @ 2021-12-24 3:22 UTC (permalink / raw)
To: Tsukasa OI, Nelson Chu, Vineet Gupta; +Cc: binutils
[DIFFERENCES: V1 and V2]
Test failures on "1p12" testcases are fixed (only Patch 3 is affected).
This patchset adds minimal support for the Privileged Architecture
version 1.12.
This is preparation for my upcoming patchset to add all CSRs as defined
in recently ratified documents. Because my copyright assignment to FSF
is not complete, this patchset is intentionally designed to be
*not legally significant* (despite large patch size at first glance).
I haven't even received the assignment form but it's okay because
it's the holidays.
It also improves testcases for maintainability. Those changes are hardly
functional but can be a foundation of upcoming changes (by Vineet and me,
at least).
To quote Information for Maintainers of GNU Software
<https://www.gnu.org/prep/maintain/html_node/Legally-Significant.html>,
> A regular series of repeated changes, such as renaming a symbol, is not
> legally significant even if the symbol has to be renamed in many places.
[Patch 1/3: Make testcase indentation consistent]
When "[(SPACE)(TAB)]+" pattern (regex) should be tested in RISC-V
testcases, following 4 files have "[(x*SPACE)(TAB)]+" (x >= 2):
- gas/testsuite/gas/riscv/option-arch-01a.d
- gas/testsuite/gas/riscv/priv-reg-version-1p10.d
- gas/testsuite/gas/riscv/priv-reg-version-1p11.d
- gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
They even have different indentation. For instance, similar
"priv-reg-version-1p10.d" and "priv-reg-version-1p11.d" have different
indentation and that makes making testcases tedious (per-file adoptation
is required).
This commit makes all such instances (except 2 occurrences in
"option-arch-01a.d", which will be unaligned if I change that) to
"[(1*SPACE)(TAB)]+".
All those changes are considered non-creative.
[Patch 2/3: Unify "access all CSRs" testcases]
On some RISC-V testcases, we have to test access to all (or almost all)
CSRs. However, we have two similar but separate files exist:
- gas/testsuite/gas/riscv/priv-reg.s
- gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s
This commit moves main contents of "priv-reg.s" to "priv-reg-access-all.s"
and makes two files above include that common source file.
As a side effect, many .d files need additional "-I$srcdir/$subdir" option.
This idea is from gas/testsuite/gas/arm/cde.[ds].
Only two lines (.include directives) are considered minimally creative.
[Patch 3/3: Add Privileged Architecture version 1.12]
This commit adds minimal support (with help string and testcases) to the
Privileged Architecture version 1.12.
Unlike Vineet Gupta's patch,
1. It also adds help string
2. It also copies "1p11" testcases to "1p12"
(with non-creative version adoptation)
(cf.) Vineet Gupta's privileged architecture 1.12 patch:
<https://sourceware.org/pipermail/binutils/2021-December/118982.html>
Three lines (in total) from three files are considered minimally creative:
- bfd/cpu-riscv.c
- bfd/cpu-riscv.h
- gas/config/tc-riscv.c
From my view, only 5 lines are minimally creative and all the rest are
non-creative changes (regular series of repeated changes), hoping that
this whole patchset is *not* legally significant.
Tsukasa OI (3):
RISC-V: Make testcase indentation consistent
RISC-V: Unify "access all CSRs" testcases
RISC-V: Add Privileged Architecture version 1.12
bfd/cpu-riscv.c | 1 +
bfd/cpu-riscv.h | 1 +
gas/config/tc-riscv.c | 2 +-
gas/testsuite/gas/riscv/csr-dw-regnums.d | 2 +-
gas/testsuite/gas/riscv/option-arch-01a.d | 8 +-
gas/testsuite/gas/riscv/priv-reg-access-all.s | 292 ++++++++++
gas/testsuite/gas/riscv/priv-reg-fail-fext.d | 2 +-
.../gas/riscv/priv-reg-fail-read-only-01.d | 2 +-
.../gas/riscv/priv-reg-fail-read-only-01.s | 267 +--------
.../gas/riscv/priv-reg-fail-read-only-02.d | 2 +-
.../gas/riscv/priv-reg-fail-rv32-only.d | 2 +-
.../gas/riscv/priv-reg-fail-version-1p10.d | 2 +-
.../gas/riscv/priv-reg-fail-version-1p11.d | 2 +-
.../gas/riscv/priv-reg-fail-version-1p12.d | 11 +
.../gas/riscv/priv-reg-fail-version-1p12.l | 24 +
.../gas/riscv/priv-reg-fail-version-1p9p1.d | 2 +-
gas/testsuite/gas/riscv/priv-reg-fail-zkr.d | 2 +-
.../gas/riscv/priv-reg-version-1p10.d | 534 +++++++++---------
.../gas/riscv/priv-reg-version-1p11.d | 534 +++++++++---------
.../gas/riscv/priv-reg-version-1p12.d | 275 +++++++++
.../gas/riscv/priv-reg-version-1p9p1.d | 534 +++++++++---------
gas/testsuite/gas/riscv/priv-reg.s | 294 +---------
22 files changed, 1421 insertions(+), 1374 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/priv-reg-access-all.s
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.d
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.l
create mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p12.d
base-commit: d20236e748ab70e9243960850eef64838f1b9721
--
2.32.0
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 1/3] RISC-V: Make testcase indentation consistent
2021-12-24 3:22 [PATCH v2 0/3] RISC-V: Prepare Privileged Architecture 1.12 Tsukasa OI
@ 2021-12-24 3:22 ` Tsukasa OI
2021-12-24 3:22 ` [PATCH v2 2/3] RISC-V: Unify "access all CSRs" testcases Tsukasa OI
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Tsukasa OI @ 2021-12-24 3:22 UTC (permalink / raw)
To: Tsukasa OI, Nelson Chu, Vineet Gupta; +Cc: binutils
This commit makes some indentation used in testcase regular expressions
"[(n*SPACE)(1*TAB)]+" consistent "[(1*SPACE)(1*TAB)]+" unless changing
the pattern would create unaligned lines.
gas/ChangeLog:
* testsuite/gas/riscv/option-arch-01a.d: Make indentation
consistent.
* testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise.
---
gas/testsuite/gas/riscv/option-arch-01a.d | 8 +-
.../gas/riscv/priv-reg-version-1p10.d | 532 +++++++++---------
.../gas/riscv/priv-reg-version-1p11.d | 532 +++++++++---------
.../gas/riscv/priv-reg-version-1p9p1.d | 532 +++++++++---------
4 files changed, 802 insertions(+), 802 deletions(-)
diff --git a/gas/testsuite/gas/riscv/option-arch-01a.d b/gas/testsuite/gas/riscv/option-arch-01a.d
index aed4ca8e4d9..2aeb17900cf 100644
--- a/gas/testsuite/gas/riscv/option-arch-01a.d
+++ b/gas/testsuite/gas/riscv/option-arch-01a.d
@@ -2,13 +2,13 @@
#source: option-arch-01.s
#objdump: -d
-.*:[ ]+file format .*
+.*:[ ]+file format .*
Disassembly of section .text:
0+000 <.text>:
-[ ]+[0-9a-f]+:[ ]+952e[ ]+add[ ]+a0,a0,a1
-[ ]+[0-9a-f]+:[ ]+00b50533[ ]+add[ ]+a0,a0,a1
-[ ]+[0-9a-f]+:[ ]+00302573[ ]+csrr[ ]+a0,fcsr
+[ ]+[0-9a-f]+:[ ]+952e[ ]+add[ ]+a0,a0,a1
+[ ]+[0-9a-f]+:[ ]+00b50533[ ]+add[ ]+a0,a0,a1
+[ ]+[0-9a-f]+:[ ]+00302573[ ]+csrr[ ]+a0,fcsr
#...
diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
index ee4f405adaa..928c9c089ba 100644
--- a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
@@ -2,274 +2,274 @@
#source: priv-reg.s
#objdump: -dr -Mpriv-spec=1.10
-.*:[ ]+file format .*
+.*:[ ]+file format .*
Disassembly of section .text:
0+000 <.text>:
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diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
index 185e84dbd70..a283049d7b3 100644
--- a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
@@ -2,274 +2,274 @@
#source: priv-reg.s
#objdump: -dr -Mpriv-spec=1.11
-.*:[ ]+file format .*
+.*:[ ]+file format .*
Disassembly of section .text:
0+000 <.text>:
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diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
index 0e0ba779701..d9b86ed92ab 100644
--- a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
@@ -2,274 +2,274 @@
#source: priv-reg.s
#objdump: -dr -Mpriv-spec=1.9.1
-.*:[ ]+file format .*
+.*:[ ]+file format .*
Disassembly of section .text:
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+[ ]+[0-9a-f]+:[ ]+32402573[ ]+csrr[ ]+a0,mhpmevent4
+[ ]+[0-9a-f]+:[ ]+32502573[ ]+csrr[ ]+a0,mhpmevent5
+[ ]+[0-9a-f]+:[ ]+32602573[ ]+csrr[ ]+a0,mhpmevent6
+[ ]+[0-9a-f]+:[ ]+32702573[ ]+csrr[ ]+a0,mhpmevent7
+[ ]+[0-9a-f]+:[ ]+32802573[ ]+csrr[ ]+a0,mhpmevent8
+[ ]+[0-9a-f]+:[ ]+32902573[ ]+csrr[ ]+a0,mhpmevent9
+[ ]+[0-9a-f]+:[ ]+32a02573[ ]+csrr[ ]+a0,mhpmevent10
+[ ]+[0-9a-f]+:[ ]+32b02573[ ]+csrr[ ]+a0,mhpmevent11
+[ ]+[0-9a-f]+:[ ]+32c02573[ ]+csrr[ ]+a0,mhpmevent12
+[ ]+[0-9a-f]+:[ ]+32d02573[ ]+csrr[ ]+a0,mhpmevent13
+[ ]+[0-9a-f]+:[ ]+32e02573[ ]+csrr[ ]+a0,mhpmevent14
+[ ]+[0-9a-f]+:[ ]+32f02573[ ]+csrr[ ]+a0,mhpmevent15
+[ ]+[0-9a-f]+:[ ]+33002573[ ]+csrr[ ]+a0,mhpmevent16
+[ ]+[0-9a-f]+:[ ]+33102573[ ]+csrr[ ]+a0,mhpmevent17
+[ ]+[0-9a-f]+:[ ]+33202573[ ]+csrr[ ]+a0,mhpmevent18
+[ ]+[0-9a-f]+:[ ]+33302573[ ]+csrr[ ]+a0,mhpmevent19
+[ ]+[0-9a-f]+:[ ]+33402573[ ]+csrr[ ]+a0,mhpmevent20
+[ ]+[0-9a-f]+:[ ]+33502573[ ]+csrr[ ]+a0,mhpmevent21
+[ ]+[0-9a-f]+:[ ]+33602573[ ]+csrr[ ]+a0,mhpmevent22
+[ ]+[0-9a-f]+:[ ]+33702573[ ]+csrr[ ]+a0,mhpmevent23
+[ ]+[0-9a-f]+:[ ]+33802573[ ]+csrr[ ]+a0,mhpmevent24
+[ ]+[0-9a-f]+:[ ]+33902573[ ]+csrr[ ]+a0,mhpmevent25
+[ ]+[0-9a-f]+:[ ]+33a02573[ ]+csrr[ ]+a0,mhpmevent26
+[ ]+[0-9a-f]+:[ ]+33b02573[ ]+csrr[ ]+a0,mhpmevent27
+[ ]+[0-9a-f]+:[ ]+33c02573[ ]+csrr[ ]+a0,mhpmevent28
+[ ]+[0-9a-f]+:[ ]+33d02573[ ]+csrr[ ]+a0,mhpmevent29
+[ ]+[0-9a-f]+:[ ]+33e02573[ ]+csrr[ ]+a0,mhpmevent30
+[ ]+[0-9a-f]+:[ ]+33f02573[ ]+csrr[ ]+a0,mhpmevent31
+[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,ubadaddr
+[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,sbadaddr
+[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,sptbr
+[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mbadaddr
+[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mucounteren
+[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,hstatus
+[ ]+[0-9a-f]+:[ ]+20202573[ ]+csrr[ ]+a0,hedeleg
+[ ]+[0-9a-f]+:[ ]+20302573[ ]+csrr[ ]+a0,hideleg
+[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,hie
+[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,htvec
+[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,hscratch
+[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,hepc
+[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,hcause
+[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,hbadaddr
+[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,hip
+[ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,mbase
+[ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,mbound
+[ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,mibase
+[ ]+[0-9a-f]+:[ ]+38302573[ ]+csrr[ ]+a0,mibound
+[ ]+[0-9a-f]+:[ ]+38402573[ ]+csrr[ ]+a0,mdbase
+[ ]+[0-9a-f]+:[ ]+38502573[ ]+csrr[ ]+a0,mdbound
+[ ]+[0-9a-f]+:[ ]+32102573[ ]+csrr[ ]+a0,mscounteren
+[ ]+[0-9a-f]+:[ ]+32202573[ ]+csrr[ ]+a0,mhcounteren
+[ ]+[0-9a-f]+:[ ]+00102573[ ]+frflags[ ]+a0
+[ ]+[0-9a-f]+:[ ]+00202573[ ]+frrm[ ]+a0
+[ ]+[0-9a-f]+:[ ]+00302573[ ]+frcsr[ ]+a0
+[ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
+[ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
+[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
+[ ]+[0-9a-f]+:[ ]+7b302573[ ]+csrr[ ]+a0,dscratch1
+[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
+[ ]+[0-9a-f]+:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
+[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
+[ ]+[0-9a-f]+:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
+[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
+[ ]+[0-9a-f]+:[ ]+7a402573[ ]+csrr[ ]+a0,tinfo
+[ ]+[0-9a-f]+:[ ]+7a502573[ ]+csrr[ ]+a0,tcontrol
+[ ]+[0-9a-f]+:[ ]+7a802573[ ]+csrr[ ]+a0,mcontext
+[ ]+[0-9a-f]+:[ ]+7aa02573[ ]+csrr[ ]+a0,scontext
+[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
+[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
+[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
+[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
+[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
+[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
+[ ]+[0-9a-f]+:[ ]+01502573[ ]+csrr[ ]+a0,seed
+[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart
+[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat
+[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm
+[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr
+[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl
+[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype
+[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
--
2.32.0
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 2/3] RISC-V: Unify "access all CSRs" testcases
2021-12-24 3:22 [PATCH v2 0/3] RISC-V: Prepare Privileged Architecture 1.12 Tsukasa OI
2021-12-24 3:22 ` [PATCH v2 1/3] RISC-V: Make testcase indentation consistent Tsukasa OI
@ 2021-12-24 3:22 ` Tsukasa OI
2021-12-24 3:22 ` [PATCH v2 3/3] RISC-V: Add Privileged Architecture version 1.12 Tsukasa OI
2022-02-21 13:21 ` [PATCH v2 0/3] RISC-V: Prepare Privileged Architecture 1.12 Jan Beulich
3 siblings, 0 replies; 7+ messages in thread
From: Tsukasa OI @ 2021-12-24 3:22 UTC (permalink / raw)
To: Tsukasa OI, Nelson Chu, Vineet Gupta; +Cc: binutils
This commit unifies two "access all CSRs" sources using
.include directive.
gas/ChangeLog:
* testsuite/gas/riscv/priv-reg.s: Move main contents to
priv-reg-all-access.s.
* testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Move main
contents to priv-reg-all-access.s.
* testsuite/gas/riscv/priv-reg-access-all.s: New: common part
of "access all CSRs" testcases.
* testsuite/gas/riscv/priv-reg-fail-fext.d: Add necessary
assembler option.
* testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-zkr.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise.
---
gas/testsuite/gas/riscv/priv-reg-access-all.s | 292 +++++++++++++++++
gas/testsuite/gas/riscv/priv-reg-fail-fext.d | 2 +-
.../gas/riscv/priv-reg-fail-read-only-01.d | 2 +-
.../gas/riscv/priv-reg-fail-read-only-01.s | 267 +---------------
.../gas/riscv/priv-reg-fail-rv32-only.d | 2 +-
.../gas/riscv/priv-reg-fail-version-1p10.d | 2 +-
.../gas/riscv/priv-reg-fail-version-1p11.d | 2 +-
.../gas/riscv/priv-reg-fail-version-1p9p1.d | 2 +-
gas/testsuite/gas/riscv/priv-reg-fail-zkr.d | 2 +-
.../gas/riscv/priv-reg-version-1p10.d | 2 +-
.../gas/riscv/priv-reg-version-1p11.d | 2 +-
.../gas/riscv/priv-reg-version-1p9p1.d | 2 +-
gas/testsuite/gas/riscv/priv-reg.s | 294 +-----------------
13 files changed, 304 insertions(+), 569 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/priv-reg-access-all.s
diff --git a/gas/testsuite/gas/riscv/priv-reg-access-all.s b/gas/testsuite/gas/riscv/priv-reg-access-all.s
new file mode 100644
index 00000000000..2479b29a976
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-access-all.s
@@ -0,0 +1,292 @@
+ # Supported the current priv spec 1.11.
+ csr ustatus
+ csr uie
+ csr utvec
+
+ csr uscratch
+ csr uepc
+ csr ucause
+ csr utval # Added in 1.10
+ csr uip
+
+ csr cycle
+ csr time
+ csr instret
+ csr hpmcounter3
+ csr hpmcounter4
+ csr hpmcounter5
+ csr hpmcounter6
+ csr hpmcounter7
+ csr hpmcounter8
+ csr hpmcounter9
+ csr hpmcounter10
+ csr hpmcounter11
+ csr hpmcounter12
+ csr hpmcounter13
+ csr hpmcounter14
+ csr hpmcounter15
+ csr hpmcounter16
+ csr hpmcounter17
+ csr hpmcounter18
+ csr hpmcounter19
+ csr hpmcounter20
+ csr hpmcounter21
+ csr hpmcounter22
+ csr hpmcounter23
+ csr hpmcounter24
+ csr hpmcounter25
+ csr hpmcounter26
+ csr hpmcounter27
+ csr hpmcounter28
+ csr hpmcounter29
+ csr hpmcounter30
+ csr hpmcounter31
+ csr cycleh
+ csr timeh
+ csr instreth
+ csr hpmcounter3h
+ csr hpmcounter4h
+ csr hpmcounter5h
+ csr hpmcounter6h
+ csr hpmcounter7h
+ csr hpmcounter8h
+ csr hpmcounter9h
+ csr hpmcounter10h
+ csr hpmcounter11h
+ csr hpmcounter12h
+ csr hpmcounter13h
+ csr hpmcounter14h
+ csr hpmcounter15h
+ csr hpmcounter16h
+ csr hpmcounter17h
+ csr hpmcounter18h
+ csr hpmcounter19h
+ csr hpmcounter20h
+ csr hpmcounter21h
+ csr hpmcounter22h
+ csr hpmcounter23h
+ csr hpmcounter24h
+ csr hpmcounter25h
+ csr hpmcounter26h
+ csr hpmcounter27h
+ csr hpmcounter28h
+ csr hpmcounter29h
+ csr hpmcounter30h
+ csr hpmcounter31h
+
+ csr sstatus
+ csr sedeleg
+ csr sideleg
+ csr sie
+ csr stvec
+ csr scounteren # Added in 1.10
+
+ csr sscratch
+ csr sepc
+ csr scause
+ csr stval # Added in 1.10
+ csr sip
+
+ csr satp # Added in 1.10
+
+ csr mvendorid
+ csr marchid
+ csr mimpid
+ csr mhartid
+
+ csr mstatus
+ csr misa # 0xf10 in 1.9, but changed to 0x301 since 1.9.1.
+ csr medeleg
+ csr mideleg
+ csr mie
+ csr mtvec
+ csr mcounteren # Added in 1.10
+
+ csr mscratch
+ csr mepc
+ csr mcause
+ csr mtval # Added in 1.10
+ csr mip
+
+ csr pmpcfg0 # Added in 1.10
+ csr pmpcfg1 # Added in 1.10
+ csr pmpcfg2 # Added in 1.10
+ csr pmpcfg3 # Added in 1.10
+ csr pmpaddr0 # Added in 1.10
+ csr pmpaddr1 # Added in 1.10
+ csr pmpaddr2 # Added in 1.10
+ csr pmpaddr3 # Added in 1.10
+ csr pmpaddr4 # Added in 1.10
+ csr pmpaddr5 # Added in 1.10
+ csr pmpaddr6 # Added in 1.10
+ csr pmpaddr7 # Added in 1.10
+ csr pmpaddr8 # Added in 1.10
+ csr pmpaddr9 # Added in 1.10
+ csr pmpaddr10 # Added in 1.10
+ csr pmpaddr11 # Added in 1.10
+ csr pmpaddr12 # Added in 1.10
+ csr pmpaddr13 # Added in 1.10
+ csr pmpaddr14 # Added in 1.10
+ csr pmpaddr15 # Added in 1.10
+
+ csr mcycle
+ csr minstret
+ csr mhpmcounter3
+ csr mhpmcounter4
+ csr mhpmcounter5
+ csr mhpmcounter6
+ csr mhpmcounter7
+ csr mhpmcounter8
+ csr mhpmcounter9
+ csr mhpmcounter10
+ csr mhpmcounter11
+ csr mhpmcounter12
+ csr mhpmcounter13
+ csr mhpmcounter14
+ csr mhpmcounter15
+ csr mhpmcounter16
+ csr mhpmcounter17
+ csr mhpmcounter18
+ csr mhpmcounter19
+ csr mhpmcounter20
+ csr mhpmcounter21
+ csr mhpmcounter22
+ csr mhpmcounter23
+ csr mhpmcounter24
+ csr mhpmcounter25
+ csr mhpmcounter26
+ csr mhpmcounter27
+ csr mhpmcounter28
+ csr mhpmcounter29
+ csr mhpmcounter30
+ csr mhpmcounter31
+ csr mcycleh
+ csr minstreth
+ csr mhpmcounter3h
+ csr mhpmcounter4h
+ csr mhpmcounter5h
+ csr mhpmcounter6h
+ csr mhpmcounter7h
+ csr mhpmcounter8h
+ csr mhpmcounter9h
+ csr mhpmcounter10h
+ csr mhpmcounter11h
+ csr mhpmcounter12h
+ csr mhpmcounter13h
+ csr mhpmcounter14h
+ csr mhpmcounter15h
+ csr mhpmcounter16h
+ csr mhpmcounter17h
+ csr mhpmcounter18h
+ csr mhpmcounter19h
+ csr mhpmcounter20h
+ csr mhpmcounter21h
+ csr mhpmcounter22h
+ csr mhpmcounter23h
+ csr mhpmcounter24h
+ csr mhpmcounter25h
+ csr mhpmcounter26h
+ csr mhpmcounter27h
+ csr mhpmcounter28h
+ csr mhpmcounter29h
+ csr mhpmcounter30h
+ csr mhpmcounter31h
+
+ csr mcountinhibit # Added in 1.11
+ csr mhpmevent3
+ csr mhpmevent4
+ csr mhpmevent5
+ csr mhpmevent6
+ csr mhpmevent7
+ csr mhpmevent8
+ csr mhpmevent9
+ csr mhpmevent10
+ csr mhpmevent11
+ csr mhpmevent12
+ csr mhpmevent13
+ csr mhpmevent14
+ csr mhpmevent15
+ csr mhpmevent16
+ csr mhpmevent17
+ csr mhpmevent18
+ csr mhpmevent19
+ csr mhpmevent20
+ csr mhpmevent21
+ csr mhpmevent22
+ csr mhpmevent23
+ csr mhpmevent24
+ csr mhpmevent25
+ csr mhpmevent26
+ csr mhpmevent27
+ csr mhpmevent28
+ csr mhpmevent29
+ csr mhpmevent30
+ csr mhpmevent31
+
+ # Supported in previous priv spec, but dropped now.
+ csr ubadaddr # 0x043 in 1.9.1, but the value is utval since 1.10
+ csr sbadaddr # 0x143 in 1.9.1, but the value is stval since 1.10
+ csr sptbr # 0x180 in 1.9.1, but the value is satp since 1.10
+ csr mbadaddr # 0x343 in 1.9.1, but the value is mtval since 1.10
+ csr mucounteren # 0x320 in 1.9.1, dropped in 1.10, but the value is mcountinhibit since 1.11
+
+ csr hstatus # 0x200, dropped in 1.10
+ csr hedeleg # 0x202, dropped in 1.10
+ csr hideleg # 0x203, dropped in 1.10
+ csr hie # 0x204, dropped in 1.10
+ csr htvec # 0x205, dropped in 1.10
+ csr hscratch # 0x240, dropped in 1.10
+ csr hepc # 0x241, dropped in 1.10
+ csr hcause # 0x242, dropped in 1.10
+ csr hbadaddr # 0x243, dropped in 1.10
+ csr hip # 0x244, dropped in 1.10
+ csr mbase # 0x380, dropped in 1.10
+ csr mbound # 0x381, dropped in 1.10
+ csr mibase # 0x382, dropped in 1.10
+ csr mibound # 0x383, dropped in 1.10
+ csr mdbase # 0x384, dropped in 1.10
+ csr mdbound # 0x385, dropped in 1.10
+ csr mscounteren # 0x321, dropped in 1.10
+ csr mhcounteren # 0x322, dropped in 1.10
+
+ # Unprivileged CSR which are not controlled by privilege spec.
+
+ # Float
+ csr fflags
+ csr frm
+ csr fcsr
+
+ # Core debug
+ csr dcsr
+ csr dpc
+ csr dscratch0
+ csr dscratch1
+ csr dscratch # 0x7b2, alias to dscratch0
+
+ # Trigger debug
+ csr tselect
+ csr tdata1
+ csr tdata2
+ csr tdata3
+ csr tinfo
+ csr tcontrol
+ csr mcontext
+ csr scontext
+ csr mcontrol # 0x7a1, alias to tdata1
+ csr icount # 0x7a1, alias to tdata1
+ csr itrigger # 0x7a1, alias to tdata1
+ csr etrigger # 0x7a1, alias to tdata1
+ csr textra32 # 0x7a3, alias to tdata3
+ csr textra64 # 0x7a3, alias to tdata3
+
+ # Scalar crypto
+ csr seed # 0x015, Entropy Source
+
+ # Vector
+ csr vstart
+ csr vxsat
+ csr vxrm
+ csr vcsr
+ csr vl
+ csr vtype
+ csr vlenb
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-fext.d b/gas/testsuite/gas/riscv/priv-reg-fail-fext.d
index da535663693..cce806e8705 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-fext.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-fext.d
@@ -1,3 +1,3 @@
-#as: -march=rv32i -mcsr-check
+#as: -I$srcdir/$subdir -march=rv32i -mcsr-check
#source: priv-reg.s
#warning_output: priv-reg-fail-fext.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d
index ae190c053c6..1134c4c7955 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d
@@ -1,3 +1,3 @@
-#as: -march=rv32if -mcsr-check
+#as: -I$srcdir/$subdir -march=rv32if -mcsr-check
#source: priv-reg-fail-read-only-01.s
#warning_output: priv-reg-fail-read-only-01.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s
index af0fc4e14a4..fc996f6159f 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s
@@ -1,269 +1,4 @@
.macro csr val
csrw \val, a1
.endm
-
- # Supported the current priv spec 1.11.
- csr ustatus
- csr uie
- csr utvec
-
- csr uscratch
- csr uepc
- csr ucause
- csr utval # Added in 1.10
- csr uip
-
- csr fflags
- csr frm
- csr fcsr
-
- csr cycle
- csr time
- csr instret
- csr hpmcounter3
- csr hpmcounter4
- csr hpmcounter5
- csr hpmcounter6
- csr hpmcounter7
- csr hpmcounter8
- csr hpmcounter9
- csr hpmcounter10
- csr hpmcounter11
- csr hpmcounter12
- csr hpmcounter13
- csr hpmcounter14
- csr hpmcounter15
- csr hpmcounter16
- csr hpmcounter17
- csr hpmcounter18
- csr hpmcounter19
- csr hpmcounter20
- csr hpmcounter21
- csr hpmcounter22
- csr hpmcounter23
- csr hpmcounter24
- csr hpmcounter25
- csr hpmcounter26
- csr hpmcounter27
- csr hpmcounter28
- csr hpmcounter29
- csr hpmcounter30
- csr hpmcounter31
- csr cycleh
- csr timeh
- csr instreth
- csr hpmcounter3h
- csr hpmcounter4h
- csr hpmcounter5h
- csr hpmcounter6h
- csr hpmcounter7h
- csr hpmcounter8h
- csr hpmcounter9h
- csr hpmcounter10h
- csr hpmcounter11h
- csr hpmcounter12h
- csr hpmcounter13h
- csr hpmcounter14h
- csr hpmcounter15h
- csr hpmcounter16h
- csr hpmcounter17h
- csr hpmcounter18h
- csr hpmcounter19h
- csr hpmcounter20h
- csr hpmcounter21h
- csr hpmcounter22h
- csr hpmcounter23h
- csr hpmcounter24h
- csr hpmcounter25h
- csr hpmcounter26h
- csr hpmcounter27h
- csr hpmcounter28h
- csr hpmcounter29h
- csr hpmcounter30h
- csr hpmcounter31h
-
- csr sstatus
- csr sedeleg
- csr sideleg
- csr sie
- csr stvec
- csr scounteren # Added in 1.10
-
- csr sscratch
- csr sepc
- csr scause
- csr stval # Added in 1.10
- csr sip
-
- csr satp # Added in 1.10
-
- csr mvendorid
- csr marchid
- csr mimpid
- csr mhartid
-
- csr mstatus
- csr misa # 0xf10 in 1.9, but changed to 0x301 since 1.9.1.
- csr medeleg
- csr mideleg
- csr mie
- csr mtvec
- csr mcounteren # Added in 1.10
-
- csr mscratch
- csr mepc
- csr mcause
- csr mtval # Added in 1.10
- csr mip
-
- csr pmpcfg0 # Added in 1.10
- csr pmpcfg1 # Added in 1.10
- csr pmpcfg2 # Added in 1.10
- csr pmpcfg3 # Added in 1.10
- csr pmpaddr0 # Added in 1.10
- csr pmpaddr1 # Added in 1.10
- csr pmpaddr2 # Added in 1.10
- csr pmpaddr3 # Added in 1.10
- csr pmpaddr4 # Added in 1.10
- csr pmpaddr5 # Added in 1.10
- csr pmpaddr6 # Added in 1.10
- csr pmpaddr7 # Added in 1.10
- csr pmpaddr8 # Added in 1.10
- csr pmpaddr9 # Added in 1.10
- csr pmpaddr10 # Added in 1.10
- csr pmpaddr11 # Added in 1.10
- csr pmpaddr12 # Added in 1.10
- csr pmpaddr13 # Added in 1.10
- csr pmpaddr14 # Added in 1.10
- csr pmpaddr15 # Added in 1.10
-
- csr mcycle
- csr minstret
- csr mhpmcounter3
- csr mhpmcounter4
- csr mhpmcounter5
- csr mhpmcounter6
- csr mhpmcounter7
- csr mhpmcounter8
- csr mhpmcounter9
- csr mhpmcounter10
- csr mhpmcounter11
- csr mhpmcounter12
- csr mhpmcounter13
- csr mhpmcounter14
- csr mhpmcounter15
- csr mhpmcounter16
- csr mhpmcounter17
- csr mhpmcounter18
- csr mhpmcounter19
- csr mhpmcounter20
- csr mhpmcounter21
- csr mhpmcounter22
- csr mhpmcounter23
- csr mhpmcounter24
- csr mhpmcounter25
- csr mhpmcounter26
- csr mhpmcounter27
- csr mhpmcounter28
- csr mhpmcounter29
- csr mhpmcounter30
- csr mhpmcounter31
- csr mcycleh
- csr minstreth
- csr mhpmcounter3h
- csr mhpmcounter4h
- csr mhpmcounter5h
- csr mhpmcounter6h
- csr mhpmcounter7h
- csr mhpmcounter8h
- csr mhpmcounter9h
- csr mhpmcounter10h
- csr mhpmcounter11h
- csr mhpmcounter12h
- csr mhpmcounter13h
- csr mhpmcounter14h
- csr mhpmcounter15h
- csr mhpmcounter16h
- csr mhpmcounter17h
- csr mhpmcounter18h
- csr mhpmcounter19h
- csr mhpmcounter20h
- csr mhpmcounter21h
- csr mhpmcounter22h
- csr mhpmcounter23h
- csr mhpmcounter24h
- csr mhpmcounter25h
- csr mhpmcounter26h
- csr mhpmcounter27h
- csr mhpmcounter28h
- csr mhpmcounter29h
- csr mhpmcounter30h
- csr mhpmcounter31h
-
- csr mcountinhibit # Added in 1.11
- csr mhpmevent3
- csr mhpmevent4
- csr mhpmevent5
- csr mhpmevent6
- csr mhpmevent7
- csr mhpmevent8
- csr mhpmevent9
- csr mhpmevent10
- csr mhpmevent11
- csr mhpmevent12
- csr mhpmevent13
- csr mhpmevent14
- csr mhpmevent15
- csr mhpmevent16
- csr mhpmevent17
- csr mhpmevent18
- csr mhpmevent19
- csr mhpmevent20
- csr mhpmevent21
- csr mhpmevent22
- csr mhpmevent23
- csr mhpmevent24
- csr mhpmevent25
- csr mhpmevent26
- csr mhpmevent27
- csr mhpmevent28
- csr mhpmevent29
- csr mhpmevent30
- csr mhpmevent31
-
- csr tselect
- csr tdata1
- csr tdata2
- csr tdata3
-
- csr dcsr
- csr dpc
- csr dscratch0 # Added in 1.11
- csr dscratch1 # Added in 1.11
-
- # Supported in previous priv spec, but dropped now.
- csr ubadaddr # 0x043 in 1.9.1, but the value is utval since 1.10
- csr sbadaddr # 0x143 in 1.9.1, but the value is stval since 1.10
- csr sptbr # 0x180 in 1.9.1, but the value is satp since 1.10
- csr mbadaddr # 0x343 in 1.9.1, but the value is mtval since 1.10
- csr mucounteren # 0x320 in 1.9.1, dropped in 1.10, but the value is mcountinhibit since 1.11
- csr dscratch # 0x7b2 in 1.10, but the value is dscratch0 since 1.11
-
- csr hstatus # 0x200, dropped in 1.10
- csr hedeleg # 0x202, dropped in 1.10
- csr hideleg # 0x203, dropped in 1.10
- csr hie # 0x204, dropped in 1.10
- csr htvec # 0x205, dropped in 1.10
- csr hscratch # 0x240, dropped in 1.10
- csr hepc # 0x241, dropped in 1.10
- csr hcause # 0x242, dropped in 1.10
- csr hbadaddr # 0x243, dropped in 1.10
- csr hip # 0x244, dropped in 1.10
- csr mbase # 0x380, dropped in 1.10
- csr mbound # 0x381, dropped in 1.10
- csr mibase # 0x382, dropped in 1.10
- csr mibound # 0x383, dropped in 1.10
- csr mdbase # 0x384, dropped in 1.10
- csr mdbound # 0x385, dropped in 1.10
- csr mscounteren # 0x321, dropped in 1.10
- csr mhcounteren # 0x322, dropped in 1.10
+ .include "priv-reg-access-all.s"
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
index d71b2615c5f..a1f27ec0622 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
@@ -1,3 +1,3 @@
-#as: -march=rv64if -mcsr-check
+#as: -I$srcdir/$subdir -march=rv64if -mcsr-check
#source: priv-reg.s
#warning_output: priv-reg-fail-rv32-only.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
index 3e1836a64a9..aa95d3396f4 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d
@@ -1,4 +1,4 @@
-#as: -march=rv32ifv_zkr -mcsr-check -mpriv-spec=1.10 -march-attr
+#as: -I$srcdir/$subdir -march=rv32ifv_zkr -mcsr-check -mpriv-spec=1.10 -march-attr
#source: priv-reg.s
#warning_output: priv-reg-fail-version-1p10.l
#readelf: -A
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
index e1705e7cafc..d57b5423485 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d
@@ -1,4 +1,4 @@
-#as: -march=rv32ifv_zkr -mcsr-check -mpriv-spec=1.11 -march-attr
+#as: -I$srcdir/$subdir -march=rv32ifv_zkr -mcsr-check -mpriv-spec=1.11 -march-attr
#source: priv-reg.s
#warning_output: priv-reg-fail-version-1p11.l
#readelf: -A
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
index 56ade5932c9..d03754cbcc3 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d
@@ -1,4 +1,4 @@
-#as: -march=rv32ifv_zkr -mcsr-check -mpriv-spec=1.9.1 -march-attr
+#as: -I$srcdir/$subdir -march=rv32ifv_zkr -mcsr-check -mpriv-spec=1.9.1 -march-attr
#source: priv-reg.s
#warning_output: priv-reg-fail-version-1p9p1.l
#readelf: -A
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-zkr.d b/gas/testsuite/gas/riscv/priv-reg-fail-zkr.d
index d65d5104099..e5c9c51713a 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-zkr.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-zkr.d
@@ -1,3 +1,3 @@
-#as: -march=rv32if -mcsr-check
+#as: -I$srcdir/$subdir -march=rv32if -mcsr-check
#source: priv-reg.s
#warning_output: priv-reg-fail-zkr.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
index 928c9c089ba..81e338d5747 100644
--- a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d
@@ -1,4 +1,4 @@
-#as: -march=rv32if -mpriv-spec=1.10
+#as: -I$srcdir/$subdir -march=rv32if -mpriv-spec=1.10
#source: priv-reg.s
#objdump: -dr -Mpriv-spec=1.10
diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
index a283049d7b3..1925ba09235 100644
--- a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d
@@ -1,4 +1,4 @@
-#as: -march=rv32if -mpriv-spec=1.11
+#as: -I$srcdir/$subdir -march=rv32if -mpriv-spec=1.11
#source: priv-reg.s
#objdump: -dr -Mpriv-spec=1.11
diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
index d9b86ed92ab..d02c0e71893 100644
--- a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d
@@ -1,4 +1,4 @@
-#as: -march=rv32if -mpriv-spec=1.9.1
+#as: -I$srcdir/$subdir -march=rv32if -mpriv-spec=1.9.1
#source: priv-reg.s
#objdump: -dr -Mpriv-spec=1.9.1
diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s
index 5cf3ebc1b3e..74ff4a48f83 100644
--- a/gas/testsuite/gas/riscv/priv-reg.s
+++ b/gas/testsuite/gas/riscv/priv-reg.s
@@ -1,296 +1,4 @@
.macro csr val
csrr a0,\val
.endm
-
- # Supported the current priv spec 1.11.
- csr ustatus
- csr uie
- csr utvec
-
- csr uscratch
- csr uepc
- csr ucause
- csr utval # Added in 1.10
- csr uip
-
- csr cycle
- csr time
- csr instret
- csr hpmcounter3
- csr hpmcounter4
- csr hpmcounter5
- csr hpmcounter6
- csr hpmcounter7
- csr hpmcounter8
- csr hpmcounter9
- csr hpmcounter10
- csr hpmcounter11
- csr hpmcounter12
- csr hpmcounter13
- csr hpmcounter14
- csr hpmcounter15
- csr hpmcounter16
- csr hpmcounter17
- csr hpmcounter18
- csr hpmcounter19
- csr hpmcounter20
- csr hpmcounter21
- csr hpmcounter22
- csr hpmcounter23
- csr hpmcounter24
- csr hpmcounter25
- csr hpmcounter26
- csr hpmcounter27
- csr hpmcounter28
- csr hpmcounter29
- csr hpmcounter30
- csr hpmcounter31
- csr cycleh
- csr timeh
- csr instreth
- csr hpmcounter3h
- csr hpmcounter4h
- csr hpmcounter5h
- csr hpmcounter6h
- csr hpmcounter7h
- csr hpmcounter8h
- csr hpmcounter9h
- csr hpmcounter10h
- csr hpmcounter11h
- csr hpmcounter12h
- csr hpmcounter13h
- csr hpmcounter14h
- csr hpmcounter15h
- csr hpmcounter16h
- csr hpmcounter17h
- csr hpmcounter18h
- csr hpmcounter19h
- csr hpmcounter20h
- csr hpmcounter21h
- csr hpmcounter22h
- csr hpmcounter23h
- csr hpmcounter24h
- csr hpmcounter25h
- csr hpmcounter26h
- csr hpmcounter27h
- csr hpmcounter28h
- csr hpmcounter29h
- csr hpmcounter30h
- csr hpmcounter31h
-
- csr sstatus
- csr sedeleg
- csr sideleg
- csr sie
- csr stvec
- csr scounteren # Added in 1.10
-
- csr sscratch
- csr sepc
- csr scause
- csr stval # Added in 1.10
- csr sip
-
- csr satp # Added in 1.10
-
- csr mvendorid
- csr marchid
- csr mimpid
- csr mhartid
-
- csr mstatus
- csr misa # 0xf10 in 1.9, but changed to 0x301 since 1.9.1.
- csr medeleg
- csr mideleg
- csr mie
- csr mtvec
- csr mcounteren # Added in 1.10
-
- csr mscratch
- csr mepc
- csr mcause
- csr mtval # Added in 1.10
- csr mip
-
- csr pmpcfg0 # Added in 1.10
- csr pmpcfg1 # Added in 1.10
- csr pmpcfg2 # Added in 1.10
- csr pmpcfg3 # Added in 1.10
- csr pmpaddr0 # Added in 1.10
- csr pmpaddr1 # Added in 1.10
- csr pmpaddr2 # Added in 1.10
- csr pmpaddr3 # Added in 1.10
- csr pmpaddr4 # Added in 1.10
- csr pmpaddr5 # Added in 1.10
- csr pmpaddr6 # Added in 1.10
- csr pmpaddr7 # Added in 1.10
- csr pmpaddr8 # Added in 1.10
- csr pmpaddr9 # Added in 1.10
- csr pmpaddr10 # Added in 1.10
- csr pmpaddr11 # Added in 1.10
- csr pmpaddr12 # Added in 1.10
- csr pmpaddr13 # Added in 1.10
- csr pmpaddr14 # Added in 1.10
- csr pmpaddr15 # Added in 1.10
-
- csr mcycle
- csr minstret
- csr mhpmcounter3
- csr mhpmcounter4
- csr mhpmcounter5
- csr mhpmcounter6
- csr mhpmcounter7
- csr mhpmcounter8
- csr mhpmcounter9
- csr mhpmcounter10
- csr mhpmcounter11
- csr mhpmcounter12
- csr mhpmcounter13
- csr mhpmcounter14
- csr mhpmcounter15
- csr mhpmcounter16
- csr mhpmcounter17
- csr mhpmcounter18
- csr mhpmcounter19
- csr mhpmcounter20
- csr mhpmcounter21
- csr mhpmcounter22
- csr mhpmcounter23
- csr mhpmcounter24
- csr mhpmcounter25
- csr mhpmcounter26
- csr mhpmcounter27
- csr mhpmcounter28
- csr mhpmcounter29
- csr mhpmcounter30
- csr mhpmcounter31
- csr mcycleh
- csr minstreth
- csr mhpmcounter3h
- csr mhpmcounter4h
- csr mhpmcounter5h
- csr mhpmcounter6h
- csr mhpmcounter7h
- csr mhpmcounter8h
- csr mhpmcounter9h
- csr mhpmcounter10h
- csr mhpmcounter11h
- csr mhpmcounter12h
- csr mhpmcounter13h
- csr mhpmcounter14h
- csr mhpmcounter15h
- csr mhpmcounter16h
- csr mhpmcounter17h
- csr mhpmcounter18h
- csr mhpmcounter19h
- csr mhpmcounter20h
- csr mhpmcounter21h
- csr mhpmcounter22h
- csr mhpmcounter23h
- csr mhpmcounter24h
- csr mhpmcounter25h
- csr mhpmcounter26h
- csr mhpmcounter27h
- csr mhpmcounter28h
- csr mhpmcounter29h
- csr mhpmcounter30h
- csr mhpmcounter31h
-
- csr mcountinhibit # Added in 1.11
- csr mhpmevent3
- csr mhpmevent4
- csr mhpmevent5
- csr mhpmevent6
- csr mhpmevent7
- csr mhpmevent8
- csr mhpmevent9
- csr mhpmevent10
- csr mhpmevent11
- csr mhpmevent12
- csr mhpmevent13
- csr mhpmevent14
- csr mhpmevent15
- csr mhpmevent16
- csr mhpmevent17
- csr mhpmevent18
- csr mhpmevent19
- csr mhpmevent20
- csr mhpmevent21
- csr mhpmevent22
- csr mhpmevent23
- csr mhpmevent24
- csr mhpmevent25
- csr mhpmevent26
- csr mhpmevent27
- csr mhpmevent28
- csr mhpmevent29
- csr mhpmevent30
- csr mhpmevent31
-
- # Supported in previous priv spec, but dropped now.
- csr ubadaddr # 0x043 in 1.9.1, but the value is utval since 1.10
- csr sbadaddr # 0x143 in 1.9.1, but the value is stval since 1.10
- csr sptbr # 0x180 in 1.9.1, but the value is satp since 1.10
- csr mbadaddr # 0x343 in 1.9.1, but the value is mtval since 1.10
- csr mucounteren # 0x320 in 1.9.1, dropped in 1.10, but the value is mcountinhibit since 1.11
-
- csr hstatus # 0x200, dropped in 1.10
- csr hedeleg # 0x202, dropped in 1.10
- csr hideleg # 0x203, dropped in 1.10
- csr hie # 0x204, dropped in 1.10
- csr htvec # 0x205, dropped in 1.10
- csr hscratch # 0x240, dropped in 1.10
- csr hepc # 0x241, dropped in 1.10
- csr hcause # 0x242, dropped in 1.10
- csr hbadaddr # 0x243, dropped in 1.10
- csr hip # 0x244, dropped in 1.10
- csr mbase # 0x380, dropped in 1.10
- csr mbound # 0x381, dropped in 1.10
- csr mibase # 0x382, dropped in 1.10
- csr mibound # 0x383, dropped in 1.10
- csr mdbase # 0x384, dropped in 1.10
- csr mdbound # 0x385, dropped in 1.10
- csr mscounteren # 0x321, dropped in 1.10
- csr mhcounteren # 0x322, dropped in 1.10
-
- # Unprivileged CSR which are not controlled by privilege spec.
-
- # Float
- csr fflags
- csr frm
- csr fcsr
-
- # Core debug
- csr dcsr
- csr dpc
- csr dscratch0
- csr dscratch1
- csr dscratch # 0x7b2, alias to dscratch0
-
- # Trigger debug
- csr tselect
- csr tdata1
- csr tdata2
- csr tdata3
- csr tinfo
- csr tcontrol
- csr mcontext
- csr scontext
- csr mcontrol # 0x7a1, alias to tdata1
- csr icount # 0x7a1, alias to tdata1
- csr itrigger # 0x7a1, alias to tdata1
- csr etrigger # 0x7a1, alias to tdata1
- csr textra32 # 0x7a3, alias to tdata3
- csr textra64 # 0x7a3, alias to tdata3
-
- # Scalar crypto
- csr seed # 0x015, Entropy Source
-
- # Vector
- csr vstart
- csr vxsat
- csr vxrm
- csr vcsr
- csr vl
- csr vtype
- csr vlenb
+ .include "priv-reg-access-all.s"
--
2.32.0
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 3/3] RISC-V: Add Privileged Architecture version 1.12
2021-12-24 3:22 [PATCH v2 0/3] RISC-V: Prepare Privileged Architecture 1.12 Tsukasa OI
2021-12-24 3:22 ` [PATCH v2 1/3] RISC-V: Make testcase indentation consistent Tsukasa OI
2021-12-24 3:22 ` [PATCH v2 2/3] RISC-V: Unify "access all CSRs" testcases Tsukasa OI
@ 2021-12-24 3:22 ` Tsukasa OI
2022-02-21 13:21 ` [PATCH v2 0/3] RISC-V: Prepare Privileged Architecture 1.12 Jan Beulich
3 siblings, 0 replies; 7+ messages in thread
From: Tsukasa OI @ 2021-12-24 3:22 UTC (permalink / raw)
To: Tsukasa OI, Nelson Chu, Vineet Gupta; +Cc: binutils
This commit adds Privileged Architecture version 1.12.
bfd/ChangeLog:
* cpu-riscv.c (riscv_priv_specs): Add version 1.12.
* cpu-riscv.h (enum riscv_spec_class): Add PRIV_SPEC_CLASS_1P12
for Privileged Architecture version 1.12.
gas/ChangeLog:
* config/tc-riscv.c (md_show_usage): Change help string.
* testsuite/gas/riscv/csr-dw-regnums.d: Use -mpriv-spec=1.12
to test latest specification.
* testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p12.d: New test that is
to be modified for Privileged Architecture version 1.12.
* testsuite/gas/riscv/priv-reg-fail-version-1p12.d: New test
that is to be modified for Privileged Architecture version 1.12.
* testsuite/gas/riscv/priv-reg-fail-version-1p12.l: Likewise.
---
bfd/cpu-riscv.c | 1 +
bfd/cpu-riscv.h | 1 +
gas/config/tc-riscv.c | 2 +-
gas/testsuite/gas/riscv/csr-dw-regnums.d | 2 +-
.../gas/riscv/priv-reg-fail-read-only-02.d | 2 +-
.../gas/riscv/priv-reg-fail-rv32-only.d | 2 +-
.../gas/riscv/priv-reg-fail-version-1p12.d | 11 +
.../gas/riscv/priv-reg-fail-version-1p12.l | 24 ++
.../gas/riscv/priv-reg-version-1p12.d | 275 ++++++++++++++++++
9 files changed, 316 insertions(+), 4 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.d
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.l
create mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p12.d
diff --git a/bfd/cpu-riscv.c b/bfd/cpu-riscv.c
index 813f2c3df8d..5038029ce01 100644
--- a/bfd/cpu-riscv.c
+++ b/bfd/cpu-riscv.c
@@ -117,6 +117,7 @@ const struct riscv_spec riscv_priv_specs[] =
{"1.9.1", PRIV_SPEC_CLASS_1P9P1},
{"1.10", PRIV_SPEC_CLASS_1P10},
{"1.11", PRIV_SPEC_CLASS_1P11},
+ {"1.12", PRIV_SPEC_CLASS_1P12},
};
/* Get the corresponding CSR version class by giving privilege
diff --git a/bfd/cpu-riscv.h b/bfd/cpu-riscv.h
index ed5ee7e60d5..b251d6312b8 100644
--- a/bfd/cpu-riscv.h
+++ b/bfd/cpu-riscv.h
@@ -32,6 +32,7 @@ enum riscv_spec_class
PRIV_SPEC_CLASS_1P9P1,
PRIV_SPEC_CLASS_1P10,
PRIV_SPEC_CLASS_1P11,
+ PRIV_SPEC_CLASS_1P12,
PRIV_SPEC_CLASS_DRAFT,
};
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index e8061217e7c..8bc48d77747 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -4167,7 +4167,7 @@ RISC-V options:\n\
-fno-pic don't generate position-independent code (default)\n\
-march=ISA set the RISC-V architecture\n\
-misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
- -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9.1, 1.10, 1.11)\n\
+ -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9.1, 1.10, 1.11, 1.12)\n\
-mabi=ABI set the RISC-V ABI\n\
-mrelax enable relax (default)\n\
-mno-relax disable relax\n\
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
index de17ad81fbd..efcbdc6d5fb 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
@@ -1,4 +1,4 @@
-#as: -march=rv32if -mpriv-spec=1.11
+#as: -march=rv32if -mpriv-spec=1.12
#objdump: --dwarf=frames
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
index ec206e4d6d1..aaf1206cc39 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
@@ -1,3 +1,3 @@
-#as: -march=rv32if -mcsr-check -mpriv-spec=1.11
+#as: -march=rv32if -mcsr-check -mpriv-spec=1.12
#source: priv-reg-fail-read-only-02.s
#warning_output: priv-reg-fail-read-only-02.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
index a1f27ec0622..3edf5e0d5ee 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
@@ -1,3 +1,3 @@
-#as: -I$srcdir/$subdir -march=rv64if -mcsr-check
+#as: -I$srcdir/$subdir -march=rv64if -mcsr-check -mpriv-spec=1.12
#source: priv-reg.s
#warning_output: priv-reg-fail-rv32-only.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.d
new file mode 100644
index 00000000000..97b04d1ee6c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.d
@@ -0,0 +1,11 @@
+#as: -I$srcdir/$subdir -march=rv32ifv_zkr -mcsr-check -mpriv-spec=1.12 -march-attr
+#source: priv-reg.s
+#warning_output: priv-reg-fail-version-1p12.l
+#readelf: -A
+
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: [a-zA-Z0-9_\"].*
+ Tag_RISCV_priv_spec: 1
+ Tag_RISCV_priv_spec_minor: 12
+#...
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.l b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.l
new file mode 100644
index 00000000000..9b9c9aa2f3e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.l
@@ -0,0 +1,24 @@
+.*Assembler messages:
+.*Warning: invalid CSR `ubadaddr' for the privileged spec `1.12'
+.*Warning: invalid CSR `sbadaddr' for the privileged spec `1.12'
+.*Warning: invalid CSR `sptbr' for the privileged spec `1.12'
+.*Warning: invalid CSR `mbadaddr' for the privileged spec `1.12'
+.*Warning: invalid CSR `mucounteren' for the privileged spec `1.12'
+.*Warning: invalid CSR `hstatus' for the privileged spec `1.12'
+.*Warning: invalid CSR `hedeleg' for the privileged spec `1.12'
+.*Warning: invalid CSR `hideleg' for the privileged spec `1.12'
+.*Warning: invalid CSR `hie' for the privileged spec `1.12'
+.*Warning: invalid CSR `htvec' for the privileged spec `1.12'
+.*Warning: invalid CSR `hscratch' for the privileged spec `1.12'
+.*Warning: invalid CSR `hepc' for the privileged spec `1.12'
+.*Warning: invalid CSR `hcause' for the privileged spec `1.12'
+.*Warning: invalid CSR `hbadaddr' for the privileged spec `1.12'
+.*Warning: invalid CSR `hip' for the privileged spec `1.12'
+.*Warning: invalid CSR `mbase' for the privileged spec `1.12'
+.*Warning: invalid CSR `mbound' for the privileged spec `1.12'
+.*Warning: invalid CSR `mibase' for the privileged spec `1.12'
+.*Warning: invalid CSR `mibound' for the privileged spec `1.12'
+.*Warning: invalid CSR `mdbase' for the privileged spec `1.12'
+.*Warning: invalid CSR `mdbound' for the privileged spec `1.12'
+.*Warning: invalid CSR `mscounteren' for the privileged spec `1.12'
+.*Warning: invalid CSR `mhcounteren' for the privileged spec `1.12'
diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p12.d b/gas/testsuite/gas/riscv/priv-reg-version-1p12.d
new file mode 100644
index 00000000000..87af71dd65d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p12.d
@@ -0,0 +1,275 @@
+#as: -I$srcdir/$subdir -march=rv32if -mpriv-spec=1.12
+#source: priv-reg.s
+#objdump: -dr -Mpriv-spec=1.12
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+00002573[ ]+csrr[ ]+a0,ustatus
+[ ]+[0-9a-f]+:[ ]+00402573[ ]+csrr[ ]+a0,uie
+[ ]+[0-9a-f]+:[ ]+00502573[ ]+csrr[ ]+a0,utvec
+[ ]+[0-9a-f]+:[ ]+04002573[ ]+csrr[ ]+a0,uscratch
+[ ]+[0-9a-f]+:[ ]+04102573[ ]+csrr[ ]+a0,uepc
+[ ]+[0-9a-f]+:[ ]+04202573[ ]+csrr[ ]+a0,ucause
+[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval
+[ ]+[0-9a-f]+:[ ]+04402573[ ]+csrr[ ]+a0,uip
+[ ]+[0-9a-f]+:[ ]+c0002573[ ]+rdcycle[ ]+a0
+[ ]+[0-9a-f]+:[ ]+c0102573[ ]+rdtime[ ]+a0
+[ ]+[0-9a-f]+:[ ]+c0202573[ ]+rdinstret[ ]+a0
+[ ]+[0-9a-f]+:[ ]+c0302573[ ]+csrr[ ]+a0,hpmcounter3
+[ ]+[0-9a-f]+:[ ]+c0402573[ ]+csrr[ ]+a0,hpmcounter4
+[ ]+[0-9a-f]+:[ ]+c0502573[ ]+csrr[ ]+a0,hpmcounter5
+[ ]+[0-9a-f]+:[ ]+c0602573[ ]+csrr[ ]+a0,hpmcounter6
+[ ]+[0-9a-f]+:[ ]+c0702573[ ]+csrr[ ]+a0,hpmcounter7
+[ ]+[0-9a-f]+:[ ]+c0802573[ ]+csrr[ ]+a0,hpmcounter8
+[ ]+[0-9a-f]+:[ ]+c0902573[ ]+csrr[ ]+a0,hpmcounter9
+[ ]+[0-9a-f]+:[ ]+c0a02573[ ]+csrr[ ]+a0,hpmcounter10
+[ ]+[0-9a-f]+:[ ]+c0b02573[ ]+csrr[ ]+a0,hpmcounter11
+[ ]+[0-9a-f]+:[ ]+c0c02573[ ]+csrr[ ]+a0,hpmcounter12
+[ ]+[0-9a-f]+:[ ]+c0d02573[ ]+csrr[ ]+a0,hpmcounter13
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+[ ]+[0-9a-f]+:[ ]+c1a02573[ ]+csrr[ ]+a0,hpmcounter26
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+[ ]+[0-9a-f]+:[ ]+c1d02573[ ]+csrr[ ]+a0,hpmcounter29
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+[ ]+[0-9a-f]+:[ ]+c1f02573[ ]+csrr[ ]+a0,hpmcounter31
+[ ]+[0-9a-f]+:[ ]+c8002573[ ]+rdcycleh[ ]+a0
+[ ]+[0-9a-f]+:[ ]+c8102573[ ]+rdtimeh[ ]+a0
+[ ]+[0-9a-f]+:[ ]+c8202573[ ]+rdinstreth[ ]+a0
+[ ]+[0-9a-f]+:[ ]+c8302573[ ]+csrr[ ]+a0,hpmcounter3h
+[ ]+[0-9a-f]+:[ ]+c8402573[ ]+csrr[ ]+a0,hpmcounter4h
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+[ ]+[0-9a-f]+:[ ]+c8e02573[ ]+csrr[ ]+a0,hpmcounter14h
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+[ ]+[0-9a-f]+:[ ]+c9002573[ ]+csrr[ ]+a0,hpmcounter16h
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+[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp
+[ ]+[0-9a-f]+:[ ]+f1102573[ ]+csrr[ ]+a0,mvendorid
+[ ]+[0-9a-f]+:[ ]+f1202573[ ]+csrr[ ]+a0,marchid
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+[ ]+[0-9a-f]+:[ ]+30402573[ ]+csrr[ ]+a0,mie
+[ ]+[0-9a-f]+:[ ]+30502573[ ]+csrr[ ]+a0,mtvec
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+[ ]+[0-9a-f]+:[ ]+34402573[ ]+csrr[ ]+a0,mip
+[ ]+[0-9a-f]+:[ ]+3a002573[ ]+csrr[ ]+a0,pmpcfg0
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+[ ]+[0-9a-f]+:[ ]+3a202573[ ]+csrr[ ]+a0,pmpcfg2
+[ ]+[0-9a-f]+:[ ]+3a302573[ ]+csrr[ ]+a0,pmpcfg3
+[ ]+[0-9a-f]+:[ ]+3b002573[ ]+csrr[ ]+a0,pmpaddr0
+[ ]+[0-9a-f]+:[ ]+3b102573[ ]+csrr[ ]+a0,pmpaddr1
+[ ]+[0-9a-f]+:[ ]+3b202573[ ]+csrr[ ]+a0,pmpaddr2
+[ ]+[0-9a-f]+:[ ]+3b302573[ ]+csrr[ ]+a0,pmpaddr3
+[ ]+[0-9a-f]+:[ ]+3b402573[ ]+csrr[ ]+a0,pmpaddr4
+[ ]+[0-9a-f]+:[ ]+3b502573[ ]+csrr[ ]+a0,pmpaddr5
+[ ]+[0-9a-f]+:[ ]+3b602573[ ]+csrr[ ]+a0,pmpaddr6
+[ ]+[0-9a-f]+:[ ]+3b702573[ ]+csrr[ ]+a0,pmpaddr7
+[ ]+[0-9a-f]+:[ ]+3b802573[ ]+csrr[ ]+a0,pmpaddr8
+[ ]+[0-9a-f]+:[ ]+3b902573[ ]+csrr[ ]+a0,pmpaddr9
+[ ]+[0-9a-f]+:[ ]+3ba02573[ ]+csrr[ ]+a0,pmpaddr10
+[ ]+[0-9a-f]+:[ ]+3bb02573[ ]+csrr[ ]+a0,pmpaddr11
+[ ]+[0-9a-f]+:[ ]+3bc02573[ ]+csrr[ ]+a0,pmpaddr12
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+[ ]+[0-9a-f]+:[ ]+3be02573[ ]+csrr[ ]+a0,pmpaddr14
+[ ]+[0-9a-f]+:[ ]+3bf02573[ ]+csrr[ ]+a0,pmpaddr15
+[ ]+[0-9a-f]+:[ ]+b0002573[ ]+csrr[ ]+a0,mcycle
+[ ]+[0-9a-f]+:[ ]+b0202573[ ]+csrr[ ]+a0,minstret
+[ ]+[0-9a-f]+:[ ]+b0302573[ ]+csrr[ ]+a0,mhpmcounter3
+[ ]+[0-9a-f]+:[ ]+b0402573[ ]+csrr[ ]+a0,mhpmcounter4
+[ ]+[0-9a-f]+:[ ]+b0502573[ ]+csrr[ ]+a0,mhpmcounter5
+[ ]+[0-9a-f]+:[ ]+b0602573[ ]+csrr[ ]+a0,mhpmcounter6
+[ ]+[0-9a-f]+:[ ]+b0702573[ ]+csrr[ ]+a0,mhpmcounter7
+[ ]+[0-9a-f]+:[ ]+b0802573[ ]+csrr[ ]+a0,mhpmcounter8
+[ ]+[0-9a-f]+:[ ]+b0902573[ ]+csrr[ ]+a0,mhpmcounter9
+[ ]+[0-9a-f]+:[ ]+b0a02573[ ]+csrr[ ]+a0,mhpmcounter10
+[ ]+[0-9a-f]+:[ ]+b0b02573[ ]+csrr[ ]+a0,mhpmcounter11
+[ ]+[0-9a-f]+:[ ]+b0c02573[ ]+csrr[ ]+a0,mhpmcounter12
+[ ]+[0-9a-f]+:[ ]+b0d02573[ ]+csrr[ ]+a0,mhpmcounter13
+[ ]+[0-9a-f]+:[ ]+b0e02573[ ]+csrr[ ]+a0,mhpmcounter14
+[ ]+[0-9a-f]+:[ ]+b0f02573[ ]+csrr[ ]+a0,mhpmcounter15
+[ ]+[0-9a-f]+:[ ]+b1002573[ ]+csrr[ ]+a0,mhpmcounter16
+[ ]+[0-9a-f]+:[ ]+b1102573[ ]+csrr[ ]+a0,mhpmcounter17
+[ ]+[0-9a-f]+:[ ]+b1202573[ ]+csrr[ ]+a0,mhpmcounter18
+[ ]+[0-9a-f]+:[ ]+b1302573[ ]+csrr[ ]+a0,mhpmcounter19
+[ ]+[0-9a-f]+:[ ]+b1402573[ ]+csrr[ ]+a0,mhpmcounter20
+[ ]+[0-9a-f]+:[ ]+b1502573[ ]+csrr[ ]+a0,mhpmcounter21
+[ ]+[0-9a-f]+:[ ]+b1602573[ ]+csrr[ ]+a0,mhpmcounter22
+[ ]+[0-9a-f]+:[ ]+b1702573[ ]+csrr[ ]+a0,mhpmcounter23
+[ ]+[0-9a-f]+:[ ]+b1802573[ ]+csrr[ ]+a0,mhpmcounter24
+[ ]+[0-9a-f]+:[ ]+b1902573[ ]+csrr[ ]+a0,mhpmcounter25
+[ ]+[0-9a-f]+:[ ]+b1a02573[ ]+csrr[ ]+a0,mhpmcounter26
+[ ]+[0-9a-f]+:[ ]+b1b02573[ ]+csrr[ ]+a0,mhpmcounter27
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+[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
--
2.32.0
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 0/3] RISC-V: Prepare Privileged Architecture 1.12
2021-12-24 3:22 [PATCH v2 0/3] RISC-V: Prepare Privileged Architecture 1.12 Tsukasa OI
` (2 preceding siblings ...)
2021-12-24 3:22 ` [PATCH v2 3/3] RISC-V: Add Privileged Architecture version 1.12 Tsukasa OI
@ 2022-02-21 13:21 ` Jan Beulich
2022-02-21 13:38 ` Tsukasa OI
3 siblings, 1 reply; 7+ messages in thread
From: Jan Beulich @ 2022-02-21 13:21 UTC (permalink / raw)
To: Tsukasa OI, Nelson Chu; +Cc: binutils, Vineet Gupta
On 24.12.2021 04:22, Tsukasa OI via Binutils wrote:
> Tsukasa OI (3):
> RISC-V: Make testcase indentation consistent
> RISC-V: Unify "access all CSRs" testcases
> RISC-V: Add Privileged Architecture version 1.12
>
> bfd/cpu-riscv.c | 1 +
> bfd/cpu-riscv.h | 1 +
> gas/config/tc-riscv.c | 2 +-
> gas/testsuite/gas/riscv/csr-dw-regnums.d | 2 +-
> gas/testsuite/gas/riscv/option-arch-01a.d | 8 +-
> gas/testsuite/gas/riscv/priv-reg-access-all.s | 292 ++++++++++
> gas/testsuite/gas/riscv/priv-reg-fail-fext.d | 2 +-
> .../gas/riscv/priv-reg-fail-read-only-01.d | 2 +-
> .../gas/riscv/priv-reg-fail-read-only-01.s | 267 +--------
> .../gas/riscv/priv-reg-fail-read-only-02.d | 2 +-
> .../gas/riscv/priv-reg-fail-rv32-only.d | 2 +-
> .../gas/riscv/priv-reg-fail-version-1p10.d | 2 +-
> .../gas/riscv/priv-reg-fail-version-1p11.d | 2 +-
> .../gas/riscv/priv-reg-fail-version-1p12.d | 11 +
> .../gas/riscv/priv-reg-fail-version-1p12.l | 24 +
> .../gas/riscv/priv-reg-fail-version-1p9p1.d | 2 +-
> gas/testsuite/gas/riscv/priv-reg-fail-zkr.d | 2 +-
> .../gas/riscv/priv-reg-version-1p10.d | 534 +++++++++---------
> .../gas/riscv/priv-reg-version-1p11.d | 534 +++++++++---------
> .../gas/riscv/priv-reg-version-1p12.d | 275 +++++++++
Comparing with the spec I find SCONTEXT still is numbered 0x7aa in here,
when the doc says 0x5a8. Was this overlooked? Or is the doc wrong?
Jan
> .../gas/riscv/priv-reg-version-1p9p1.d | 534 +++++++++---------
> gas/testsuite/gas/riscv/priv-reg.s | 294 +---------
> 22 files changed, 1421 insertions(+), 1374 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-access-all.s
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.l
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p12.d
>
>
> base-commit: d20236e748ab70e9243960850eef64838f1b9721
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 0/3] RISC-V: Prepare Privileged Architecture 1.12
2022-02-21 13:21 ` [PATCH v2 0/3] RISC-V: Prepare Privileged Architecture 1.12 Jan Beulich
@ 2022-02-21 13:38 ` Tsukasa OI
2022-02-21 13:49 ` Tsukasa OI
0 siblings, 1 reply; 7+ messages in thread
From: Tsukasa OI @ 2022-02-21 13:38 UTC (permalink / raw)
To: Jan Beulich; +Cc: Binutils, Vineet Gupta
On 2022/02/21 22:21, Jan Beulich wrote:
> On 24.12.2021 04:22, Tsukasa OI via Binutils wrote:
>> Tsukasa OI (3):
>> RISC-V: Make testcase indentation consistent
>> RISC-V: Unify "access all CSRs" testcases
>> RISC-V: Add Privileged Architecture version 1.12
>>
>> bfd/cpu-riscv.c | 1 +
>> bfd/cpu-riscv.h | 1 +
>> gas/config/tc-riscv.c | 2 +-
>> gas/testsuite/gas/riscv/csr-dw-regnums.d | 2 +-
>> gas/testsuite/gas/riscv/option-arch-01a.d | 8 +-
>> gas/testsuite/gas/riscv/priv-reg-access-all.s | 292 ++++++++++
>> gas/testsuite/gas/riscv/priv-reg-fail-fext.d | 2 +-
>> .../gas/riscv/priv-reg-fail-read-only-01.d | 2 +-
>> .../gas/riscv/priv-reg-fail-read-only-01.s | 267 +--------
>> .../gas/riscv/priv-reg-fail-read-only-02.d | 2 +-
>> .../gas/riscv/priv-reg-fail-rv32-only.d | 2 +-
>> .../gas/riscv/priv-reg-fail-version-1p10.d | 2 +-
>> .../gas/riscv/priv-reg-fail-version-1p11.d | 2 +-
>> .../gas/riscv/priv-reg-fail-version-1p12.d | 11 +
>> .../gas/riscv/priv-reg-fail-version-1p12.l | 24 +
>> .../gas/riscv/priv-reg-fail-version-1p9p1.d | 2 +-
>> gas/testsuite/gas/riscv/priv-reg-fail-zkr.d | 2 +-
>> .../gas/riscv/priv-reg-version-1p10.d | 534 +++++++++---------
>> .../gas/riscv/priv-reg-version-1p11.d | 534 +++++++++---------
>> .../gas/riscv/priv-reg-version-1p12.d | 275 +++++++++
>
> Comparing with the spec I find SCONTEXT still is numbered 0x7aa in here,
> when the doc says 0x5a8. Was this overlooked? Or is the doc wrong?
>
> Jan
You pointed out that right but still, this is intentional.
In PATCH 3/6 commit message, I wrote:
> (except moved "scontext" and
> new "mscontext").
Because `scontext' is a part of debug specification (NOT privileged
specification), I thought it should be controlled by debug specification
version option like one proposed by Nelson Chu:
<https://sourceware.org/pipermail/binutils/2021-August/117568.html>
Note that debug specification 1.0 (with moved `scontext' and new
`mscontext') is not ratified yet.
<https://github.com/riscv/riscv-debug-spec/commit/b659d7dc7f578e1a2a76f9e62a5eec0f2d80045c>
Tsukasa
>
>> .../gas/riscv/priv-reg-version-1p9p1.d | 534 +++++++++---------
>> gas/testsuite/gas/riscv/priv-reg.s | 294 +---------
>> 22 files changed, 1421 insertions(+), 1374 deletions(-)
>> create mode 100644 gas/testsuite/gas/riscv/priv-reg-access-all.s
>> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.d
>> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.l
>> create mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p12.d
>>
>>
>> base-commit: d20236e748ab70e9243960850eef64838f1b9721
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 0/3] RISC-V: Prepare Privileged Architecture 1.12
2022-02-21 13:38 ` Tsukasa OI
@ 2022-02-21 13:49 ` Tsukasa OI
0 siblings, 0 replies; 7+ messages in thread
From: Tsukasa OI @ 2022-02-21 13:49 UTC (permalink / raw)
To: Jan Beulich; +Cc: Vineet Gupta, Binutils
Ah, I forgot to note.
The original Privileged Architecture 1.12 patchsets:
<https://sourceware.org/pipermail/binutils/2021-December/119004.html> (v1)
<https://sourceware.org/pipermail/binutils/2021-December/119008.html> (v2)
are superseded by the latest one:
<https://sourceware.org/pipermail/binutils/2022-January/119282.html> (CSR only v1)
... as Privileged Architecture 1.12 itself is implemented as a part of
hypervisor support (this is merged into master):
<https://sourceware.org/pipermail/binutils/2021-December/118980.html>
Thanks,
Tsukasa
On 2022/02/21 22:38, Tsukasa OI via Binutils wrote:
> On 2022/02/21 22:21, Jan Beulich wrote:
>> On 24.12.2021 04:22, Tsukasa OI via Binutils wrote:
>>> Tsukasa OI (3):
>>> RISC-V: Make testcase indentation consistent
>>> RISC-V: Unify "access all CSRs" testcases
>>> RISC-V: Add Privileged Architecture version 1.12
>>>
>>> bfd/cpu-riscv.c | 1 +
>>> bfd/cpu-riscv.h | 1 +
>>> gas/config/tc-riscv.c | 2 +-
>>> gas/testsuite/gas/riscv/csr-dw-regnums.d | 2 +-
>>> gas/testsuite/gas/riscv/option-arch-01a.d | 8 +-
>>> gas/testsuite/gas/riscv/priv-reg-access-all.s | 292 ++++++++++
>>> gas/testsuite/gas/riscv/priv-reg-fail-fext.d | 2 +-
>>> .../gas/riscv/priv-reg-fail-read-only-01.d | 2 +-
>>> .../gas/riscv/priv-reg-fail-read-only-01.s | 267 +--------
>>> .../gas/riscv/priv-reg-fail-read-only-02.d | 2 +-
>>> .../gas/riscv/priv-reg-fail-rv32-only.d | 2 +-
>>> .../gas/riscv/priv-reg-fail-version-1p10.d | 2 +-
>>> .../gas/riscv/priv-reg-fail-version-1p11.d | 2 +-
>>> .../gas/riscv/priv-reg-fail-version-1p12.d | 11 +
>>> .../gas/riscv/priv-reg-fail-version-1p12.l | 24 +
>>> .../gas/riscv/priv-reg-fail-version-1p9p1.d | 2 +-
>>> gas/testsuite/gas/riscv/priv-reg-fail-zkr.d | 2 +-
>>> .../gas/riscv/priv-reg-version-1p10.d | 534 +++++++++---------
>>> .../gas/riscv/priv-reg-version-1p11.d | 534 +++++++++---------
>>> .../gas/riscv/priv-reg-version-1p12.d | 275 +++++++++
>>
>> Comparing with the spec I find SCONTEXT still is numbered 0x7aa in here,
>> when the doc says 0x5a8. Was this overlooked? Or is the doc wrong?
>>
>> Jan
>
> You pointed out that right but still, this is intentional.
>
> In PATCH 3/6 commit message, I wrote:
>> (except moved "scontext" and
>> new "mscontext").
>
> Because `scontext' is a part of debug specification (NOT privileged
> specification), I thought it should be controlled by debug specification
> version option like one proposed by Nelson Chu:
>
> <https://sourceware.org/pipermail/binutils/2021-August/117568.html>
>
> Note that debug specification 1.0 (with moved `scontext' and new
> `mscontext') is not ratified yet.
>
> <https://github.com/riscv/riscv-debug-spec/commit/b659d7dc7f578e1a2a76f9e62a5eec0f2d80045c>
>
> Tsukasa
>
>>
>>> .../gas/riscv/priv-reg-version-1p9p1.d | 534 +++++++++---------
>>> gas/testsuite/gas/riscv/priv-reg.s | 294 +---------
>>> 22 files changed, 1421 insertions(+), 1374 deletions(-)
>>> create mode 100644 gas/testsuite/gas/riscv/priv-reg-access-all.s
>>> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.d
>>> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.l
>>> create mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p12.d
>>>
>>>
>>> base-commit: d20236e748ab70e9243960850eef64838f1b9721
>>
>
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2021-12-24 3:22 [PATCH v2 0/3] RISC-V: Prepare Privileged Architecture 1.12 Tsukasa OI
2021-12-24 3:22 ` [PATCH v2 1/3] RISC-V: Make testcase indentation consistent Tsukasa OI
2021-12-24 3:22 ` [PATCH v2 2/3] RISC-V: Unify "access all CSRs" testcases Tsukasa OI
2021-12-24 3:22 ` [PATCH v2 3/3] RISC-V: Add Privileged Architecture version 1.12 Tsukasa OI
2022-02-21 13:21 ` [PATCH v2 0/3] RISC-V: Prepare Privileged Architecture 1.12 Jan Beulich
2022-02-21 13:38 ` Tsukasa OI
2022-02-21 13:49 ` Tsukasa OI
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