From: Jan Beulich <jbeulich@suse.com>
To: Binutils <binutils@sourceware.org>
Subject: [PATCH 03/12] x86: fold AVX VGATHERDPD / VPGATHERDQ
Date: Fri, 5 Aug 2022 14:20:52 +0200 [thread overview]
Message-ID: <f1dd22f8-9a56-734d-d3c4-938e913a4b8d@suse.com> (raw)
In-Reply-To: <b45b6c58-e06a-2cef-ad97-0cb7956d3fd5@suse.com>
While the other three variants each differ in attributes and hence can't
be folded, these two pairs actually can be (and were previously
overlooked). This effectively matches their AVX512VL counterparts, which
are also expressed as a single template.
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -1827,8 +1827,7 @@ vpsrlvd, 0x6645, None, CpuAVX2, Modrm|Ve
vpsrlvq, 0x6645, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV=1|VexW=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
// AVX gather instructions
-vgatherdpd, 0x6692, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Qword|Unspecified|BaseIndex, RegXMM }
-vgatherdpd, 0x6692, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM }
+vgatherdpd, 0x6692, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM }
vgatherdps, 0x6692, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
vgatherdps, 0x6692, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM }
vgatherqpd, 0x6693, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Qword|Unspecified|BaseIndex, RegXMM }
@@ -1837,8 +1836,7 @@ vgatherqps, 0x6693, None, CpuAVX2, Modrm
vgatherqps, 0x6693, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
vpgatherdd, 0x6690, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
vpgatherdd, 0x6690, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM }
-vpgatherdq, 0x6690, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Qword|Unspecified|BaseIndex, RegXMM }
-vpgatherdq, 0x6690, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM }
+vpgatherdq, 0x6690, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM }
vpgatherqd, 0x6691, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
vpgatherqd, 0x6691, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
vpgatherqq, 0x6691, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Qword|Unspecified|BaseIndex, RegXMM }
next prev parent reply other threads:[~2022-08-05 12:20 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-05 12:17 [PATCH 00/12] x86: more templatization of insn templates Jan Beulich
2022-08-05 12:19 ` [PATCH 01/12] x86/Intel: split certain AVX512-FP16 VCVT*2PH templates Jan Beulich
2022-08-05 22:28 ` H.J. Lu
2022-08-05 12:20 ` [PATCH 02/12] x86: allow use of broadcast with X/Y/Z-suffixed AVX512-FP16 insns Jan Beulich
2022-08-05 22:31 ` H.J. Lu
2022-08-05 12:20 ` Jan Beulich [this message]
2022-08-05 22:32 ` [PATCH 03/12] x86: fold AVX VGATHERDPD / VPGATHERDQ H.J. Lu
2022-08-05 12:21 ` [PATCH 04/12] x86: adjust MOVSD attributes Jan Beulich
2022-08-05 22:46 ` H.J. Lu
2022-08-05 12:22 ` [PATCH 05/12] x86-64: adjust MOVQ to/from SReg attributes Jan Beulich
2022-08-05 23:00 ` H.J. Lu
2022-08-05 12:23 ` [PATCH 06/12] revert "x86: Also pass -P to $(CPP) when processing i386-opc.tbl" Jan Beulich
2022-08-05 23:17 ` H.J. Lu
2022-08-09 7:22 ` Jan Beulich
2022-08-08 12:49 ` Michael Matz
2022-08-09 7:33 ` Jan Beulich
2022-08-11 16:40 ` H.J. Lu
2022-08-05 12:24 ` [PATCH 07/12] x86: template-ize packed/scalar vector floating point insns Jan Beulich
2022-08-05 23:07 ` H.J. Lu
2022-08-11 1:12 ` Jiang, Haochen
2022-08-11 6:03 ` Jan Beulich
2022-08-11 16:38 ` H.J. Lu
2022-08-05 12:25 ` [PATCH 08/12] x86: template-ize vector packed dword/qword integer insns Jan Beulich
2022-08-11 17:23 ` H.J. Lu
2022-08-16 7:37 ` Jan Beulich
2022-08-16 15:53 ` H.J. Lu
2022-08-16 16:20 ` Jan Beulich
2022-08-16 16:32 ` H.J. Lu
2022-08-05 12:26 ` [PATCH 09/12] x86: re-order AVX512 S/G templates Jan Beulich
2022-08-11 17:24 ` H.J. Lu
2022-08-05 12:27 ` [PATCH 10/12] x86: template-ize vector packed byte/word integer insns Jan Beulich
2022-08-11 17:38 ` H.J. Lu
2022-08-05 12:28 ` [PATCH 11/12] x86: template-ize certain vector conversion insns Jan Beulich
2022-08-11 17:48 ` H.J. Lu
2022-08-05 12:29 ` [PATCH 12/12] x86: shorten certain template names Jan Beulich
2022-08-11 17:49 ` H.J. Lu
2022-08-12 11:33 ` [PATCH v1.1 06/12] revert "x86: Also pass -P to $(CPP) when processing i386-opc.tbl" Jan Beulich
2022-08-15 18:11 ` H.J. Lu
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