From: "H.J. Lu" <hjl.tools@gmail.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: Binutils <binutils@sourceware.org>
Subject: Re: [PATCH 05/12] x86-64: adjust MOVQ to/from SReg attributes
Date: Fri, 5 Aug 2022 16:00:39 -0700 [thread overview]
Message-ID: <CAMe9rOr5d2M38xNHh_wuX4Tm2Ji-5kpZu8rBXywWXygZenccLw@mail.gmail.com> (raw)
In-Reply-To: <03949571-5dbb-f6c1-e2fb-9fbbd8c4b54c@suse.com>
On Fri, Aug 5, 2022 at 5:22 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> It is unclear to me why the corresponding MOV (no Q suffix) can be
> issued without REX.W, but MOVQ has to have that prefix (bit). Add
> NoRex64 and in exchange drop Size64.
>
> --- a/gas/testsuite/gas/i386/x86-64-segment.l
> +++ b/gas/testsuite/gas/i386/x86-64-segment.l
> @@ -5,8 +5,15 @@
> 5 0002 8C18 mov %ds,\(%rax\)
> 6 0004 8E18 movw \(%rax\),%ds
> 7 0006 8E18 mov \(%rax\),%ds
> - 8 # test segment reg insns with REX
> - 9 0008 488CD8 movq %ds,%rax
> - 10 000b 488ED8 movq %rax,%ds
> - 11 # Force a good alignment.
> - 12 000e 0000 .p2align 4,0
> + 8 # test segment reg insns with avoided REX
> + 9 0008 8CD8 mov %ds,%rax
> + 10 000a 8CD8 movq %ds,%rax
> + 11 000c 8ED8 mov %rax,%ds
> + 12 000e 8ED8 movq %rax,%ds
> + 13 # test segment reg insns with REX
> + 14 0010 418CD8 mov %ds,%r8
> + 15 0013 418CD8 movq %ds,%r8
> + 16 0016 418ED8 mov %r8,%ds
> + 17 0019 418ED8 movq %r8,%ds
> + 18 # Force a good alignment.
> + 19 001c 0+ + *\.p2align 4,0
> --- a/gas/testsuite/gas/i386/x86-64-segment.s
> +++ b/gas/testsuite/gas/i386/x86-64-segment.s
> @@ -5,8 +5,15 @@
> mov %ds,(%rax)
> movw (%rax),%ds
> mov (%rax),%ds
> -# test segment reg insns with REX
> +# test segment reg insns with avoided REX
> + mov %ds,%rax
> movq %ds,%rax
> + mov %rax,%ds
> movq %rax,%ds
> +# test segment reg insns with REX
> + mov %ds,%r8
> + movq %ds,%r8
> + mov %r8,%ds
> + movq %r8,%ds
> # Force a good alignment.
> .p2align 4,0
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -148,7 +148,7 @@ movq, 0xb8, None, Cpu64, Size64|No_bSuf|
> // implementation defined value is zero).
> mov, 0x8c, None, 0, RegMem|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { SReg, Reg16|Reg32|Reg64 }
> mov, 0x8c, None, 0, D|Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg, Word|Unspecified|BaseIndex }
> -movq, 0x8c, None, Cpu64, D|RegMem|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg, Reg64 }
> +movq, 0x8c, None, Cpu64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { SReg, Reg64 }
> mov, 0x8e, None, 0, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg16|Reg32|Reg64, SReg }
> // Move to/from control debug registers. In the 16 or 32bit modes
> // they are 32bit. In the 64bit mode they are 64bit.
>
OK.
Thanks.
--
H.J.
next prev parent reply other threads:[~2022-08-05 23:01 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-05 12:17 [PATCH 00/12] x86: more templatization of insn templates Jan Beulich
2022-08-05 12:19 ` [PATCH 01/12] x86/Intel: split certain AVX512-FP16 VCVT*2PH templates Jan Beulich
2022-08-05 22:28 ` H.J. Lu
2022-08-05 12:20 ` [PATCH 02/12] x86: allow use of broadcast with X/Y/Z-suffixed AVX512-FP16 insns Jan Beulich
2022-08-05 22:31 ` H.J. Lu
2022-08-05 12:20 ` [PATCH 03/12] x86: fold AVX VGATHERDPD / VPGATHERDQ Jan Beulich
2022-08-05 22:32 ` H.J. Lu
2022-08-05 12:21 ` [PATCH 04/12] x86: adjust MOVSD attributes Jan Beulich
2022-08-05 22:46 ` H.J. Lu
2022-08-05 12:22 ` [PATCH 05/12] x86-64: adjust MOVQ to/from SReg attributes Jan Beulich
2022-08-05 23:00 ` H.J. Lu [this message]
2022-08-05 12:23 ` [PATCH 06/12] revert "x86: Also pass -P to $(CPP) when processing i386-opc.tbl" Jan Beulich
2022-08-05 23:17 ` H.J. Lu
2022-08-09 7:22 ` Jan Beulich
2022-08-08 12:49 ` Michael Matz
2022-08-09 7:33 ` Jan Beulich
2022-08-11 16:40 ` H.J. Lu
2022-08-05 12:24 ` [PATCH 07/12] x86: template-ize packed/scalar vector floating point insns Jan Beulich
2022-08-05 23:07 ` H.J. Lu
2022-08-11 1:12 ` Jiang, Haochen
2022-08-11 6:03 ` Jan Beulich
2022-08-11 16:38 ` H.J. Lu
2022-08-05 12:25 ` [PATCH 08/12] x86: template-ize vector packed dword/qword integer insns Jan Beulich
2022-08-11 17:23 ` H.J. Lu
2022-08-16 7:37 ` Jan Beulich
2022-08-16 15:53 ` H.J. Lu
2022-08-16 16:20 ` Jan Beulich
2022-08-16 16:32 ` H.J. Lu
2022-08-05 12:26 ` [PATCH 09/12] x86: re-order AVX512 S/G templates Jan Beulich
2022-08-11 17:24 ` H.J. Lu
2022-08-05 12:27 ` [PATCH 10/12] x86: template-ize vector packed byte/word integer insns Jan Beulich
2022-08-11 17:38 ` H.J. Lu
2022-08-05 12:28 ` [PATCH 11/12] x86: template-ize certain vector conversion insns Jan Beulich
2022-08-11 17:48 ` H.J. Lu
2022-08-05 12:29 ` [PATCH 12/12] x86: shorten certain template names Jan Beulich
2022-08-11 17:49 ` H.J. Lu
2022-08-12 11:33 ` [PATCH v1.1 06/12] revert "x86: Also pass -P to $(CPP) when processing i386-opc.tbl" Jan Beulich
2022-08-15 18:11 ` H.J. Lu
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