From: "H.J. Lu" <hjl.tools@gmail.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: Binutils <binutils@sourceware.org>
Subject: Re: [PATCH 08/12] x86: template-ize vector packed dword/qword integer insns
Date: Tue, 16 Aug 2022 08:53:40 -0700 [thread overview]
Message-ID: <CAMe9rOpMXeMjLOGVk1iAuP9kHzmPg5Y6NNJ8kTaWB1DHSxsgow@mail.gmail.com> (raw)
In-Reply-To: <baaa4d68-a6ec-71a3-7ebc-c07f0f7b4f0c@suse.com>
On Tue, Aug 16, 2022 at 12:37 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 11.08.2022 19:23, H.J. Lu wrote:
> > On Fri, Aug 5, 2022 at 5:26 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> Many of the vector integer insns come in dword/qword element pairs. Most
> >> of these pairs follow certain encoding patterns. Introduce a "dq"
> >> template to reduce redundancy.
> >>
> >> Note that in the course of the conversion
> >> - a few otherwise untouched templates are moved, so they end up next to
> >> their siblings),
> >> - drop an unhelpful Cpu64 from the GPR form of VPBROADCASTQ, matching
> >> what we already have for KMOVQ - the diagnostic is better this way for
> >> insns with multiple forms (i.e. the same Cpu64 attributes on {,V}MOVQ,
> >> {,V}PEXTRQ, and {,V}PINSRQ are useful to keep),
> >> - this adds benign/meaningless IgnoreSize attributes to the GPR forms of
> >> KMOVD and VPBROADCASTD; it didn't seem worth avoiding this.
> >> ---
> >> For VPCOMPRESS{D,Q} and VPEXPAND{D,Q} the conversion could only be done
> >> if we allowed Dword/Qword on the memory operands. Imo permitting this
> >> makes sense anyway (as the memory operands aren't full [XYZ]mmword
> >> ones), but such a functional change should probably be a separate patch.
>
> Do you have any view on this and the similar remarks in two other of the
> patches in this series?
>
Since these instructions don't take Dword/Qword memory operands, please
leave them alone.
--
H.J.
next prev parent reply other threads:[~2022-08-16 15:54 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-05 12:17 [PATCH 00/12] x86: more templatization of insn templates Jan Beulich
2022-08-05 12:19 ` [PATCH 01/12] x86/Intel: split certain AVX512-FP16 VCVT*2PH templates Jan Beulich
2022-08-05 22:28 ` H.J. Lu
2022-08-05 12:20 ` [PATCH 02/12] x86: allow use of broadcast with X/Y/Z-suffixed AVX512-FP16 insns Jan Beulich
2022-08-05 22:31 ` H.J. Lu
2022-08-05 12:20 ` [PATCH 03/12] x86: fold AVX VGATHERDPD / VPGATHERDQ Jan Beulich
2022-08-05 22:32 ` H.J. Lu
2022-08-05 12:21 ` [PATCH 04/12] x86: adjust MOVSD attributes Jan Beulich
2022-08-05 22:46 ` H.J. Lu
2022-08-05 12:22 ` [PATCH 05/12] x86-64: adjust MOVQ to/from SReg attributes Jan Beulich
2022-08-05 23:00 ` H.J. Lu
2022-08-05 12:23 ` [PATCH 06/12] revert "x86: Also pass -P to $(CPP) when processing i386-opc.tbl" Jan Beulich
2022-08-05 23:17 ` H.J. Lu
2022-08-09 7:22 ` Jan Beulich
2022-08-08 12:49 ` Michael Matz
2022-08-09 7:33 ` Jan Beulich
2022-08-11 16:40 ` H.J. Lu
2022-08-05 12:24 ` [PATCH 07/12] x86: template-ize packed/scalar vector floating point insns Jan Beulich
2022-08-05 23:07 ` H.J. Lu
2022-08-11 1:12 ` Jiang, Haochen
2022-08-11 6:03 ` Jan Beulich
2022-08-11 16:38 ` H.J. Lu
2022-08-05 12:25 ` [PATCH 08/12] x86: template-ize vector packed dword/qword integer insns Jan Beulich
2022-08-11 17:23 ` H.J. Lu
2022-08-16 7:37 ` Jan Beulich
2022-08-16 15:53 ` H.J. Lu [this message]
2022-08-16 16:20 ` Jan Beulich
2022-08-16 16:32 ` H.J. Lu
2022-08-05 12:26 ` [PATCH 09/12] x86: re-order AVX512 S/G templates Jan Beulich
2022-08-11 17:24 ` H.J. Lu
2022-08-05 12:27 ` [PATCH 10/12] x86: template-ize vector packed byte/word integer insns Jan Beulich
2022-08-11 17:38 ` H.J. Lu
2022-08-05 12:28 ` [PATCH 11/12] x86: template-ize certain vector conversion insns Jan Beulich
2022-08-11 17:48 ` H.J. Lu
2022-08-05 12:29 ` [PATCH 12/12] x86: shorten certain template names Jan Beulich
2022-08-11 17:49 ` H.J. Lu
2022-08-12 11:33 ` [PATCH v1.1 06/12] revert "x86: Also pass -P to $(CPP) when processing i386-opc.tbl" Jan Beulich
2022-08-15 18:11 ` H.J. Lu
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