[RFC PATCH V2 0/4] RISC-V : Support ilp32 abi on rv64 isa

[RFC PATCH V2 0/4] RISC-V : Support ilp32 abi on rv64 isa

[Liao Shihua]

These patches support ilp32 abi on rv64 isa.
In these patches, I add a new bfd_mach, a new e_flags and a new riscv_gdbarch_features.
The difference between rv64 ilp32 and rv64 lp64 are pointer type_size, long type_size, and 
link spec.

The series kernel support in this link. 
https://lore.kernel.org/linux-riscv/20230518131013.3366406-1-guoren@kernel.org/

Liao Shihua (4):
  Remove checking when -march=rv64XX and -mabi=ilp32X
  Add support for rv64 arch using ilp32 abi
  Add rv64 ilp32 support in disassemble
  Add rv64 ilp32 support in gdb

 bfd/archures.c                                |  1 +
 bfd/bfd-in2.h                                 |  1 +
 bfd/cpu-riscv.c                               |  2 ++
 bfd/elfnn-riscv.c                             | 33 ++++++++++++-------
 binutils/readelf.c                            |  3 ++
 gas/config/tc-riscv.c                         | 23 ++++++++++---
 .../gas/riscv/mabi-fail-rv64iq-ilp32.d        |  3 --
 .../gas/riscv/mabi-fail-rv64iq-ilp32.l        |  2 --
 gdb/arch/riscv.h                              | 10 +++++-
 gdb/riscv-tdep.c                              | 20 ++++++++---
 include/elf/riscv.h                           |  3 ++
 opcodes/riscv-dis.c                           |  6 ++--
 12 files changed, 78 insertions(+), 29 deletions(-)
 delete mode 100644 gas/testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.d
 delete mode 100644 gas/testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.l

-- 
2.38.1.windows.1

[RFC PATCH 1/4] RISC-V : Remove checking when -march=rv64XX and -mabi=ilp32X

[Liao Shihua]

This patch remove check in riscv_set_abi_by_arch() when -march=rv64XX and -mabi=ilp32X


gas/ChangeLog:

        * config/tc-riscv.c (riscv_set_abi_by_arch): Remove check.
        * testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.d: Removed.
        * testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.l: Removed.

---
 gas/config/tc-riscv.c                            | 2 +-
 gas/testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.d | 3 ---
 gas/testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.l | 2 --
 3 files changed, 1 insertion(+), 6 deletions(-)
 delete mode 100644 gas/testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.d
 delete mode 100644 gas/testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.l

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 0cc2484b049..99903deccec 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -379,7 +379,7 @@ riscv_set_abi_by_arch (void)
       gas_assert (abi_xlen != 0 && xlen != 0 && float_abi != FLOAT_ABI_DEFAULT);
       if (abi_xlen > xlen)
 	as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen);
-      else if (abi_xlen < xlen)
+      else if (abi_xlen < xlen && (abi_xlen != 32 && xlen != 64))
 	as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen);
 
       if (riscv_subset_supports (&riscv_rps_as, "e") && !rve_abi)
diff --git a/gas/testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.d b/gas/testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.d
deleted file mode 100644
index e3155f48956..00000000000
--- a/gas/testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march-attr -mabi=ilp32
-#source: mabi-attr-rv64iq.s
-#error_output: mabi-fail-rv64iq-ilp32.l
diff --git a/gas/testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.l b/gas/testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.l
deleted file mode 100644
index 8d45a07fd36..00000000000
--- a/gas/testsuite/gas/riscv/mabi-fail-rv64iq-ilp32.l
+++ /dev/null
@@ -1,2 +0,0 @@
-.*Assembler messages:
-.*Error: 32-bit ABI not yet supported on 64-bit ISA
-- 
2.38.1.windows.1

[RFC PATCH 2/4] RISC-V : Add support for rv64 arch using ilp32 abi

[Liao Shihua]

This patch add a new bfd_mach bfd_mach_riscv64x32 and a new e_flags X32.
bfd_mach_riscv64x32 has the same bits in a word/address and ARCH_SIZE with rv32, but use rv64's
PRSTATUS. X32 use the 6th bit of e_flags layout.
In addition, this patch replace xlen with abi_xlen in riscv_target_format().

Thanks for Jim Wilson's help.

bfd/ChangeLog:

        * archures.c: Add bfd_mach_riscv64x32.
        * bfd-in2.h (bfd_mach_riscv64x32): Likewise.
        * cpu-riscv.c:Likewise.
        * elfnn-riscv.c (ABI_X32_P): Add a flag when used x32.
        (perform_relocation): Check relocation. 
        (riscv_merge_arch_attr_info): Remove elf check when use x32.
        (_bfd_riscv_elf_merge_private_bfd_data):Allow linking X32 flag.
        (_bfd_riscv_relax_call):Check relocation. 
        (_bfd_riscv_relax_section):Check relocation. 
        (riscv_elf_object_p): Set bfd_default_set_arch_mach 
        is bfd_mach_riscv64x32 when use x32.

binutils/ChangeLog:

        * readelf.c (get_machine_flags): 

gas/ChangeLog:

        * config/tc-riscv.c (riscv_set_x32):Add X32 flag when use X32.
        (riscv_set_abi_by_arch):
        (riscv_target_format):init target_format by abi_xlen
        (md_begin):set mach.
        (s_riscv_attribute):Likewise

include/ChangeLog:

        * elf/riscv.h (EF_RISCV_X32):Add e_flags X32.

---
 bfd/archures.c        |  1 +
 bfd/bfd-in2.h         |  1 +
 bfd/cpu-riscv.c       |  2 ++
 bfd/elfnn-riscv.c     | 33 ++++++++++++++++++++++-----------
 binutils/readelf.c    |  3 +++
 gas/config/tc-riscv.c | 21 +++++++++++++++++----
 include/elf/riscv.h   |  3 +++
 7 files changed, 49 insertions(+), 15 deletions(-)

diff --git a/bfd/archures.c b/bfd/archures.c
index 6fe8701b412..fb3554d253a 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -447,6 +447,7 @@ DESCRIPTION
 .  bfd_arch_riscv,
 .#define bfd_mach_riscv32	132
 .#define bfd_mach_riscv64	164
+.#define bfd_mach_riscv64x32	16432
 .  bfd_arch_rl78,
 .#define bfd_mach_rl78		0x75
 .  bfd_arch_rx,	       {* Renesas RX.  *}
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 7be18db20a8..c0615d3aeed 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1700,6 +1700,7 @@ enum bfd_architecture
   bfd_arch_riscv,
 #define bfd_mach_riscv32       132
 #define bfd_mach_riscv64       164
+#define bfd_mach_riscv64x32    16432
   bfd_arch_rl78,
 #define bfd_mach_rl78          0x75
   bfd_arch_rx,        /* Renesas RX.  */
diff --git a/bfd/cpu-riscv.c b/bfd/cpu-riscv.c
index a478797da69..38b7eb4a7b5 100644
--- a/bfd/cpu-riscv.c
+++ b/bfd/cpu-riscv.c
@@ -86,6 +86,7 @@ riscv_scan (const struct bfd_arch_info *info, const char *string)
 enum
 {
   I_riscv64,
+  I_riscv64x32,
   I_riscv32
 };
 
@@ -96,6 +97,7 @@ enum
 static const bfd_arch_info_type arch_info_struct[] =
 {
   N (64, bfd_mach_riscv64, "riscv:rv64", false, NN (I_riscv64)),
+  N (32, bfd_mach_riscv64x32, "riscv:rv64", false, NN (I_riscv64x32)),
   N (32, bfd_mach_riscv32, "riscv:rv32", false, NULL)
 };
 
diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index a23b91ac15c..f1f72e9bd35 100644
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -122,6 +122,11 @@
 
 #define RISCV_ELF_WORD_BYTES (1 << RISCV_ELF_LOG_WORD_BYTES)
 
+#define ABI_X32_P(abfd) \
+  ((elf_elfheader (abfd)->e_flags & EF_RISCV_X32) != 0)
+
+static bool ABI_X32 = false;
+
 /* The name of the dynamic interpreter.  This is put in the .interp
    section.  */
 
@@ -1721,7 +1726,7 @@ perform_relocation (const reloc_howto_type *howto,
     case R_RISCV_GOT_HI20:
     case R_RISCV_TLS_GOT_HI20:
     case R_RISCV_TLS_GD_HI20:
-      if (ARCH_SIZE > 32 && !VALID_UTYPE_IMM (RISCV_CONST_HIGH_PART (value)))
+      if ((ARCH_SIZE > 32 || ABI_X32_P(input_bfd)) && !VALID_UTYPE_IMM (RISCV_CONST_HIGH_PART (value)))
 	return bfd_reloc_overflow;
       value = ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value));
       break;
@@ -1744,7 +1749,7 @@ perform_relocation (const reloc_howto_type *howto,
 
     case R_RISCV_CALL:
     case R_RISCV_CALL_PLT:
-      if (ARCH_SIZE > 32 && !VALID_UTYPE_IMM (RISCV_CONST_HIGH_PART (value)))
+      if ((ARCH_SIZE > 32 || ABI_X32_P(input_bfd))&& !VALID_UTYPE_IMM (RISCV_CONST_HIGH_PART (value)))
 	return bfd_reloc_overflow;
       value = ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value))
 	      | (ENCODE_ITYPE_IMM (value) << 32);
@@ -3685,7 +3690,7 @@ riscv_merge_arch_attr_info (bfd *ibfd, char *in_arch, char *out_arch)
     return NULL;
 
   /* Checking XLEN.  */
-  if (xlen_out != xlen_in)
+  if (xlen_out != xlen_in && !ABI_X32_P(ibfd))
     {
       _bfd_error_handler
 	(_("error: %pB: ISA string of input (%s) doesn't match "
@@ -3705,7 +3710,7 @@ riscv_merge_arch_attr_info (bfd *ibfd, char *in_arch, char *out_arch)
   if (!riscv_merge_multi_letter_ext (&in, &out))
     return NULL;
 
-  if (xlen_in != xlen_out)
+  if (xlen_in != xlen_out && !ABI_X32_P(ibfd))
     {
       _bfd_error_handler
 	(_("error: %pB: XLEN of input (%u) doesn't match "
@@ -3713,7 +3718,7 @@ riscv_merge_arch_attr_info (bfd *ibfd, char *in_arch, char *out_arch)
       return NULL;
     }
 
-  if (xlen_in != ARCH_SIZE)
+  if (xlen_in != ARCH_SIZE && !ABI_X32_P(ibfd))
     {
       _bfd_error_handler
 	(_("error: %pB: unsupported XLEN (%u), you might be "
@@ -3721,7 +3726,7 @@ riscv_merge_arch_attr_info (bfd *ibfd, char *in_arch, char *out_arch)
       return NULL;
     }
 
-  merged_arch_str = riscv_arch_str (ARCH_SIZE, &merged_subsets);
+  merged_arch_str = riscv_arch_str (xlen_in, &merged_subsets);
 
   /* Release the subset lists.  */
   riscv_release_subset_list (&in_subsets);
@@ -3992,6 +3997,9 @@ _bfd_riscv_elf_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
   /* Allow linking TSO and non-TSO, and keep the TSO flag.  */
   elf_elfheader (obfd)->e_flags |= new_flags & EF_RISCV_TSO;
 
+  /* Allow linking X32 and non-X32, and keep the X32 flag.  */
+  elf_elfheader (obfd)->e_flags |= new_flags & EF_RISCV_X32;
+
   return true;
 
  fail:
@@ -4431,7 +4439,7 @@ _bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
   rvc = rvc && VALID_CJTYPE_IMM (foff);
 
   /* C.J exists on RV32 and RV64, but C.JAL is RV32-only.  */
-  rvc = rvc && (rd == 0 || (rd == X_RA && ARCH_SIZE == 32));
+  rvc = rvc && (rd == 0 || (rd == X_RA && ARCH_SIZE == 32 && !ABI_X32_P(abfd)));
 
   if (rvc)
     {
@@ -5140,7 +5148,7 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
   return ret;
 }
 
-#if ARCH_SIZE == 32
+#if ARCH_SIZE == 32 && !ABI_X32
 # define PRSTATUS_SIZE			204
 # define PRSTATUS_OFFSET_PR_CURSIG	12
 # define PRSTATUS_OFFSET_PR_PID		24
@@ -5310,9 +5318,12 @@ riscv_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
 static bool
 riscv_elf_object_p (bfd *abfd)
 {
-  /* There are only two mach types in RISCV currently.  */
-  if (strcmp (abfd->xvec->name, "elf32-littleriscv") == 0
-      || strcmp (abfd->xvec->name, "elf32-bigriscv") == 0)
+  ABI_X32 = ABI_X32_P(abfd);
+  /* There are only three mach types in RISCV currently.  */
+  if (ABI_X32)
+    bfd_default_set_arch_mach (abfd, bfd_arch_riscv, bfd_mach_riscv64x32);
+  else if (strcmp (abfd->xvec->name, "elf32-littleriscv") == 0
+      	|| strcmp (abfd->xvec->name, "elf32-bigriscv") == 0)
     bfd_default_set_arch_mach (abfd, bfd_arch_riscv, bfd_mach_riscv32);
   else
     bfd_default_set_arch_mach (abfd, bfd_arch_riscv, bfd_mach_riscv64);
diff --git a/binutils/readelf.c b/binutils/readelf.c
index b872876a8b6..5e3378457c7 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -4119,6 +4119,9 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine)
 	  if (e_flags & EF_RISCV_TSO)
 	    strcat (buf, ", TSO");
 
+	  if (e_flags & EF_RISCV_X32)
+	    strcat (buf, ", X32");
+
 	  switch (e_flags & EF_RISCV_FLOAT_ABI)
 	    {
 	    case EF_RISCV_FLOAT_ABI_SOFT:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 99903deccec..7c47530801e 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -278,6 +278,14 @@ riscv_set_tso (void)
   elf_flags |= EF_RISCV_TSO;
 }
 
+/* Turn on the x32 flag for elf_flags once we have enabled x32 model.  */
+
+static void
+riscv_set_x32 (void)
+{
+  elf_flags |= EF_RISCV_X32;
+}
+
 /* The linked list hanging off of .subsets_list records all enabled extensions,
    which are parsed from the architecture string.  The architecture string can
    be set by the -march option, the elf architecture attributes, and the
@@ -405,6 +413,9 @@ riscv_set_abi_by_arch (void)
 
   if (rve_abi)
     elf_flags |= EF_RISCV_RVE;
+
+  if (abi_xlen == 32 && xlen == 64)
+    riscv_set_x32 ();
 }
 
 /* Handle of the OPCODE hash table.  */
@@ -706,9 +717,9 @@ const char *
 riscv_target_format (void)
 {
   if (target_big_endian)
-    return xlen == 64 ? "elf64-bigriscv" : "elf32-bigriscv";
+    return abi_xlen == 64 ? "elf64-bigriscv" : "elf32-bigriscv";
   else
-    return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv";
+    return abi_xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv";
 }
 
 /* Return the length of instruction INSN.  */
@@ -1505,7 +1516,8 @@ init_opcode_hash (const struct riscv_opcode *opcodes,
 void
 md_begin (void)
 {
-  unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
+  unsigned long mach = xlen == 64 ? 
+      (abi_xlen == 32 ? bfd_mach_riscv64x32 : bfd_mach_riscv64) : bfd_mach_riscv32;
 
   if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
     as_warn (_("could not set architecture and machine"));
@@ -4912,7 +4924,8 @@ s_riscv_attribute (int ignored ATTRIBUTE_UNUSED)
       if (old_xlen != xlen)
 	{
 	  /* We must re-init bfd again if xlen is changed.  */
-	  unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
+	  unsigned long mach = xlen == 64 ? (abi_xlen == 32 ? 
+        bfd_mach_riscv64x32 : bfd_mach_riscv64) : bfd_mach_riscv32;
 	  bfd_find_target (riscv_target_format (), stdoutput);
 
 	  if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
diff --git a/include/elf/riscv.h b/include/elf/riscv.h
index aabc71cf979..932ce42bf97 100644
--- a/include/elf/riscv.h
+++ b/include/elf/riscv.h
@@ -124,6 +124,9 @@ END_RELOC_NUMBERS (R_RISCV_max)
 /* File uses the TSO model. */
 #define EF_RISCV_TSO 0x0010
 
+/* File uses the X32 model. */
+#define EF_RISCV_X32 0x0020
+
 /* Additional section types.  */
 #define SHT_RISCV_ATTRIBUTES 0x70000003 /* Section holds attributes.  */
 
-- 
2.38.1.windows.1

[RFC PATCH 3/4] RISC-V : Add rv64 ilp32 support in disassemble

[Liao Shihua]

This patch supports rv64 ilp32 in disassemble.


opcodes/ChangeLog:

        * riscv-dis.c (print_insn_args):
        (riscv_disassemble_insn):
---
 opcodes/riscv-dis.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index f25993d1e45..550cabf875e 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -263,7 +263,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	    case 'j':
 	      if (((l & MASK_C_ADDI) == MATCH_C_ADDI) && rd != 0)
 		maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 0);
-	      if (info->mach == bfd_mach_riscv64
+	      if ((info->mach == bfd_mach_riscv64 || info->mach == bfd_mach_riscv64x32)
 		  && ((l & MASK_C_ADDIW) == MATCH_C_ADDIW) && rd != 0)
 		maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 1);
 	      print (info->stream, dis_style_immediate, "%d",
@@ -463,7 +463,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	  if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
 	      || (l & MASK_JALR) == MATCH_JALR)
 	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
-	  if (info->mach == bfd_mach_riscv64
+	  if ((info->mach == bfd_mach_riscv64 || info->mach == bfd_mach_riscv64x32)
 	      && ((l & MASK_ADDIW) == MATCH_ADDIW) && rs1 != 0)
 	    maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 1);
 	  print (info->stream, dis_style_immediate, "%d",
@@ -724,7 +724,7 @@ riscv_disassemble_insn (bfd_vma memaddr,
   if (op != NULL)
     {
       /* If XLEN is not known, get its value from the ELF class.  */
-      if (info->mach == bfd_mach_riscv64)
+      if (info->mach == bfd_mach_riscv64 || info->mach == bfd_mach_riscv64x32)
 	xlen = 64;
       else if (info->mach == bfd_mach_riscv32)
 	xlen = 32;
-- 
2.38.1.windows.1

[RFC PATCH 4/4] gdb/riscv : Add rv64 ilp32 support in gdb

[Liao Shihua]

This patch supports rv64 ilp32 in gdb. I know should send it
to gdb maillist, but due to its close correlation with the 
previous patch, it is temporarily placed here.
It add a new gdb features abi_xlen.


ChangeLog:

        * gdb/arch/riscv.h (struct riscv_gdbarch_features):Add abi_xlen .
        * gdb/riscv-tdep.c (riscv_abi_xlen):Likewise
        (riscv_features_from_bfd):Likewise
        (riscv_gdbarch_init):change long_bit by abi_xlen.
---
 gdb/arch/riscv.h | 10 +++++++++-
 gdb/riscv-tdep.c | 20 ++++++++++++++++----
 2 files changed, 25 insertions(+), 5 deletions(-)

diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h
index 54610ed6c16..a41faba1168 100644
--- a/gdb/arch/riscv.h
+++ b/gdb/arch/riscv.h
@@ -41,6 +41,12 @@ struct riscv_gdbarch_features
      uninitialised.  */
   int xlen = 0;
 
+  /* The size of the pointer_size in bytes.  This is either 4 (ILP32), 8
+     (LP64).  No other value is valid.  Initialise to the
+     invalid 0 value so we can spot if one of these is used
+     uninitialised.  */
+  int abi_xlen = 0;
+
   /* The size of the f-registers in bytes.  This is either 4 (RV32), 8
      (RV64), or 16 (RV128).  This can also hold the value 0 to indicate
      that there are no f-registers.  No other value is valid.  */
@@ -68,6 +74,7 @@ struct riscv_gdbarch_features
   bool operator== (const struct riscv_gdbarch_features &rhs) const
   {
     return (xlen == rhs.xlen && flen == rhs.flen
+	    && abi_xlen == rhs.abi_xlen
 	    && embedded == rhs.embedded && vlen == rhs.vlen
 	    && has_fflags_reg == rhs.has_fflags_reg
 	    && has_frm_reg == rhs.has_frm_reg
@@ -88,8 +95,9 @@ struct riscv_gdbarch_features
 		       | (has_frm_reg ? 1 : 0) << 12
 		       | (has_fcsr_reg ? 1 : 0) << 13
 		       | (xlen & 0x1f) << 5
+		       | (abi_xlen & 0x1f) << 14
 		       | (flen & 0x1f) << 0
-		       | (vlen & 0xfff) << 14);
+		       | (vlen & 0xfff) << 19);
     return val;
   }
 };
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 500279e1ae9..d4531896cc1 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -774,7 +774,7 @@ int
 riscv_abi_xlen (struct gdbarch *gdbarch)
 {
   riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
-  return tdep->abi_features.xlen;
+  return tdep->abi_features.abi_xlen;
 }
 
 /* See riscv-tdep.h.  */
@@ -3835,9 +3835,15 @@ riscv_features_from_bfd (const bfd *abfd)
       int e_flags = elf_elfheader (abfd)->e_flags;
 
       if (eclass == ELFCLASS32)
-	features.xlen = 4;
+	{
+	  features.xlen == 4;
+    features.abi_xlen = 4;
+	}
       else if (eclass == ELFCLASS64)
-	features.xlen = 8;
+	{
+	  features.xlen == 8;
+    features.abi_xlen = 8;
+	}
       else
 	internal_error (_("unknown ELF header class %d"), eclass);
 
@@ -3846,6 +3852,12 @@ riscv_features_from_bfd (const bfd *abfd)
       else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE)
 	features.flen = 4;
 
+      if (e_flags & EF_RISCV_X32)
+	{
+	  features.xlen == 8;
+    features.abi_xlen = 4;
+	}
+
       if (e_flags & EF_RISCV_RVE)
 	{
 	  if (features.xlen == 8)
@@ -4175,7 +4187,7 @@ riscv_gdbarch_init (struct gdbarch_info info,
   /* Target data types.  */
   set_gdbarch_short_bit (gdbarch, 16);
   set_gdbarch_int_bit (gdbarch, 32);
-  set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
+  set_gdbarch_long_bit (gdbarch, riscv_abi_xlen (gdbarch) * 8);
   set_gdbarch_long_long_bit (gdbarch, 64);
   set_gdbarch_float_bit (gdbarch, 32);
   set_gdbarch_double_bit (gdbarch, 64);
-- 
2.38.1.windows.1

Re: [RFC PATCH 1/4] RISC-V : Remove checking when -march=rv64XX and -mabi=ilp32X

[Jan Beulich]

On 19.05.2023 05:48, Liao Shihua wrote:
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -379,7 +379,7 @@ riscv_set_abi_by_arch (void)
>        gas_assert (abi_xlen != 0 && xlen != 0 && float_abi != FLOAT_ABI_DEFAULT);
>        if (abi_xlen > xlen)
>  	as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen);
> -      else if (abi_xlen < xlen)
> +      else if (abi_xlen < xlen && (abi_xlen != 32 && xlen != 64))
>  	as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen);

Did you mean || as the inner operator of the condition you add?

Also I think this change ought to come after patch 2, not first.

Jan

Re: [RFC PATCH 2/4] RISC-V : Add support for rv64 arch using ilp32 abi

[Jan Beulich]

On 19.05.2023 05:48, Liao Shihua wrote:
> This patch add a new bfd_mach bfd_mach_riscv64x32 and a new e_flags X32.
> bfd_mach_riscv64x32 has the same bits in a word/address and ARCH_SIZE
> with rv32, but use rv64's PRSTATUS. X32 use the 6th bit of e_flags layout.

And this has been added already to the official version of the spec? (A
reference might be good, maybe here or maybe in the cover letter.)

> --- a/bfd/elfnn-riscv.c
> +++ b/bfd/elfnn-riscv.c
> @@ -122,6 +122,11 @@
>  
>  #define RISCV_ELF_WORD_BYTES (1 << RISCV_ELF_LOG_WORD_BYTES)
>  
> +#define ABI_X32_P(abfd) \
> +  ((elf_elfheader (abfd)->e_flags & EF_RISCV_X32) != 0)
> +
> +static bool ABI_X32 = false;

While I'm not sure in how far libbfd, when built as a shared object, is
fully usable in multi-threaded programs, I don't think new code should
make the situation worse by adding new (non-const) static/global
variables. What's yet more odd about this variable is that ...

> @@ -5140,7 +5148,7 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
>    return ret;
>  }
>  
> -#if ARCH_SIZE == 32
> +#if ARCH_SIZE == 32 && !ABI_X32
>  # define PRSTATUS_SIZE			204
>  # define PRSTATUS_OFFSET_PR_CURSIG	12
>  # define PRSTATUS_OFFSET_PR_PID		24

... you use it in a pre-processor conditional here.

Jan

Re: Re: [RFC PATCH 2/4] RISC-V : Add support for rv64 arch using ilp32 abi

[shihua]

Hello Jan,
> And this has been added already to the official version of the spec? (A
> reference might be good, maybe here or maybe in the cover letter.)
> 

At the moment I have only initiated pr in psABI, but it is still under discussion.
You can see it in https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/381


> 
> While I'm not sure in how far libbfd, when built as a shared object, is
> fully usable in multi-threaded programs, I don't think new code should
> make the situation worse by adding new (non-const) static/global
> variables. What's yet more odd about this variable is that ...

> 
> ... you use it in a pre-processor conditional here.
> 
> Jan

Thank you for you advice, I will revise this part in the future.

Best Regards
Liao Shihua

Re: [RFC PATCH 3/4] RISC-V : Add rv64 ilp32 support in disassemble

[Guo Ren]

On Fri, May 19, 2023 at 11:49 AM Liao Shihua <shihua@iscas.ac.cn> wrote:
>
> This patch supports rv64 ilp32 in disassemble.
>
>
> opcodes/ChangeLog:
>
>         * riscv-dis.c (print_insn_args):
>         (riscv_disassemble_insn):
> ---
>  opcodes/riscv-dis.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> index f25993d1e45..550cabf875e 100644
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -263,7 +263,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
>             case 'j':
>               if (((l & MASK_C_ADDI) == MATCH_C_ADDI) && rd != 0)
>                 maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 0);
> -             if (info->mach == bfd_mach_riscv64
> +             if ((info->mach == bfd_mach_riscv64 || info->mach == bfd_mach_riscv64x32)
>                   && ((l & MASK_C_ADDIW) == MATCH_C_ADDIW) && rd != 0)
>                 maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 1);
>               print (info->stream, dis_style_immediate, "%d",
> @@ -463,7 +463,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
>           if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
>               || (l & MASK_JALR) == MATCH_JALR)
>             maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
> -         if (info->mach == bfd_mach_riscv64
> +         if ((info->mach == bfd_mach_riscv64 || info->mach == bfd_mach_riscv64x32)
keep the name of bfd_mach_riscv64ilp32

>               && ((l & MASK_ADDIW) == MATCH_ADDIW) && rs1 != 0)
>             maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 1);
>           print (info->stream, dis_style_immediate, "%d",
> @@ -724,7 +724,7 @@ riscv_disassemble_insn (bfd_vma memaddr,
>    if (op != NULL)
>      {
>        /* If XLEN is not known, get its value from the ELF class.  */
> -      if (info->mach == bfd_mach_riscv64)
> +      if (info->mach == bfd_mach_riscv64 || info->mach == bfd_mach_riscv64x32)
>         xlen = 64;
>        else if (info->mach == bfd_mach_riscv32)
>         xlen = 32;
> --
> 2.38.1.windows.1
>


-- 
Best Regards
 Guo Ren