* [REVIEW ONLY 0/1] RISC-V (unratified): Add 'Smrnmi' extension
@ 2022-07-09 8:53 Tsukasa OI
2022-07-09 8:53 ` [REVIEW ONLY 1/1] UNRATIFIED RISC-V: " Tsukasa OI
2022-11-29 1:21 ` [REVIEW ONLY 0/1] RISC-V (unratified): " Tsukasa OI
0 siblings, 2 replies; 7+ messages in thread
From: Tsukasa OI @ 2022-07-09 8:53 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
*** WAIT FOR SPECIFICATION FREEZE ***
This is an implementation for unratified and unfrozen RISC-V extension
and not intended to be merged as of now.
The only intent to submit this patchset is to test new instructions for
your (possibly virtual) environment and early review for fast adoption
after ratification.
This patchset adds following unratified extension to GNU Binutils:
- Smrnmi (Resumable NMI)
version 0.4 (may change on ratification)
... which adds `mnret' instruction and 4 CSRs related to RNMI.
This is based on a pull request to riscv-isa-manual:
<https://github.com/riscv/riscv-isa-manual/pull/766>
Note that it has **different** CSR values between proposed RNMI version
0.4 and RNMI as optionally implemented in SiFive U74-MC:
<https://sifive.cdn.prismic.io/sifive/2dd11994-693c-4360-8aea-5453d8642c42_u74mc_core_complex_manual_21G3.pdf>
CSR | proposed | SiFive |
--------- | -------- | ------ |
mnscratch | 0x740 | 0x350 |
mnepc | 0x741 | 0x351 |
mncause | 0x742 | 0x352 |
mnstatus | 0x744 | 0x353 |
Tsukasa OI (1):
UNRATIFIED RISC-V: Add 'Smrnmi' extension
bfd/elfxx-riscv.c | 5 +++++
gas/config/tc-riscv.c | 4 ++++
gas/testsuite/gas/riscv/csr-dw-regnums.d | 4 ++++
gas/testsuite/gas/riscv/csr-dw-regnums.s | 5 +++++
gas/testsuite/gas/riscv/csr-version-1p10.d | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p10.l | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p11.d | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p11.l | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p12.d | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p12.l | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p9p1.d | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p9p1.l | 8 ++++++++
gas/testsuite/gas/riscv/csr.s | 6 ++++++
gas/testsuite/gas/riscv/smrnmi.d | 10 ++++++++++
gas/testsuite/gas/riscv/smrnmi.s | 2 ++
include/opcode/riscv-opc.h | 14 ++++++++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 3 +++
18 files changed, 118 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/smrnmi.d
create mode 100644 gas/testsuite/gas/riscv/smrnmi.s
base-commit: d2acd4b0c5bab349aaa152d60268bc144634a844
--
2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [REVIEW ONLY 1/1] UNRATIFIED RISC-V: Add 'Smrnmi' extension
2022-07-09 8:53 [REVIEW ONLY 0/1] RISC-V (unratified): Add 'Smrnmi' extension Tsukasa OI
@ 2022-07-09 8:53 ` Tsukasa OI
2022-11-29 1:21 ` [REVIEW ONLY 0/1] RISC-V (unratified): " Tsukasa OI
1 sibling, 0 replies; 7+ messages in thread
From: Tsukasa OI @ 2022-07-09 8:53 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
This commit adds `mnret' instruction and RNMI-related CSRs from Smrnmi
extension.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add new
instruction class handling.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* config/tc-riscv.c (enum riscv_csr_class): Add new CSR class.
(riscv_csr_address): Add new CSR class handling.
* testsuite/gas/riscv/csr.s: Add new CSR test.
* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
* testsuite/gas/riscv/csr-version-1p10.d: Likewise.
* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
* testsuite/gas/riscv/smrnmi.s: New test for mnret instruction.
* testsuite/gas/riscv/smrnmi.d: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_MNRET, MASK_MNRET, CSR_MNSCRATCH,
CSR_MNEPC, CSR_MNCAUSE, CSR_MNSTATUS): New.
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
class.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Add 'mnret' instruction.
---
bfd/elfxx-riscv.c | 5 +++++
gas/config/tc-riscv.c | 4 ++++
gas/testsuite/gas/riscv/csr-dw-regnums.d | 4 ++++
gas/testsuite/gas/riscv/csr-dw-regnums.s | 5 +++++
gas/testsuite/gas/riscv/csr-version-1p10.d | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p10.l | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p11.d | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p11.l | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p12.d | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p12.l | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p9p1.d | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p9p1.l | 8 ++++++++
gas/testsuite/gas/riscv/csr.s | 6 ++++++
gas/testsuite/gas/riscv/smrnmi.d | 10 ++++++++++
gas/testsuite/gas/riscv/smrnmi.s | 2 ++
include/opcode/riscv-opc.h | 14 ++++++++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 3 +++
18 files changed, 118 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/smrnmi.d
create mode 100644 gas/testsuite/gas/riscv/smrnmi.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 0b2021f5cc7..ac4897ed364 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1233,6 +1233,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
static struct riscv_supported_ext riscv_supported_std_s_ext[] =
{
+ {"smrnmi", ISA_SPEC_CLASS_DRAFT, 0, 4, 0 },
{"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"sstc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2398,6 +2399,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
|| riscv_subset_supports (rps, "zve64d")
|| riscv_subset_supports (rps, "zve64f")
|| riscv_subset_supports (rps, "zve32f"));
+ case INSN_CLASS_SMRNMI:
+ return riscv_subset_supports (rps, "smrnmi");
case INSN_CLASS_SVINVAL:
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
@@ -2523,6 +2526,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("v' or `zve64x' or `zve32x");
case INSN_CLASS_ZVEF:
return _("v' or `zve64d' or `zve64f' or `zve32f");
+ case INSN_CLASS_SMRNMI:
+ return "smrnmi";
case INSN_CLASS_SVINVAL:
return "svinval";
case INSN_CLASS_H:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index a0e8456a0d1..9020132fcb8 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -68,6 +68,7 @@ enum riscv_csr_class
CSR_CLASS_DEBUG, /* debug CSR */
CSR_CLASS_H, /* hypervisor */
CSR_CLASS_H_32, /* hypervisor, rv32 only */
+ CSR_CLASS_SMRNMI, /* Smrnmi only */
CSR_CLASS_SMSTATEEN, /* Smstateen only */
CSR_CLASS_SMSTATEEN_AND_H, /* Smstateen only (with H) */
CSR_CLASS_SMSTATEEN_32, /* Smstateen RV32 only */
@@ -937,6 +938,9 @@ riscv_csr_address (const char *csr_name,
case CSR_CLASS_V:
extension = "v";
break;
+ case CSR_CLASS_SMRNMI:
+ extension = "smrnmi";
+ break;
case CSR_CLASS_SMSTATEEN:
case CSR_CLASS_SMSTATEEN_AND_H:
case CSR_CLASS_SMSTATEEN_32:
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
index b4b3806a085..a9a81130064 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
@@ -313,6 +313,10 @@ Contents of the .* section:
DW_CFA_offset_extended_sf: r4675 \(vstval\) at cfa\+2316
DW_CFA_offset_extended_sf: r4676 \(vsip\) at cfa\+2320
DW_CFA_offset_extended_sf: r4736 \(vsatp\) at cfa\+2560
+ DW_CFA_offset_extended_sf: r5952 \(mnscratch\) at cfa\+7424
+ DW_CFA_offset_extended_sf: r5953 \(mnepc\) at cfa\+7428
+ DW_CFA_offset_extended_sf: r5954 \(mncause\) at cfa\+7432
+ DW_CFA_offset_extended_sf: r5956 \(mnstatus\) at cfa\+7440
DW_CFA_offset_extended_sf: r4876 \(mstateen0\) at cfa\+3120
DW_CFA_offset_extended_sf: r4877 \(mstateen1\) at cfa\+3124
DW_CFA_offset_extended_sf: r4878 \(mstateen2\) at cfa\+3128
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s
index 6cfa415ebc2..d46164007b9 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.s
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s
@@ -307,6 +307,11 @@ _start:
.cfi_offset vstval, 2316
.cfi_offset vsip, 2320
.cfi_offset vsatp, 2560
+ # Smrnmi extension
+ .cfi_offset mnscratch, 7424
+ .cfi_offset mnepc, 7428
+ .cfi_offset mncause, 7432
+ .cfi_offset mnstatus, 7440
# Smstateen extension
.cfi_offset mstateen0, 3120
.cfi_offset mstateen1, 3124
diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d
index bd8b10302e3..e0393c532a7 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p10.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.d
@@ -601,6 +601,14 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+24459073[ ]+csrw[ ]+vsip,a1
[ ]+[0-9a-f]+:[ ]+28002573[ ]+csrr[ ]+a0,vsatp
[ ]+[0-9a-f]+:[ ]+28059073[ ]+csrw[ ]+vsatp,a1
+[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch
+[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1
+[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc
+[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1
+[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause
+[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1
+[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus
+[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1
[ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0
[ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1
[ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l
index b778453b556..6f7c6ea1f87 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p10.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.l
@@ -411,6 +411,14 @@
.*Warning: invalid CSR `vsip', needs `h' extension
.*Warning: invalid CSR `vsatp', needs `h' extension
.*Warning: invalid CSR `vsatp', needs `h' extension
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
.*Warning: invalid CSR `mstateen1', needs `smstateen' extension
diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d
index 5d6333884f1..09d23bb7d77 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p11.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.d
@@ -601,6 +601,14 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+24459073[ ]+csrw[ ]+vsip,a1
[ ]+[0-9a-f]+:[ ]+28002573[ ]+csrr[ ]+a0,vsatp
[ ]+[0-9a-f]+:[ ]+28059073[ ]+csrw[ ]+vsatp,a1
+[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch
+[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1
+[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc
+[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1
+[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause
+[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1
+[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus
+[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1
[ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0
[ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1
[ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l
index 78bae817470..b0671ec3fc5 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p11.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.l
@@ -409,6 +409,14 @@
.*Warning: invalid CSR `vsip', needs `h' extension
.*Warning: invalid CSR `vsatp', needs `h' extension
.*Warning: invalid CSR `vsatp', needs `h' extension
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
.*Warning: invalid CSR `mstateen1', needs `smstateen' extension
diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d
index 728e647c552..ed121f9569b 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p12.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.d
@@ -601,6 +601,14 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+24459073[ ]+csrw[ ]+vsip,a1
[ ]+[0-9a-f]+:[ ]+28002573[ ]+csrr[ ]+a0,vsatp
[ ]+[0-9a-f]+:[ ]+28059073[ ]+csrw[ ]+vsatp,a1
+[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch
+[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1
+[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc
+[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1
+[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause
+[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1
+[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus
+[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1
[ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0
[ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1
[ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l
index cb026bb55e0..7fe7ab962a8 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p12.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.l
@@ -271,6 +271,14 @@
.*Warning: invalid CSR `vsip', needs `h' extension
.*Warning: invalid CSR `vsatp', needs `h' extension
.*Warning: invalid CSR `vsatp', needs `h' extension
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
.*Warning: invalid CSR `mstateen1', needs `smstateen' extension
diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.d b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
index a34b99f4632..e5ac11addf3 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p9p1.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
@@ -601,6 +601,14 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+24459073[ ]+csrw[ ]+vsip,a1
[ ]+[0-9a-f]+:[ ]+28002573[ ]+csrr[ ]+a0,vsatp
[ ]+[0-9a-f]+:[ ]+28059073[ ]+csrw[ ]+vsatp,a1
+[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch
+[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1
+[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc
+[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1
+[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause
+[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1
+[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus
+[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1
[ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0
[ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1
[ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l b/gas/testsuite/gas/riscv/csr-version-1p9p1.l
index 4fac40fb589..de965606a2b 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.l
@@ -461,6 +461,14 @@
.*Warning: invalid CSR `vsip', needs `h' extension
.*Warning: invalid CSR `vsatp', needs `h' extension
.*Warning: invalid CSR `vsatp', needs `h' extension
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
.*Warning: invalid CSR `mstateen1', needs `smstateen' extension
diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s
index 128aeb83a04..c80716d511e 100644
--- a/gas/testsuite/gas/riscv/csr.s
+++ b/gas/testsuite/gas/riscv/csr.s
@@ -337,6 +337,12 @@
csr vsip
csr vsatp
+ # Smrnmi extension
+ csr mnscratch
+ csr mnepc
+ csr mncause
+ csr mnstatus
+
# Smstateen extension
csr mstateen0
csr mstateen1
diff --git a/gas/testsuite/gas/riscv/smrnmi.d b/gas/testsuite/gas/riscv/smrnmi.d
new file mode 100644
index 00000000000..f2be1e2e34d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/smrnmi.d
@@ -0,0 +1,10 @@
+#as: -march=rv64i_smrnmi
+#source: smrnmi.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+70200073[ ]+mnret
diff --git a/gas/testsuite/gas/riscv/smrnmi.s b/gas/testsuite/gas/riscv/smrnmi.s
new file mode 100644
index 00000000000..f2008bd8704
--- /dev/null
+++ b/gas/testsuite/gas/riscv/smrnmi.s
@@ -0,0 +1,2 @@
+target:
+ mnret
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 88b8d7ff595..49fa236bd64 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2055,6 +2055,9 @@
#define MASK_VDOTUVV 0xfc00707f
#define MATCH_VFDOTVV 0xe4001057
#define MASK_VFDOTVV 0xfc00707f
+/* Smrnmi instruction. */
+#define MATCH_MNRET 0x70200073
+#define MASK_MNRET 0xffffffff
/* Svinval instruction. */
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
@@ -2432,6 +2435,11 @@
#define CSR_UIP 0x44
#define CSR_SEDELEG 0x102
#define CSR_SIDELEG 0x103
+/* Smrnmi extension */
+#define CSR_MNSCRATCH 0x740
+#define CSR_MNEPC 0x741
+#define CSR_MNCAUSE 0x742
+#define CSR_MNSTATUS 0x744
/* Smstateen extension */
#define CSR_MSTATEEN0 0x30c
#define CSR_MSTATEEN1 0x30d
@@ -2823,6 +2831,7 @@ DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
+DECLARE_INSN(mnret, MATCH_MNRET, MASK_MNRET)
DECLARE_INSN(sinval_vma, MATCH_SINVAL_VMA, MASK_SINVAL_VMA)
DECLARE_INSN(sfence_w_inval, MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL)
DECLARE_INSN(sfence_inval_ir, MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR)
@@ -3154,6 +3163,11 @@ DECLARE_CSR(vscause, CSR_VSCAUSE, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_C
DECLARE_CSR(vstval, CSR_VSTVAL, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(vsip, CSR_VSIP, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(vsatp, CSR_VSATP, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+/* Smrnmi extension */
+DECLARE_CSR(mnscratch, CSR_MNSCRATCH, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mnepc, CSR_MNEPC, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mncause, CSR_MNCAUSE, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mnstatus, CSR_MNSTATUS, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
/* Smstateen extension */
DECLARE_CSR(mstateen0, CSR_MSTATEEN0, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mstateen1, CSR_MSTATEEN1, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index b115e338a05..5814565acf1 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -392,6 +392,7 @@ enum riscv_insn_class
INSN_CLASS_ZKND_OR_ZKNE,
INSN_CLASS_V,
INSN_CLASS_ZVEF,
+ INSN_CLASS_SMRNMI,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 2f9945aa930..942b851fa79 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1797,6 +1797,9 @@ const struct riscv_opcode riscv_opcodes[] =
{"vmv4r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, match_opcode, 0},
{"vmv8r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_opcode, 0},
+/* Smrnmi instructions. */
+{"mnret", 0, INSN_CLASS_SMRNMI, "", MATCH_MNRET, MASK_MNRET, match_opcode, 0 },
+
/* Svinval instructions. */
{"sinval.vma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_SINVAL_VMA, MASK_SINVAL_VMA, match_opcode, 0 },
{"sfence.w.inval", 0, INSN_CLASS_SVINVAL, "", MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL, match_opcode, 0 },
--
2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [REVIEW ONLY 0/1] RISC-V (unratified): Add 'Smrnmi' extension
2022-07-09 8:53 [REVIEW ONLY 0/1] RISC-V (unratified): Add 'Smrnmi' extension Tsukasa OI
2022-07-09 8:53 ` [REVIEW ONLY 1/1] UNRATIFIED RISC-V: " Tsukasa OI
@ 2022-11-29 1:21 ` Tsukasa OI
2022-11-29 1:21 ` [REVIEW ONLY 1/1] UNRATIFIED RISC-V: Add 'Smrnmi' extension and its CSRs Tsukasa OI
2023-09-12 1:40 ` [REVIEW ONLY v3 0/1] RISC-V (unratified): Add 'Smrnmi' extension Tsukasa OI
1 sibling, 2 replies; 7+ messages in thread
From: Tsukasa OI @ 2022-11-29 1:21 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
*** WAIT FOR SPECIFICATION FREEZE ***
This is an implementation for unratified and not frozen RISC-V extension
and not intended to be merged for now.
The only intent to submit this patchset is to test new instructions for
your (possibly virtual) environment and early review for fast adoption
after ratification.
This is the review-only PATCH v2 to keep track with latest GNU Binutils.
In this version, a dependency to 'Zicsr' is added.
This patchset adds following unratified extension to GNU Binutils:
- Smrnmi (Resumable NMI)
version 0.4 (may change on ratification)
... which adds "mnret" instruction and 4 CSRs related to RNMI.
This extension provides "resumable NMIs" to provide special non-maskable
interrupts (NMIs) with "resume" capability (normally, NMIs are are only used
for hardware error conditions and not resumable; however on some conditions,
there are some cases where using NMIs fits better yet resumable after
proper handling by the NMI handler [which may fail though]).
This is based on a draft version of the RISC-V ISA Manual:
<https://github.com/riscv/riscv-isa-manual/commit/28b46de77ca7fb94ffcf6cf669cc27269f6013de>
Note that it has **different** CSR values between proposed RNMI version
0.4 and RNMI as optionally implemented in SiFive U74-MC:
<https://sifive.cdn.prismic.io/sifive/2dd11994-693c-4360-8aea-5453d8642c42_u74mc_core_complex_manual_21G3.pdf>
| CSR | proposed | SiFive |
| --------- | -------- | ------ |
| mnscratch | 0x740 | 0x350 |
| mnepc | 0x741 | 0x351 |
| mncause | 0x742 | 0x352 |
| mnstatus | 0x744 | 0x353 |
Also, although that 4 CSRs are assigned with actual numbers (this is why I'm
not attaching "CSR instantiation" script in this patchset), it may be
changed before ratification. Be careful.
Tsukasa OI (1):
UNRATIFIED RISC-V: Add 'Smrnmi' extension and its CSRs
bfd/elfxx-riscv.c | 6 ++++++
gas/config/tc-riscv.c | 4 ++++
gas/testsuite/gas/riscv/csr-dw-regnums.d | 4 ++++
gas/testsuite/gas/riscv/csr-dw-regnums.s | 5 +++++
gas/testsuite/gas/riscv/csr-version-1p10.d | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p10.l | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p11.d | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p11.l | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p12.d | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p12.l | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p9p1.d | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p9p1.l | 8 ++++++++
gas/testsuite/gas/riscv/csr.s | 6 ++++++
gas/testsuite/gas/riscv/smrnmi-noarch.d | 3 +++
gas/testsuite/gas/riscv/smrnmi-noarch.l | 2 ++
gas/testsuite/gas/riscv/smrnmi.d | 10 ++++++++++
gas/testsuite/gas/riscv/smrnmi.s | 2 ++
include/opcode/riscv-opc.h | 15 +++++++++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 3 +++
20 files changed, 125 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/smrnmi-noarch.d
create mode 100644 gas/testsuite/gas/riscv/smrnmi-noarch.l
create mode 100644 gas/testsuite/gas/riscv/smrnmi.d
create mode 100644 gas/testsuite/gas/riscv/smrnmi.s
base-commit: cb44f89ce977b1ab2d4063f2487950bddfb75bc7
--
2.38.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [REVIEW ONLY 1/1] UNRATIFIED RISC-V: Add 'Smrnmi' extension and its CSRs
2022-11-29 1:21 ` [REVIEW ONLY 0/1] RISC-V (unratified): " Tsukasa OI
@ 2022-11-29 1:21 ` Tsukasa OI
2022-11-29 2:38 ` Palmer Dabbelt
2023-09-12 1:40 ` [REVIEW ONLY v3 0/1] RISC-V (unratified): Add 'Smrnmi' extension Tsukasa OI
1 sibling, 1 reply; 7+ messages in thread
From: Tsukasa OI @ 2022-11-29 1:21 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
From: Tsukasa OI <research_trasio@irq.a4lg.com>
[DO NOT MERGE]
Until 'Smrnmi' extension is frozen/ratified and final version number is
determined, this patch should not be merged upstream. This commit uses
unratified version 0.4 as in the documentation (instead of possible 1.0
after ratification).
This commit adds "mnret" instruction and RNMI-related CSRs from the
Resumable Non-Maskable Interrupts ('Smrnmi') extension.
This is based on:
<https://github.com/riscv/riscv-isa-manual/commit/28b46de77ca7fb94ffcf6cf669cc27269f6013de>,
latest 'Smrnmi' change on the master branch of the RISC-V ISA Manual
as of this writing.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): Make 'Smrnmi' to imply
'Zicsr' extension. (riscv_multi_subset_supports): Add new
instruction class handling.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* config/tc-riscv.c (enum riscv_csr_class): Add new CSR class.
(riscv_csr_address): Add new CSR class handling.
* testsuite/gas/riscv/csr.s: Add new CSR test.
* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
* testsuite/gas/riscv/csr-version-1p10.d: Likewise.
* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
* testsuite/gas/riscv/smrnmi.s: New test for mnret instruction.
* testsuite/gas/riscv/smrnmi.d: Likewise.
* testsuite/gas/riscv/smrnmi-noarch.d: New test for architecture
failure.
* testsuite/gas/riscv/smrnmi-noarch.l: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_MNRET, MASK_MNRET, CSR_MNSCRATCH,
CSR_MNEPC, CSR_MNCAUSE, CSR_MNSTATUS): New.
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
class.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Add 'mnret' instruction.
---
bfd/elfxx-riscv.c | 6 ++++++
gas/config/tc-riscv.c | 4 ++++
gas/testsuite/gas/riscv/csr-dw-regnums.d | 4 ++++
gas/testsuite/gas/riscv/csr-dw-regnums.s | 5 +++++
gas/testsuite/gas/riscv/csr-version-1p10.d | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p10.l | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p11.d | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p11.l | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p12.d | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p12.l | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p9p1.d | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p9p1.l | 8 ++++++++
gas/testsuite/gas/riscv/csr.s | 6 ++++++
gas/testsuite/gas/riscv/smrnmi-noarch.d | 3 +++
gas/testsuite/gas/riscv/smrnmi-noarch.l | 2 ++
gas/testsuite/gas/riscv/smrnmi.d | 10 ++++++++++
gas/testsuite/gas/riscv/smrnmi.s | 2 ++
include/opcode/riscv-opc.h | 15 +++++++++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 3 +++
20 files changed, 125 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/smrnmi-noarch.d
create mode 100644 gas/testsuite/gas/riscv/smrnmi-noarch.l
create mode 100644 gas/testsuite/gas/riscv/smrnmi.d
create mode 100644 gas/testsuite/gas/riscv/smrnmi.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 0bcf2fdcfa34..d4f580733ddd 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1104,6 +1104,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"smaia", "ssaia", check_implicit_always},
{"smstateen", "ssstateen", check_implicit_always},
{"smepmp", "zicsr", check_implicit_always},
+ {"smrnmi", "zicsr", check_implicit_always},
{"ssaia", "zicsr", check_implicit_always},
{"sscofpmf", "zicsr", check_implicit_always},
{"ssstateen", "zicsr", check_implicit_always},
@@ -1225,6 +1226,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] =
{
{"smaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"smrnmi", ISA_SPEC_CLASS_DRAFT, 0, 4, 0 },
{"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"ssaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2415,6 +2417,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
|| riscv_subset_supports (rps, "zve64d")
|| riscv_subset_supports (rps, "zve64f")
|| riscv_subset_supports (rps, "zve32f"));
+ case INSN_CLASS_SMRNMI:
+ return riscv_subset_supports (rps, "smrnmi");
case INSN_CLASS_SVINVAL:
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
@@ -2573,6 +2577,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("v' or `zve64x' or `zve32x");
case INSN_CLASS_ZVEF:
return _("v' or `zve64d' or `zve64f' or `zve32f");
+ case INSN_CLASS_SMRNMI:
+ return "smrnmi";
case INSN_CLASS_SVINVAL:
return "svinval";
case INSN_CLASS_H:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 0682eb355241..85aa4d1d00d4 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -74,6 +74,7 @@ enum riscv_csr_class
CSR_CLASS_H_32, /* hypervisor, rv32 only */
CSR_CLASS_SMAIA, /* Smaia */
CSR_CLASS_SMAIA_32, /* Smaia, rv32 only */
+ CSR_CLASS_SMRNMI, /* Smrnmi only */
CSR_CLASS_SMSTATEEN, /* Smstateen only */
CSR_CLASS_SMSTATEEN_32, /* Smstateen RV32 only */
CSR_CLASS_SSAIA, /* Ssaia */
@@ -1049,6 +1050,9 @@ riscv_csr_address (const char *csr_name,
case CSR_CLASS_SMAIA:
extension = "smaia";
break;
+ case CSR_CLASS_SMRNMI:
+ extension = "smrnmi";
+ break;
case CSR_CLASS_SMSTATEEN:
case CSR_CLASS_SMSTATEEN_32:
is_rv32_only = (csr_class == CSR_CLASS_SMSTATEEN_32);
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
index fd830666ab89..a87df625da9d 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
@@ -324,6 +324,10 @@ Contents of the .* section:
DW_CFA_offset_extended_sf: r4888 \(mvienh\) at cfa\+3168
DW_CFA_offset_extended_sf: r4889 \(mviph\) at cfa\+3172
DW_CFA_offset_extended_sf: r4948 \(miph\) at cfa\+3408
+ DW_CFA_offset_extended_sf: r5952 \(mnscratch\) at cfa\+7424
+ DW_CFA_offset_extended_sf: r5953 \(mnepc\) at cfa\+7428
+ DW_CFA_offset_extended_sf: r5954 \(mncause\) at cfa\+7432
+ DW_CFA_offset_extended_sf: r5956 \(mnstatus\) at cfa\+7440
DW_CFA_offset_extended_sf: r4876 \(mstateen0\) at cfa\+3120
DW_CFA_offset_extended_sf: r4877 \(mstateen1\) at cfa\+3124
DW_CFA_offset_extended_sf: r4878 \(mstateen2\) at cfa\+3128
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s
index b8b0f7902297..3ea3853a2cc5 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.s
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s
@@ -321,6 +321,11 @@ _start:
.cfi_offset mvienh, 3168
.cfi_offset mviph, 3172
.cfi_offset miph, 3408
+ # Smrnmi extension
+ .cfi_offset mnscratch, 7424
+ .cfi_offset mnepc, 7428
+ .cfi_offset mncause, 7432
+ .cfi_offset mnstatus, 7440
# Smstateen extension
.cfi_offset mstateen0, 3120
.cfi_offset mstateen1, 3124
diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d
index ee41e1025cce..9c2bf4bc9628 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p10.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.d
@@ -623,6 +623,14 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+31959073[ ]+csrw[ ]+mviph,a1
[ ]+[0-9a-f]+:[ ]+35402573[ ]+csrr[ ]+a0,miph
[ ]+[0-9a-f]+:[ ]+35459073[ ]+csrw[ ]+miph,a1
+[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch
+[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1
+[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc
+[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1
+[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause
+[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1
+[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus
+[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1
[ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0
[ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1
[ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l
index e677b78b8bb8..b00515d2cf13 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p10.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.l
@@ -444,6 +444,14 @@
.*Warning: invalid CSR `miph', needs `smaia' extension
.*Warning: invalid CSR `miph', needs rv32i extension
.*Warning: invalid CSR `miph', needs `smaia' extension
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
.*Warning: invalid CSR `mstateen1', needs `smstateen' extension
diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d
index a83b1bf68f98..9783cb795e2c 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p11.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.d
@@ -623,6 +623,14 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+31959073[ ]+csrw[ ]+mviph,a1
[ ]+[0-9a-f]+:[ ]+35402573[ ]+csrr[ ]+a0,miph
[ ]+[0-9a-f]+:[ ]+35459073[ ]+csrw[ ]+miph,a1
+[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch
+[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1
+[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc
+[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1
+[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause
+[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1
+[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus
+[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1
[ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0
[ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1
[ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l
index 81ca86ca7bcc..da5167dab7e3 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p11.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.l
@@ -442,6 +442,14 @@
.*Warning: invalid CSR `miph', needs `smaia' extension
.*Warning: invalid CSR `miph', needs rv32i extension
.*Warning: invalid CSR `miph', needs `smaia' extension
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
.*Warning: invalid CSR `mstateen1', needs `smstateen' extension
diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d
index 612aac280768..e39473062d5a 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p12.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.d
@@ -623,6 +623,14 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+31959073[ ]+csrw[ ]+mviph,a1
[ ]+[0-9a-f]+:[ ]+35402573[ ]+csrr[ ]+a0,miph
[ ]+[0-9a-f]+:[ ]+35459073[ ]+csrw[ ]+miph,a1
+[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch
+[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1
+[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc
+[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1
+[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause
+[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1
+[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus
+[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1
[ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0
[ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1
[ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l
index 1c0bb4ef2d8f..011e5d578309 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p12.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.l
@@ -304,6 +304,14 @@
.*Warning: invalid CSR `miph', needs `smaia' extension
.*Warning: invalid CSR `miph', needs rv32i extension
.*Warning: invalid CSR `miph', needs `smaia' extension
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
.*Warning: invalid CSR `mstateen1', needs `smstateen' extension
diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.d b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
index 0fe849c269c2..819292888aaa 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p9p1.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
@@ -623,6 +623,14 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+31959073[ ]+csrw[ ]+mviph,a1
[ ]+[0-9a-f]+:[ ]+35402573[ ]+csrr[ ]+a0,miph
[ ]+[0-9a-f]+:[ ]+35459073[ ]+csrw[ ]+miph,a1
+[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch
+[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1
+[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc
+[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1
+[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause
+[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1
+[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus
+[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1
[ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0
[ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1
[ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l b/gas/testsuite/gas/riscv/csr-version-1p9p1.l
index c65d0b48e414..daf7e94bbace 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.l
@@ -494,6 +494,14 @@
.*Warning: invalid CSR `miph', needs `smaia' extension
.*Warning: invalid CSR `miph', needs rv32i extension
.*Warning: invalid CSR `miph', needs `smaia' extension
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
.*Warning: invalid CSR `mstateen1', needs `smstateen' extension
diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s
index c7406ce34c2e..3508c42f623c 100644
--- a/gas/testsuite/gas/riscv/csr.s
+++ b/gas/testsuite/gas/riscv/csr.s
@@ -350,6 +350,12 @@
csr mviph
csr miph
+ # Smrnmi extension
+ csr mnscratch
+ csr mnepc
+ csr mncause
+ csr mnstatus
+
# Smstateen/Ssstateen extensions
csr mstateen0
csr mstateen1
diff --git a/gas/testsuite/gas/riscv/smrnmi-noarch.d b/gas/testsuite/gas/riscv/smrnmi-noarch.d
new file mode 100644
index 000000000000..d28da9736300
--- /dev/null
+++ b/gas/testsuite/gas/riscv/smrnmi-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i
+#source: smrnmi.s
+#error_output: smrnmi-noarch.l
diff --git a/gas/testsuite/gas/riscv/smrnmi-noarch.l b/gas/testsuite/gas/riscv/smrnmi-noarch.l
new file mode 100644
index 000000000000..1ad5141c1245
--- /dev/null
+++ b/gas/testsuite/gas/riscv/smrnmi-noarch.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `mnret', extension `smrnmi' required
diff --git a/gas/testsuite/gas/riscv/smrnmi.d b/gas/testsuite/gas/riscv/smrnmi.d
new file mode 100644
index 000000000000..2b628e91a103
--- /dev/null
+++ b/gas/testsuite/gas/riscv/smrnmi.d
@@ -0,0 +1,10 @@
+#as: -march=rv32i_smrnmi
+#source: smrnmi.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+70200073[ ]+mnret
diff --git a/gas/testsuite/gas/riscv/smrnmi.s b/gas/testsuite/gas/riscv/smrnmi.s
new file mode 100644
index 000000000000..f2008bd8704e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/smrnmi.s
@@ -0,0 +1,2 @@
+target:
+ mnret
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 06e3df0f5a63..d80c7fb5a876 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2055,6 +2055,9 @@
#define MASK_VDOTUVV 0xfc00707f
#define MATCH_VFDOTVV 0xe4001057
#define MASK_VFDOTVV 0xfc00707f
+/* Smrnmi instruction. */
+#define MATCH_MNRET 0x70200073
+#define MASK_MNRET 0xffffffff
/* Svinval instruction. */
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
@@ -2673,6 +2676,11 @@
#define CSR_MVIENH 0x318
#define CSR_MVIPH 0x319
#define CSR_MIPH 0x354
+/* Smrnmi extension CSR addresses. */
+#define CSR_MNSCRATCH 0x740
+#define CSR_MNEPC 0x741
+#define CSR_MNCAUSE 0x742
+#define CSR_MNSTATUS 0x744
/* Smstateen extension */
#define CSR_MSTATEEN0 0x30c
#define CSR_MSTATEEN1 0x30d
@@ -3106,6 +3114,8 @@ DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B)
DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H)
DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W)
DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D)
+/* Smrnmi instructions. */
+DECLARE_INSN(mnret, MATCH_MNRET, MASK_MNRET)
/* Zicbop instructions. */
DECLARE_INSN(prefetch_r, MATCH_PREFETCH_R, MASK_PREFETCH_R);
DECLARE_INSN(prefetch_w, MATCH_PREFETCH_W, MASK_PREFETCH_W);
@@ -3550,6 +3560,11 @@ DECLARE_CSR(mieh, CSR_MIEH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_
DECLARE_CSR(mvienh, CSR_MVIENH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mviph, CSR_MVIPH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(miph, CSR_MIPH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+/* Smrnmi extension CSRs. */
+DECLARE_CSR(mnscratch, CSR_MNSCRATCH, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mnepc, CSR_MNEPC, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mncause, CSR_MNCAUSE, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mnstatus, CSR_MNSTATUS, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
/* Smstateen/Ssstateen extensions. */
DECLARE_CSR(mstateen0, CSR_MSTATEEN0, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mstateen1, CSR_MSTATEEN1, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index c3cbde600cb0..d979ef4ac6db 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -405,6 +405,7 @@ enum riscv_insn_class
INSN_CLASS_ZKND_OR_ZKNE,
INSN_CLASS_V,
INSN_CLASS_ZVEF,
+ INSN_CLASS_SMRNMI,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 0e691544f9bc..2194289469cd 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1847,6 +1847,9 @@ const struct riscv_opcode riscv_opcodes[] =
{"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
{"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
+/* Smrnmi instructions. */
+{"mnret", 0, INSN_CLASS_SMRNMI, "", MATCH_MNRET, MASK_MNRET, match_opcode, 0 },
+
/* Svinval instructions. */
{"sinval.vma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_SINVAL_VMA, MASK_SINVAL_VMA, match_opcode, 0 },
{"sfence.w.inval", 0, INSN_CLASS_SVINVAL, "", MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL, match_opcode, 0 },
--
2.38.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [REVIEW ONLY 1/1] UNRATIFIED RISC-V: Add 'Smrnmi' extension and its CSRs
2022-11-29 1:21 ` [REVIEW ONLY 1/1] UNRATIFIED RISC-V: Add 'Smrnmi' extension and its CSRs Tsukasa OI
@ 2022-11-29 2:38 ` Palmer Dabbelt
0 siblings, 0 replies; 7+ messages in thread
From: Palmer Dabbelt @ 2022-11-29 2:38 UTC (permalink / raw)
To: binutils; +Cc: research_trasio, binutils
On Mon, 28 Nov 2022 17:21:51 PST (-0800), binutils@sourceware.org wrote:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>
> [DO NOT MERGE]
> Until 'Smrnmi' extension is frozen/ratified and final version number is
> determined, this patch should not be merged upstream. This commit uses
> unratified version 0.4 as in the documentation (instead of possible 1.0
> after ratification).
>
> This commit adds "mnret" instruction and RNMI-related CSRs from the
> Resumable Non-Maskable Interrupts ('Smrnmi') extension.
>
> This is based on:
> <https://github.com/riscv/riscv-isa-manual/commit/28b46de77ca7fb94ffcf6cf669cc27269f6013de>,
> latest 'Smrnmi' change on the master branch of the RISC-V ISA Manual
> as of this writing.
>
> bfd/ChangeLog:
>
> * elfxx-riscv.c (riscv_implicit_subsets): Make 'Smrnmi' to imply
> 'Zicsr' extension. (riscv_multi_subset_supports): Add new
> instruction class handling.
> (riscv_multi_subset_supports_ext): Likewise.
>
> gas/ChangeLog:
>
> * config/tc-riscv.c (enum riscv_csr_class): Add new CSR class.
> (riscv_csr_address): Add new CSR class handling.
> * testsuite/gas/riscv/csr.s: Add new CSR test.
> * testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
> * testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
> * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
> * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
> * testsuite/gas/riscv/csr-version-1p10.d: Likewise.
> * testsuite/gas/riscv/csr-version-1p10.l: Likewise.
> * testsuite/gas/riscv/csr-version-1p11.d: Likewise.
> * testsuite/gas/riscv/csr-version-1p11.l: Likewise.
> * testsuite/gas/riscv/csr-version-1p12.d: Likewise.
> * testsuite/gas/riscv/csr-version-1p12.l: Likewise.
> * testsuite/gas/riscv/smrnmi.s: New test for mnret instruction.
> * testsuite/gas/riscv/smrnmi.d: Likewise.
> * testsuite/gas/riscv/smrnmi-noarch.d: New test for architecture
> failure.
> * testsuite/gas/riscv/smrnmi-noarch.l: Likewise.
>
> include/ChangeLog:
>
> * opcode/riscv-opc.h (MATCH_MNRET, MASK_MNRET, CSR_MNSCRATCH,
> CSR_MNEPC, CSR_MNCAUSE, CSR_MNSTATUS): New.
> * opcode/riscv.h (enum riscv_insn_class): Add new instruction
> class.
>
> opcodes/ChangeLog:
>
> * riscv-opc.c (riscv_opcodes): Add 'mnret' instruction.
> ---
> bfd/elfxx-riscv.c | 6 ++++++
> gas/config/tc-riscv.c | 4 ++++
> gas/testsuite/gas/riscv/csr-dw-regnums.d | 4 ++++
> gas/testsuite/gas/riscv/csr-dw-regnums.s | 5 +++++
> gas/testsuite/gas/riscv/csr-version-1p10.d | 8 ++++++++
> gas/testsuite/gas/riscv/csr-version-1p10.l | 8 ++++++++
> gas/testsuite/gas/riscv/csr-version-1p11.d | 8 ++++++++
> gas/testsuite/gas/riscv/csr-version-1p11.l | 8 ++++++++
> gas/testsuite/gas/riscv/csr-version-1p12.d | 8 ++++++++
> gas/testsuite/gas/riscv/csr-version-1p12.l | 8 ++++++++
> gas/testsuite/gas/riscv/csr-version-1p9p1.d | 8 ++++++++
> gas/testsuite/gas/riscv/csr-version-1p9p1.l | 8 ++++++++
> gas/testsuite/gas/riscv/csr.s | 6 ++++++
> gas/testsuite/gas/riscv/smrnmi-noarch.d | 3 +++
> gas/testsuite/gas/riscv/smrnmi-noarch.l | 2 ++
> gas/testsuite/gas/riscv/smrnmi.d | 10 ++++++++++
> gas/testsuite/gas/riscv/smrnmi.s | 2 ++
> include/opcode/riscv-opc.h | 15 +++++++++++++++
> include/opcode/riscv.h | 1 +
> opcodes/riscv-opc.c | 3 +++
> 20 files changed, 125 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/smrnmi-noarch.d
> create mode 100644 gas/testsuite/gas/riscv/smrnmi-noarch.l
> create mode 100644 gas/testsuite/gas/riscv/smrnmi.d
> create mode 100644 gas/testsuite/gas/riscv/smrnmi.s
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 0bcf2fdcfa34..d4f580733ddd 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1104,6 +1104,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
> {"smaia", "ssaia", check_implicit_always},
> {"smstateen", "ssstateen", check_implicit_always},
> {"smepmp", "zicsr", check_implicit_always},
> + {"smrnmi", "zicsr", check_implicit_always},
> {"ssaia", "zicsr", check_implicit_always},
> {"sscofpmf", "zicsr", check_implicit_always},
> {"ssstateen", "zicsr", check_implicit_always},
> @@ -1225,6 +1226,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] =
> {
> {"smaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"smrnmi", ISA_SPEC_CLASS_DRAFT, 0, 4, 0 },
> {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"ssaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> @@ -2415,6 +2417,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
> || riscv_subset_supports (rps, "zve64d")
> || riscv_subset_supports (rps, "zve64f")
> || riscv_subset_supports (rps, "zve32f"));
> + case INSN_CLASS_SMRNMI:
> + return riscv_subset_supports (rps, "smrnmi");
> case INSN_CLASS_SVINVAL:
> return riscv_subset_supports (rps, "svinval");
> case INSN_CLASS_H:
> @@ -2573,6 +2577,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
> return _("v' or `zve64x' or `zve32x");
> case INSN_CLASS_ZVEF:
> return _("v' or `zve64d' or `zve64f' or `zve32f");
> + case INSN_CLASS_SMRNMI:
> + return "smrnmi";
> case INSN_CLASS_SVINVAL:
> return "svinval";
> case INSN_CLASS_H:
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index 0682eb355241..85aa4d1d00d4 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -74,6 +74,7 @@ enum riscv_csr_class
> CSR_CLASS_H_32, /* hypervisor, rv32 only */
> CSR_CLASS_SMAIA, /* Smaia */
> CSR_CLASS_SMAIA_32, /* Smaia, rv32 only */
> + CSR_CLASS_SMRNMI, /* Smrnmi only */
> CSR_CLASS_SMSTATEEN, /* Smstateen only */
> CSR_CLASS_SMSTATEEN_32, /* Smstateen RV32 only */
> CSR_CLASS_SSAIA, /* Ssaia */
> @@ -1049,6 +1050,9 @@ riscv_csr_address (const char *csr_name,
> case CSR_CLASS_SMAIA:
> extension = "smaia";
> break;
> + case CSR_CLASS_SMRNMI:
> + extension = "smrnmi";
> + break;
> case CSR_CLASS_SMSTATEEN:
> case CSR_CLASS_SMSTATEEN_32:
> is_rv32_only = (csr_class == CSR_CLASS_SMSTATEEN_32);
> diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
> index fd830666ab89..a87df625da9d 100644
> --- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
> +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
> @@ -324,6 +324,10 @@ Contents of the .* section:
> DW_CFA_offset_extended_sf: r4888 \(mvienh\) at cfa\+3168
> DW_CFA_offset_extended_sf: r4889 \(mviph\) at cfa\+3172
> DW_CFA_offset_extended_sf: r4948 \(miph\) at cfa\+3408
> + DW_CFA_offset_extended_sf: r5952 \(mnscratch\) at cfa\+7424
> + DW_CFA_offset_extended_sf: r5953 \(mnepc\) at cfa\+7428
> + DW_CFA_offset_extended_sf: r5954 \(mncause\) at cfa\+7432
> + DW_CFA_offset_extended_sf: r5956 \(mnstatus\) at cfa\+7440
> DW_CFA_offset_extended_sf: r4876 \(mstateen0\) at cfa\+3120
> DW_CFA_offset_extended_sf: r4877 \(mstateen1\) at cfa\+3124
> DW_CFA_offset_extended_sf: r4878 \(mstateen2\) at cfa\+3128
> diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s
> index b8b0f7902297..3ea3853a2cc5 100644
> --- a/gas/testsuite/gas/riscv/csr-dw-regnums.s
> +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s
> @@ -321,6 +321,11 @@ _start:
> .cfi_offset mvienh, 3168
> .cfi_offset mviph, 3172
> .cfi_offset miph, 3408
> + # Smrnmi extension
> + .cfi_offset mnscratch, 7424
> + .cfi_offset mnepc, 7428
> + .cfi_offset mncause, 7432
> + .cfi_offset mnstatus, 7440
> # Smstateen extension
> .cfi_offset mstateen0, 3120
> .cfi_offset mstateen1, 3124
> diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d
> index ee41e1025cce..9c2bf4bc9628 100644
> --- a/gas/testsuite/gas/riscv/csr-version-1p10.d
> +++ b/gas/testsuite/gas/riscv/csr-version-1p10.d
> @@ -623,6 +623,14 @@ Disassembly of section .text:
> [ ]+[0-9a-f]+:[ ]+31959073[ ]+csrw[ ]+mviph,a1
> [ ]+[0-9a-f]+:[ ]+35402573[ ]+csrr[ ]+a0,miph
> [ ]+[0-9a-f]+:[ ]+35459073[ ]+csrw[ ]+miph,a1
> +[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch
> +[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1
> +[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc
> +[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1
> +[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause
> +[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1
> +[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus
> +[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1
> [ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0
> [ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1
> [ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1
> diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l
> index e677b78b8bb8..b00515d2cf13 100644
> --- a/gas/testsuite/gas/riscv/csr-version-1p10.l
> +++ b/gas/testsuite/gas/riscv/csr-version-1p10.l
> @@ -444,6 +444,14 @@
> .*Warning: invalid CSR `miph', needs `smaia' extension
> .*Warning: invalid CSR `miph', needs rv32i extension
> .*Warning: invalid CSR `miph', needs `smaia' extension
> +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
> +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
> +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
> +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
> +.*Warning: invalid CSR `mncause', needs `smrnmi' extension
> +.*Warning: invalid CSR `mncause', needs `smrnmi' extension
> +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
> +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
> .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
> .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
> .*Warning: invalid CSR `mstateen1', needs `smstateen' extension
> diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d
> index a83b1bf68f98..9783cb795e2c 100644
> --- a/gas/testsuite/gas/riscv/csr-version-1p11.d
> +++ b/gas/testsuite/gas/riscv/csr-version-1p11.d
> @@ -623,6 +623,14 @@ Disassembly of section .text:
> [ ]+[0-9a-f]+:[ ]+31959073[ ]+csrw[ ]+mviph,a1
> [ ]+[0-9a-f]+:[ ]+35402573[ ]+csrr[ ]+a0,miph
> [ ]+[0-9a-f]+:[ ]+35459073[ ]+csrw[ ]+miph,a1
> +[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch
> +[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1
> +[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc
> +[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1
> +[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause
> +[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1
> +[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus
> +[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1
> [ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0
> [ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1
> [ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1
> diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l
> index 81ca86ca7bcc..da5167dab7e3 100644
> --- a/gas/testsuite/gas/riscv/csr-version-1p11.l
> +++ b/gas/testsuite/gas/riscv/csr-version-1p11.l
> @@ -442,6 +442,14 @@
> .*Warning: invalid CSR `miph', needs `smaia' extension
> .*Warning: invalid CSR `miph', needs rv32i extension
> .*Warning: invalid CSR `miph', needs `smaia' extension
> +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
> +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
> +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
> +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
> +.*Warning: invalid CSR `mncause', needs `smrnmi' extension
> +.*Warning: invalid CSR `mncause', needs `smrnmi' extension
> +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
> +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
> .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
> .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
> .*Warning: invalid CSR `mstateen1', needs `smstateen' extension
> diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d
> index 612aac280768..e39473062d5a 100644
> --- a/gas/testsuite/gas/riscv/csr-version-1p12.d
> +++ b/gas/testsuite/gas/riscv/csr-version-1p12.d
> @@ -623,6 +623,14 @@ Disassembly of section .text:
> [ ]+[0-9a-f]+:[ ]+31959073[ ]+csrw[ ]+mviph,a1
> [ ]+[0-9a-f]+:[ ]+35402573[ ]+csrr[ ]+a0,miph
> [ ]+[0-9a-f]+:[ ]+35459073[ ]+csrw[ ]+miph,a1
> +[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch
> +[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1
> +[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc
> +[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1
> +[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause
> +[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1
> +[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus
> +[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1
> [ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0
> [ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1
> [ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1
> diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l
> index 1c0bb4ef2d8f..011e5d578309 100644
> --- a/gas/testsuite/gas/riscv/csr-version-1p12.l
> +++ b/gas/testsuite/gas/riscv/csr-version-1p12.l
> @@ -304,6 +304,14 @@
> .*Warning: invalid CSR `miph', needs `smaia' extension
> .*Warning: invalid CSR `miph', needs rv32i extension
> .*Warning: invalid CSR `miph', needs `smaia' extension
> +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
> +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
> +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
> +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
> +.*Warning: invalid CSR `mncause', needs `smrnmi' extension
> +.*Warning: invalid CSR `mncause', needs `smrnmi' extension
> +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
> +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
> .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
> .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
> .*Warning: invalid CSR `mstateen1', needs `smstateen' extension
> diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.d b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
> index 0fe849c269c2..819292888aaa 100644
> --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.d
> +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
> @@ -623,6 +623,14 @@ Disassembly of section .text:
> [ ]+[0-9a-f]+:[ ]+31959073[ ]+csrw[ ]+mviph,a1
> [ ]+[0-9a-f]+:[ ]+35402573[ ]+csrr[ ]+a0,miph
> [ ]+[0-9a-f]+:[ ]+35459073[ ]+csrw[ ]+miph,a1
> +[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch
> +[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1
> +[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc
> +[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1
> +[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause
> +[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1
> +[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus
> +[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1
> [ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0
> [ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1
> [ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1
> diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l b/gas/testsuite/gas/riscv/csr-version-1p9p1.l
> index c65d0b48e414..daf7e94bbace 100644
> --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l
> +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.l
> @@ -494,6 +494,14 @@
> .*Warning: invalid CSR `miph', needs `smaia' extension
> .*Warning: invalid CSR `miph', needs rv32i extension
> .*Warning: invalid CSR `miph', needs `smaia' extension
> +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
> +.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
> +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
> +.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
> +.*Warning: invalid CSR `mncause', needs `smrnmi' extension
> +.*Warning: invalid CSR `mncause', needs `smrnmi' extension
> +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
> +.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
> .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
> .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
> .*Warning: invalid CSR `mstateen1', needs `smstateen' extension
> diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s
> index c7406ce34c2e..3508c42f623c 100644
> --- a/gas/testsuite/gas/riscv/csr.s
> +++ b/gas/testsuite/gas/riscv/csr.s
> @@ -350,6 +350,12 @@
> csr mviph
> csr miph
>
> + # Smrnmi extension
> + csr mnscratch
> + csr mnepc
> + csr mncause
> + csr mnstatus
> +
> # Smstateen/Ssstateen extensions
> csr mstateen0
> csr mstateen1
> diff --git a/gas/testsuite/gas/riscv/smrnmi-noarch.d b/gas/testsuite/gas/riscv/smrnmi-noarch.d
> new file mode 100644
> index 000000000000..d28da9736300
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/smrnmi-noarch.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i
> +#source: smrnmi.s
> +#error_output: smrnmi-noarch.l
> diff --git a/gas/testsuite/gas/riscv/smrnmi-noarch.l b/gas/testsuite/gas/riscv/smrnmi-noarch.l
> new file mode 100644
> index 000000000000..1ad5141c1245
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/smrnmi-noarch.l
> @@ -0,0 +1,2 @@
> +.*: Assembler messages:
> +.*: Error: unrecognized opcode `mnret', extension `smrnmi' required
> diff --git a/gas/testsuite/gas/riscv/smrnmi.d b/gas/testsuite/gas/riscv/smrnmi.d
> new file mode 100644
> index 000000000000..2b628e91a103
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/smrnmi.d
> @@ -0,0 +1,10 @@
> +#as: -march=rv32i_smrnmi
> +#source: smrnmi.s
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+70200073[ ]+mnret
> diff --git a/gas/testsuite/gas/riscv/smrnmi.s b/gas/testsuite/gas/riscv/smrnmi.s
> new file mode 100644
> index 000000000000..f2008bd8704e
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/smrnmi.s
> @@ -0,0 +1,2 @@
> +target:
> + mnret
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index 06e3df0f5a63..d80c7fb5a876 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -2055,6 +2055,9 @@
> #define MASK_VDOTUVV 0xfc00707f
> #define MATCH_VFDOTVV 0xe4001057
> #define MASK_VFDOTVV 0xfc00707f
> +/* Smrnmi instruction. */
> +#define MATCH_MNRET 0x70200073
> +#define MASK_MNRET 0xffffffff
> /* Svinval instruction. */
> #define MATCH_SINVAL_VMA 0x16000073
> #define MASK_SINVAL_VMA 0xfe007fff
> @@ -2673,6 +2676,11 @@
> #define CSR_MVIENH 0x318
> #define CSR_MVIPH 0x319
> #define CSR_MIPH 0x354
> +/* Smrnmi extension CSR addresses. */
> +#define CSR_MNSCRATCH 0x740
> +#define CSR_MNEPC 0x741
> +#define CSR_MNCAUSE 0x742
> +#define CSR_MNSTATUS 0x744
> /* Smstateen extension */
> #define CSR_MSTATEEN0 0x30c
> #define CSR_MSTATEEN1 0x30d
> @@ -3106,6 +3114,8 @@ DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B)
> DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H)
> DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W)
> DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D)
> +/* Smrnmi instructions. */
> +DECLARE_INSN(mnret, MATCH_MNRET, MASK_MNRET)
> /* Zicbop instructions. */
> DECLARE_INSN(prefetch_r, MATCH_PREFETCH_R, MASK_PREFETCH_R);
> DECLARE_INSN(prefetch_w, MATCH_PREFETCH_W, MASK_PREFETCH_W);
> @@ -3550,6 +3560,11 @@ DECLARE_CSR(mieh, CSR_MIEH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_
> DECLARE_CSR(mvienh, CSR_MVIENH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
> DECLARE_CSR(mviph, CSR_MVIPH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
> DECLARE_CSR(miph, CSR_MIPH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
> +/* Smrnmi extension CSRs. */
> +DECLARE_CSR(mnscratch, CSR_MNSCRATCH, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
> +DECLARE_CSR(mnepc, CSR_MNEPC, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
> +DECLARE_CSR(mncause, CSR_MNCAUSE, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
> +DECLARE_CSR(mnstatus, CSR_MNSTATUS, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
> /* Smstateen/Ssstateen extensions. */
> DECLARE_CSR(mstateen0, CSR_MSTATEEN0, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
> DECLARE_CSR(mstateen1, CSR_MSTATEEN1, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index c3cbde600cb0..d979ef4ac6db 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -405,6 +405,7 @@ enum riscv_insn_class
> INSN_CLASS_ZKND_OR_ZKNE,
> INSN_CLASS_V,
> INSN_CLASS_ZVEF,
> + INSN_CLASS_SMRNMI,
> INSN_CLASS_SVINVAL,
> INSN_CLASS_ZICBOM,
> INSN_CLASS_ZICBOP,
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index 0e691544f9bc..2194289469cd 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -1847,6 +1847,9 @@ const struct riscv_opcode riscv_opcodes[] =
> {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
> {"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
>
> +/* Smrnmi instructions. */
> +{"mnret", 0, INSN_CLASS_SMRNMI, "", MATCH_MNRET, MASK_MNRET, match_opcode, 0 },
> +
> /* Svinval instructions. */
> {"sinval.vma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_SINVAL_VMA, MASK_SINVAL_VMA, match_opcode, 0 },
> {"sfence.w.inval", 0, INSN_CLASS_SVINVAL, "", MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL, match_opcode, 0 },
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> # pending freeze
^ permalink raw reply [flat|nested] 7+ messages in thread
* [REVIEW ONLY v3 0/1] RISC-V (unratified): Add 'Smrnmi' extension
2022-11-29 1:21 ` [REVIEW ONLY 0/1] RISC-V (unratified): " Tsukasa OI
2022-11-29 1:21 ` [REVIEW ONLY 1/1] UNRATIFIED RISC-V: Add 'Smrnmi' extension and its CSRs Tsukasa OI
@ 2023-09-12 1:40 ` Tsukasa OI
2023-09-12 1:40 ` [REVIEW ONLY v3 1/1] UNRATIFIED RISC-V: Add 'Smrnmi' extension and its CSRs Tsukasa OI
1 sibling, 1 reply; 7+ messages in thread
From: Tsukasa OI @ 2023-09-12 1:40 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
*** WAIT FOR SPECIFICATION FREEZE ***
This is an implementation for unratified and not frozen RISC-V extension
and not intended to be merged for now.
The only intent to submit this patchset is to test new instructions for
your (possibly virtual) environment and early review for fast adoption
after ratification.
This is the review-only PATCH v3 to keep track with the latest GNU Binutils.
In this version, I didn't add anything new but rebases on the latest master
(previous one should cause merge conflicts).
This patchset adds following unratified extension to GNU Binutils:
- Smrnmi (Resumable NMI)
version 0.4 (may change on ratification)
... which adds "mnret" instruction and 4 CSRs related to RNMI.
This extension provides "resumable NMIs" to provide special non-maskable
interrupts (NMIs) with "resume" capability (normally, NMIs are are only used
for hardware error conditions and not resumable; however on some conditions,
there are some cases where using NMIs fits better yet resumable after
proper handling by the NMI handler [which may fail though]).
This is based on a draft version of the RISC-V ISA Manual:
<https://github.com/riscv/riscv-isa-manual/commit/934552c832a70206dd026a3d54aee543d902ef4b>
Note that it has **different** CSR values between proposed RNMI version
0.4 and RNMI as optionally implemented in SiFive U74-MC:
<https://sifive.cdn.prismic.io/sifive/2dd11994-693c-4360-8aea-5453d8642c42_u74mc_core_complex_manual_21G3.pdf>
| CSR | proposed | SiFive |
| --------- | -------- | ------ |
| mnscratch | 0x740 | 0x350 |
| mnepc | 0x741 | 0x351 |
| mncause | 0x742 | 0x352 |
| mnstatus | 0x744 | 0x353 |
Also, although that 4 CSRs are assigned with actual numbers (this is why I'm
not attaching "CSR instantiation" script in this patchset), it may be
changed before ratification. Be careful.
Tsukasa OI (1):
UNRATIFIED RISC-V: Add 'Smrnmi' extension and its CSRs
bfd/elfxx-riscv.c | 6 ++++++
gas/config/tc-riscv.c | 4 ++++
gas/testsuite/gas/riscv/csr-dw-regnums.d | 4 ++++
gas/testsuite/gas/riscv/csr-dw-regnums.s | 5 +++++
gas/testsuite/gas/riscv/csr-version-1p10.d | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p10.l | 16 ++++++++++++++++
gas/testsuite/gas/riscv/csr-version-1p11.d | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p11.l | 16 ++++++++++++++++
gas/testsuite/gas/riscv/csr-version-1p12.d | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p12.l | 16 ++++++++++++++++
gas/testsuite/gas/riscv/csr-version-1p9p1.d | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p9p1.l | 16 ++++++++++++++++
gas/testsuite/gas/riscv/csr.s | 6 ++++++
gas/testsuite/gas/riscv/smrnmi-noarch.d | 3 +++
gas/testsuite/gas/riscv/smrnmi-noarch.l | 2 ++
gas/testsuite/gas/riscv/smrnmi.d | 10 ++++++++++
gas/testsuite/gas/riscv/smrnmi.s | 2 ++
include/opcode/riscv-opc.h | 15 +++++++++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 3 +++
20 files changed, 157 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/smrnmi-noarch.d
create mode 100644 gas/testsuite/gas/riscv/smrnmi-noarch.l
create mode 100644 gas/testsuite/gas/riscv/smrnmi.d
create mode 100644 gas/testsuite/gas/riscv/smrnmi.s
base-commit: 318d3bda5cad124bd11eebb0349d0f183ba625b1
--
2.42.0
^ permalink raw reply [flat|nested] 7+ messages in thread
* [REVIEW ONLY v3 1/1] UNRATIFIED RISC-V: Add 'Smrnmi' extension and its CSRs
2023-09-12 1:40 ` [REVIEW ONLY v3 0/1] RISC-V (unratified): Add 'Smrnmi' extension Tsukasa OI
@ 2023-09-12 1:40 ` Tsukasa OI
0 siblings, 0 replies; 7+ messages in thread
From: Tsukasa OI @ 2023-09-12 1:40 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils
From: Tsukasa OI <research_trasio@irq.a4lg.com>
[DO NOT MERGE]
Until 'Smrnmi' extension is frozen/ratified and final version number is
determined, this patch should not be merged upstream. This commit uses
unratified version 0.4 as in the documentation (instead of possible 1.0
after ratification).
This commit adds "mnret" instruction and RNMI-related CSRs from the
Resumable Non-Maskable Interrupts ('Smrnmi') extension.
This is based on:
<https://github.com/riscv/riscv-isa-manual/commit/28b46de77ca7fb94ffcf6cf669cc27269f6013de>,
latest 'Smrnmi' change on the master branch of the RISC-V ISA Manual
as of this writing.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): Make 'Smrnmi' to imply
'Zicsr' extension. (riscv_multi_subset_supports): Add new
instruction class handling.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* config/tc-riscv.c (enum riscv_csr_class): Add new CSR class.
(riscv_csr_address): Add new CSR class handling.
* testsuite/gas/riscv/csr.s: Add new CSR test.
* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
* testsuite/gas/riscv/csr-version-1p10.d: Likewise.
* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
* testsuite/gas/riscv/smrnmi.s: New test for mnret instruction.
* testsuite/gas/riscv/smrnmi.d: Likewise.
* testsuite/gas/riscv/smrnmi-noarch.d: New test for architecture
failure.
* testsuite/gas/riscv/smrnmi-noarch.l: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_MNRET, MASK_MNRET, CSR_MNSCRATCH,
CSR_MNEPC, CSR_MNCAUSE, CSR_MNSTATUS): New.
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
class.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Add 'mnret' instruction.
---
bfd/elfxx-riscv.c | 6 ++++++
gas/config/tc-riscv.c | 4 ++++
gas/testsuite/gas/riscv/csr-dw-regnums.d | 4 ++++
gas/testsuite/gas/riscv/csr-dw-regnums.s | 5 +++++
gas/testsuite/gas/riscv/csr-version-1p10.d | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p10.l | 16 ++++++++++++++++
gas/testsuite/gas/riscv/csr-version-1p11.d | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p11.l | 16 ++++++++++++++++
gas/testsuite/gas/riscv/csr-version-1p12.d | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p12.l | 16 ++++++++++++++++
gas/testsuite/gas/riscv/csr-version-1p9p1.d | 8 ++++++++
gas/testsuite/gas/riscv/csr-version-1p9p1.l | 16 ++++++++++++++++
gas/testsuite/gas/riscv/csr.s | 6 ++++++
gas/testsuite/gas/riscv/smrnmi-noarch.d | 3 +++
gas/testsuite/gas/riscv/smrnmi-noarch.l | 2 ++
gas/testsuite/gas/riscv/smrnmi.d | 10 ++++++++++
gas/testsuite/gas/riscv/smrnmi.s | 2 ++
include/opcode/riscv-opc.h | 15 +++++++++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 3 +++
20 files changed, 157 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/smrnmi-noarch.d
create mode 100644 gas/testsuite/gas/riscv/smrnmi-noarch.l
create mode 100644 gas/testsuite/gas/riscv/smrnmi.d
create mode 100644 gas/testsuite/gas/riscv/smrnmi.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 6ed657171f0f..bcf9caecff5d 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1186,6 +1186,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"smcntrpmf", "zicsr", check_implicit_always},
{"smstateen", "ssstateen", check_implicit_always},
{"smepmp", "zicsr", check_implicit_always},
+ {"smrnmi", "zicsr", check_implicit_always},
{"ssaia", "zicsr", check_implicit_always},
{"sscofpmf", "zicsr", check_implicit_always},
{"ssstateen", "zicsr", check_implicit_always},
@@ -1332,6 +1333,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] =
{"smaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"smcntrpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"smrnmi", ISA_SPEC_CLASS_DRAFT, 0, 4, 0 },
{"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"ssaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2545,6 +2547,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
case INSN_CLASS_ZCB_AND_ZMMUL:
return (riscv_subset_supports (rps, "zcb")
&& riscv_subset_supports (rps, "zmmul"));
+ case INSN_CLASS_SMRNMI:
+ return riscv_subset_supports (rps, "smrnmi");
case INSN_CLASS_SVINVAL:
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
@@ -2785,6 +2789,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("zcb' and `zbb");
case INSN_CLASS_ZCB_AND_ZMMUL:
return _("zcb' and `zmmul', or `zcb' and `m");
+ case INSN_CLASS_SMRNMI:
+ return "smrnmi";
case INSN_CLASS_SVINVAL:
return "svinval";
case INSN_CLASS_H:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index cf6e0d8b0150..538e1ee62c7f 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -76,6 +76,7 @@ enum riscv_csr_class
CSR_CLASS_SMAIA_32, /* Smaia, rv32 only */
CSR_CLASS_SMCNTRPMF, /* Smcntrpmf */
CSR_CLASS_SMCNTRPMF_32, /* Smcntrpmf, rv32 only */
+ CSR_CLASS_SMRNMI, /* Smrnmi only */
CSR_CLASS_SMSTATEEN, /* Smstateen only */
CSR_CLASS_SMSTATEEN_32, /* Smstateen RV32 only */
CSR_CLASS_SSAIA, /* Ssaia */
@@ -1061,6 +1062,9 @@ riscv_csr_address (const char *csr_name,
need_check_version = true;
extension = "smcntrpmf";
break;
+ case CSR_CLASS_SMRNMI:
+ extension = "smrnmi";
+ break;
case CSR_CLASS_SMSTATEEN_32:
is_rv32_only = true;
/* Fall through. */
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
index cabb7c719181..518a6d833643 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
@@ -328,6 +328,10 @@ Contents of the .* section:
DW_CFA_offset_extended_sf: r4898 \(minstretcfg\) at cfa\+3208
DW_CFA_offset_extended_sf: r5921 \(mcyclecfgh\) at cfa\+7300
DW_CFA_offset_extended_sf: r5922 \(minstretcfgh\) at cfa\+7304
+ DW_CFA_offset_extended_sf: r5952 \(mnscratch\) at cfa\+7424
+ DW_CFA_offset_extended_sf: r5953 \(mnepc\) at cfa\+7428
+ DW_CFA_offset_extended_sf: r5954 \(mncause\) at cfa\+7432
+ DW_CFA_offset_extended_sf: r5956 \(mnstatus\) at cfa\+7440
DW_CFA_offset_extended_sf: r4876 \(mstateen0\) at cfa\+3120
DW_CFA_offset_extended_sf: r4877 \(mstateen1\) at cfa\+3124
DW_CFA_offset_extended_sf: r4878 \(mstateen2\) at cfa\+3128
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s
index 428d07707790..030d4687a506 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.s
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s
@@ -326,6 +326,11 @@ _start:
.cfi_offset minstretcfg, 3208
.cfi_offset mcyclecfgh, 7300
.cfi_offset minstretcfgh, 7304
+ # Smrnmi extension
+ .cfi_offset mnscratch, 7424
+ .cfi_offset mnepc, 7428
+ .cfi_offset mncause, 7432
+ .cfi_offset mnstatus, 7440
# Smstateen extension
.cfi_offset mstateen0, 3120
.cfi_offset mstateen1, 3124
diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d
index dbdc077adac8..94836dd26b0e 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p10.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.d
@@ -631,6 +631,14 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+72159073[ ]+csrw[ ]+mcyclecfgh,a1
[ ]+[0-9a-f]+:[ ]+72202573[ ]+csrr[ ]+a0,minstretcfgh
[ ]+[0-9a-f]+:[ ]+72259073[ ]+csrw[ ]+minstretcfgh,a1
+[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch
+[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1
+[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc
+[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1
+[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause
+[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1
+[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus
+[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1
[ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0
[ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1
[ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l
index 054179a416db..475ab3c93577 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p10.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.l
@@ -913,6 +913,22 @@
.*Info: macro .*
.*Warning: invalid CSR `minstretcfgh', needs `smcntrpmf' extension
.*Info: macro .*
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
.*Info: macro .*
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d
index 7ba88b6d1d53..12f19e80e9b7 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p11.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.d
@@ -631,6 +631,14 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+72159073[ ]+csrw[ ]+mcyclecfgh,a1
[ ]+[0-9a-f]+:[ ]+72202573[ ]+csrr[ ]+a0,minstretcfgh
[ ]+[0-9a-f]+:[ ]+72259073[ ]+csrw[ ]+minstretcfgh,a1
+[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch
+[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1
+[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc
+[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1
+[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause
+[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1
+[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus
+[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1
[ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0
[ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1
[ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l
index cc365f1df415..43c913935b92 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p11.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.l
@@ -909,6 +909,22 @@
.*Info: macro .*
.*Warning: invalid CSR `minstretcfgh', needs `smcntrpmf' extension
.*Info: macro .*
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
.*Info: macro .*
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d
index 677820b95265..b1c1e7646ea2 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p12.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.d
@@ -631,6 +631,14 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+72159073[ ]+csrw[ ]+mcyclecfgh,a1
[ ]+[0-9a-f]+:[ ]+72202573[ ]+csrr[ ]+a0,minstretcfgh
[ ]+[0-9a-f]+:[ ]+72259073[ ]+csrw[ ]+minstretcfgh,a1
+[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch
+[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1
+[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc
+[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1
+[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause
+[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1
+[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus
+[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1
[ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0
[ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1
[ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l
index 7a7f5f717c52..20501c5987f6 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p12.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.l
@@ -633,6 +633,22 @@
.*Info: macro .*
.*Warning: invalid CSR `minstretcfgh', needs `smcntrpmf' extension
.*Info: macro .*
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
.*Info: macro .*
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.d b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
index f4d2b04ca6a4..c40017b81638 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p9p1.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
@@ -631,6 +631,14 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+72159073[ ]+csrw[ ]+0x721,a1
[ ]+[0-9a-f]+:[ ]+72202573[ ]+csrr[ ]+a0,0x722
[ ]+[0-9a-f]+:[ ]+72259073[ ]+csrw[ ]+0x722,a1
+[ ]+[0-9a-f]+:[ ]+74002573[ ]+csrr[ ]+a0,mnscratch
+[ ]+[0-9a-f]+:[ ]+74059073[ ]+csrw[ ]+mnscratch,a1
+[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc
+[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1
+[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause
+[ ]+[0-9a-f]+:[ ]+74259073[ ]+csrw[ ]+mncause,a1
+[ ]+[0-9a-f]+:[ ]+74402573[ ]+csrr[ ]+a0,mnstatus
+[ ]+[0-9a-f]+:[ ]+74459073[ ]+csrw[ ]+mnstatus,a1
[ ]+[0-9a-f]+:[ ]+30c02573[ ]+csrr[ ]+a0,mstateen0
[ ]+[0-9a-f]+:[ ]+30c59073[ ]+csrw[ ]+mstateen0,a1
[ ]+[0-9a-f]+:[ ]+30d02573[ ]+csrr[ ]+a0,mstateen1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l b/gas/testsuite/gas/riscv/csr-version-1p9p1.l
index 7fcd73ab7ddd..b375bb03ac5d 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.l
@@ -1029,6 +1029,22 @@
.*Info: macro .*
.*Warning: invalid CSR `minstretcfgh' for the privileged spec `1.9.1'
.*Info: macro .*
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
.*Info: macro .*
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s
index 3d8da5488a04..e43b8a1fed1a 100644
--- a/gas/testsuite/gas/riscv/csr.s
+++ b/gas/testsuite/gas/riscv/csr.s
@@ -356,6 +356,12 @@
csr mcyclecfgh
csr minstretcfgh
+ # Smrnmi extension
+ csr mnscratch
+ csr mnepc
+ csr mncause
+ csr mnstatus
+
# Smstateen/Ssstateen extensions
csr mstateen0
csr mstateen1
diff --git a/gas/testsuite/gas/riscv/smrnmi-noarch.d b/gas/testsuite/gas/riscv/smrnmi-noarch.d
new file mode 100644
index 000000000000..d28da9736300
--- /dev/null
+++ b/gas/testsuite/gas/riscv/smrnmi-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i
+#source: smrnmi.s
+#error_output: smrnmi-noarch.l
diff --git a/gas/testsuite/gas/riscv/smrnmi-noarch.l b/gas/testsuite/gas/riscv/smrnmi-noarch.l
new file mode 100644
index 000000000000..1ad5141c1245
--- /dev/null
+++ b/gas/testsuite/gas/riscv/smrnmi-noarch.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `mnret', extension `smrnmi' required
diff --git a/gas/testsuite/gas/riscv/smrnmi.d b/gas/testsuite/gas/riscv/smrnmi.d
new file mode 100644
index 000000000000..2b628e91a103
--- /dev/null
+++ b/gas/testsuite/gas/riscv/smrnmi.d
@@ -0,0 +1,10 @@
+#as: -march=rv32i_smrnmi
+#source: smrnmi.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+70200073[ ]+mnret
diff --git a/gas/testsuite/gas/riscv/smrnmi.s b/gas/testsuite/gas/riscv/smrnmi.s
new file mode 100644
index 000000000000..f2008bd8704e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/smrnmi.s
@@ -0,0 +1,2 @@
+target:
+ mnret
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 2a26c45f0c24..1a85762f9575 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2235,6 +2235,9 @@
#define MASK_C_NOT 0xfc7f
#define MATCH_C_MUL 0x9c41
#define MASK_C_MUL 0xfc63
+/* Smrnmi instruction. */
+#define MATCH_MNRET 0x70200073
+#define MASK_MNRET 0xffffffff
/* Svinval instruction. */
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
@@ -2883,6 +2886,11 @@
#define CSR_MINSTRETCFG 0x322
#define CSR_MCYCLECFGH 0x721
#define CSR_MINSTRETCFGH 0x722
+/* Smrnmi extension CSR addresses. */
+#define CSR_MNSCRATCH 0x740
+#define CSR_MNEPC 0x741
+#define CSR_MNCAUSE 0x742
+#define CSR_MNSTATUS 0x744
/* Smstateen extension */
#define CSR_MSTATEEN0 0x30c
#define CSR_MSTATEEN1 0x30d
@@ -3349,6 +3357,8 @@ DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B)
DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H)
DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W)
DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D)
+/* Smrnmi instructions. */
+DECLARE_INSN(mnret, MATCH_MNRET, MASK_MNRET)
/* Zicbop instructions. */
DECLARE_INSN(prefetch_r, MATCH_PREFETCH_R, MASK_PREFETCH_R);
DECLARE_INSN(prefetch_w, MATCH_PREFETCH_W, MASK_PREFETCH_W);
@@ -3874,6 +3884,11 @@ DECLARE_CSR(mcyclecfg, CSR_MCYCLECFG, CSR_CLASS_SMCNTRPMF, PRIV_SPEC_CLASS_1P10,
DECLARE_CSR(minstretcfg, CSR_MINSTRETCFG, CSR_CLASS_SMCNTRPMF, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mcyclecfgh, CSR_MCYCLECFGH, CSR_CLASS_SMCNTRPMF_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(minstretcfgh, CSR_MINSTRETCFGH, CSR_CLASS_SMCNTRPMF_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
+/* Smrnmi extension CSRs. */
+DECLARE_CSR(mnscratch, CSR_MNSCRATCH, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mnepc, CSR_MNEPC, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mncause, CSR_MNCAUSE, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mnstatus, CSR_MNSTATUS, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
/* Smstateen/Ssstateen extensions. */
DECLARE_CSR(mstateen0, CSR_MSTATEEN0, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mstateen1, CSR_MSTATEEN1, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 93dd5169ebce..583ee425d6ac 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -438,6 +438,7 @@ enum riscv_insn_class
INSN_CLASS_ZCB_AND_ZBA,
INSN_CLASS_ZCB_AND_ZBB,
INSN_CLASS_ZCB_AND_ZMMUL,
+ INSN_CLASS_SMRNMI,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 8e0ae85eb064..74356a63ad28 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2011,6 +2011,9 @@ const struct riscv_opcode riscv_opcodes[] =
{"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
{"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
+/* Smrnmi instructions. */
+{"mnret", 0, INSN_CLASS_SMRNMI, "", MATCH_MNRET, MASK_MNRET, match_opcode, 0 },
+
/* Svinval instructions. */
{"sinval.vma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_SINVAL_VMA, MASK_SINVAL_VMA, match_opcode, 0 },
{"sfence.w.inval", 0, INSN_CLASS_SVINVAL, "", MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL, match_opcode, 0 },
--
2.42.0
^ permalink raw reply [flat|nested] 7+ messages in thread
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2022-07-09 8:53 [REVIEW ONLY 0/1] RISC-V (unratified): Add 'Smrnmi' extension Tsukasa OI
2022-07-09 8:53 ` [REVIEW ONLY 1/1] UNRATIFIED RISC-V: " Tsukasa OI
2022-11-29 1:21 ` [REVIEW ONLY 0/1] RISC-V (unratified): " Tsukasa OI
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2022-11-29 2:38 ` Palmer Dabbelt
2023-09-12 1:40 ` [REVIEW ONLY v3 0/1] RISC-V (unratified): Add 'Smrnmi' extension Tsukasa OI
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