cgen->sim question

cgen->sim question

[Dmitry Eremin-Solenikov]

Hello,

I have a question regarding generating sim code from cgen description.

I have an instruction operand instantiated from field with type h-addr.
If in the semantics part of the instruction I try to access the operandr
as an address: '(mem QI ddaddr)', I get an error from cgen:

simplify.inc:131:3: op:new-mode: invalid mode for operand `ddaddr': USI

This is the definition of ddaddr:

(dif f-dd-1 "1-byte direct address at 1 position" (ABS-ADDR) 8 8 0 8 UINT #f #f)
(dno ddaddr "direct address" () h-addr f-dd-1)

-- 
With best wishes
Dmitry

Re: cgen->sim question

[Dave Korn]

Dmitry Eremin-Solenikov wrote:
> Hello,
> 
> I have a question regarding generating sim code from cgen description.
> 
> I have an instruction operand instantiated from field with type h-addr.
> If in the semantics part of the instruction I try to access the operandr
> as an address: '(mem QI ddaddr)', I get an error from cgen:
> 
> simplify.inc:131:3: op:new-mode: invalid mode for operand `ddaddr': USI
> 
> This is the definition of ddaddr:
> 
> (dif f-dd-1 "1-byte direct address at 1 position" (ABS-ADDR) 8 8 0 8 UINT #f #f)
> (dno ddaddr "direct address" () h-addr f-dd-1)
> 

  I've seen this too.  I made it go away by changing the hardware element type
in the define-normal-operand from h-addr to h-uint (or h-sint in some cases).
 I don't know for a fact if it was the right thing to do, but all the
generated code ended up looking sane; it does leave me a little unsure,
however, because now I don't know what h-addr is actually supposed to be used
for - my port ends up not using it at all anywhere, and everything appears to
work.

    cheers,
      DaveK

Re: cgen->sim question

[Doug Evans]

Dave Korn wrote:
> Dmitry Eremin-Solenikov wrote:
>   
>> Hello,
>>
>> I have a question regarding generating sim code from cgen description.
>>
>> I have an instruction operand instantiated from field with type h-addr.
>> If in the semantics part of the instruction I try to access the operandr
>> as an address: '(mem QI ddaddr)', I get an error from cgen:
>>
>> simplify.inc:131:3: op:new-mode: invalid mode for operand `ddaddr': USI
>>
>> This is the definition of ddaddr:
>>
>> (dif f-dd-1 "1-byte direct address at 1 position" (ABS-ADDR) 8 8 0 8 UINT #f #f)
>> (dno ddaddr "direct address" () h-addr f-dd-1)
>>
>>     
>
>   I've seen this too.  I made it go away by changing the hardware element type
> in the define-normal-operand from h-addr to h-uint (or h-sint in some cases).
>  I don't know for a fact if it was the right thing to do, but all the
> generated code ended up looking sane; it does leave me a little unsure,
> however, because now I don't know what h-addr is actually supposed to be used
> for - my port ends up not using it at all anywhere, and everything appears to
> work.
>   

Huh.  I tried it and it worked ok.

(dni dmitry-test "dmitry's h-addr issue"
     ()
     "dmitry $ddaddr"
     (+ OP1_7 OP1_1 ddaddr)
     (set (mem QI ddaddr) 0)
     ()
)

The generated code for a basic simulator has:

  i_ddaddr = f_dd_1;

  {
    QI opval = 0;
    SETMEMQI (current_cpu, pc, i_ddaddr, opval);
    TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
  }


What does the instruction definition look like?

Re: cgen->sim question

[Dmitry Eremin-Solenikov]

[-- Attachment #1: Type: text/plain, Size: 883 bytes --]

Hello,

On Mon, Oct 26, 2009 at 7:12 PM, Doug Evans <dje@sebabeach.org> wrote:
> Dave Korn wrote:
>>
>> Dmitry Eremin-Solenikov wrote:
>>
>>>
>>> Hello,
>>>
>>> I have a question regarding generating sim code from cgen description.
>>>
>>> I have an instruction operand instantiated from field with type h-addr.
>>> If in the semantics part of the instruction I try to access the operandr
>>> as an address: '(mem QI ddaddr)', I get an error from cgen:
>>>
>>> simplify.inc:131:3: op:new-mode: invalid mode for operand `ddaddr': USI
>>>
>>> This is the definition of ddaddr:
>>>
>>> (dif f-dd-1 "1-byte direct address at 1 position" (ABS-ADDR) 8 8 0 8 UINT
>>> #f #f)
>>> (dno ddaddr "direct address" () h-addr f-dd-1)

> What does the instruction definition look like?

Please see the attachment. The stamp-cpu (cgen-cpu-decode) fails on
this CPU file.

-- 
With best wishes
Dmitry

[-- Attachment #2: m68hc08.cpu --]
[-- Type: application/octet-stream, Size: 2077 bytes --]


(include "simplify.inc")

(define-pmacro (dif x-name x-comment x-attrs x-word-offset x-word-length x-start x-length x-mode x-encode x-decode)
  (define-ifield
    (name x-name)
    (comment x-comment)
    (.splice attrs (.unsplice x-attrs))
    (word-offset x-word-offset)
    (word-length x-word-length)
    (start x-start)
    (length x-length)
    (mode x-mode)
    (.if (.equal? x-encode #f)
	    (encode #f)
	    (.splice encode (.unsplice x-encode)))
    (.if (.equal? x-decode #f)
	    (decode #f)
	    (.splice decode (.unsplice x-decode)))
    )
)

(define-pmacro (dnif x-name x-comment x-attrs x-word-offset x-word-length x-start x-length)
  (dif x-name x-comment x-attrs x-word-offset x-word-length x-start x-length
       UINT #f #f)
)


(define-arch
  (name m68hc08) ; name of cpu architecture
  (comment "M68HC08")
  (insn-lsb0? #f)
  (machs m68hc08 m68hcs08)
  (isas m68hc08)
)

(define-isa
  (name m68hc08)
  (base-insn-bitsize 8)
  (default-insn-word-bitsize 8)
  (liw-insns 1)
  (parallel-insns 1)
)

(define-cpu
  (name m68hc08bf)
  (endian big)
  (word-bitsize 8)
)

(define-mach
  (name m68hc08)
  (cpu m68hc08bf)
)

(define-model
  (name m68hc08)
  (comment "Generic M68HC08 model")
  (attrs)
  (mach m68hc08)
  (unit u-exec "Execution Unit" ()
	1 1 ; issue done
	() ; state
	() ; inputs
	() ; outputs
	() ; profile action (default)
	)
)

(dnif f-bitsel "bit for bit set/clear ops" () 0 8 4 3)
(dnif f-dd-1 "1-byte direct address at 1 position" (ABS-ADDR) 8 8 0 8)
(define-pmacro (opbit bit)
  (begin
  (dnif (.sym "f-opbit" bit) (.str "insn bit " bit) () 0 8 bit 1)
  (define-normal-insn-enum (.sym "insn-opbit" bit) (.str "insn opbit " bit " enums")
    () (.sym "OP" bit "_") (.sym f-opbit bit) (.map .str (.iota 2)))
  ))
(.splice begin (.unsplice (.map opbit (.iota 8))))


(dno bitsel "bit for bit set/clear ops" () h-sint f-bitsel)

(dno ddaddr "direct address" () h-addr f-dd-1)

(dni bset "bit set insn" ()
  "bset $bitsel,$ddaddr"
  (+ OP0_0 OP1_0 OP2_0 OP3_1 bitsel OP7_0 ddaddr)
  (set QI (mem QI ddaddr) (sll QI (const QI 1) bitsel))
  ())

Re: cgen->sim question

[Doug Evans]

Dmitry Eremin-Solenikov wrote:
> Hello,
>
> On Mon, Oct 26, 2009 at 7:12 PM, Doug Evans <dje@sebabeach.org> wrote:
>   
>> Dave Korn wrote:
>>     
>>> Dmitry Eremin-Solenikov wrote:
>>>
>>>       
>>>> Hello,
>>>>
>>>> I have a question regarding generating sim code from cgen description.
>>>>
>>>> I have an instruction operand instantiated from field with type h-addr.
>>>> If in the semantics part of the instruction I try to access the operandr
>>>> as an address: '(mem QI ddaddr)', I get an error from cgen:
>>>>
>>>> simplify.inc:131:3: op:new-mode: invalid mode for operand `ddaddr': USI
>>>>
>>>> This is the definition of ddaddr:
>>>>
>>>> (dif f-dd-1 "1-byte direct address at 1 position" (ABS-ADDR) 8 8 0 8 UINT
>>>> #f #f)
>>>> (dno ddaddr "direct address" () h-addr f-dd-1)
>>>>         
>
>   
>> What does the instruction definition look like?
>>     
>
> Please see the attachment. The stamp-cpu (cgen-cpu-decode) fails on
> this CPU file.
>   

Thanks for the reproducible test case.  I'm testing a fix now.

Re: cgen->sim question

[Dave Korn]

Doug Evans wrote:

>>   I've seen this too.  I made it go away by changing the hardware
>> element type
>> in the define-normal-operand from h-addr to h-uint (or h-sint in some
>> cases).
>>  I don't know for a fact if it was the right thing to do, but all the
>> generated code ended up looking sane; it does leave me a little unsure,
>> however, because now I don't know what h-addr is actually supposed to
>> be used
>> for - my port ends up not using it at all anywhere, and everything
>> appears to
>> work.
>>   
> 
> Huh.  I tried it and it worked ok.

  In my case it's probably related to the unusual machine word size.

    cheers,
      DaveK

Re: cgen->sim question

[Doug Evans]

Dmitry Eremin-Solenikov wrote:
> Hello,
>
> On Mon, Oct 26, 2009 at 7:12 PM, Doug Evans <dje@sebabeach.org> wrote:
>   
>> Dave Korn wrote:
>>     
>>> Dmitry Eremin-Solenikov wrote:
>>>
>>>       
>>>> Hello,
>>>>
>>>> I have a question regarding generating sim code from cgen description.
>>>>
>>>> I have an instruction operand instantiated from field with type h-addr.
>>>> If in the semantics part of the instruction I try to access the operandr
>>>> as an address: '(mem QI ddaddr)', I get an error from cgen:
>>>>
>>>> simplify.inc:131:3: op:new-mode: invalid mode for operand `ddaddr': USI
>>>>
>>>> This is the definition of ddaddr:
>>>>
>>>> (dif f-dd-1 "1-byte direct address at 1 position" (ABS-ADDR) 8 8 0 8 UINT
>>>> #f #f)
>>>> (dno ddaddr "direct address" () h-addr f-dd-1)
>>>>         
>
>   
>> What does the instruction definition look like?
>>     
>
> Please see the attachment. The stamp-cpu (cgen-cpu-decode) fails on
> this CPU file.
>
>   

I checked in this patch.

2009-10-28  Doug Evans  <dje@sebabeach.org>

        * cos.scm (object-assign!): New function.
        * mode.scm (/mode-set-word-params!): Call it.

Re: cgen->sim question

[Dmitry Eremin-Solenikov]

Hello,


> I checked in this patch.
>
> 2009-10-28  Doug Evans  <dje@sebabeach.org>
>
>       * cos.scm (object-assign!): New function.
>       * mode.scm (/mode-set-word-params!): Call it.

Thank you, this seems to work.


-- 
With best wishes
Dmitry