Disassembly of instruction with 4 bit opcode

Disassembly of instruction with 4 bit opcode

[Michael Chapman]

I have now got the assembler working. However I still have a
little problem with disassembly which I do not understand.

The problem is with the "call" instructions which use only 4 bits
of the opcode using the remained for the address.  Everything is
strictly little endian with the opcode always appearing in the
least significant 8 bits (or 4 bits in the case of call) of the
instruction.

When I dissassemble the following (listing output from the
assembler)


Dw32 GAS  test1.asm 			page 1


   1
   2 0000 06100010 	start:  mov     r1, #0x1000
   3
   4 0004 06302800 	        mov     r3, #low(msg)
   5 0008 56230000 	l1:     ldsb    r2, (r3)0x0
   6 000c 4120     	        cmp     r2, #0
   7 000e 8A0B     	        beq     finish
   8 0010 CC000000 	        call    putc
   9 0014 2131     	        add     r3, #1
  10 0016 FAF8     	        bra     l1
  11
  12 0018 A62000F0 	putc:   st      r2, (r0)0xf000
  13 001c 0620FFFF 	        mov     r2, #0xffff

I get

$ od -d test1.o

test1.o:     file format elf32-dw32

Disassembly of section .text:

00000000 <start>:
   0:	06 10 00 10 	mov r1,#0x1000
   4:	06 30 30 00 	mov r3,#0x30

00000008 <l1>:
   8:	56 23 00 00 	ldsb r2,(r3)0x0
   c:	41 20       	cmp r2,#0x0
   e:	8a 0f       	beq.s 2e <finish>
  10:	cc 00       	*unknown*
  12:	00 00       	mov r0,r0
  14:	21 31       	add r3,#0x1
  16:	fa f8       	bra.s 8 <l1>

00000018 <putc>:
  18:	a6 20 00 f0 	st r2,(r0)0xf000
  1c:	06 20 ff ff 	mov r2,#0xffff



The relevant bits of my cgen .cpu file are

(define-arch
  (name dw32)
  (comment "DW32")
  (insn-lsb0? #t)
  (machs dw32)
  (isas dw32)
)

\f
; Attributes

\f
; Instruction set parameters.

(define-isa
  ; Name of the ISA.
  (name dw32)
  (comment "Basic DW32 instruction set")

  ; (Size of unknown instructions)
  (default-insn-word-bitsize 16)

  ; Shortest instruction is 16 bits
  (default-insn-bitsize 32)
  (base-insn-bitsize 32)
)

\f
; CPU family definitions.

(define-cpu
  ; CPU names must be distinct from the architecture name and machine names.
  ; The "b" suffix stands for "base" and is the convention.
  ; The "f" suffix stands for "family" and is the convention.
  (name dw32bf)
  (comment "DW32 generic cpu")
  (endian little)
  (word-bitsize 32)
)

; Opcode fields
(dnf f-opcode      "opcode" () 7 8)
(dnf f-call-opcode "call opcode" () 3 4)

; absolute, 28-bit (shifted 1 bit to right)
(df f-abs28   "abs28"  (ABS-ADDR)
    31 28 UINT
    ((value pc) (sra WI value (const 1)))
    ((value pc) (sll WI value (const 1))))

(dni call-abs28 "call abs28"
     (UNCOND-CTI)
     "call $abs28"
     (+ (f-call-opcode #xc) abs28)
     (set pc abs28)
     ()
)



Any ideas as to what my problem is?

Thanks for any help,
Mike Chapman

Re: Disassembly of instruction with 4 bit opcode

[Ben Elliston]

Hi Michael,

>>>>> "Michael" == Michael Chapman <Michael.Chapman@synopsys.com> writes:

  Michael> The problem is with the "call" instructions which use only
  Michael> 4 bits of the opcode using the remained for the address.
  Michael> Everything is strictly little endian with the opcode always
  Michael> appearing in the least significant 8 bits (or 4 bits in the
  Michael> case of call) of the instruction.  When I dissassemble the
  Michael> following (listing output from the assembler)
  [...]
  Michael>   10:	cc 00       	*unknown*

Investigate using something like this in your <arch>.opc file:

  /* Override disassembly hashing - there are variable bits in the top
     byte of these instructions.  */
  #define CGEN_DIS_HASH_SIZE 8
  #define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 5) % CGEN_DIS_HASH_SIZE)

Cheers, Ben

RE: Disassembly of instruction with 4 bit opcode

[Michael Chapman]

Hi Ben,

What worked for me was:-

/* Override disassembly hashing - there are variable bits in the top
   byte of these instructions.  */
#define CGEN_DIS_HASH_SIZE 16
#define CGEN_DIS_HASH(buf,value) ((* (unsigned char*) (buf)) & 0x0f)

However, presumably it would be more efficient to make this a bit
more intelligent and only mask out the rest of the opcode in the
case that the 4 LSB bits are 0xc.

Regards,
Mike Chapman

-----Original Message-----
From: bje@scooby.brisbane.redhat.com
[mailto:bje@scooby.brisbane.redhat.com]On Behalf Of Ben Elliston
Sent: Monday, 04 November, 2002 13:33
To: Michael Chapman
Cc: cgen@sources.redhat.com
Subject: Re: Disassembly of instruction with 4 bit opcode


Hi Michael,

>>>>> "Michael" == Michael Chapman <Michael.Chapman@synopsys.com> writes:

  Michael> The problem is with the "call" instructions which use only
  Michael> 4 bits of the opcode using the remained for the address.
  Michael> Everything is strictly little endian with the opcode always
  Michael> appearing in the least significant 8 bits (or 4 bits in the
  Michael> case of call) of the instruction.  When I dissassemble the
  Michael> following (listing output from the assembler)
  [...]
  Michael>   10:	cc 00       	*unknown*

Investigate using something like this in your <arch>.opc file:

  /* Override disassembly hashing - there are variable bits in the top
     byte of these instructions.  */
  #define CGEN_DIS_HASH_SIZE 8
  #define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 5) %
CGEN_DIS_HASH_SIZE)

Cheers, Ben