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From: "vineetg at rivosinc dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/106602] riscv: suboptimal codegen for zero_extendsidi2_shifted w/o bitmanip
Date: Tue, 01 Nov 2022 23:39:30 +0000 [thread overview]
Message-ID: <bug-106602-4-FtiFWQ8A7b@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-106602-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106602
--- Comment #10 from Vineet Gupta <vineetg at rivosinc dot com> ---
At expand time, RV backend was NOT creating REQ_EQUAL note for 1 << 38
(insn 8 7 9 2 (set (reg:DI 79)
(ashift:DI (reg:DI 78)
(const_int 38 [0x26]))) "../../../shifter.c":10:40 -1
However cse1 adds it anyways, so that was a false alarm.
(insn 8 7 9 2 (set (reg:DI 79)
(ashift:DI (reg:DI 78)
(const_int 38 [0x26]))) "../../../../shifter.c":10:40 159 {ashldi3}
(expr_list:REG_EQUAL (const_int 274877906944 [0x4000000000])
So when entering combine, we have following
(insn 6 3 7 2 (set (reg:DI 76)
(ashift:DI (reg/v:DI 74 [ a ])
(const_int 6 [0x6])))
(insn 7 6 8 2 (set (reg:DI 78)
(const_int 1 [0x1]))
(insn 8 7 9 2 (set (reg:DI 79)
(ashift:DI (reg:DI 78)
(const_int 38 [0x26])))
(expr_list:REG_EQUAL (const_int 274877906944 [0x4000000000])
(insn 9 8 10 2 (set (reg:DI 77)
(plus:DI (reg:DI 79)
(const_int -64 [0xffffffffffffffc0])))
(expr_list:REG_EQUAL (const_int 274877906880 [0x3fffffffc0])
(insn 10 9 15 2 (set (reg:DI 75)
(and:DI (reg:DI 76)
(reg:DI 77)))
Obviously the regular code flow can't merge/match 5.
The trailing note processing in combine replaces the pattern with available set
REG_EQUAL but it only handles two instructions at a time. This issue needs it
to handle three: insn 9, 10, 6
Perhaps we need to do the REQ_EQUAL note handling not seperately in the end,
but as part of each of 2 insn combine / 3 insn combine / 4 insn combine (after
the regular try_combine() fails for each of them ?
next prev parent reply other threads:[~2022-11-01 23:39 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-12 20:34 [Bug target/106602] New: riscv: suboptimal codegen for shift left, right, left vineetg at rivosinc dot com
2022-08-12 20:39 ` [Bug target/106602] " pinskia at gcc dot gnu.org
2022-08-12 20:40 ` vineetg at rivosinc dot com
2022-11-01 0:12 ` [Bug target/106602] riscv: suboptimal codegen for zero_extendsidi2_shifted w/o bitmanip vineetg at rivosinc dot com
2022-11-01 0:18 ` pinskia at gcc dot gnu.org
2022-11-01 0:29 ` vineetg at rivosinc dot com
2022-11-01 0:32 ` vineetg at rivosinc dot com
2022-11-01 19:56 ` law at gcc dot gnu.org
2022-11-01 19:58 ` law at gcc dot gnu.org
2022-11-01 20:15 ` palmer at gcc dot gnu.org
2022-11-01 20:31 ` vineetg at rivosinc dot com
2022-11-01 23:39 ` vineetg at rivosinc dot com [this message]
2022-11-02 0:38 ` vineetg at rivosinc dot com
2022-11-02 0:46 ` law at gcc dot gnu.org
2022-11-02 1:03 ` law at gcc dot gnu.org
2022-11-02 1:24 ` vineetg at rivosinc dot com
2022-11-02 1:31 ` law at gcc dot gnu.org
2022-11-02 1:35 ` pinskia at gcc dot gnu.org
2022-11-02 1:35 ` pinskia at gcc dot gnu.org
2022-11-02 15:11 ` law at gcc dot gnu.org
2022-11-02 17:02 ` vineetg at rivosinc dot com
2022-11-02 17:05 ` vineetg at rivosinc dot com
2022-11-02 17:16 ` law at gcc dot gnu.org
2022-11-03 4:15 ` vineetg at rivosinc dot com
2022-11-03 20:41 ` vineetg at rivosinc dot com
2022-11-03 21:21 ` vineetg at rivosinc dot com
2022-11-16 17:55 ` law at gcc dot gnu.org
2022-11-16 18:47 ` law at gcc dot gnu.org
2022-12-27 23:31 ` cvs-commit at gcc dot gnu.org
2022-12-27 23:33 ` law at gcc dot gnu.org
2023-04-17 18:14 ` cvs-commit at gcc dot gnu.org
2023-04-19 2:41 ` cvs-commit at gcc dot gnu.org
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