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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/106602] riscv: suboptimal codegen for zero_extendsidi2_shifted w/o bitmanip
Date: Wed, 02 Nov 2022 01:35:06 +0000 [thread overview]
Message-ID: <bug-106602-4-5Wa8pNVW1t@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-106602-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106602
--- Comment #16 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to Vineet Gupta from comment #14)
> (In reply to Jeffrey A. Law from comment #13)
> > Trying 7, 8, 9 -> 10:
> > 7: r140:DI=0x1
> > 8: r141:DI=r140:DI<<0x26
> > REG_DEAD r140:DI
> > REG_EQUAL 0x4000000000
> > 9: r139:DI=r141:DI-0x40
> > REG_DEAD r141:DI
> > REG_EQUAL 0x3fffffffc0
> > 10: r137:DI=r138:DI&r139:DI
> > REG_DEAD r139:DI
> > REG_DEAD r138:DI
> > Failed to match this instruction:
> > (set (reg:DI 137)
> > (and:DI (reg:DI 138)
> > (const_int 274877906880 [0x3fffffffc0])))
> >
> >
> > That's what we're looking for. I think I had a wrong switch somewhere.
> > Match that with a define_split and you should be good to go.
>
> I think you are missing the original left shift 6.
> So insn 6 from my dumps is important if we are to match
> zero_extendsidi2_shifted which matches and+shift (iff 3>>2==0xffffffff).
>
> But it feels like you agree on using REG_EQUAL note (if avail) to created
> merged pattern in try_combine() as opposed to my original thinking of only
> doing it if regular pattern match failed.
So what Jeff is saying is you just need a define_split which matches that final
set.
Something like:
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(and:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "shifted_mask_operand" "")))]
""
[(set (match_operand:DI 0 ....
next prev parent reply other threads:[~2022-11-02 1:35 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-12 20:34 [Bug target/106602] New: riscv: suboptimal codegen for shift left, right, left vineetg at rivosinc dot com
2022-08-12 20:39 ` [Bug target/106602] " pinskia at gcc dot gnu.org
2022-08-12 20:40 ` vineetg at rivosinc dot com
2022-11-01 0:12 ` [Bug target/106602] riscv: suboptimal codegen for zero_extendsidi2_shifted w/o bitmanip vineetg at rivosinc dot com
2022-11-01 0:18 ` pinskia at gcc dot gnu.org
2022-11-01 0:29 ` vineetg at rivosinc dot com
2022-11-01 0:32 ` vineetg at rivosinc dot com
2022-11-01 19:56 ` law at gcc dot gnu.org
2022-11-01 19:58 ` law at gcc dot gnu.org
2022-11-01 20:15 ` palmer at gcc dot gnu.org
2022-11-01 20:31 ` vineetg at rivosinc dot com
2022-11-01 23:39 ` vineetg at rivosinc dot com
2022-11-02 0:38 ` vineetg at rivosinc dot com
2022-11-02 0:46 ` law at gcc dot gnu.org
2022-11-02 1:03 ` law at gcc dot gnu.org
2022-11-02 1:24 ` vineetg at rivosinc dot com
2022-11-02 1:31 ` law at gcc dot gnu.org
2022-11-02 1:35 ` pinskia at gcc dot gnu.org [this message]
2022-11-02 1:35 ` pinskia at gcc dot gnu.org
2022-11-02 15:11 ` law at gcc dot gnu.org
2022-11-02 17:02 ` vineetg at rivosinc dot com
2022-11-02 17:05 ` vineetg at rivosinc dot com
2022-11-02 17:16 ` law at gcc dot gnu.org
2022-11-03 4:15 ` vineetg at rivosinc dot com
2022-11-03 20:41 ` vineetg at rivosinc dot com
2022-11-03 21:21 ` vineetg at rivosinc dot com
2022-11-16 17:55 ` law at gcc dot gnu.org
2022-11-16 18:47 ` law at gcc dot gnu.org
2022-12-27 23:31 ` cvs-commit at gcc dot gnu.org
2022-12-27 23:33 ` law at gcc dot gnu.org
2023-04-17 18:14 ` cvs-commit at gcc dot gnu.org
2023-04-19 2:41 ` cvs-commit at gcc dot gnu.org
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