[Bug target/106602] riscv: suboptimal codegen for zero_extendsidi2_shifted w/o bitmanip

["palmer at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106602

palmer at gcc dot gnu.org changed:

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--- Comment #8 from palmer at gcc dot gnu.org ---
(In reply to Jeffrey A. Law from comment #7)
> There's some code in combine that's supposed to take advantage of REG_EQUAL
> notes which is supposed to help with this kind of scenario.  Digging into
> that might help.

IMO that's the right way to go here.  I think anything we do in the RISC-V
backend would likely just push around the problem: splitting early seems like
generally the right thing to do, but we'll eventually trip up combine just by
virtue of making instruction sequences longer.  IIUC something like REG_EQUAL
would allow us to keep both flavors around so something can sort it out later.

That said, I've never really reached this deep into the middle end so it's all
a bit over my head and I decided it'd be saner to just close the file and say
nothing ;)