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From: "vineetg at rivosinc dot com" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/106602] riscv: suboptimal codegen for zero_extendsidi2_shifted w/o bitmanip Date: Wed, 02 Nov 2022 00:38:55 +0000 [thread overview] Message-ID: <bug-106602-4-LXo96zBAiU@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-106602-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106602 --- Comment #11 from Vineet Gupta <vineetg at rivosinc dot com> --- This definitely seems worth pursuing: For bitmanip, following four insn seq matches Trying 7, 8, 6 -> 9: 7: r78:DI=0x4000000000 8: r77:DI=r78:DI-0x40 REG_EQUAL 0x3fffffffc0 6: r76:DI=r79:DI<<0x6 9: r75:DI=r76:DI&r77:DI Successfully matched this instruction: (set (reg:DI 75) (and:DI (ashift:DI (reg:DI 79) For non-bitmanip, a similar 3 insn seq doesn't Trying 9, 6 -> 10: 9: r77:DI=r79:DI-0x40 REG_EQUAL 0x3fffffffc0 6: r76:DI=r80:DI<<0x6 10: r75:DI=r76:DI&r77:DI Failed to match this instruction: (set (reg:DI 75) (and:DI (plus:DI (reg:DI 79) (const_int -64 [0xffffffffffffffc0])) (ashift:DI (reg:DI 80) (const_int 6 [0x6])))) If we re-ran last failing case with REQ_EQUAL note it would match.
next prev parent reply other threads:[~2022-11-02 0:38 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-08-12 20:34 [Bug target/106602] New: riscv: suboptimal codegen for shift left, right, left vineetg at rivosinc dot com 2022-08-12 20:39 ` [Bug target/106602] " pinskia at gcc dot gnu.org 2022-08-12 20:40 ` vineetg at rivosinc dot com 2022-11-01 0:12 ` [Bug target/106602] riscv: suboptimal codegen for zero_extendsidi2_shifted w/o bitmanip vineetg at rivosinc dot com 2022-11-01 0:18 ` pinskia at gcc dot gnu.org 2022-11-01 0:29 ` vineetg at rivosinc dot com 2022-11-01 0:32 ` vineetg at rivosinc dot com 2022-11-01 19:56 ` law at gcc dot gnu.org 2022-11-01 19:58 ` law at gcc dot gnu.org 2022-11-01 20:15 ` palmer at gcc dot gnu.org 2022-11-01 20:31 ` vineetg at rivosinc dot com 2022-11-01 23:39 ` vineetg at rivosinc dot com 2022-11-02 0:38 ` vineetg at rivosinc dot com [this message] 2022-11-02 0:46 ` law at gcc dot gnu.org 2022-11-02 1:03 ` law at gcc dot gnu.org 2022-11-02 1:24 ` vineetg at rivosinc dot com 2022-11-02 1:31 ` law at gcc dot gnu.org 2022-11-02 1:35 ` pinskia at gcc dot gnu.org 2022-11-02 1:35 ` pinskia at gcc dot gnu.org 2022-11-02 15:11 ` law at gcc dot gnu.org 2022-11-02 17:02 ` vineetg at rivosinc dot com 2022-11-02 17:05 ` vineetg at rivosinc dot com 2022-11-02 17:16 ` law at gcc dot gnu.org 2022-11-03 4:15 ` vineetg at rivosinc dot com 2022-11-03 20:41 ` vineetg at rivosinc dot com 2022-11-03 21:21 ` vineetg at rivosinc dot com 2022-11-16 17:55 ` law at gcc dot gnu.org 2022-11-16 18:47 ` law at gcc dot gnu.org 2022-12-27 23:31 ` cvs-commit at gcc dot gnu.org 2022-12-27 23:33 ` law at gcc dot gnu.org 2023-04-17 18:14 ` cvs-commit at gcc dot gnu.org 2023-04-19 2:41 ` cvs-commit at gcc dot gnu.org
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