[Bug c/106635] New: AARCH64 STUR instruction causes bus error

[Bug c/106635] New: AARCH64 STUR instruction causes bus error

[xgchenshy at 126 dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106635

            Bug ID: 106635
           Summary: AARCH64 STUR instruction causes bus error
           Product: gcc
           Version: 11.2.1
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: xgchenshy at 126 dot com
  Target Milestone: ---

Hi, We are using aarch64-none-linux-gnueabi-gcc (version 11.2.1) to compile our
userspace code with cortex A55 platform in linux environment, we met an bus
error which causes the program to exit.
with closer look, we found such STUR instruction causes this issue



this is the cflags:
 CFLAGS   = -fpic -Wall -ansi -std=c99 -Wno-variadic-macros -g -Werror -fPIC
-shared -Wall -O2 -ggdb3

below is the C code:

void CWLCollectReadRegData(u32* dst,u16 reg_start, u32 reg_length,u32*
total_length, addr_t status_data_base_addr)
{
  u32 data_length=0;
  {
    //opcode
    *dst++ = (OPCODE_RREG<<27)|(reg_length<<16)|(reg_start*4);
    data_length++;

    //data
    *dst++ = (u32)status_data_base_addr; <<----this line of code causes bus
error
    data_length++;
 ....
}

below is the disassemble code:
(gdb) disassemble CWLCollectReadRegData
Dump of assembler code for function CWLCollectReadRegData:
0x0000000000000080 <+0>: ubfiz w1, w1, #2, #16
0x0000000000000084 <+4>: stur x4, [x0, #4]   <<------this is the code that
causes bus error
0x0000000000000088 <+8>: orr w2, w1, w2, lsl #16
0x000000000000008c <+12>: mov w1, #0xb0000000 // #-1342177280
0x0000000000000090 <+16>: orr w2, w2, w1
0x0000000000000094 <+20>: str w2, [x0]
0x0000000000000098 <+24>: str wzr, [x0, #12]
0x000000000000009c <+28>: mov w1, #0x4 // #4
0x00000000000000a0 <+32>: str w1, [x3]
0x00000000000000a4 <+36>: ret
End of assembler dump.

this line of code causes bus error. 
stur x4, [x0, #4]

our program expects to write a 32 bit value to [x0,#4], but this instrunction
writes a 64 bit value X4, this is already wrong.
but STUR instrunction should support unaligned access, I also dont' quite know
why the bus error happens.

Thanks

[Bug target/106635] AARCH64 STUR instruction causes bus error

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106635

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Last reconfirmed|                            |2022-08-16
     Ever confirmed|0                           |1
             Status|UNCONFIRMED                 |WAITING
           Keywords|                            |wrong-code

--- Comment #1 from Richard Biener <rguenth at gcc dot gnu.org> ---
Can you provide preprocessed source of the whole translation unit so the
testcase is compilable?

[Bug target/106635] AARCH64 STUR instruction causes bus error

[xgchenshy at 126 dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106635

--- Comment #2 from Xiaoguang <xgchenshy at 126 dot com> ---
(In reply to Richard Biener from comment #1)
> Can you provide preprocessed source of the whole translation unit so the
> testcase is compilable?

Sure, please see below complete code.

void CWLCollectReadRegData(u32* dst,u16 reg_start, u32 reg_length,u32*
total_length, addr_t status_data_base_addr)
{
  u32 data_length=0;
  {
    //opcode
    *dst++ = (OPCODE_RREG<<27)|(reg_length<<16)|(reg_start*4);
    data_length++;

    //data
    volatile u32 temp_32 = (u32)status_data_base_addr; // fix compiler
optimization -O2 bug:  stur  x4, [x0, #4]
    *dst++ = temp_32;
    data_length++;

    if(sizeof(addr_t) == 8) {
      *dst++ = (u32)(((u64)status_data_base_addr)>>32);
      data_length++;
    } else {
      *dst++ = 0;
      data_length++;
    }
    //alignment
    *dst = 0;
    data_length++;

    *total_length = data_length;
  }
}

[Bug target/106635] AARCH64 STUR instruction causes bus error

[xgchenshy at 126 dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106635

--- Comment #3 from Xiaoguang <xgchenshy at 126 dot com> ---
(In reply to Richard Biener from comment #1)
> Can you provide preprocessed source of the whole translation unit so the
> testcase is compilable?

please see below code:
void CWLCollectReadRegData(u32* dst,u16 reg_start, u32 reg_length,u32*
total_length, addr_t status_data_base_addr)
{
  u32 data_length=0;
  {
    //opcode
    *dst++ = (OPCODE_RREG<<27)|(reg_length<<16)|(reg_start*4);
    data_length++;

    //data
    *dst++ = (u32)status_data_base_addr;
    data_length++;

    if(sizeof(addr_t) == 8) {
      *dst++ = (u32)(((u64)status_data_base_addr)>>32);
      data_length++;
    } else {
      *dst++ = 0;
      data_length++;
    }
    //alignment
    *dst = 0;
    data_length++;

    *total_length = data_length;
  }
}

[Bug target/106635] AARCH64 STUR instruction causes bus error

[xgchenshy at 126 dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106635

--- Comment #4 from Xiaoguang <xgchenshy at 126 dot com> ---
(In reply to Xiaoguang from comment #2)
> (In reply to Richard Biener from comment #1)
> > Can you provide preprocessed source of the whole translation unit so the
> > testcase is compilable?
> 
> Sure, please see below complete code.
> 
> void CWLCollectReadRegData(u32* dst,u16 reg_start, u32 reg_length,u32*
> total_length, addr_t status_data_base_addr)
> {
>   u32 data_length=0;
>   {
>     //opcode
>     *dst++ = (OPCODE_RREG<<27)|(reg_length<<16)|(reg_start*4);
>     data_length++;
>  
>     //data
>     volatile u32 temp_32 = (u32)status_data_base_addr; // fix compiler
> optimization -O2 bug:  stur  x4, [x0, #4]
>     *dst++ = temp_32;
>     data_length++;
>  
>     if(sizeof(addr_t) == 8) {
>       *dst++ = (u32)(((u64)status_data_base_addr)>>32);
>       data_length++;
>     } else {
>       *dst++ = 0;
>       data_length++;
>     }
>     //alignment
>     *dst = 0;
>     data_length++;
>  
>     *total_length = data_length;
>   }
> }

please ignore this, we added volatile to avoid such issue

[Bug target/106635] AARCH64 STUR instruction causes bus error

[rearnsha at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106635

Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |INVALID
             Status|WAITING                     |RESOLVED

--- Comment #5 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
Your original code contains (after stripping out the volatile):
    u32 temp_32 = (u32)status_data_base_addr;
    *dst++ = temp_32;
    data_length++;

    if(sizeof(addr_t) == 8) {
      *dst++ = (u32)(((u64)status_data_base_addr)>>32);
      data_length++;
    }

Which of course on a 64-bit machine simplifies to 

    u32 temp_32 = (u32)status_data_base_addr;
    *dst++ = temp_32;
    data_length++;

    *dst++ = (u32)(((u64)status_data_base_addr)>>32);
    data_length++;

And which the compiler then further simplifies to 

   *([unaligned]u64*)dst = status_data_base_addr;
   data_length += 2;
   dst += 2;

If the location that dst points to is in normal, cachable, memory, then this
will be fine.  But if you're writing to non-cachable memory, then you might get
a trap.

the correct fix is to mark dst as volatile in this case.

void CWLCollectReadRegData(volatile u32* dst,u16 reg_start, u32 reg_length,u32*
total_length, addr_t status_data_base_addr)

[Bug target/106635] AARCH64 STUR instruction causes bus error

[xgchenshy at 126 dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106635

--- Comment #6 from Xiaoguang <xgchenshy at 126 dot com> ---
(In reply to Richard Earnshaw from comment #5)
> Your original code contains (after stripping out the volatile):
>     u32 temp_32 = (u32)status_data_base_addr;
>     *dst++ = temp_32;
>     data_length++;
>  
>     if(sizeof(addr_t) == 8) {
>       *dst++ = (u32)(((u64)status_data_base_addr)>>32);
>       data_length++;
>     }
> 
> Which of course on a 64-bit machine simplifies to 
> 
>     u32 temp_32 = (u32)status_data_base_addr;
>     *dst++ = temp_32;
>     data_length++;
>  
>     *dst++ = (u32)(((u64)status_data_base_addr)>>32);
>     data_length++;
> 
> And which the compiler then further simplifies to 
> 
>    *([unaligned]u64*)dst = status_data_base_addr;
>    data_length += 2;
>    dst += 2;
> 
> If the location that dst points to is in normal, cachable, memory, then this
> will be fine.  But if you're writing to non-cachable memory, then you might
> get a trap.
Thanks Very much for the explaination, Can you tell me why unaligned access
only  works in normal cachable memory? where does this constraint come from? 

> 
> the correct fix is to mark dst as volatile in this case.
> 
> void CWLCollectReadRegData(volatile u32* dst,u16 reg_start, u32
> reg_length,u32*
> total_length, addr_t status_data_base_addr)

[Bug target/106635] AARCH64 STUR instruction causes bus error

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106635

--- Comment #7 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to Xiaoguang from comment #6)
> (In reply to Richard Earnshaw from comment #5)
> > Your original code contains (after stripping out the volatile):
> >     u32 temp_32 = (u32)status_data_base_addr;
> >     *dst++ = temp_32;
> >     data_length++;
> >  
> >     if(sizeof(addr_t) == 8) {
> >       *dst++ = (u32)(((u64)status_data_base_addr)>>32);
> >       data_length++;
> >     }
> > 
> > Which of course on a 64-bit machine simplifies to 
> > 
> >     u32 temp_32 = (u32)status_data_base_addr;
> >     *dst++ = temp_32;
> >     data_length++;
> >  
> >     *dst++ = (u32)(((u64)status_data_base_addr)>>32);
> >     data_length++;
> > 
> > And which the compiler then further simplifies to 
> > 
> >    *([unaligned]u64*)dst = status_data_base_addr;
> >    data_length += 2;
> >    dst += 2;
> > 
> > If the location that dst points to is in normal, cachable, memory, then this
> > will be fine.  But if you're writing to non-cachable memory, then you might
> > get a trap.
> Thanks Very much for the explaination, Can you tell me why unaligned access
> only  works in normal cachable memory? where does this constraint come from? 

The architect (armv8) explains this. Basically the hardware does not know what
to do when there is a unaligned access as it has to two reads and two writes to
get the data correct.
It in the arm armv8 document.




> 
> > 
> > the correct fix is to mark dst as volatile in this case.
> > 
> > void CWLCollectReadRegData(volatile u32* dst,u16 reg_start, u32
> > reg_length,u32*
> > total_length, addr_t status_data_base_addr)

[Bug target/106635] AARCH64 STUR instruction causes bus error

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106635

--- Comment #8 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
In ARM Armv8, for A-profile architecture (ARM DDI 0487G.b (ID072021)): 

>From section B2.5.2 Alignment of data accesses:

An unaligned access to any type of Device memory causes an Alignment fault.

Unaligned accesses to Normal memory

[Bug target/106635] AARCH64 STUR instruction causes bus error

[xgchenshy at 126 dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106635

--- Comment #9 from Xiaoguang <xgchenshy at 126 dot com> ---
(In reply to Andrew Pinski from comment #8)
> In ARM Armv8, for A-profile architecture (ARM DDI 0487G.b (ID072021)): 
> 
> From section B2.5.2 Alignment of data accesses:
> 
> An unaligned access to any type of Device memory causes an Alignment fault.
> 
> Unaligned accesses to Normal memory

Yeah, I also find such description, my memory type is uncachable normal memory,
but not device memory
I use mmap to get the virtual address with an O_SYNC in fd

[Bug target/106635] AARCH64 STUR instruction causes bus error

[xgchenshy at 126 dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106635

--- Comment #10 from Xiaoguang <xgchenshy at 126 dot com> ---
(In reply to Xiaoguang from comment #9)
> (In reply to Andrew Pinski from comment #8)
> > In ARM Armv8, for A-profile architecture (ARM DDI 0487G.b (ID072021)): 
> > 
> > From section B2.5.2 Alignment of data accesses:
> > 
> > An unaligned access to any type of Device memory causes an Alignment fault.
> > 
> > Unaligned accesses to Normal memory
> 
> Yeah, I also find such description, my memory type is uncachable normal
> memory, but not device memory
> I use mmap to get the virtual address with an O_SYNC in fd

Also I didn't see whether normal memory cacheable or not impacts alignment
access , besides, STUR instruction has unscaled imm offset, it should support
unaligned access on normal memory, no matter cached or not,and my X0 is normal
memory so I'm still confusing why it fails, please correct my if my
understanding is wrong. thanks very much