* [Bug target/109725] [14 Regression] ICE: RTL check: expected code 'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4430
2023-05-04 4:10 [Bug target/109725] New: [14 Regression] ICE: RTL check: expected code 'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4430 zsojka at seznam dot cz
@ 2023-05-04 4:27 ` pinskia at gcc dot gnu.org
2023-06-07 17:38 ` cvs-commit at gcc dot gnu.org
` (5 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: pinskia at gcc dot gnu.org @ 2023-05-04 4:27 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109725
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Last reconfirmed| |2023-05-04
Status|UNCONFIRMED |NEW
Target Milestone|--- |14.0
Ever confirmed|0 |1
Keywords| |ice-checking
--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Yes this is bad coding:
static void
riscv_print_operand (FILE *file, rtx op, int letter)
{
/* `~` does not take an operand so op will be null
Check for before accessing op.
*/
if (letter == '~')
{
if (TARGET_64BIT)
fputc('w', file);
return;
}
machine_mode mode = GET_MODE (op);
enum rtx_code code = GET_CODE (op);
const enum memmodel model = memmodel_base (INTVAL (op));
model should only be defined where it is used rather than in the top.
^ permalink raw reply [flat|nested] 8+ messages in thread* [Bug target/109725] [14 Regression] ICE: RTL check: expected code 'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4430
2023-05-04 4:10 [Bug target/109725] New: [14 Regression] ICE: RTL check: expected code 'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4430 zsojka at seznam dot cz
2023-05-04 4:27 ` [Bug target/109725] " pinskia at gcc dot gnu.org
@ 2023-06-07 17:38 ` cvs-commit at gcc dot gnu.org
2023-06-09 17:36 ` dimitar at gcc dot gnu.org
` (4 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2023-06-07 17:38 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109725
--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Dimitar Dimitrov <dimitar@gcc.gnu.org>:
https://gcc.gnu.org/g:7f26e76c9848aeea9ec10ea701a6168464a4a9c2
commit r14-1621-g7f26e76c9848aeea9ec10ea701a6168464a4a9c2
Author: Dimitar Dimitrov <dimitar@dinux.eu>
Date: Mon Jun 5 21:39:16 2023 +0300
riscv: Fix scope for memory model calculation
During libgcc configure stage for riscv32-none-elf, when
"--enable-checking=yes,rtl" has been activated, the following error
is observed:
during RTL pass: final
conftest.c: In function 'main':
conftest.c:16:1: internal compiler error: RTL check: expected code
'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4462
16 | }
| ^
0x843c4d rtl_check_failed_code1(rtx_def const*, rtx_code, char const*,
int, char const*)
/mnt/nvme/dinux/local-workspace/gcc/gcc/rtl.cc:916
0x8ea823 riscv_print_operand
/mnt/nvme/dinux/local-workspace/gcc/gcc/config/riscv/riscv.cc:4462
0xde84b5 output_operand(rtx_def*, int)
/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:3632
0xde8ef8 output_asm_insn(char const*, rtx_def**)
/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:3544
0xded33b output_asm_insn(char const*, rtx_def**)
/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:3421
0xded33b final_scan_insn_1
/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:2841
0xded6cb final_scan_insn(rtx_insn*, _IO_FILE*, int, int, int*)
/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:2887
0xded8b7 final_1
/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:1979
0xdee518 rest_of_handle_final
/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:4240
0xdee518 execute
/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:4318
Fix by moving the calculation of memmodel to the cases where it is used.
Regression tested for riscv32-none-elf. No changes in gcc.sum and
g++.sum.
PR target/109725
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_print_operand): Calculate
memmodel only when it is valid.
Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
^ permalink raw reply [flat|nested] 8+ messages in thread* [Bug target/109725] [14 Regression] ICE: RTL check: expected code 'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4430
2023-05-04 4:10 [Bug target/109725] New: [14 Regression] ICE: RTL check: expected code 'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4430 zsojka at seznam dot cz
2023-05-04 4:27 ` [Bug target/109725] " pinskia at gcc dot gnu.org
2023-06-07 17:38 ` cvs-commit at gcc dot gnu.org
@ 2023-06-09 17:36 ` dimitar at gcc dot gnu.org
2023-08-30 4:20 ` xuli1 at eswincomputing dot com
` (3 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: dimitar at gcc dot gnu.org @ 2023-06-09 17:36 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109725
Dimitar Dimitrov <dimitar at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Resolution|--- |FIXED
Status|NEW |RESOLVED
--- Comment #3 from Dimitar Dimitrov <dimitar at gcc dot gnu.org> ---
Should be fixed now.
^ permalink raw reply [flat|nested] 8+ messages in thread* [Bug target/109725] [14 Regression] ICE: RTL check: expected code 'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4430
2023-05-04 4:10 [Bug target/109725] New: [14 Regression] ICE: RTL check: expected code 'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4430 zsojka at seznam dot cz
` (2 preceding siblings ...)
2023-06-09 17:36 ` dimitar at gcc dot gnu.org
@ 2023-08-30 4:20 ` xuli1 at eswincomputing dot com
2023-08-30 4:32 ` xuli1 at eswincomputing dot com
` (2 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: xuli1 at eswincomputing dot com @ 2023-08-30 4:20 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109725
xuli1 at eswincomputing dot com <xuli1 at eswincomputing dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |xuli1 at eswincomputing dot com
--- Comment #4 from xuli1 at eswincomputing dot com <xuli1 at eswincomputing dot com> ---
The gcc-13 branch also has the same issue
(https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111161), can I backport this
patch to gcc-13？
^ permalink raw reply [flat|nested] 8+ messages in thread* [Bug target/109725] [14 Regression] ICE: RTL check: expected code 'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4430
2023-05-04 4:10 [Bug target/109725] New: [14 Regression] ICE: RTL check: expected code 'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4430 zsojka at seznam dot cz
` (3 preceding siblings ...)
2023-08-30 4:20 ` xuli1 at eswincomputing dot com
@ 2023-08-30 4:32 ` xuli1 at eswincomputing dot com
2023-08-30 4:41 ` kito at gcc dot gnu.org
2023-08-30 5:31 ` cvs-commit at gcc dot gnu.org
6 siblings, 0 replies; 8+ messages in thread
From: xuli1 at eswincomputing dot com @ 2023-08-30 4:32 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109725
--- Comment #5 from xuli1 at eswincomputing dot com <xuli1 at eswincomputing dot com> ---
(In reply to xuli1@eswincomputing.com from comment #4)
> The gcc-13 branch also has the same issue
> (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111161), can I backport this
> patch to gcc-13？
@kito.cheng@gmail.com @juzhe.zhong@rivai.ai @dimitar@gcc.gnu.org
^ permalink raw reply [flat|nested] 8+ messages in thread* [Bug target/109725] [14 Regression] ICE: RTL check: expected code 'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4430
2023-05-04 4:10 [Bug target/109725] New: [14 Regression] ICE: RTL check: expected code 'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4430 zsojka at seznam dot cz
` (4 preceding siblings ...)
2023-08-30 4:32 ` xuli1 at eswincomputing dot com
@ 2023-08-30 4:41 ` kito at gcc dot gnu.org
2023-08-30 5:31 ` cvs-commit at gcc dot gnu.org
6 siblings, 0 replies; 8+ messages in thread
From: kito at gcc dot gnu.org @ 2023-08-30 4:41 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109725
Kito Cheng <kito at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |kito at gcc dot gnu.org
--- Comment #6 from Kito Cheng <kito at gcc dot gnu.org> ---
Ok for back port :)
^ permalink raw reply [flat|nested] 8+ messages in thread* [Bug target/109725] [14 Regression] ICE: RTL check: expected code 'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4430
2023-05-04 4:10 [Bug target/109725] New: [14 Regression] ICE: RTL check: expected code 'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4430 zsojka at seznam dot cz
` (5 preceding siblings ...)
2023-08-30 4:41 ` kito at gcc dot gnu.org
@ 2023-08-30 5:31 ` cvs-commit at gcc dot gnu.org
6 siblings, 0 replies; 8+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2023-08-30 5:31 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109725
--- Comment #7 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-13 branch has been updated by Li Xu <xuli@gcc.gnu.org>:
https://gcc.gnu.org/g:b81d476756a1f17617f0837761785c4b5d1d195d
commit r13-7766-gb81d476756a1f17617f0837761785c4b5d1d195d
Author: Dimitar Dimitrov <dimitar@dinux.eu>
Date: Mon Jun 5 21:39:16 2023 +0300
riscv: Fix scope for memory model calculation
During libgcc configure stage for riscv32-none-elf, when
"--enable-checking=yes,rtl" has been activated, the following error
is observed:
during RTL pass: final
conftest.c: In function 'main':
conftest.c:16:1: internal compiler error: RTL check: expected code
'const_int', have 'reg' in riscv_print_operand, at config/riscv/riscv.cc:4462
16 | }
| ^
0x843c4d rtl_check_failed_code1(rtx_def const*, rtx_code, char const*,
int, char const*)
/mnt/nvme/dinux/local-workspace/gcc/gcc/rtl.cc:916
0x8ea823 riscv_print_operand
/mnt/nvme/dinux/local-workspace/gcc/gcc/config/riscv/riscv.cc:4462
0xde84b5 output_operand(rtx_def*, int)
/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:3632
0xde8ef8 output_asm_insn(char const*, rtx_def**)
/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:3544
0xded33b output_asm_insn(char const*, rtx_def**)
/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:3421
0xded33b final_scan_insn_1
/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:2841
0xded6cb final_scan_insn(rtx_insn*, _IO_FILE*, int, int, int*)
/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:2887
0xded8b7 final_1
/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:1979
0xdee518 rest_of_handle_final
/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:4240
0xdee518 execute
/mnt/nvme/dinux/local-workspace/gcc/gcc/final.cc:4318
Fix by moving the calculation of memmodel to the cases where it is used.
Regression tested for riscv32-none-elf. No changes in gcc.sum and
g++.sum.
PR target/109725
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_print_operand): Calculate
memmodel only when it is valid.
Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
^ permalink raw reply [flat|nested] 8+ messages in thread