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From: "rguenth at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/110751] RISC-V: Suport undefined value that allows VSETVL PASS use TA/MA
Date: Fri, 21 Jul 2023 06:17:48 +0000 [thread overview]
Message-ID: <bug-110751-4-4z5gLbUQrW@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-110751-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110751
--- Comment #17 from Richard Biener <rguenth at gcc dot gnu.org> ---
(In reply to JuzheZhong from comment #15)
> I am wondering: do we have have other situations need "undef" value to do
> optimizations? If yes, I am aggree with Richard that we need to support
> "undef"
> value. But "undef" value in Gimple IR support would be a long term work
> since it
> is not an easy job. For example, in llvm, undef + a -> undef, but undef & a
> -> 0.
We do have "undef" in the GIMPLE IR, for SSA variables it's the default
definition.
Note I think that a formal "undef" is different from "unspecified"
(or in this case "target specified"). In GIMPLE an "undef" use is
invoking undefined behavior but clearly doing a MASK/LEN operation
with some "undef" lanes and then operating on the vector is _not_
invoking undefined behavior. In fact with RVV intrinsics the programmer
can rely on RVV semantics, thus either all-ones _or_ merge which means
if you know the old value has some specific bits set you know the new
value will as well. That's _not_ "undef" in the classical sense so
I think LLVMs "undef" isn't a very good fit here (nor would putting
a SSA default def as the "else" value).
next prev parent reply other threads:[~2023-07-21 6:17 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-20 9:03 [Bug target/110751] New: " xuli1 at eswincomputing dot com
2023-07-20 9:10 ` [Bug target/110751] " juzhe.zhong at rivai dot ai
2023-07-20 9:30 ` rguenth at gcc dot gnu.org
2023-07-20 9:37 ` rguenth at gcc dot gnu.org
2023-07-20 9:58 ` kito at gcc dot gnu.org
2023-07-20 11:28 ` rguenther at suse dot de
2023-07-20 11:43 ` juzhe.zhong at rivai dot ai
2023-07-20 12:00 ` juzhe.zhong at rivai dot ai
2023-07-20 12:35 ` rguenther at suse dot de
2023-07-20 12:42 ` juzhe.zhong at rivai dot ai
2023-07-20 12:45 ` rguenther at suse dot de
2023-07-20 12:50 ` juzhe.zhong at rivai dot ai
2023-07-20 12:56 ` rguenther at suse dot de
2023-07-20 13:29 ` rsandifo at gcc dot gnu.org
2023-07-20 13:32 ` rguenther at suse dot de
2023-07-20 22:03 ` juzhe.zhong at rivai dot ai
2023-07-21 1:53 ` xuli1 at eswincomputing dot com
2023-07-21 6:17 ` rguenth at gcc dot gnu.org [this message]
2023-07-21 12:47 ` rsandifo at gcc dot gnu.org
2023-07-21 12:53 ` rguenth at gcc dot gnu.org
2023-07-21 13:23 ` rsandifo at gcc dot gnu.org
2023-07-24 6:20 ` rguenther at suse dot de
2023-07-25 7:05 ` juzhe.zhong at rivai dot ai
2023-09-12 11:44 ` juzhe.zhong at rivai dot ai
2023-09-12 14:24 ` rsandifo at gcc dot gnu.org
2023-09-12 14:53 ` juzhe.zhong at rivai dot ai
2023-09-12 15:59 ` rsandifo at gcc dot gnu.org
2023-09-12 16:21 ` juzhe.zhong at rivai dot ai
2023-09-12 16:27 ` juzhe.zhong at rivai dot ai
2023-09-12 16:31 ` juzhe.zhong at rivai dot ai
2023-09-12 22:44 ` juzhe.zhong at rivai dot ai
2023-09-13 7:56 ` rguenth at gcc dot gnu.org
2023-09-13 8:34 ` juzhe.zhong at rivai dot ai
2023-09-13 8:39 ` juzhe.zhong at rivai dot ai
2023-09-13 9:38 ` rguenth at gcc dot gnu.org
2023-09-13 9:39 ` rguenth at gcc dot gnu.org
2023-09-13 9:48 ` juzhe.zhong at rivai dot ai
2023-09-13 9:48 ` juzhe.zhong at rivai dot ai
2023-09-13 10:15 ` rguenther at suse dot de
2023-09-13 22:39 ` rsandifo at gcc dot gnu.org
2023-09-14 8:53 ` juzhe.zhong at rivai dot ai
2023-09-14 9:15 ` richard.sandiford at arm dot com
2023-09-20 16:27 ` cvs-commit at gcc dot gnu.org
2023-09-21 9:13 ` cvs-commit at gcc dot gnu.org
2023-09-21 9:28 ` juzhe.zhong at rivai dot ai
2023-09-22 7:31 ` xuli1 at eswincomputing dot com
2023-09-22 7:33 ` xuli1 at eswincomputing dot com
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