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From: "rguenth at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/110751] RISC-V: Suport undefined value that allows VSETVL PASS use TA/MA
Date: Thu, 20 Jul 2023 09:30:12 +0000 [thread overview]
Message-ID: <bug-110751-4-ceSwuTfg6c@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-110751-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110751
Richard Biener <rguenth at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Target| |riscv
--- Comment #2 from Richard Biener <rguenth at gcc dot gnu.org> ---
AVX512 can do zeroing or merging (with existing destination contents)
for masked ops, on the GIMPLE side merging would need another source operand
so what we effectively only support is zeroing for AVX512.
I see aarch64 SVE picks the value from specific operands where I'm assuming
that's what the ISA implements (only).
For any suggestion can you please elaborate on what MU/TU and TA/MA are?
Searching for two-letter things in the RVV spec has way to many hits to
find the relevant parts of the spec.
If 'undefined' means there's ISA that leaves the choice to implementors
and that's usually "cheaper" then rather than a new undef_type I always
point to 'error_mark_node' that could be used but you also need a
representation on the RTL side. I'd also like to add that 'undefined'
is in the end always problematic for an IL.
I would assume that in case 'undefined' allows the implementation to
completely skip operating on a vector subpart, like not issue it, the
actual value will be what's already in the target register so it looks
like "merge" to me but for not skipped subparts that adds a data dependence
on the previous (sub-)register contents (not an issue for "skipped" parts).
next prev parent reply other threads:[~2023-07-20 9:30 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-20 9:03 [Bug target/110751] New: " xuli1 at eswincomputing dot com
2023-07-20 9:10 ` [Bug target/110751] " juzhe.zhong at rivai dot ai
2023-07-20 9:30 ` rguenth at gcc dot gnu.org [this message]
2023-07-20 9:37 ` rguenth at gcc dot gnu.org
2023-07-20 9:58 ` kito at gcc dot gnu.org
2023-07-20 11:28 ` rguenther at suse dot de
2023-07-20 11:43 ` juzhe.zhong at rivai dot ai
2023-07-20 12:00 ` juzhe.zhong at rivai dot ai
2023-07-20 12:35 ` rguenther at suse dot de
2023-07-20 12:42 ` juzhe.zhong at rivai dot ai
2023-07-20 12:45 ` rguenther at suse dot de
2023-07-20 12:50 ` juzhe.zhong at rivai dot ai
2023-07-20 12:56 ` rguenther at suse dot de
2023-07-20 13:29 ` rsandifo at gcc dot gnu.org
2023-07-20 13:32 ` rguenther at suse dot de
2023-07-20 22:03 ` juzhe.zhong at rivai dot ai
2023-07-21 1:53 ` xuli1 at eswincomputing dot com
2023-07-21 6:17 ` rguenth at gcc dot gnu.org
2023-07-21 12:47 ` rsandifo at gcc dot gnu.org
2023-07-21 12:53 ` rguenth at gcc dot gnu.org
2023-07-21 13:23 ` rsandifo at gcc dot gnu.org
2023-07-24 6:20 ` rguenther at suse dot de
2023-07-25 7:05 ` juzhe.zhong at rivai dot ai
2023-09-12 11:44 ` juzhe.zhong at rivai dot ai
2023-09-12 14:24 ` rsandifo at gcc dot gnu.org
2023-09-12 14:53 ` juzhe.zhong at rivai dot ai
2023-09-12 15:59 ` rsandifo at gcc dot gnu.org
2023-09-12 16:21 ` juzhe.zhong at rivai dot ai
2023-09-12 16:27 ` juzhe.zhong at rivai dot ai
2023-09-12 16:31 ` juzhe.zhong at rivai dot ai
2023-09-12 22:44 ` juzhe.zhong at rivai dot ai
2023-09-13 7:56 ` rguenth at gcc dot gnu.org
2023-09-13 8:34 ` juzhe.zhong at rivai dot ai
2023-09-13 8:39 ` juzhe.zhong at rivai dot ai
2023-09-13 9:38 ` rguenth at gcc dot gnu.org
2023-09-13 9:39 ` rguenth at gcc dot gnu.org
2023-09-13 9:48 ` juzhe.zhong at rivai dot ai
2023-09-13 9:48 ` juzhe.zhong at rivai dot ai
2023-09-13 10:15 ` rguenther at suse dot de
2023-09-13 22:39 ` rsandifo at gcc dot gnu.org
2023-09-14 8:53 ` juzhe.zhong at rivai dot ai
2023-09-14 9:15 ` richard.sandiford at arm dot com
2023-09-20 16:27 ` cvs-commit at gcc dot gnu.org
2023-09-21 9:13 ` cvs-commit at gcc dot gnu.org
2023-09-21 9:28 ` juzhe.zhong at rivai dot ai
2023-09-22 7:31 ` xuli1 at eswincomputing dot com
2023-09-22 7:33 ` xuli1 at eswincomputing dot com
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