[Bug target/111634] New: RISC-V vector: ICE RTL check: expected code 'reg', have 'lo_sum' in rhs_regno, at rtl.h:1934

[Bug target/111634] New: RISC-V vector: ICE RTL check: expected code 'reg', have 'lo_sum' in rhs_regno, at rtl.h:1934

[patrick at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111634

            Bug ID: 111634
           Summary: RISC-V vector: ICE RTL check: expected code 'reg',
                    have 'lo_sum' in rhs_regno, at rtl.h:1934
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: patrick at rivosinc dot com
  Target Milestone: ---

Created attachment 56011
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=56011&action=edit
-freport-bug output

RTL check fails on testsuite/gcc.dg/pr109417.c -O3

Found using r14-4312-g8552dcd8e44 rv64gcv lp64d --enable-checking=rtl

Does not occur when GCC is compiled using rv64gc lp64d --enable-checking=rtl

during RTL pass: expand
../gcc/gcc/testsuite/gcc.dg/pr109417.c: In function 'main':
../gcc/gcc/testsuite/gcc.dg/pr109417.c:17:17: internal compiler error: RTL
check: expected code 'reg', have 'lo_sum' in rhs_regno, at rtl.h:1934
0x956453 rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int,
char const*)
        ../../../gcc/gcc/rtl.cc:770
0x9833f5 rhs_regno(rtx_def const*)
        ../../../gcc/gcc/rtl.h:1934
0x985924 rhs_regno(rtx_def const*)
        ../../../gcc/gcc/config/riscv/riscv.cc:2058
0x985924 riscv_legitimize_address
        ../../../gcc/gcc/config/riscv/riscv.cc:2045
0xf58089 memory_address_addr_space(machine_mode, rtx_def*, unsigned char)
        ../../../gcc/gcc/explow.cc:477
0xf3e6ba change_address_1
        ../../../gcc/gcc/emit-rtl.cc:2294
0xf40d7c offset_address(rtx_def*, rtx_def*, unsigned long)
        ../../../gcc/gcc/emit-rtl.cc:2532
0xf8a321 expand_assignment(tree_node*, tree_node*, bool)
        ../../../gcc/gcc/expr.cc:5734
0xe5c075 expand_gimple_stmt_1
        ../../../gcc/gcc/cfgexpand.cc:3946
0xe5c075 expand_gimple_stmt
        ../../../gcc/gcc/cfgexpand.cc:4044
0xe61927 expand_gimple_basic_block
        ../../../gcc/gcc/cfgexpand.cc:6100
0xe63bd6 execute
        ../../../gcc/gcc/cfgexpand.cc:6835

[Bug target/111634] RISC-V vector: ICE RTL check: expected code 'reg', have 'lo_sum' in rhs_regno, at rtl.h:1934

[patrick at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111634

--- Comment #1 from Patrick O'Neill <patrick at rivosinc dot com> ---
Comment on attachment 56011
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=56011
-freport-bug output

>// Target: riscv64-unknown-linux-gnu
>// Configured with: /scratch/tc-testing/rtl-checking-testsuite/build-rv64gcv/../gcc/configure --target=riscv64-unknown-linux-gnu --prefix=/
>// Thread model: posix
>// Supported LTO compression algorithms: zlib zstd
>// gcc version 14.0.0 20230928 (experimental) (g8552dcd8e44)
>//
>// during RTL pass: expand
>// ../gcc/gcc/testsuite/gcc.dg/pr109417.c: In function 'main':
>// ../gcc/gcc/testsuite/gcc.dg/pr109417.c:17:17: internal compiler error: RTL check: expected code 'reg', have 'lo_sum' in rhs_regno, at rtl.h:1934
>// 0x956453 rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int, char const*)
>//      ../../../gcc/gcc/rtl.cc:770
>// 0x9833f5 rhs_regno(rtx_def const*)
>//      ../../../gcc/gcc/rtl.h:1934
>// 0x985924 rhs_regno(rtx_def const*)
>//      ../../../gcc/gcc/config/riscv/riscv.cc:2058
>// 0x985924 riscv_legitimize_address
>//      ../../../gcc/gcc/config/riscv/riscv.cc:2045
>// 0xf58089 memory_address_addr_space(machine_mode, rtx_def*, unsigned char)
>//      ../../../gcc/gcc/explow.cc:477
>// 0xf3e6ba change_address_1
>//      ../../../gcc/gcc/emit-rtl.cc:2294
>// 0xf40d7c offset_address(rtx_def*, rtx_def*, unsigned long)
>//      ../../../gcc/gcc/emit-rtl.cc:2532
>// 0xf8a321 expand_assignment(tree_node*, tree_node*, bool)
>//      ../../../gcc/gcc/expr.cc:5734
>// 0xe5c075 expand_gimple_stmt_1
>//      ../../../gcc/gcc/cfgexpand.cc:3946
>// 0xe5c075 expand_gimple_stmt
>//      ../../../gcc/gcc/cfgexpand.cc:4044
>// 0xe61927 expand_gimple_basic_block
>//      ../../../gcc/gcc/cfgexpand.cc:6100
>// 0xe63bd6 execute
>//      ../../../gcc/gcc/cfgexpand.cc:6835
>// Please submit a full bug report, with preprocessed source.
>// Please include the complete backtrace with any bug report.
>// See <https://gcc.gnu.org/bugs/> for instructions.
>
>// /scratch/tc-testing/rtl-checking-testsuite/build-rv64gcv/libexec/gcc/riscv64-unknown-linux-gnu/14.0.0/cc1 -quiet -imultilib lib64/lp64d ../gcc/gcc/testsuite/gcc.dg/pr109417.c -quiet -dumpbase pr109417.c -dumpbase-ext .c -march=rv64gc -mabi=lp64d -mcmodel=medlow -mtune=rocket -misa-spec=20191213 -march=rv64imafdc_zicsr_zifencei -O3 -fdiagnostics-color=never -fno-diagnostics-show-caret -fno-diagnostics-show-line-numbers -fdiagnostics-urls=never -fdiagnostics-path-format=separate-events -fdiagnostics-text-art-charset=none -freport-bug -o - -frandom-seed=0 -fdump-noaddr
>
># 0 "../gcc/gcc/testsuite/gcc.dg/pr109417.c"
># 0 "<built-in>"
># 0 "<command-line>"
># 1 "/scratch/tc-testing/rtl-checking-testsuite/build-rv64gcv/sysroot/usr/include/stdc-predef.h" 1 3 4
># 0 "<command-line>" 2
># 1 "../gcc/gcc/testsuite/gcc.dg/pr109417.c"
>
>
>
>int printf(const char *, ...);
>int c, d, *e, f[1][2], g;
>int main() {
>  int h = 0, *a = &h, **b[1] = {&a};
>  while (e)
>    while (g) {
>    L:
>      for (h = 0; h < 2; h++) {
>        while (d)
>          for (*e = 0; *e < 1;)
>            printf("0");
>        while (c)
>          ;
>        f[g][h] = 0;
>      }
>    }
>  if (h)
>    goto L;
>  return 0;
>}

[Bug target/111634] RISC-V vector: ICE RTL check: expected code 'reg', have 'lo_sum' in rhs_regno, at rtl.h:1934

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111634

--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:a809a556dc0792a34fca7b754ff96ea3ea7d1e7f

commit r14-4443-ga809a556dc0792a34fca7b754ff96ea3ea7d1e7f
Author: Pan Li <pan2.li@intel.com>
Date:   Sat Oct 7 12:39:14 2023 +0800

    RISC-V: Bugfix for legitimize address PR/111634

    Given we have RTL as below.

    (plus:DI (mult:DI (reg:DI 138 [ g.4_6 ])
                      (const_int 8 [0x8]))
             (lo_sum:DI (reg:DI 167)
                        (symbol_ref:DI ("f") [flags 0x86] <var_decl
0x7fa96ea1cc60 f>)
    ))

    When handling (plus (plus (mult (a) (mem_shadd_constant)) (fp)) (C)) case,
    the fp will be the lo_sum operand as above. We have assumption that the fp
    is reg but actually not here. It will have ICE when building with option
    --enable-checking=rtl.

    This patch would like to fix it by adding the REG_P to ensure the operand
    is a register. The test case gcc/testsuite/gcc.dg/pr109417.c covered this
    fix when build with --enable-checking=rtl.

            PR target/111634

    gcc/ChangeLog:

            * config/riscv/riscv.cc (riscv_legitimize_address): Ensure
            object is a REG before extracting its' REGNO.

    Signed-off-by: Pan Li <pan2.li@intel.com>

[Bug target/111634] RISC-V vector: ICE RTL check: expected code 'reg', have 'lo_sum' in rhs_regno, at rtl.h:1934

[patrick at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111634

Patrick O'Neill <patrick at rivosinc dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|UNCONFIRMED                 |RESOLVED

--- Comment #3 from Patrick O'Neill <patrick at rivosinc dot com> ---
Confirmed to be fixed on r14-4443-ga809a556dc0.

Built and ran testsuite on rv32/64gcv glibc/newlib with --enable-checking=rtl.
They all built successfully and no tests fail due to rtl checking!