public inbox for gcc-bugs@sourceware.org
help / color / mirror / Atom feed
* [Bug target/58166] New: ARMv5: poor register allocation in function containing smull instruction
@ 2013-08-15 12:29 jay.foad at gmail dot com
2013-08-21 14:29 ` [Bug target/58166] " rearnsha at gcc dot gnu.org
` (6 more replies)
0 siblings, 7 replies; 8+ messages in thread
From: jay.foad at gmail dot com @ 2013-08-15 12:29 UTC (permalink / raw)
To: gcc-bugs
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58166
Bug ID: 58166
Summary: ARMv5: poor register allocation in function containing
smull instruction
Product: gcc
Version: 4.9.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: jay.foad at gmail dot com
Created attachment 30660
--> http://gcc.gnu.org/bugzilla/attachment.cgi?id=30660&action=edit
C source for testcase
On the attached test case I get:
$ gcc -marm -S -O2 mul.c -o - -fomit-frame-pointer -march=armv5
...
mul:
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
str r4, [sp, #-4]!
smull r3, r4, r0, r1
mov r1, r4
mov r0, r3
ldr r4, [sp], #4
bx lr
If the register allocator picked r2 and r3 for the result of the multiply, then
there would be no need to push and pop r4.
I'm using gcc built from svn r201719 configured with --target=arm-eabi.
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Bug target/58166] ARMv5: poor register allocation in function containing smull instruction
2013-08-15 12:29 [Bug target/58166] New: ARMv5: poor register allocation in function containing smull instruction jay.foad at gmail dot com
@ 2013-08-21 14:29 ` rearnsha at gcc dot gnu.org
2013-08-21 15:14 ` jay.foad at gmail dot com
` (5 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: rearnsha at gcc dot gnu.org @ 2013-08-21 14:29 UTC (permalink / raw)
To: gcc-bugs
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58166
Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |NEW
Last reconfirmed| |2013-08-21
Known to work| |4.7.4
Ever confirmed|0 |1
Known to fail| |4.8.2, 4.9.0
--- Comment #1 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
Confirmed, used to do the right thing in gcc-4.7.
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Bug target/58166] ARMv5: poor register allocation in function containing smull instruction
2013-08-15 12:29 [Bug target/58166] New: ARMv5: poor register allocation in function containing smull instruction jay.foad at gmail dot com
2013-08-21 14:29 ` [Bug target/58166] " rearnsha at gcc dot gnu.org
@ 2013-08-21 15:14 ` jay.foad at gmail dot com
2013-08-22 10:24 ` jay.foad at gmail dot com
` (4 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: jay.foad at gmail dot com @ 2013-08-21 15:14 UTC (permalink / raw)
To: gcc-bugs
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58166
Jay Foad <jay.foad at gmail dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Known to fail| |4.8.0
--- Comment #2 from Jay Foad <jay.foad at gmail dot com> ---
I've just built 4.8.0 from a source tarball and I see the same problem.
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Bug target/58166] ARMv5: poor register allocation in function containing smull instruction
2013-08-15 12:29 [Bug target/58166] New: ARMv5: poor register allocation in function containing smull instruction jay.foad at gmail dot com
2013-08-21 14:29 ` [Bug target/58166] " rearnsha at gcc dot gnu.org
2013-08-21 15:14 ` jay.foad at gmail dot com
@ 2013-08-22 10:24 ` jay.foad at gmail dot com
2013-08-22 14:03 ` rearnsha at gcc dot gnu.org
` (3 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: jay.foad at gmail dot com @ 2013-08-22 10:24 UTC (permalink / raw)
To: gcc-bugs
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58166
--- Comment #3 from Jay Foad <jay.foad at gmail dot com> ---
I've bisected this to r191805:
http://gcc.gnu.org/viewcvs/gcc?view=revision&revision=191805
http://gcc.gnu.org/ml/gcc-patches/2012-09/msg01764.html
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Bug target/58166] ARMv5: poor register allocation in function containing smull instruction
2013-08-15 12:29 [Bug target/58166] New: ARMv5: poor register allocation in function containing smull instruction jay.foad at gmail dot com
` (2 preceding siblings ...)
2013-08-22 10:24 ` jay.foad at gmail dot com
@ 2013-08-22 14:03 ` rearnsha at gcc dot gnu.org
2013-08-22 14:11 ` rearnsha at gcc dot gnu.org
` (2 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: rearnsha at gcc dot gnu.org @ 2013-08-22 14:03 UTC (permalink / raw)
To: gcc-bugs
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58166
Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |rearnsha at gcc dot gnu.org,
| |vmakarov at redhat dot com
--- Comment #4 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
Vlad,
Would you mind commenting on this please?
I suspect it's related to the fact that REG_ALLOC_ORDER on ARM is
{r3, r2, r1, r0, IP, LR, r4, ...}
Which is done to encourage register allocation to use the argument registers
that are least likely to be used for parameters.
What seems to happen is that the compiler picks r3 and r4 over r2 and r3, even
though r4 is a callee saved register and r2 is unused.
Is IRA handling the cost of additional registers for multi-reg pseduos
correctly?
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Bug target/58166] ARMv5: poor register allocation in function containing smull instruction
2013-08-15 12:29 [Bug target/58166] New: ARMv5: poor register allocation in function containing smull instruction jay.foad at gmail dot com
` (3 preceding siblings ...)
2013-08-22 14:03 ` rearnsha at gcc dot gnu.org
@ 2013-08-22 14:11 ` rearnsha at gcc dot gnu.org
2013-08-25 14:16 ` vmakarov at redhat dot com
2024-03-28 5:08 ` pinskia at gcc dot gnu.org
6 siblings, 0 replies; 8+ messages in thread
From: rearnsha at gcc dot gnu.org @ 2013-08-22 14:11 UTC (permalink / raw)
To: gcc-bugs
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58166
--- Comment #5 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
(In reply to Jay Foad from comment #3)
> I've bisected this to r191805:
>
> http://gcc.gnu.org/viewcvs/gcc?view=revision&revision=191805
> http://gcc.gnu.org/ml/gcc-patches/2012-09/msg01764.html
I suspect that is just exposing a latent problem.
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Bug target/58166] ARMv5: poor register allocation in function containing smull instruction
2013-08-15 12:29 [Bug target/58166] New: ARMv5: poor register allocation in function containing smull instruction jay.foad at gmail dot com
` (4 preceding siblings ...)
2013-08-22 14:11 ` rearnsha at gcc dot gnu.org
@ 2013-08-25 14:16 ` vmakarov at redhat dot com
2024-03-28 5:08 ` pinskia at gcc dot gnu.org
6 siblings, 0 replies; 8+ messages in thread
From: vmakarov at redhat dot com @ 2013-08-25 14:16 UTC (permalink / raw)
To: gcc-bugs
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58166
--- Comment #6 from Vladimir Makarov <vmakarov at redhat dot com> ---
On 13-08-22 10:11 AM, rearnsha at gcc dot gnu.org wrote:
> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58166
>
> --- Comment #5 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
> (In reply to Jay Foad from comment #3)
>> I've bisected this to r191805:
>>
>> http://gcc.gnu.org/viewcvs/gcc?view=revision&revision=191805
>> http://gcc.gnu.org/ml/gcc-patches/2012-09/msg01764.html
> I suspect that is just exposing a latent problem.
>
Sorry, I am on vacation now. I'll look at this after my vacation (after
the Labor day).
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Bug target/58166] ARMv5: poor register allocation in function containing smull instruction
2013-08-15 12:29 [Bug target/58166] New: ARMv5: poor register allocation in function containing smull instruction jay.foad at gmail dot com
` (5 preceding siblings ...)
2013-08-25 14:16 ` vmakarov at redhat dot com
@ 2024-03-28 5:08 ` pinskia at gcc dot gnu.org
6 siblings, 0 replies; 8+ messages in thread
From: pinskia at gcc dot gnu.org @ 2024-03-28 5:08 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58166
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|NEW |RESOLVED
Target Milestone|--- |5.0
Resolution|--- |FIXED
--- Comment #7 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
The trunk-GCC9 produces:
```
mov r3, r0
mov r2, r1
smull r0, r1, r3, r2
bx lr
```
GCC 5.4.0-8.5.0 produces:
```
smull r2, r3, r0, r1
mov r0, r2
mov r1, r3
bx lr
```
I don't have a 4.9.x compiler around to test.
So I am going to assume this was fixed, at least in GCC 5.
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2024-03-28 5:08 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-08-15 12:29 [Bug target/58166] New: ARMv5: poor register allocation in function containing smull instruction jay.foad at gmail dot com
2013-08-21 14:29 ` [Bug target/58166] " rearnsha at gcc dot gnu.org
2013-08-21 15:14 ` jay.foad at gmail dot com
2013-08-22 10:24 ` jay.foad at gmail dot com
2013-08-22 14:03 ` rearnsha at gcc dot gnu.org
2013-08-22 14:11 ` rearnsha at gcc dot gnu.org
2013-08-25 14:16 ` vmakarov at redhat dot com
2024-03-28 5:08 ` pinskia at gcc dot gnu.org
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).