[Bug target/58166] New: ARMv5: poor register allocation in function containing smull instruction

[Bug target/58166] New: ARMv5: poor register allocation in function containing smull instruction

[jay.foad at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58166

            Bug ID: 58166
           Summary: ARMv5: poor register allocation in function containing
                    smull instruction
           Product: gcc
           Version: 4.9.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: jay.foad at gmail dot com

Created attachment 30660
  --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=30660&action=edit
C source for testcase

On the attached test case I get:

$ gcc -marm -S -O2 mul.c -o - -fomit-frame-pointer -march=armv5
...
mul:
    @ args = 0, pretend = 0, frame = 0
    @ frame_needed = 0, uses_anonymous_args = 0
    @ link register save eliminated.
    str    r4, [sp, #-4]!
    smull    r3, r4, r0, r1
    mov    r1, r4
    mov    r0, r3
    ldr    r4, [sp], #4
    bx    lr

If the register allocator picked r2 and r3 for the result of the multiply, then
there would be no need to push and pop r4.

I'm using gcc built from svn r201719 configured with --target=arm-eabi.

[Bug target/58166] ARMv5: poor register allocation in function containing smull instruction

[rearnsha at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58166

Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2013-08-21
      Known to work|                            |4.7.4
     Ever confirmed|0                           |1
      Known to fail|                            |4.8.2, 4.9.0

--- Comment #1 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
Confirmed, used to do the right thing in gcc-4.7.

[Bug target/58166] ARMv5: poor register allocation in function containing smull instruction

[jay.foad at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58166

Jay Foad <jay.foad at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
      Known to fail|                            |4.8.0

--- Comment #2 from Jay Foad <jay.foad at gmail dot com> ---
I've just built 4.8.0 from a source tarball and I see the same problem.

[Bug target/58166] ARMv5: poor register allocation in function containing smull instruction

[jay.foad at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58166

--- Comment #3 from Jay Foad <jay.foad at gmail dot com> ---
I've bisected this to r191805:

http://gcc.gnu.org/viewcvs/gcc?view=revision&revision=191805
http://gcc.gnu.org/ml/gcc-patches/2012-09/msg01764.html

[Bug target/58166] ARMv5: poor register allocation in function containing smull instruction

[rearnsha at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58166

Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |rearnsha at gcc dot gnu.org,
                   |                            |vmakarov at redhat dot com

--- Comment #4 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
Vlad,

Would you mind commenting on this please?

I suspect it's related to the fact that REG_ALLOC_ORDER on ARM is

{r3, r2, r1, r0, IP, LR, r4, ...}

Which is done to encourage register allocation to use the argument registers
that are least likely to be used for parameters.

What seems to happen is that the compiler picks r3 and r4 over r2 and r3, even
though r4 is a callee saved register and r2 is unused.

Is IRA handling the cost of additional registers for multi-reg pseduos
correctly?

[Bug target/58166] ARMv5: poor register allocation in function containing smull instruction

[rearnsha at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58166

--- Comment #5 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
(In reply to Jay Foad from comment #3)
> I've bisected this to r191805:
> 
> http://gcc.gnu.org/viewcvs/gcc?view=revision&revision=191805
> http://gcc.gnu.org/ml/gcc-patches/2012-09/msg01764.html

I suspect that is just exposing a latent problem.

[Bug target/58166] ARMv5: poor register allocation in function containing smull instruction

[vmakarov at redhat dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58166

--- Comment #6 from Vladimir Makarov <vmakarov at redhat dot com> ---
On 13-08-22 10:11 AM, rearnsha at gcc dot gnu.org wrote:
> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58166
>
> --- Comment #5 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
> (In reply to Jay Foad from comment #3)
>> I've bisected this to r191805:
>>
>> http://gcc.gnu.org/viewcvs/gcc?view=revision&revision=191805
>> http://gcc.gnu.org/ml/gcc-patches/2012-09/msg01764.html
> I suspect that is just exposing a latent problem.
>
Sorry, I am on vacation now.  I'll look at this after my vacation (after 
the Labor day).

[Bug target/58166] ARMv5: poor register allocation in function containing smull instruction

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58166

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
   Target Milestone|---                         |5.0
         Resolution|---                         |FIXED

--- Comment #7 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
The trunk-GCC9 produces:
```
        mov     r3, r0
        mov     r2, r1
        smull   r0, r1, r3, r2
        bx      lr
```

GCC 5.4.0-8.5.0 produces:
```
        smull   r2, r3, r0, r1
        mov     r0, r2
        mov     r1, r3
        bx      lr
```

I don't have a 4.9.x compiler around to test.

So I am going to assume this was fixed, at least in GCC 5.